1K x 8 Registered PROM
CY7C235A
Cypress Semiconductor Corporation • 3901 North F irs t Street • San Jos e • CA 95134 • 408-943-2600
Document #: 38-04002 Rev. *B Revised December 27, 2002
1CY7C235A
Features
• CMOS for optimum speed/power
• High speed
—25 ns address set-up
—12 ns clock to output
• Low power
—495 mW (Commercial)
—660 mW (Military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Programmable asynchronous registers (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
LCC and PLCC
•5V ±10% VCC, commercial and military
• TTL-compatible I /O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Descri p tion
The CY7C235A is a high-performance 1024-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, or 2 8-pin p lastic l eaded ch ip carr ier. The mem ory ce lls
utilize prov en EPROM fl oating gate tech nolog y and byt e-wid e
intelligent programming algorithms.
The CY7C 235A repl aces bipola r devices pin for pi n and of fers
the advantages of lower power, superior performance, and
high pr ogra mming y ield. The EPROM c ell require s onl y 12. 5V
for the supervoltage, and low current requirements allow for
gang prog rammi ng. The EPROM cells allow for ea ch mem ory
location to be tested 100%, as each location is written into,
erase d, and repe atedly exe rcised pr ior to enca psulatio n. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer
programming.
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
A9
E
INIT
CP
O7
O6
O4
O5
O3
A8
A7
A6
A5
A4
A3
A2
A1
A0
PROGRAMMABLE
ARRAY MULTIPLEXER
COLUMN
ADDRESS
ROW
ADDRESS
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O7
O6
O5
O4
O3
O2
O1
O0
CP
CP
ES
E
ES
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3E
NC
NC
NC
INIT
ES
O7
O6
A2
A1CP
O2
A8
A9
INIT
INITIALIZE WORD
PROGRAMMABLE
A9
DIP
LCC/PLCC
Top View
Top View
ADDRESS
DECODER
Logic Block Diagram Pin Configurati on
Selection Guide
7C235A-25 7C235A-30 7C235A-40 Unit
Minimum Address Set-Up Time 25 30 40 ns
Maxim um C loc k to Out put 12 15 20 ns
Maximum Operating
Current Commercial 90 90 90 mA
Military 120 mA
CY7C235A
Document #: 38-04002 Rev. *B Page 2 of 10
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12 for DIP).................................. −0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z Stat e .................................................... −0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20 for DIP)...............13.0V
Static Discha rge Voltage..... ................. ...... ................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[2] −55°C to +125°C 5V ±10%
Electrical Characteristi cs Ov er Operating Rang e [3]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 16 mA
VIN = VIH or VIL 0.4 V
VIH Input HIGH Level Guaranteed Input Logical HIGH V oltage for All
Inputs[4] 2.0 V
VIL Input LOW Level Guarante ed Input Logica l LOW V olt age for All
Inputs[4] 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 µA
VCD Input Clamp Diode Voltage Note 5
IOZ Output Leakage Current GND < VOUT < VCC Output Disabled[4] −10 +10 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0.0V[6] −20 −90 mA
ICC Power Supply Current IOUT = 0 mA,
VCC = Max. Commercial 90 mA
Military 120
VPP Programmi ng Supp ly Voltage 12 13 V
IPP Programmi ng Supp ly Curren t 50 mA
VIHP Inpu t HIG H Program m ing Voltage 3.0 V
VILP Input LOW Programming Voltage 0.4 V
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Cap a ci tance TA = 25°C, f = 1 MHz, VCC =5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
1. The volatge on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C235A
Document #: 38-04002 Rev. *B Page 3 of 10
a
Operating Modes
The CY7C235A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with sy nc hron ous (ES) an d as yn chronous (E) output
enables and asynchronous initialization (INIT).
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O0−O7) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address input (A0−A9) and a logic LOW
to the enable (ES) input. The stored data is accessed and
loaded into the m ast er f lip-flop s of th e d ata re gis ter du ring th e
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outpu ts (O0−O7), provi ded the asy nchronous e nable (E) is
also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the sy nchronou s enable (ES) inp ut is swi tched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW ,
the subs equent positive clock edge will return the out put to the
acti ve state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C235A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock w ithout in troduc ing race condit ions. Th e on-chi p
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C235A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated fu nctions s uch as a built -in “jump st art” address . When
activated the initialize control input causes the contents of a
user programmed 1025th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the registe r . In the unprogra mmed state , activa ting
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and th e ES input pin mu st be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
When the as ynchrono us initiali ze input, INIT, is LOW, the dat a
in the initialize byte will be asynchronously loaded into the
output register. It will not, however, appear on the output pins
until they are enabled, as described in the preceding
paragraph.
AC Test Loads and Waveforms[5]
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10%
90%
10%
5ns 5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(b) High-ZLoad
OUTPUT 2.0V
Equivalent to: TH ÉVENIN EQUIVALENT
100Ω
R1 250Ω
(a) NormalLoad
R2
167Ω
ALL INPUT PULSES
≤≤
CY7C235A
Document #: 38-04002 Rev. *B Page 4 of 10
Switching Waveforms[5]
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Switching Characteristics Over Operating Range[3 , 5]
7C235A-25 7C235A-30 7C235A-40
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tSA Address Set-Up to Clock HIGH 25 30 40 ns
tHA Address Hold from Clock HIGH 000ns
tCO Clock HIGH to Va lid Output 12 15 20 ns
tPWC Clock Pulse Width 12 15 20 ns
tSES ES Set-Up to Clock HIGH 10 10 15 ns
tHES ES Hold from Clock HIGH 555ns
tDI Delay from INIT to Valid Output 25 25 35 ns
tRI INIT Recovery to Clock HIGH 20 20 20 ns
tPWI INIT Pulse Wid t h 20 20 25 ns
tCOS Inactive to Valid Output from Clock HIGH[7] 20 20 25 ns
tHZC Inactive Output from Clock HIGH[7] 20 20 25 ns
tDOE Valid Output from E LOW 20 20 25 ns
tHZE Inactive Output from E HIGH 20 20 25 ns
Note:
7. Applies only when the synchronous (ES) function is used.
tDI
tCO tDOE
tHZE
tHZC
tSA tHA
tHES
tSES
tPWC tPWC tPWC tPWC tPWC tPWC
tHA
tCO tCOS
O0−O7
A0−A10
INIT
CP
ES
EtRI
tPWI
tHES
tSES
tHES
tSES
CY7C235A
Document #: 38-04002 Rev. *B Page 5 of 10
Table 1. Mode Selection
Pin Function[8]
Read or Output Disable A0, A3−A9A1A2CP ESEINIT O7−O0
Mode Other A0, A3−A9A1A2PGM VFY E VPP D7−D0
Read A0, A3−A9A1A2X VIL VIL VIH O7−O0
Output Disable A0, A3−A9A1A2X VIH X VIH High Z
Output Disable A0, A3−A9A1A2X X VIH VIH High Z
Initialize A0, A3−A9A1A2X X VIL VIL Init Byte
Program A0, A3−A9A1A2VILP VIHP VIHP VPP D7−D0
Program Verify A0, A3−A9A1A2VIHP VILP VIHP VPP O7−O0
Program Inhibit A0, A3−A9A1A2VIHP VIHP VIHP VPP High Z
Intellig ent Program A0, A3−A9A1A2VILP VIHP VIHP VPP D7−D0
Program Initialize Byte A0, A3−A9VPP VILP VILP VIHP VIHP VPP D7−D0
Blank Check A0, A3−A9A1A2VIHP VILP VIHP VPP Zeros
Note:
8. X = “don’t care” but not to exceed VCC ±5%.
Figure 1. Programming Pinouts
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
A9
E
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
NC
NC
D7
D6
A2
A1
D2
E
VPP
VFY
PGM
NC
A9
DIP LCC/PLCC
Top View Top View
CY7C235A
Document #: 38-04002 Rev. *B Page 6 of 10
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
1.6
4.0 4.5 5.0 5.5 6.0
NOR M ALIZED CLOCK-TO-OUTPU T TI ME
SUPP LY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLT AGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C) SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. V
CC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
AMBI EN T TEMPERATURE (°C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED ICC
NORMALIZED ICC
VCC =5.0V
TA=25°C
TA=25°C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
025 5075
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
−55 125
NORM ALI Z ED SET-UP
0.6 25
AMBIENT TEMPERATURE (°C)
NORM ALI Z ED SET-UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK -TO-OUTPUT TIME
0.4
SUPPLY VOLTAGE (V)
NORM ALI Z ED SET-UP TIME
vs. SUPPLY VOLT AGE
TA=25°C
1.0
0.8
0.6
C235A-10
NORMALIZED ICC
0.90
VCC =5.5V
TA=25°C
CY7C235A
Document #: 38-04002 Rev. *B Page 7 of 10
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Speed
(ns) Package
Name Operating RangetSA tCO Ordering Code Package Type
25 12 CY7C235A-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
30 15 CY7C235A-30JC J64 28-Lead Plas ti c Lead ed Chip Carri er
40 20 CY7C235A-40PC P13 24-Lead (300-Mil) Molded DIP
CY7C235A-40DMB D14 24-Le ad (300 -Mil) CerDIP Military
CY7C235A-40LMB L64 28-Square Leadless Chip Carrier
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
CY7C235A
Document #: 38-04002 Rev. *B Page 8 of 10
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
CY7C235A
Document #: 38-04002 Rev. *B Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other ri ghts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85013-A
24-Lead (300-Mil) Molded DIP P13
CY7C235A
Document #: 38-04002 Rev. *B Page 10 of 10
Document History Page
Document Title: CY7C235A 1K x 8 Registered PROM
Document Number: 38-04002
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113857 03/06/02 DSG Change from Spec number: 38-00229 to 38-04002
*A 118893 10 /09 /02 GBI Update ordering inform ati on
*B 122243 12/27/02 RBI Add power up requirements to maximum ratings information.
