2-98
HIP6005A
Buck Pulse-Width Modulator (PWM)
Controller and Output Voltage Monitor
The HIP6005A provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive an
N-Channel MOSFET in a standard buck topology. The
HIP6005A integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6005A includes a fully TTL-
compatible 5-input digital-to-analog converter (DAC) that
adjusts the output voltage from 2.1VDC to 3.5VDC in 0.1V
increments and from 1.8VDC to 2.05VDC in 0.05V steps.
The precision reference and voltage-mode regulator hold the
selected output voltage to within ±1% over temperature and
line voltage variations.
The HIP6005A provides simple, single feedback loop, voltage-
mode control with f ast tr ansient response . It includes a
200kHz free-running triangle-wave oscillator that is adjustable
from below 50kHz to o ver 1MHz. The error amplifier f eatures
a 15MHz gain-bandwidth product and 6V/µs slew r ate which
enables high converter bandwidth for fast transient
performance. The resulting PWM duty ratio ranges from 0% to
100%.
The HIP6005A monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6005A
protects against over-current and over-voltage conditions by
inhibiting PWM operation. Additional built-in over-voltage
protection triggers an external SCR to crowbar the input
supply. The HIP6005A monitors the current by using the
rDS(ON) of the upper MOSFET which eliminates the need for
a current sensing resistor.
6X86™ is a trademark of Cyrix Corporation.
Alpha™ is a trademark of Digital Equipment Corporation.
K6™ is a trademark of Advanced Micro Devices, Inc.
Pentium® is a registered trademark of Intel Corporation.
PowerPC™ is a trademark of IBM.
Features
• Drives N-Channel MOSFET
• Operates from +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
-±1% Over Line Voltage and Temperature
• TTL-Compatible 5-Bit Digital-to-Analog Output Voltage
Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.8VDC to 3.5VDC
- 0.1V Binary Steps. . . . . . . . . . . . . . . 2.1VDC to 3.5VDC
- 0.05V Binary Steps. . . . . . . . . . . . . 1.8VDC to 2.05VDC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
Applications
• Power Supply for Pentium®, Pentium Pro, Pentium II,
PowerPC™, K6™, 6X86™ and Alpha™ Microprocessors
•High-Power 5V to 3.xV DC-DC Regulators
•Low-Voltage Distributed Power Supplies
Pinout
HIP6005A
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HIP6005ACB 0 to 70 20 Ld SOIC M20.3
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
VSEN
OCSET
SS
VID0
VID1
VID2
VID4
VID3
COMP
FB
RT
VCC
NC
NC
OVP
BOOT
UGATE
PHASE
PGOOD
GND
Data Sheet September 1997 File Number
4418.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
2-99
Typical Application
Block Diagram
+
-
+
-
+12V
+VOUT
HIP6005A
VSEN
RT
FB
COMP
SS
PGOOD
GND
MONITOR AND
PROTECTION
OSC UGATE
OCSET
PHASE
BOOT
VCC VIN = +5V OR +12V
OVP
VID0
VID1
VID2
VID3 D/A
VID4
D/A
CONVERTER
(DAC)
OSCILLATOR
SOFT-
START
REFERENCE
POWER-ON
RESET (POR)
115%
110%
90%
INHIBIT
PWM
COMPARATOR
ERROR
AMP
VCC
PGOOD
SS
PWM
OVP
RT GND
VSEN
OCSET
VID0
VID1
VID2
VID3
FB
COMP
DACOUT
OVER-
VOLTAGE
OVER-
CURRENT
GATE
CONTROL
LOGIC
BOOT
UGATE
PHASE
200µA
10µA
4V
+
-
+
-
+
-
+
-
+
-+
-
VID4
HIP6005A
2-100
Absolute Maximum Ratings Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
Boot Voltage, VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . . . . . . +15V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SOIC Package (with 3in2 of Copper) . . . . . . . . . . . 86
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply ICC UGATE Open - 5 - mA
POWER-ON RESET
Rising VCC Threshold VOCSET = 4.5V - - 10.4 V
Falling VCC Threshold VOCSET = 4.5V 8.2 - - V
Rising VOCSET Threshold - 1.26 - V
OSCILLATOR
Free Running Frequency RT = Open 185 200 215 kHz
Total Variation 6kΩ < RT to GND < 200kΩ-15 - +15 %
Ramp Amplitude ∆VOSC RT = Open - 1.9 - VP-P
REFERENCE AND DAC
DAC(VID0-VID4) Input Low Voltage - - 0.8 V
DAC(VID0-VID4) Input High Voltage 2.0 - - V
DACOUT Voltage Accuracy -1.0 - +1.0 %
ERROR AMPLIFIER
DC Gain -88- dB
Gain-Bandwidth Product GBW - 15 - MHz
Slew Rate SR COMP = 10pF - 6 - V/µs
GATE DRIVER
Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA
Upper Gate Sink RUGATE - 5.5 10 Ω
PROTECTION
Over-Voltage Trip (VSEN/DACOUT) - 115 120 %
OCSET Current Source IOCSET VOCSET = 4.5V 170 200 230 µA
OVP Sourcing Current IOVP VSEN = 5.5V; VOVP = 0V 60 - - mA
Soft Start Current ISS -10- µA
HIP6005A
2-101
POWER GOOD
Upper Threshold (VSEN/DACOUT) VSEN Rising 106 - 111 %
Lower Threshold (VSEN/DACOUT) VSEN Falling 89 - 94 %
Hysteresis (VSEN/DACOUT) Upper and Lower Threshold - 2 - %
PGOOD Voltage Low VPGOOD IPGOOD = -5mA - 0.5 - V
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Typical Performance Curves
FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
10 100 1000
SWITCHING FREQUENCY (kHz)
RESISTANCE (kΩ)
10
100
1000 RT PULLUP
TO +12V
RT PULLDOWN TO VSS
100 200 300 400 500 600 700 800 900 1000
40
35
30
25
20
15
10
5
0
ICC (mA)
SWITCHING FREQUENCY (kHz)
CUGATE = 3300pF
CUGATE = 1000pF
CUGATE = 10pF
HIP6005A
2-102
Functional Pin Description
V
SEN
(Pin 1)
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
OCSET (Pin 2)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 200µA current source
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set
the converter over-current (OC) trip point according to the
following equation:
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
VID0-4 (Pins 4-8)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the 32 combinations of DAC inputs.
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage.
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
NC (Pin 16)
No connection.
NC (Pin 17)
No connection.
V
CC
(Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
VSEN
OCSET
SS
VID0
VID1
VID2
VID4
VID3
COMP
FB
RT
VCC
NC
NC
OVP
BOOT
UGATE
PHASE
PGOOD
GND
IPEAK IOCS ROCSET
•
rDS ON()
--------------------------------------------=
Fs 200kHz 510
6
•
R
T
kΩ()
---------------------+≈(RT to GND)
Fs 200kHz 410
7
•
R
T
kΩ()
---------------------–≈(RT to 12V)
HIP6005A
2-103
Functional Description
Initialization
The HIP6005A automatically initializes upon receipt of
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage at the VCC pin and the input voltage (VIN) on
the OCSET pin. The level on OCSET is equal to VIN less a
fixed voltage drop (see over-current protection). The POR
function initiates soft start operation after both input supply
voltages exceed their POR thresholds. For operation with a
single +12V power source, VIN and VCC are equivalent and
the +12V power source must exceed the rising VCC
threshold before POR initiates operation.
Soft Start
The POR function initiates the soft start sequence. An
internal 10µA current source charges an external capacitor
(CSS) on the SS pin to 4V. Soft start clamps the error
amplifier output (COMP pin) and reference input (+ terminal
of error amp) to the SS pin voltage. Figure 3 shows the soft
start interval with CSS = 0.1µF. Initially the clamp on the error
amplifier (COMP pin) controls the converter’s output voltage.
At t1 in Figure 3, the SS voltage reaches the valley of the
oscillator’s triangle wave. The oscillator’s triangular
waveform is compared to the ramping error amplifier voltage.
This generates PHASE pulses of increasing width that
charge the output capacitor(s). This interval of increasing
pulse width continues to t2. With sufficient output voltage,
the clamp on the reference input controls the output voltage.
This is the interval between t2and t3in Figure 3. At t3the SS
voltage exceeds the DACOUT voltage and the output
voltage is in regulation. This method provides a rapid and
controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±5% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
rDS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The ov er-current function cycles the soft-start function in a
hiccup mode to provide f ault protection. A resistor (R OCSET)
programs the o v er-current trip le v el. An internal 200µA current
sink de v elops a v oltage across R OCSET that is referenced to
VIN. When the voltage across the upper MOSFET (also
ref erenced to VIN) e xceeds the v oltage across R OCSET, the
ov er-current function initiates a soft-start sequence. The soft-
start function discharges CSS with a 10µA current sink and
inhibits PWM operation. The soft-start function recharges CSS,
and PWM operation resumes with the error amplifier clamped
to the SS voltage . Should an o v erload occur while recharging
CSS, the soft start function inhibits PWM operation while fully
charging CSS to 4V to complete its cycle. Figure 4 sho ws this
operation with an overload condition. Note that the inductor
current increases to ov er 15A during the CSS charging interval
and causes an ov er-current trip . The con v erter dissipates very
little power with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
where IOCSET is the internal OCSET current source (200µA
typical). The OC trip point varies mainly due to the
MOSFETs rDS(ON) variations. To avoid over-current tripping
in the normal operating load range, find the ROCSET resistor
from the equation above with:
1. ThemaximumrDS(ON)atthehighestjunctiontemperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for ,
where ∆I is the output inductor ripple current.
0V
0V
0V
TIME (5ms/DIV.)
SOFT-START
(1V/DIV.)
OUTPUT
(1V/DIV.)
VOLTAGE
t2t3
PGOOD
(2V/DIV.)
t1
FIGURE 3. SOFT START INTERVAL
OUTPUT INDUCTOR SOFT-START
0A
0V
TIME (20ms/DIV.)
5A
10A
15A
2V
4V
FIGURE 4. OVER-CURRENT OPERATION
IPEAK IOCSET ROCSET
•
rDS ON()
---------------------------------------------------=
IPEAK IOUT MAX()
∆I()2⁄+>
HIP6005A
2-104
For an equation for the ripple current see the section under
component guidelines titled “Output Inductor Selection.”
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a HIP6005A converter is programmed
to discrete levels between 1.8VDC and 3.5VDC. The voltage
identification (VID) pins program an internal voltage
reference (DACOUT) with a TTL-compatible 5-bit digital-to-
analog converter (DAC). The level of DACOUT also sets the
PGOOD and OVP thresholds. Table 1 specifies the
DACOUT voltage for the 32 different combinations of
connections on the VID pins. The output voltage should not
be adjusted while the converter is delivering power. Remove
input power before changing the output voltage. Adjusting
the output voltage during operation could toggle the PGOOD
signal and exercise the overvoltage protection.
All VID pin combinations resulting in a 0V output setting
activate the Power-On Reset function, disable the gate drive
circuitry and output a 0 logic at PGOOD pin.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME NOMINAL OUTPUT
V OLTA GE DACOUT
PIN NAME NOMINAL OUTPUT
V OLTA GE DACOUTVID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0
01111 0 11111 0
01110 0 11110 2.1
01101 0 11101 2.2
01100 0 11100 2.3
01011 0 11011 2.4
01010 0 11010 2.5
01001 0 11001 2.6
01000 0 11000 2.7
00111 0 10111 2.8
00110 0 10110 2.9
0 0 1 0 1 1.80 1 0 1 0 1 3.0
0 0 1 0 0 1.85 1 0 1 0 0 3.1
0 0 0 1 1 1.90 1 0 0 1 1 3.2
0 0 0 1 0 1.95 1 0 0 1 0 3.3
0 0 0 0 1 2.00 1 0 0 0 1 3.4
0 0 0 0 0 2.05 1 0 0 0 0 3.5
NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors.
LO
CO
UGATE
PHASE
Q1
D2
VIN
VOUT
RETURN
HIP6005A
CIN
LOAD
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
HIP6005A
2-105
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors CIN
and CO each represent numerous physical capacitors.
Locate the HIP6005A within 3 inches of the MOSFET, Q1.
The circuit traces for the MOSFET’s gate and source
connections from the HIP6005A must be sized to handle up
to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, Css
close to the SS pin because the internal current source is
only 10µA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a buck
converter. The output voltage (VOUT) is regulated to the
Reference voltage level. The error amplifier (Error Amp)
output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6005A) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to
provide a closed loop transfer function with the highest 0dB
crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Doub le Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
HIP6005A
SS
GND
VCC
BOOT D1LO
CO
VOUT
LOAD
Q1
D2
PHASE
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+VIN
CBOOT
CVCC
CSS
+12V
VOUT
OSC
REFERENCE
LO
CO
ESR
V
IN
∆VOSC
ERROR
AMP
PWM DRIVER
(PARASITIC)
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPEN-
SATION DESIGN
ZIN
ZFB
DACOUT
R1
R3
R2C3
C2
C1
COMP
VOUT
FB
ZFB
HIP6005A
ZIN
COMPARATOR
DETAILED COMPENSATION COMPONENTS
VE/A
+
-
+
-
+
-PHASE
FLC 1
2πLOCO
••
---------------------------------------= FESR 1
2πESR CO
•()•
---------------------------------------------=
HIP6005A
2-106
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC con verter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q f actor of the output filter and is not
shown in Figure 8. Using the abo ve guidelines should give a
Compensation Gain similar to the curv e plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates abov e
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors .
The bulk filter capacitor values are generally determined by
the ESR (eff ective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF ceramic
capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the con verter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6005A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the tr ansient current lev el. During this interval the
diff erence betw een the inductor current and the tr ansient
current le vel must be supplied b y the output capacitor.
FZ2 1
2πR1R3
+()C
3
••
----------------------------------------------------=
FP1 1
2πR2C1C2
•
C1C2
+
---------------------
••
-----------------------------------------------------=
FP2 1
2πR3C3
••
---------------------------------=
FZ1 1
2πR2C1
••
---------------------------------=
100
80
60
40
20
0
-20
-40
-60
FP1
FZ2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
FZ1 FP2
FLC FESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
20LOG
(VIN/∆VOSC)
MODULATOR
GAIN
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
20LOG
(R2/R1)
CLOSED LOOP
GAIN
∆IVIN VOUT
–
FSL•
-------------------------------- VOUT
VIN
----------------
•=∆VOUT ∆IESR•=
HIP6005A
2-107
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, tFALL is the longest response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk
capacitors to supply the current needed each time Q1turns
on. Place the small ceramic capacitors physically close to
the MOSFETs and between the drain of Q1 and the anode
of Schottky diode D2.
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is
a conser vative guideline. The RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
F or a through hole design, sev er al electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution m ust be
e xercised with regard to the capacitor surge current rating.
These capacitors must be capab le of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The HIP6005A requires an N-Channel power MOSFET. It
should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET po w er dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for the MOSFET.
Switching losses also contribute to the overall MOSFET
power loss (see the equations below). These equations
assume linear voltage-current tr ansitions and are
approximations. The gate-charge losses are dissipated by the
HIP6005A and do not heat the MOSFET. Howe ver, large
gate-charge increases the s witching interval, tSW, which
increases the upper MOSFET s witching losses . Ensure that
the MOSFET is within its maximum junction temperature at
high ambient temperature b y calculating the temper ature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6005A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-
to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from VCC. The boot capacitor, CBOOT,
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the Schottky diode, D2,
conducts. Logic-level MOSFETs can only be used if the
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC. This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. F or +5V main power and +12VDC
f or the bias , the gate-to-source voltage of Q1 is 7V. A logic-
level MOSFET is a good choice for Q1under these conditions.
tRISE LI
TRAN
•
VIN VOUT
–
--------------------------------= tFALL LI
TRAN
•
VOUT
--------------------------=
PCOND = IO2• rDS(ON) • D
Where: D is the duty cycle = VOUT/VIN,
tSW is the switching interval, and
FS is the switching frequency.
PSW = 1/2 IO• VIN • tSW • FS
HIP6005A
2-108
Schottky Selection
Rectifier D2conducts when the upper MOSFET Q1is off. The
diode should be a Schottky type for low power losses. The
power dissipation in the Schottky rectifier is approximated b y:
In addition to power dissipation, package selection and heat-
sink requirements are the main design trade-offs in choosing
the schottky rectifier. Since the three factors are interrelated,
the selection process is an iterative procedure. The maxi-
mum junction temperature of the rectifier must remain below
the manufacturer’s specified value, typically 125oC. By using
the package thermal resistance specification and the schot-
tky power dissipation equation (shown above), the junction
temperature of the rectifier can be estimated. Be sure to use
the available airflow and ambient temperature to determine
the junction temperature rise.
+12V
HIP6005A
GND
UGATE
PHASE
BOOT
VCC
+5V OR +12
NOTE: VG-S ≈ VCC - VD.
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
(NOTE)
CBOOT
DBOOT
Q1
D2
+
-
+ VD -
+12V
HIP6005A
GND
UGATE
PHASE
BOOT
VCC
+5V OR LESS
Q1
+
-
FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
D2
NOTE:
VG-S ≈VCC -5V
PCOND = I0 x Vf x (1 - D)
Where: D is the duty cycle = VOUT / VIN, and
Vfis the Schottky forward voltage drop
HIP6005A
2-109
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HIP6005A DC-DC Converter Application Circuit
Figure 11 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete Bill-of-
Materials and circuit board description, can be found in
application note AN9706. Although the Application Note
details the HIP6005, the same evaluation platform can be
used to evaluate the HIP6005A. Intersil AnswerFAX (407-
724-7800) doc. #99706.
+12V
+VO
HIP6005A
VSEN
RT
FB
COMP
VID0
VID1
VID2
VID3
OVP
SS PGOOD
D/A
GND
MONITOR
OSC
VCC
C1
L2
C0
0.1µF
2x 1µF
0.1µF
0.1µF
2.2nF
8.2nF 20K
1K
7µH
5x 1000µF
9x 1000µF
0.082µF
UGATE
OCSET
PHASE
BOOT
20
D1
Q1
2N6394
1.1K
1000pF
D2
2K
VIN = +5V
OR
+12V
1
2
3
4
5
6
7
9
10
11
12
13
14
15
19
20
18
AND
PROTECTION
+
-
+
-
Component Selection Notes
C0 - C9 Each 1000µF 6.3WVDC, Sanyo MV-GX or Equivalent
C1 - C5 Each 330µF 25WVDC, Sanyo MV-GX or Equivalent
L2 - Core: Micrometals T60-52; Each Winding: 14 Turns of 17A WG
L1 - Core: Micrometals T50-52; Winding: 6 Turns of 18AWG
D1 - 1N4148 or Equivalent
D2 - 25A, 35V Schottky, Motorola MBR2535CTL or Equivalent
Q1 - Intersil MOSFET; RFP70N03
FIGURE 11. PENTIUM PRO DC-DC CONVERTER
VID4 8
L1 - 1µH
F1
HIP6005A
