I e. n. atio chang cific o spe bject t l a u fin s ot a its are is n m This etric li : e m ic Not e para Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DESCRIPTION These are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash memory. These are housed in 100-pin plastic molded QFP. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. These microcomputers include the 4-channel DMA controller and the DRAM controller. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require fast processing of large data. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. DISTINCTIVE FEATURES <Microcomputer mode> Number of basic machine instructions .................................... 203 Memory [M37920FCCGP, M37920FCCHP] Flash memory (User ROM area) ................................. 120 Kbytes RAM ............................................................................. 4096 bytes [M37920FGCGP, M37920FGCHP] Flash memory (User ROM area) ................................. 248 Kbytes RAM ............................................................................. 6144 bytes [All of the above computers] Flash memory (Boot ROM area) ................................... 16 Kbytes Instruction execution time The fastest instruction at 20 MHz frequency ........................ 50 ns Single power supply .................................................... 5 V 0.5 V Interrupts ........... 6 external sources, 20 internal sources, 7 levels Multi-functional 16-bit timer ................................................... 5 + 3 Serial I/O (UART or Clock synchronous) ..................................... 2 10-bit A-D converter ............................................ 4-channel inputs DMA controller .............................................................. 4 channels DRAM controller Real-time output .... 4 bits x 2 channels, or 6 bits x 1 channel + 2 bits x 1 channel 12-bit watchdog timer Programmable input/output (ports P0-P12) .............................. 85 * * * * * * * * * * * * * <Flash memory mode> Power supply voltage .................................................. 5 V 0.5 V Programming/Erase voltage ........................................ 5 V 0.5 V Programming method ............ Programming in a unit of 256 bytes * * * * Erase method ............................................ Block erase or Total erase * * (Data protection per block is enabled.) Programming/Erase control by software command Maximum number of reprograms ............................................ 100 APPLICATION Control devices for personal computer peripheral equipment such as CD-ROM drives, DVD-ROM drives, hard disk drives, high density FDD, printers Control devices for office equipment such as copiers and facsimiles Control devices for industrial equipment such as communication and measuring instruments P66/DMAREQ3 P65/TA4IN/DMAREQ2 P64/TA4OUT/DMAACK2 P63/TA3IN/DMAREQ1 P62/TA3OUT/DMAACK1 P61/TA1IN/DMAREQ0 P60/TA1OUT/DMAACK0 P57/TA2IN/RTP13 P56/TA2OUT/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P96/WRH/UCAS P95/WRL/LCAS P94/CAS/W P93/CS3/RAS3 P92/CS2/RAS2 P91/CS1/RAS1 P90/CS0 P44/HLDA P43/HOLD P42/TC P41/1 P40/ALE P33/BHW P32/BLW P31/RD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 P101/A1 79 P102/A2 78 P103/A3 77 P104/A4 76 P105/A5 75 P106/A6 74 P107/A7 73 P110/A8/MA0 72 P111/A9/MA1 71 P112/A10/MA2 70 P113/A11/MA3 69 P114/A12/MA4 68 P115/A13/MA5 67 P116/A14/MA6 66 P117/A15/MA7 65 P00/A16/MA8 64 P01/A17 63 P02/A18/MA9 62 P03/A19 61 P04/A20/MA10 60 P05/A21 59 P06/A22/MA11 58 P07/A23 57 VSS 56 MD1 55 P10/D0 54 P11/D1 53 P12/D2 52 P13/D3 51 P14/D4 . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR 2 MI ELI Y NAR P100/A0 81 P86/CLK0 82 P85/RXD0 83 P84/TXD0 84 P83/CTS0/RTS0 85 P82/CTS0/CLK1 86 P81/RXD1 87 P80/TXD1 88 VCC 89 AVCC 90 VREF 91 AVSS 92 VSS 93 P73/AN3/ADTRG/INT4 94 P72/AN2/INT3 95 P71/AN1 96 P70/AN0 97 P122/INT2/TB2IN 98 P121/INT1/TB1IN 99 P120/INT0/TB0IN 100 MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION M37920FxCGP PIN CONFIGURATION (TOP VIEW) M37920FCCGP M37920FGCGP Outline 100P6S-A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P15/D5 P16/D6 P17/D7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET NMI BYTE P30/RDY MI ELI Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8/MA0 P111/A9/MA1 P112/A10/MA2 P113/A11/MA3 P114/A12/MA4 P115/A13/MA5 P116/A14/MA6 P117/A15/MA7 P00/A16/MA8 P01/A17 P02/A18/MA9 P03/A19 P04/A20/MA10 P05/A21 P06/A22/MA11 P07/A23 VSS MD1 P10/D0 P11/D1 P12/D2 M37920FxCHP PIN CONFIGURATION (TOP VIEW) P13/D3 P14/D4 P15/D5 P16/D6 P17/D7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET NMI BYTE P30/RDY P31/RD P32/BLW P33/BHW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M37920FCCHP M37920FGCHP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P64/TA4OUT/DMAACK2 P63/TA3IN/DMAREQ1 P62/TA3OUT/DMAACK1 P61/TA1IN/DMAREQ0 P60/TA1OUT/DMAACK0 P57/TA2IN/RTP13 P56/TA2OUT/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P96/WRH/UCAS P95/WRL/LCAS P94/CAS/W P93/CS3/RAS3 P92/CS2/RAS2 P91/CS1/RAS1 P90/CS0 P44/HLDA P43/HOLD P42/TC P41/1 P40/ALE P103/A3 76 P102/A2 77 P101/A1 78 P100/A0 79 P86/CLK0 80 P85/RXD0 81 P84/TXD0 82 P83/CTS0/RTS0 83 P82/CTS0/CLK1 84 P81/RXD1 85 P80/TXD1 86 VCC 87 AVCC 88 VREF 89 AVSS 90 VSS 91 P73/AN3/ADTRG/INT4 92 P72/AN2/INT3 93 P71/AN1 94 P70/AN0 95 P122/INT2/TB2IN 96 P121/INT1/TB1IN 97 P120/INT0/TB0IN 98 P66/DMAREQ3 99 P65/TA4IN/DMAREQ2 100 Outline 100P6Q-A 3 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Data Bus (Even) Data Bus (Odd) Data Buffer DQ2 (8) Input/Output port P0 P0(8) Data Buffer DQ1 (8) BYTE Address Bus Data Buffer DQ3 (8) P1(8) NMI Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Input/Output port P1 External data bus width select input Data Buffer DQ0 (8) Input/Output port P2 P2(8) DMA1(16) DMA0(16) DMA3(16) Instruction Queue Buffer Q4 (8) DMA2(16) Instruction Queue Buffer Q3 (8) VREF Reference voltage input Instruction Queue Buffer Q2 (8) Program Counter PC (16) Input/Output port P4 Input/Output port P5 Input/Output port P6 P4(5) P3(4) A-D converter (10) UART1(9) MD0 Incrementer/Decrementer (24) UART0(9) MD1 Data Address Register DA (24) Bus Interface Unit (BIU) Incrementer (24) Program Address Register PA (24) P5(8) Instruction Queue Buffer Q9 (8) P6(7) DRAM controoler Instruction Queue Buffer Q8 (8) (0V) AVSS AVcc Instruction register (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Input/Output port P3 Instruction Queue Buffer Q5 (8) Input/Output port P7 Input/Output port P8 P7(4) P8(7) Timer TB1 (16) Timer TB0 (16) Timer TA1 (16) Timer TA0 (16) Timer TB2 (16) Vcc Direct Page Register DPR0 (16) Watchdog timer Processor Status Register PS (11) Timer TA4 (16) Input Buffer Register IB (16) Timer TA2 (16) (0V) Vss Data bank Register DT (8) Timer TA3 (16) Program Bank Register PG (8) 4 Input/Output port P10 P9(7) RAM (Note) RAM 4096 bytes 6144 bytes Flash memory 120 Kbytes 248 Kbytes M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP Note: Arithmetic Logic Unit (16) Input/Output port P11 Accumulator A (16) Input/Output port P12 Accumulator B (16) P10(8) Index Register X (16) P11(8) Clock Generating Circuit Clock output XOUT XIN Clock input BLOCK DIAGRAM Index Register Y (16) P12(3) Stack Pointer S (16) Central Processing Unit (CPU) Direct Page Register DPR3 (16) Flash memory (Note) RESET Reset input Direct Page Register DPR2 (16) Input/Output port P9 Direct Page Register DPR1 (16) MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION FUNCTIONS (Microcomputer mode) Parameter Number of basic machine instructions 203 Instruction execution time 50 ns (the fastest instruction at f(XIN) = 20 MHz) External clock input frequency f(XIN) 20 MHz (Max.) Memory size Flash memory (User ROM area) (Note) RAM (Note) Flash memory (Boot ROM area) 16 Kbytes Programmable input/output P0-P2, P5, P10, P11 8-bit 6 ports P3, P7 4-bit 2 P4 5-bit 1 P6, P8, P9 7-bit 3 P12 3-bit 1 TA0-TA4 16-bit 5 TB0-TB2 16-bit 3 UART0 and UART1 (UART or Clock synchronous serial I/O) 2 Multi-functional timers Serial I/O Functions A-D converter 10-bit successive approximation method 1 (4 channels) Watchdog timer 12-bit 1 DMA controller 4 channels Maximum transfer rate 20 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 1-bus cycle transfer) 10 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 2-bus cycles transfer) DRAM controller 1 channel Incorporates 8-bit refresh timer. Supports CAS before RAS refresh method or self refresh method. Chip-select wait control Chip select area 4 (CS0-CS3). A wait number and bus width can be set for each chip select area. Real-time output 4 bits 2 channels; or 6 bits 1 channel + 2 bits 1 channel Interrupts 6 external types, 20 internal types. Each interrupt except NMI can be set to a priority level within the range of 0-7 by software. Clock generating circuit Built-in (externally connected to a ceramic resonator or quartz crystal resonator). Power supply voltage 5 V0.5 V Power dissipation 125 mW (at f(XIN) = 20 MHz) Ports' input/output characteristics Input/Output withstand voltage Output current Memory expansion Operating ambient temperature range Device structure Package Note: Flash memory (User ROM area) RAM 5V 5 mA Up to 16 Mbytes. Note that bank FF16 is a reserved area. -20 to 85 C CMOS high-performance silicon gate process 100-pin plastic molded QFP M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP 120 Kbytes 248 Kbytes 4096 bytes 6144 bytes 5 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION FUNCTIONS (Flash memory mode) Power supply voltage Parameter Functions 5 V0.5 V (in the flash memory parallel I/O mode, 3.3 V0.3 V) Programming/Erase voltage 5 V0.5 V (in the flash memory parallel I/O mode, 3.3 V0.3 V) Flash memory mode Block division for erasure 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes User ROM area (Note 1) Boot ROM area 1 block (16 Kbytes 1) (Note 2) Programming method Programmed per page (in a unit of 256 Kbytes) Flash memory parallel I/O mode User ROM area + Boot ROM area Flash memory serial I/O mode User ROM area Flash memory CPU reprogramming mode User ROM area Erase method Total erase/Block erase Flash memory parallel I/O mode User ROM area + Boot ROM area Flash memory serial I/O mode User ROM area Flash memory CPU reprogramming mode User ROM area Programming/Erase control Programming/Erase control by software commands Data protection method Protected per block, by using a lock bit. Number of commands 8 commands Maximum number of reprograms 100 Notes 1: User ROM area M37920FCCGP, M37920FCCHP 5 blocks (8 Kbytes 3, 32 Kbytes 1, 64 Kbytes 1), total 120 Kbytes M37920FGCGP, M37920FGCHP 7 blocks (8 Kbytes 3, 32 Kbytes 1, 64 Kbytes 3), total 248 Kbytes 2: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area. Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode. 6 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PIN DESCRIPTION (MICROCOMPUTER MODE) Pin Name Input/ Output -- Functions Apply 5 V0.5 V to Vcc, and 0 V to Vss. Vcc, Vss Power supply input MD0 MD0 Input This pin controls the processor mode. Connect this pin to VSS for the single-chip mode or memory expansion mode, and VCC for the microprocessor mode. MD1 MD1 Input Connect this pin to Vss. RESET Reset input Input The microcomputer is reset when "L" level is applies to this pin. XIN Clock input Input XOUT Clock output These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between the XIN and X OUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. BYTE External data bus width select input AVcc, AVss Analog power supply input VREF Reference voltage input P00-P07 I/O port P0 I/O In single-chip mode Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset. In memory expansion and microprocessor modes Address (A16-A23) is output. In DRAM space is accessed, Multiplexed address (MA8-MA11) is output. P10-P17 I/O port P1 I/O In single-chip mode These pins have the same functions as port P0. In memory expansion and microprocessor modes The low-order 8 bits of data (D0-D7) are input/output. P20-P27 I/O port P2 I/O In single-chip mode or when 8-bit external data bus is used with "H" level applied to pin BYTE in memory expansion or microprocessor mode These pins have the same functions as port P0. When the 16-bit external data bus is used with "L" level applied to pin BYTE in memory expansion or microprocessor mode The high-order 8 bits of data (D8-D15) are input or output. P30-P33 I/O port P3 I/O In single-chip mode These pins have the same functions as port P0. In memory expansion mode P30 functions as an I/O port pin. According to the register setting, this pin funtions as an output pin of RDY. P31, P32, P33 funtion as output pins of RD, BLW, BHW, respectively. In microprocessor mode P30 functions as an input pin of RDY; and P31, P32, P33 function as output pins of RD, BLW, BHW, respectively. P40-P44 I/O port P4 I/O In single-chip mode These pins have the same functions as port P0. P42 also funtions as pin TC. In memory expansion mode P40-P44 function as I/O port pins. According to the register setting, these pins function as output pins or input pins of ALE, 1, TC, HOLD, HLDA, respectively. In microprocessor mode P40 and P41 function as outpout pins of ALE, 1. According to the register setting, these pins also funtion as I/O port pins. P42 funtions as an I/O port pin. According to the register setting, this pin also funtions as pin TC. P43 functions as an input pin of HOLD, and P44 functions as an output pin of HLDA. Output Input This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when "L" signal is input, and 8 bits when "H" signal is input. -- Power supply input pin for the A-D converter. Connect AVcc to Vcc, and AVss to Vss externally. Input This is the reference voltage input pin for the A-D converter. 7 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR Pin Name M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Input/ Output Functions P50-P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0, A2, and output pins for the real-time output. P60-P66 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A1, A3, A4, input pins for DMA requests, and output pins for DMA acknowledge signals. P70-P73 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as input pins for the A-D converter. P72 and P73 also function as input pins for INT3 and INT4. P80-P86 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART0, UART1. P90-P96 I/O port P9 I/O In single-chip mode These pins have the same function as port P0. In memory expansion or microprocessor mode According to the software setting, P90-P93 also funtion as chip select output pins. While DRAM space is selected, P94-P96 function as output pins for DRAM control signals. Some pins of P91-P93, coressponding to the selected DRAM space, function as pins RAS. P100-P107 I/O port P10 I/O In single-chip mode These pins have the same functions as port P0. In memory expansion and microprocessor modes Address (A0-A7) is output. P110-P117 I/O port P11 I/O In single-chip mode These pins have the same functions as port P0. In memory expansion or microprocessor mode Address (A8-A15) is output. While DRAM space is accessed, Multiplexed address (MA0-MA7) is output. P120-P122 I/O port P12 I/O In addition to having the same functions as port P0 in the single-ship mode, these pins also function as input pins for timers B0-B2. NMI Non-maskable interrupt 8 Input This pin is for a non-maskable interrupt. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BASIC FUNCTION BLOCKS These microcomputers contain the following devices on the single chip: the flash memory, RAM, CPU, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial I/O, A-D converter, I/O ports, clock generating circuit, etc. MEMORY Figures 1 and 2 show the memory maps. The address space is 16 Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered from 016 to FF16. Bank FF16 is a reserved area for the development support tool. Therefore, do not use bank FF16. 00000016 00000016 0000FF16 Bank 016 00FFFF16 01000016 Internal flash memory and internal RAM are assigned as shown in Figures 1 and 2. Addresses FFC016 to FFFF16 contain the RESET and the interrupt vector addresses, and the interrupt vectors are stored there. For details, refer to the section on interrupts. Assigned to addresses 016 to FF16 are peripheral devices such as I/O ports, A-D converter, UART, timers, interrupt control registers, DMA controoler, DRAM controller, etc. For the flash memory in the boot ROM area, refer to the section on the flash memory mode. Peripheral devices control registers Interrupt vector table 00FFC016 00080016 Bank 116 01FFFF16 Internal RAM 4096 bytes * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0017FF16 00180016 Address matching detect 001FFF16 00200016 INT4 INT3 A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Reserved area Reserved area 00FFC016 00FFFF16 Internal flash memory 120 Kbytes (User ROM area) INT2 INT1 INT0 NMI Watchdog timer FE000016 ;; ;; ;; Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 DMA3 DMA2 DMA1 DMA0 Reserved area Reserved area for development support tool 00FFFE16 DBC BRK instruction Zero divide RESET Fig. 1 Memory map of M37920FCCGP and M37920FCCHP (Single-chip mode) 9 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 00000016 00000016 0000FF16 Bank 016 00FFFF16 01000016 Peripheral devices control registers Interrupt vector table 00FFC016 00080016 Bank 116 01FFFF16 02000016 Internal RAM 6144 bytes Bank 216 02FFFF16 03000016 Address matching detect Reserved area Reserved area Bank 316 INT4 INT3 A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 001FFF16 00200016 03FFFF16 * * * * * * * * * * * * * * * * * * * * * * * 00FFC016 00FFFF16 Internal flash memory 248 Kbytes (User ROM area) INT2 INT1 INT0 NMI Watchdog timer FE000016 ;; ;; ;; Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 Reserved area for development support tool Fig. 2 Memory map of M37920FGCGP and M37920FGCHP (Single-chip mode) 10 DMA3 DMA2 DMA1 DMA0 Reserved area 00FFFE16 DBC BRK instruction Zero divide RESET MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address (Hexadecimal notation) Address (Hexadecimal notation) 00000016 Reserved area (Note) 00000116 Reserved area (Note) 00000216 Port P0 register 00000316 Port P1 register 00000416 Port P0 direction register 00000516 Port P1 direction register 00000616 Port P2 register 00000716 Port P3 register 00000816 Port P2 direction register 00000916 Port P3 direction register 00000A16 Port P4 register 00000B16 Port P5 register 00000C16 Port P4 direction register 00000D16 Port P5 direction register 00000E16 Port P6 register 00000F16 Port P7 register 00001016 Port P6 direction register 00001116 Port P7 direction register 00001216 Port P8 register 00001316 Port P9 register 00001416 Port P8 direction register 00001516 Port P9 direction register 00001616 Port P10 register 00001716 Port P11 register 00001816 Port P10 direction register 00001916 Port P11 direction register 00001A16 Port P12 register 00001B16 00001C16 Port P12 direction register 00001D16 00001E16 A-D control register 0 00001F16 A-D control register 1 00002016 A-D register 0 00002116 00002216 A-D register 1 00002316 00002416 A-D register 2 00002516 00002616 A-D register 3 00002716 00002816 00002916 00002A16 00002B16 00002C16 00002D16 00002E16 00002F16 00003016 UART0 transmit/receive mode register 00003116 UART0 baud rate register (BRG0) 00003216 UART0 transmit buffer register 00003316 00003416 UART0 transmit/receive control register 0 00003516 UART0 transmit/receive control register 1 00003616 UART0 receive buffer register 00003716 00003816 UART1 transmit/receive mode register 00003916 UART1 baud rate register (BRG1) 00003A16 UART1 transmit buffer register 00003B16 00003C16 UART1 transmit/receive control register 0 00003D16 UART1 transmit/receive control register 1 00003E16 UART1 receive buffer register 00003F16 00004016 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C16 00004D16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C16 00005D16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C16 00006D16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C16 00007D16 00007E16 00007F16 Count start register One-shot start register Up-down register Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Particular function select register 2 Reserved area (Note) Debug control register 0 Debug control register 1 Address comparison register 0 Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Note: Do not write to this address. Fig. 4 Location of SFRs (1) 11 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address (Hexadecimal notation) 00008016 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C16 00008D16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C16 00009D16 00009E16 00009F16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA16 0000AB16 0000AC16 0000AD16 0000AE16 0000AF16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA16 0000BB16 0000BC16 0000BD16 0000BE16 0000BF16 CS0 control register L CS0 control register H CS1 control register L CS1 control register H CS2 control register L CS2 control register H CS3 control register L CS3 control register H Area CS0 start address register Area CS1 start address register Area CS2 start address register Area CS3 start address register Reserved area (Note) Reserved area (Note) Flash memory control register Real-time output control register Pulse output data register 0 Pulse output data register 1 Reserved area (Note) DRAM control register Refresh timer CTS/RTS separate select register DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Note: Do not write to this address. Fig. 5 Location of SFRs (2) 12 Address (Hexadecimal notation) 0000C016 0000C116 0000C216 0000C316 0000C416 0000C516 0000C616 0000C716 0000C816 0000C916 0000CA16 0000CB16 0000CC16 0000CD16 0000CE16 0000CF16 0000D016 0000D116 0000D216 0000D316 0000D416 0000D516 0000D616 0000D716 0000D816 0000D916 0000DA16 0000DB16 0000DC16 0000DD16 0000DE16 0000DF16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA16 0000EB16 0000EC16 0000ED16 0000EE16 0000EF16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA16 0000FB16 0000FC16 0000FD16 0000FE16 0000FF16 Source address register 0 L Source address register 0 M Source address register 0 H Destination address register 0 L Destination address register 0 M Destination address register 0 H Transfer counter register 0 L Transfer counter register 0 M Transfer counter register 0 H DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 L Source address register 1 M Source address register 1 H Destination address register 1 L Destination address register 1 M Destination address register 1 H Transfer counter register 1 L Transfer counter register 1 M Transfer counter register 1 H DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 L Source address register 2 M Source address register 2 H Destination address register 2 L Destination address register 2 M Destination address register 2 H Transfer counter register 2 L Transfer counter register 2 M Transfer counter register 2 H DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 L Source address register 3 M Source address register 3 H Destination address register 3 L Destination address register 3 M Destination address register 3 H Transfer counter register 3 L Transfer counter register 3 M Transfer counter register 3 H DMA3 mode register L DMA3 mode register H DMA3 control register MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CENTRAL PROCESSING UNIT (CPU) INDEX REGISTER X (X) The CPU has 13 registers, and they are shown in Figure 6. Each of these registers is described below. Index register X consists of 16 bits and the low-order 8 bits can be used separately. Index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register X is used as the index register, the contents of this address are added to obtain the real address. Index register X functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate). ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. Data length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is "0" and as an 8-bit register when flag m is "1". Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator A. INDEX REGISTER Y (Y) ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A. ACCUMULATOR E Accumulator E is a 32-bit register and consists of accumulator A (low-order 16 bits) and accumulator B (high-order 16 bits). It is used for 32-bit data processing. Accumulator B 15 Accumulator A 7 BH Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register Y is used as the index register, the contents of this address are added to obtain the real address. Index register Y functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate). 0 15 BL 7 AH 0 AL 31 0 Accumulator E 15 7 AH 15 0 AL 7 BH 15 0 BL 0 7 XH 15 Index register X XL 7 0 Index register Y YL YH 15 7 0 PG 7 Stack pointer S S Program bank register PG 15 0 Program counter PC PC 0 DT 0 Data bank register DT 15 15 0 0 0 0 0 0 DPR0 to DPR3 7 IPL2 IPL1 IPL0 N V m x D I Direct page registers DPR0 to DPR3 0 Z C Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL Fig. 6 Register structure 13 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION STACK POINTER (S) PROCESSOR STATUS REGISTER (PS) Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode. Processor status register (PS) is an 11-bit register. It consists of flags to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V, and N. The details of each bit of the processor status register are described below. PROGRAM COUNTER (PC) Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through bus interface unit. This is described later. PROGRAM BANK REGISTER (PG) Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is increased by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. DATA BANK REGISTER (DT) Data bank register (DT) is an 8-bit register. With some addressing modes, the data bank register (DT) is used to specify a part of the memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y. DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3) The direct page register is a 16-bit register. An addressing mode of which name includes `direct' generates an address of data to be accessed, regarding the contents of this register as the base address. The 7900 Series has been expanded direct page registers up to 4 (DPR0 to DPR3), in comparison to the 7700 Series which has the single direct page register. Accordingly, the 7900 Series's direct addressing method which uses direct page registers differs from that of the 7700 Series. However, the conventional direct addressing method, using only DPR0, is still be selectable, in order to make use of the 7700 Series software property. For more details, refer to the section on the direct page. 14 1. Carry flag (C) The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions. 2. Zero flag (Z) The zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions. 3. Interrupt disable flag (I) When the interrupt disable flag is set to "1", all interrupts except ___ watchdog timer, NMI, and software interrupt are disabled. This flag is set to "1" automatically when an interrupt is accepted. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions. 4. Decimal mode flag (D) The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is "0". If it is "1", decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. Arithmetic operation is performed using four digits when data length flag m is "0" and with two digits when it is "1". Decimal adjust is automatically performed. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions. MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 5. Index register length flag (x) The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is "0" and as 8bit registers when it is "1". This flag can be set and reset with the SEP and CLP instructions. 6. Data length flag (m) The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16 bits when flag m is "0" and 8 bits when it is "1". This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions. 7. Overflow flag (V) The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. If data length flag m is "0", the overflow flag is set when the result of addition or subtraction is outside the range between -32768 and +32767. If data length flag m is "1", the overflow flag is set when the result of addition or subtraction is outside the range between -128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP instructions. Additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of -2147483648 to +2147483647 in the RMPA operation. 8. Negative flag (N) The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag m is "0", data's bit 15 is "1". If data length flag m is "1", data's bit 7 is "1".) It is reset in all other cases. It can also be set and reset with the SEP and CLP instructions. 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than the processor interrupt priority. When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. Note: Fix bits 11 to 15 of the processor status register (PS) to "0". 15 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BANK In order to effectively use the integrated hardware on the chip, this CPU core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. In other words, the 64 Kbytes specified by the low-order 16 bits are one unit (referred to as "bank"), and the address space is divided into 256 banks (016 to FF16) specified by the high-order 8 bits. In the program area on the address space, the bank is specified by the program bank register (PG), and the address in the bank is specified by the program counter (PC). As for each bank boundary, when an overflow has occurred in PC, the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the normal conditions, therefore, programming without concern for the bank boundaries is possible. Furthermore, as for the data area on the address space, the bank is specified by the data bank register (DT), and the address in the bank is specified by the operation result by using the various addressing modes (Note). Note: Some addressing modes directly specify a bank. DIRECT PAGE The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The direct page and direct addressing modes have been provided for the effective access to bank 016. In the 7900 Series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected according to the contents of bit 1 of the processor mode register 1. This bit 1 is cleared to "0" at reset. (In other words, the conventional direct addressing mode is selected.) However, once this bit 1 has been set to "1" by software, this bit cannot be cleared to "0" again, except by reset. That is to say, when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is running. Conventional direct addressing mode The direct page area consists of 256-byte space. Its bank address is "0016", and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area. Expanded direct addressing mode The direct page area consists of four 64-byte spaces. Their bank address is "0016", and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct page registers. In this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows: * High-order 2 bits: regarded as a selection field for DPR0 to DPR3. * Low-order 6 bits: regarded as an offset value for the selected direct page register. Then, the CPU accesses each address in each direct page area: 16 Refer to "7900 Series Software Manual" for details concerning the various addressing modes which use the direct page area. Instruction Set The CPU core of the 7900 Series has an expanded instruction set based on the existing 7700/7751 Series' CPU core. In addition, its source code (mnemonic) has the complete upper compatibility with the 7700 Series instruction set. For details concerning addressing modes and instruction set, refer to "7900 Series Software Manual". MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BUS INTERFACE UNIT Data transfer shown below is always performed via the bus interface unit (BIU), which is located between the CPU and the internal buses: * Between the CPU and the internal memory, internal peripheral devices, external areas * Between the DMA controller (DMAC) and the internal memory, internal peripheral devices, external areas Figure 7 shows the BIU and the bus structure. The CPU and BIU, or DMAC and BIU are connected by a dedicated bus respectivery, and any transfer between the CPU and BIU, or DMAC and BIU is controlled by this dedicated bus. On the other hand, data transfer between the BIU and internal peripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/ data bus method) is employed in order to improve data transfer ca- pabilities. As a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus. Each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. The external data bus transfers instruction codes and data. When the code or data access occurs for the external, the external access is performed via the bus conversion circuit. When the DRAM is selected in external devices, the internal DMAC controller (DRAMC) is operated, and access for DRAM and DRAM refresh operation become enabled. For details, refer to the section on the chip select wait controller and DRAMC described later. When accessing the external devices, it is possible to insert the recovery cycles. Refer to the section on the processor modes and chip select wait controller described later. When the burst ROM is used as an external device, refer to the section on the chip select wait controller described later. Internal bus CPU bus Bus Interface Unit Central Processing Unit (CPU) DMA controller Internal code bus (CB0 to CB31) (BIU) Internal data bus (DB0 to DB15) Internal address bus (AD0 to AD23) Internal memory Internal control signal Internal peripheral devices DMAC bus (SFR) (DMAC) External bus Refresh request DRAM controller DRAM control signal (DRAMC) A0 to A23 (MA0 to MA11) Bus conversion circuit D0 to D7 External devices D8 to D15 Control signal Hold request HOLD HLDA SFR : Special Function Register The CPU bus, DMAC bus, internal bus, and external bus separate out independently. Fig. 7 BIU and bus structure 17 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BIU structure The BIU consists of four registers shown in Figure 8. Table 1 lists the functions of each register. Table 1. Functions of each register Name Program address register Functions Indicates a storage address for an instruction to be next taken into an instruction queue buffer. Instruction queue buffer Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes. Data address register Indicates an address where data will be next read from or written to. Data buffer Temporarily stores data which has been read from internal memory, internal peripheral devices, and external areas by the BIU; or temporarily stores data which is to be written to internal memory, internal peripheral devices, and external areas by the CPU or DMAC. Consists of 32 bits. b23 b0 Program address register PA b7 b0 Q0 Instruction queue buffer Q9 b23 b0 Data address register DA b31 b0 DQ Fig. 8 Register structure of BIU 18 Data buffer MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BIU Functions (1) Instruction prefetch The BIU has ten instruction queue buffers; each buffer consists of 1 byte. When there is an opening in the bus and the instruction queue buffer, an instruction code is read from the program memory (in other words, the memory where a program is stored) and prefetched into an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the CPU, via a dedicated bus. When a branch occurs as a result of a branch instruction (JMP, BRA, etc.), subroutine call, or interrupt, the contents of the instruction queue buffer are initialized and the BIU reads a new instruction from the branch destination address. Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses for instructions to be prefetched are categorized as listed in Table 2. (2) Data read operation When executing an instruction for reading data from the internal memory, internal peripheral devices, or external areas, at first, the CPU informs the BIU's data address register of the address where the data has been located. Next, the BIU reads the above data from the specified address, passes it to the data buffer, and then, transfers it to the CPU. (3) Data write operation When executing an instruction for writing data into the internal memory, internal peripheral devices, or external area, at first, the CPU informs the BIU's data address register of the address where the data has been located. Next, the BIU passes the above data to the data buffer register, and then, writes it into the specified address. (4) Bus cycle In order for the BIU to execute the above operations (1) through (3), the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal control signals must be appropriately controlled during data transfer between the BIU and internal memory, internal peripheral devices, external areas. This operation is called "bus cycle". The bus cycle is affected by the following conditions at instruction prefetch and data access. [Instruction prefetch] * Whether the address area locates in the internal area or the external area. * When the address area locates in the external area Whether the bus width of external devices = 16 bits or 8 bits: (a) When the external bus width = 16 bits: whether the start address for access locates at a 4byte boundary or at an 8-byte boundary. (b) When the external bus width = 8 bits: whether the start address for access locates at an even-numbered address, a 4-byte boundary or at the 8byte bound ary. Whether the prefetch operation is generated by a branch, or not. Number of waits Others: Whether any the burst ROM access and the DRAM space is specified or not. (For details, refer to the section on the chip select wait controller and DRAM controller described later.) Table 2. Store addresses for instructions to be prefetched Low-order 3 bits of store address for instruction AD2 (A2) AD0 (A0) AD1 (A1) X 0 X Even-numbered address X 0 4-byte boundary 0 8-byte boundary 0 0 0 X: 0 or 1 [Data Access] * Whether the address area locates in the internal area or the external area. * Length of data to be transferred: byte, word, double word * When the address area locates in the external area: Whether the bus width of external devices = 16 bits or 8 bits: Number of waits Others: Whether the DRAM space is specified or not. (For details, refer to the section on the chip select wait controller and DRAM controller described later.) The BIU controls the bus cycle depending on the above conditions. Instruction prefetch and data access are performed as shown in Tables 3 to 10. 19 20 Internal code bus CB31 to CB0 Internal address bus BIU Internal RAM Code When branched or at instruction prefetch 1 D7 to D0 BHW 1 D15 to D8 D15 to D8 D7 to D0 Address + 6 1 D7 to D0 A23 to A0 RD BLW BHW RD BLW BHW ALE D15 to D8 D15 to D8 D15 to D8 D7 to D0 Address + 4 ALE D7 to D0 Address + 2 D7 to D0 Address D7 to D0 A23 to A0 D7 to D0 Address D7 to D0 Address + 1 D7 to D0 Address D7 to D0 Address + 1 D7 to D0 Address + 2 D7 to D0 Address + 3 When address of instruction to be prefetched locates at 4-byte boundary or 8-byte boundary: quadruple consecutive access BHW BLW When address of instruction to be prefetched locates at 8-byte boundary: quadruple consecutive access RD BLW RD ALE D15 to D8 D15 to D8 D15 to D8 1 A23 to A0 ALE D7 to D0 Address + 2 D7 to D0 Address D7 to D0 A23 to A0 When external data bus width = 8 bits When address is even-numbered address or when branched: double consecutive access Access to external area When address locates at 4-byte boundary or when branched: double consecutive access When external data bus width = 16 bits PR Access to internal area Table 3. Instruction prefetch . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 4. Data access (1) Access starting from even-numbered address 1 A23 to A0 Byte data read 1 Address D7 to D0 D7 to D0 Invalid Invalid D15 to D8 D15 to D8 ALE ALE RD RD BLW BLW BHW BHW External data bus width = 16 bits D7 to D0 1 Address D7 to D0 A23 to A0 D15 to D8 ALE ALE RD RD BLW BLW BHW BHW 1 Address D7 to D0 D15 to D8 A23 to A0 D15 to D8 1 Address A23 to A0 Address Address + 1 D7 to D0 D7 to D0 D7 to D0 Invalid D7 to D0 D15 to D8 D15 to D8 D15 to D8 D15 to D8 Invalid ALE ALE RD RD BLW BLW BHW BHW 1 A23 to A0 Word data written Address D7 to D0 1 Word data read A23 to A0 D15 to D8 A23 to A0 Byte data written Access starting from odd-numbered address 1 Address A23 to A0 D7 to D0 D7 to D0 D7 to D0 D15 to D8 D15 to D8 D15 to D8 ALE ALE RD RD BLW BLW BHW BHW Address Address + 1 D7 to D0 D15 to D8 21 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 5. Data access (2) Access starting from even-numbered address 1 External data bus width = 16 bits A23 to A0 22 Double word data read 1 Address Address + 1 A23 to A0 Address Address + 1 Address + 2 D7 to D0 D7 to D0 D7 to D0 D7 to D0 Invalid D7 to D0 D7 to D0 D15 to D8 D15 to D8 D15 to D8 D15 to D8 D15 to D8 D15 to D8 Invalid ALE ALE RD RD BLW BLW BHW BHW 1 A23 to A0 Double word data written Access starting from odd-numbered address 1 Address Address + 1 A23 to A0 D7 to D0 D7 to D0 D7 to D0 D7 to D0 D15 to D8 D15 to D8 D15 to D8 D15 to D8 ALE ALE RD RD BLW BLW BHW BHW Address Address + 1 D7 to D0 D15 to D8 D15 to D8 Address + 2 D7 to D0 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 6. Data access (3) Access starting from even- or odd-numbered address 1 A23 to A0 D7 to D0 Byte data read Address D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) 1 A23 to A0 External data bus width = 8 bits D7 to D0 Byte data written Address D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) 1 A23 to A0 D7 to D0 Word data read Address D7 to D0 Address + 1 D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) 1 A23 to A0 D7 to D0 Word data written Address D7 to D0 Address + 1 D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) Note: When the voltage level at pin BYTE = "L", functions as pins D15 to D8 are valid. However, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins D15 to D8 and BHW become invalid. When the voltage level at pin BYTE = "H", these pins function as programmable I/O port (P2) pins. 23 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 7. Data access (4) Access starting from even- or odd-numbered address 1 External data bus width = 8 bits A23 to A0 Double word data read D7 to D0 Address D7 to D0 Address + 1 D7 to D0 Address + 2 D7 to D0 Address + 3 D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) 1 A23 to A0 Double word data written D7 to D0 Address D7 to D0 Address + 1 D7 to D0 Address + 2 D7 to D0 Address + 3 D7 to D0 D15 to D8 (Note) ALE RD BLW BHW (Note) Note: When the voltage level at pin BYTE = "L", functions as pins D15 to D8 are valid. However, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins D15 to D8 and BHW become invalid. When the voltage level at pin BYTE = "H", these pins function as programmable I/O port (P2) pins. 24 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 8. Wait number (Instruction prefetch or data access) Access to internal area Access to external area 0-wait access BIU 1 Internal address bus Internal code bus CB31 to CB0 A23 to A0 Code External data bus Data ALE BIU RD, BLW, BHW Internal address bus Internal data bus DB15 to DB0 Data 1-wait access 1 A23 to A0 External data bus Data ALE RD, BLW, BHW 2-wait access 1 A23 to A0 External data bus Data ALE RD, BLW, BHW ALE expansion wait access 1 A23 to A0 External data bus Data ALE RD, BLW, BHW 25 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION At double consecutive access (when address locates at 4-byte boundary or when branched) Instruction prefetch Recovery cycle Next access cycle 1 Address A23 to A0 Address + 2 Address ALE RD At quadruple consecutive access (when address locates at 8-byte boundary) Instruction prefetch Next access cycle 1 Address A23 to A0 Address + 2 Address + 4 ALE RD Note: External data bus width = 16 bits and at 0 wait. Fig. 9 Recovery cycle (at instruction prefetch) Access cycle Recovery cycle Next access cycle 1 A23 to A0 Address ALE RD, BLW, BHW Note: At 0 wait. Fig. 10 Recovery cycle (at data access) 26 Address + 6 Address MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Selection of processor mode Figures 11, 12 show the bit configurations of the processor mode registers 0, 1. Any of the three processor modes (single-chip mode, memory expansion mode, microprocessor mode) can be selected with the following: * Processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5E16; Figure 11) Table 9 lists the selection method of a processor mode. The memory map which the CPU can access depends on the selected processor mode. Figure 13 shows the memory maps in three processor modes. Also, the functions of ports P0 to P4, P10, P11, and part of port P9 depend on the selected processor mode. For details, see Table 10. In the single-chip mode, ports P0 to P4, P10, P11, and P9 function as I/O ports. In this mode, only the internal area (SFRs, internal 7 6 5 4 3 2 1 RAM, internal ROM) is accessible. In the memory expansion and microprocessor modes, external devices assigned in the external memory area can be connected via buses. Therefore, ports P0 to P4, P10, P11, and part of port P9 function as I/O pins for the address bus, data bus, bus control signals. (Some of port functions are selectable.) In the memory expansion mode, all of the internal area (SFRs, internal RAM, internal ROM) and external area are accessible. In the microprocessor mode, the internal area except for the internal ROM (in other words, SFRs and internal RAM) and the external area are accessible. Note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written. Table 11 lists each bus control signal's function. 0 Processor mode register 0 Address 5E16 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. Software reset bit By a write of "1" to this bit, the microcomputer will be reset, and then, restarted. Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as an programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as the clock 1 output pin.) Fig. 11 Bit configuration of processor mode register 0 27 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR 7 6 5 4 3 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 2 1 0 0 Processor mode register 1 Address 5F16 Fix this bit to "0". Direct page register switch bit (Note 1) 0 : Only DPR0 is used. 1 : DPR0 to DPR3 are used. RDY input select bit (Notes 2 to 4) 0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.) 1 : RDY input is enabled. (P30 functions as pin RDY.) ALE output select bit (Notes 2 and 3) 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) Recovery cycle insert select bit (Notes 2 and 3) 0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area. HOLD input, HLDA output select bit (Notes 2 to 4) 0 : HOLD input and HLDA output are disabled. (P43 and P44 function as programmable I/O port pins.) 1 : HOLD input and HLDA output are enabled. (P43 and P44 function as pins HOLD and HLDA, respectively.) "0" at read. Internal ROM access wait bit (Note 5) 0 : 1 wait 1 : 0 wait Notes 1: After reset, this bit's contents can be switched only once. During the software execution, be sure not to switch this bit's contents. 2: In the single-chip mode, these bits' functions are disabled regardless of these bits' contents. 3: While VSS level voltage is applied to pin MD0, each of these bits is "0" at reset. While VCC level voltage is applied to pin MD0, on the other hand, each of these bits is "1" at reset. 4: In the memory expansion or microprocessor mode, if this bit's contents is switched from "1" to "0", this bit will be cleared to "0". After this clearance, this bit cannot return to "1". If it is necessary to set this bit to "1", be sure to reset the microcomputer. 5: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to "0". Fig. 12 Bit configuration of processor mode register 1 Table 9. Selection method of processor mode MD0 Mode Description VSS * Single-chip mode * Memory expansion mode * Microprocessor mode After reset is removed, the single-chip mode is selected. By changing the processor mode bits' contents by software, the single-chip mode, memory expansion mode or microprocessor mode can be selected. After reset is removed, the microprocessor mode is selected. * Microprocessor mode VCC Single-chip mode Memory expansion mode Microprocessor mode SFR SFR SFR RAM RAM 016 FF16 Unused area RAM Unused area ROM ROM FEFFFF16 FF000016 Reserved area (Note) FFFFFF16 Reserved area (Note) : External memory area. Note: Do not access this area. Fig. 13 Memory maps in three processor modes 28 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Memory area Table 10. Relationship between processor modes, memory area, and port function Memory expansion mode Single-chip mode VSS level voltage is applied VSS level voltage is applied Pin MD0 Mode (Note 1) Processor mode 01 00 bits (Note 2) SFR area SFR area SFR area Internal RAM area Internal RAM area Internal RAM area Internal ROM area Internal ROM area Internal ROM area (Do not access.) External memory area Other area I/O port pins P100 to P107 Low-order address (A0 to A7) is output. Port pins P100 to P107 I/O port pins P110 to P117 Middle-order address (A8 to A15) is output. Port pins P110 to P117 Multiplexed address (MA0 to MA7) is output (Note 3) I/O port pins P0 0 to P0 7 High-order address (A16 to A23) is output. Port pins P00 to P07 Multiplexed address (MA8 to MA11) is output (Note 3) External data bus I/O port pins P10 to P17 Low-order data (D 0 to D7, data at evennumbered address) is input/output. Port pins width = 16 bits P10 to P17 External data bus Low-order data (D 0 to D7, data at even-/ odd-numbered address) is input/output. width = 8 bits Low-order data (D0 to D7, data at odd-numExternal data bus I/O port pins P20 to P27 bered address) is input/output. Port pins width = 16 bits I/O port pins P20 to P27 P20 to P27 External data bus width = 8 bits Port pin P30 I/O port pin P30 Port pin P31 I/O port pin P31 External data bus I/O port pin P32 Port pin width = 16 bits P32 External data bus width = 8 bits External data bus I/O port pin P33 Port pin width = 16 bits P33 External data bus width = 8 bits I/O port pin P40 Port pin P40 Port pin P41 Port pin P42 Port pin P43 Port pin P90 Port pins P91 to P93 I/O port pin P41 Clock 1 is output (Note 4). I/O port pin P42 I/O port pin P43 I/O port pin P90 I/O port pins P91 to P93 Microprocessor mode VCC level voltage is applied 10 SFR area Internal RAM area External memory area External memory area Low-order address (A0 to A7) is output. Middle-order address (A8 to A15) is output. Multiplexed address (MA 0 to MA7) is output (Note 3) High-order address (A16 to A23) is output. Multiplexed address (MA8 to MA11) is output (Note 3) Low-order data (D0 to D7, data at evennumbered address) is input/output. Low-order data (D0 to D7, data at even-/ odd-numbered address) is input/output. Low-order data (D0 to D7, data at oddnumbered address) is input/output. I/O port pins P20 to P27 I/O port pin P30 Ready signal RDY is input (Note 5). Read signal RD is output. Write signal BLW (write to even-numbered address) is output. Write signal BLW (write to even-/odd-numbered address) is output. Write signal BHW (write to odd-numbered address) is output. I/O port pin P33 Ready signal RDY is input. I/O port pin P30 (Note 5) Read signal RD is output Write signal BLW (write to even-numbered address) is output. Write signal BLW (write to even-/oddnumbered address) is output. Write signal BHW (write to odd-numbered address) is output. I/O port pin P33 I/O port pin P40 Address latch enable signal ALE is output (Note 4). I/O port pin P41 Clock 1 is output (Note 4). I/O port pin P42 Hold acknowledge signa HLDA is output (Note 4). I/O port pin P43 Hold request signal HOLD is input (Note 4). I/O port pin P90 Chip select signal CS0 is output (Note 5). I/O port pins P91 to P93 Chip select signals CS1 to CS3 are output (Note 6). Address latch enable signal ALE is output. I/O port pin P40 (Note 4) Clock 1 is output. I/O port pin P41 (Note 4) Hold acknowledge signal HLDA is output. I/O port pin P42 (Note 4) Hold request signal HOLD is input. I/O port pin P43 (Note 4) Chip select signal CS0 is output. I/O port pin P91 to P93 Chip select signals CS1 to CS3 are output (Note 6). Notes 1: For details of the processor mode setting, see Table 9. 2: Processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5E16). 3: While DRAM space is accessed, the multiplexed address is output. 4: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E16, 5F16), port pins P30, P40 to P43 can operate as pins for RDY input, ALE output, 1 output, HLDA output, HOLD input, respectively. In the microprocessor mode, by the above select bits, the above pins (RDY, ALE, 1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respectively. 5: In the memory expansion mode, port pin P90 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address 8016). 6: In the memory expansion and microprocessor modes, port pins P91 to P93 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i = 1 to 3) (bit 7s at addresses 8216, 8416, 8616). 29 MI ELI Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 11. Each bus control signal's function Signal I/O Function RD Output Read signal. Outputs "L" at read from the external area. Remarks BLW BHW ALE Output Write signal. Outputs "L" at write to the external area. 1 Output Internal standard clock's output. Outputs system clock (fsys). Input Ready signal. The "L" level period of the last 1 in the access cycle for the external area (in other words, "L" level period of RD, BLW, BHW) will be extended while "L" level voltage is applied to this pin. Input Hold request signal. Appliance of "L" level voltage will gen- Acceptance and termination of a hold request is performed erate a hold request; appliance of "H" level voltage will re- at completion of the bus cycle while the BIU operates. quest to terminate the hold state. In the hold state, A0-A23, D0-D15, RD, BLW, BHW, ALE, Output Hold acknowledge signal. Outputs "L" in the hold state. CS0-CS3 enter the floating state. At termination of the hold state, simultaneously with the timing when HLDA becomes "H" level, the above floating state is terminated. Then, bus access will be restarted 1 cycle of 1 after. In the hold state, also, the CPU operates with access to the internal area. If the CPU accesses the external area, in the hold state, the CPU stops its operation. Output Chip select signal. Outputs "L" in access to the specified For details, refer to the section on the chip select wait conchip select area. troller. Input Input signal to select the external data bus width. When When BYTE = Vss level, by the register setting, each chip this pin's level = Vss, 16-bit width will be selected; and select area (CS1 to CS3) can have the 8-bit data bus, indewhen Vcc, 8-bit width will be selected. pendently. For details, refer to the section on the chip select wait controller. RDY HOLD HDLA CS0-CS3 BYTE 30 Output Address latch enable signal. Outputs "H" level pulse in the period just before signals RD, BLW, BHW become "L". This is used to latch an address in the external. For operation differences between BLW and BHW depending on the external data bus width, see Table 5. In order to latch an address with signal ALE, do as follows: * While ALE = "H", be sure to open a latch, so the address will pass it. * While ALE = "L", be sure to hold the address. MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Chip select wait controller Burst ROM access By the control of the chip select wait controller (CSWC), the chip select function for the maximum of 4 blocks can be set at the bus access to the external area. Also, by the setting of the CSWC, port pins P90 to P93 can operate as chip select output pins (CS0 to CS3). Figure 14 shows a chip select output waveform example. This chip select function determines the following items of the chip select area: start address, address's block size, wait number, external data bus width, RDY control validity, DRAM specification, burst ROM specification, and recovery cycle insertion validity. For the external area except for areas CS0 to CS3, the processor mode registers 0, 1 determine the above items. After reset is removed, when the microcomputer starts it's operation in the microprocessor mode, area CS0 is automatically selected. Table 12 lists the function of areas CS0 to CS3. Figure 15 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Ls. These registers determine the following items of a device to be connected: wait number, external data bus width (Note 1: The external data bus width of area CS0 is determined by pin BYTE's level.), RDY control validity, DRAM space specification (Note 2: For area CS0, this function is invalid.), burst ROM access specification, recovery cycle insertion validity. For DRAM access, refer to the section on the DRAM controller. Figure 16 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Hs. These registers determine block size of an external area to be connected. For areas CS1 and CS2, by selecting mode 1 with the area CSk setting mode select bit, an chip select area can be set to the external area in bank 0. Figure 17 shows the bit configuration of the area CS0/CS1/CS2/CS3 start address registers. For details of these addresses' setting, see Figures 18 to 20. For ROM supporting the burst ROM access, the burst ROM access can be specified. The burst ROM access is valid only when the external data bus width = 16 bits with an instruction prefetched. In the other cases, the normal access is performed regardless of the contents of the burst ROM access select bit. Figure 21 shows a waveform example at burst ROM access. When an instruction is prefetched from the burst ROM, 8 bytes are fetched starting from an 8-byte boundary (the low-order 3 bits of address, A2, A1, A0 = "000") in waveform (a). When branched, regardless of the 8-byte boundary of the branch destination address, access starting from the 4-byte boundary (the low-order 2 bits of address, A1, A0 = "00") is performed in waveform (b). Once the 8-byte boundary has been selected, instructions will be prefetched in waveform (a) until a branch. When area CSi is accessed One access cycle 1 A23 to A0 Address CSi ALE RD, BLW, BHW When the same area CSi is accessed sequentially One access cycle One access cycle Address Address + 2 1 A23 to A0 CSi ALE RD, BLW, BHW Fig. 14 Chip select output waveform example 31 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 12. Function of areas CS0 to CS3 CS0 Space where start address can be set Block size Wait External data bus width RDY control DRAM space specification Burst ROM access (Note 1) Recovery cycle insertion Bank 016 CS1, CS2 Mode 0 Banks 016 to FE16 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes Mode 1 Bank 016 Banks 216 to FE16 4 Kbytes 128 Kbytes, 128 Kbytes, or 8 Kbytes 512 Kbytes, 256 Kbytes, or 1 Mbytes 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes 0 wait, 0 wait, 0 wait, 1 wait, 1 wait, 1 wait, 2 wait, 2 wait, 2 wait, or ALE expansion wait or ALE expansion wait or ALE expansion (Selected by bits 0, 1 at address (Selected by bits 0, 1 at addresses wait 8016.) 8216, 8416.) (Selected by bits 0, 1 at address 8616.) Determined by pin BYTE's level. When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 2). Valid (When DRAM space is Valid (Selected by bit 2 at Valid (When DRAM specified, however, this control is address 5F16 and bit 3 at space is specified, invalid.) address 8016.) however, this (Selected by bit 2 at address 5F16 control is invalid.) and bit 3 at addresses 8216, 8416.) (Selected by bit 2 at address 5F16 and bit 3 at address 8616.) Available. Not available. Available. Available. Available. Available. Available. Available. Notes 1: Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch. 2: When BYTE = Vcc level, the external data bus width is fixed to 8 bits. 32 CS3 Available. External area except for CS0 to CS3 0 wait, 1 wait, 2 wait, or ALE expansion wait (Selected by bits 0, 1 at address 5E16.) Determined by pin BYTE's level Valid (Selected by bit 2 at address 5F16.) Not available. Not available. Available. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR 7 6 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 4 3 2 1 0 CS0 control register L Address 8016 Area CS0 wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait (Note 1) External data bus width select bit 0 : 16-bit width 1 : 8-bit width RDY control bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. "0" at read. Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CS0. 1 : Recovery cycle is inserted at access to area CS0. CS0 output select bit 0 : CS0 output is disabled. (P90 functions as a programmble I/O port pin.) 1 : CS0 output is enabled. (P90 functions as pin CS0.) Notes 1: When the burst ROM access is specified (bit 5= 1), be sure not to select "112" (ALE expansion wait). 2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = "1". 3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit's contents. 7 6 5 4 3 2 1 0 CS1 control register L CS2 control register L CS3 control register L Address 8216 8416 8616 Area CSj wait number select bits (j = 1 to 3) 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait (Note 1) External data bus width select bit 0 : 16-bit width 1 : 8-bit width (Note 2) RDY control bit (Note 3) 0 : RDY control is valid. 1 : RDY control is invalid. DRAM space select bit 0 : Except DRAM space 1 : DRAM space Burst ROM access select bit (Note 4) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit (Note 5) 0 : No recovery cycle is inserted at access to area CSj. 1 : Recovery cycle is inserted at access to area CSj. CSj output select bit (j = 1 to 3) 0 : CSj output is disabled. (P9j functions as programmable I/O port pins.) 1 : CSj output is enabled. (P9j functions as pin CSj.) Notes 1: When the DRAM space is specified (bit 4 = 1), fix these bits to "012" (1 wait). Also, when the burst ROM access is specified (bit 5 = 1), be sure not to select "112" (ALE expansion wait). 2: While VCC level voltage is applied to pin BYTE, this bit is fixed to "1" (8-bit width). 3: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = "1". Also, when DRAM space is specified (bit 4 = 1), the RDY control is invalid regardless of this bit's contets. 4: When only the external data bus width select bit (bit 2) = "1" or while VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit's contents. 5: When the DRAM space is specified (bit 4 = 1), fix this bit to "0" (no recovery cycle). Fig. 15 Bit configuration of CS0/CS1/CS2/CS3 control register Ls 33 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR 7 6 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 4 3 2 1 0 CS0 control register H Address 8116 Area CS0 block size select bit 0 0 0 : 0 byte (Area CS0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : Do not select. 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : Do not select. 1 1 0 : Do not select. 1 1 1 : Do not select. "0" at read. 7 6 5 4 3 2 1 0 CS1 control register H CS2 control register H Address 8316 8516 Area CSk block size select bit (k = 1, 2) When mode 0 is selected When mode 1 is selected 0 0 0 : 0 byte (Area CSk is invalid.) 0 0 0 : 0 byte (Area CSk is invalid.) 0 0 1 : 128 Kbytes 0 0 1 : Do not select. 0 1 0 : 256 Kbytes 0 1 0 : Do not select. 0 1 1 : 512 Kbytes 0 1 1 : Do not select. 1 0 0 : 1 Mbytes 1 0 0 : 4 Kbytes 1 0 1 : 2 Mbytes 1 0 1 : 8 Kbytes 1 1 0 : 4 Mbytes 1 1 0 : Do not select. 1 1 1 : 8 Mbytes 1 1 1 : Do not select. "0" at read. Area CSk setting mode select bit (k = 1, 2) 0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.) 7 6 5 4 3 2 1 0 CS3 control register H Address 8716 Area CS3 block size select bit 0 0 0 : 0 byte (Area CS3 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes "0" at read. Fig. 16 Bit configuration of CS0/CS1/CS2/CS3 control register Hs 34 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR 7 6 5 4 3 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 1 0 Area CS0 start address register Address 8A16 "0" at read. These bits determine A8 to A15 of the area CS0 start address. Any of the following values can be set to these bits: "1016", "2016", "4016", and "8016". (Bits 0 to 3 are always "0" at read.) Note: Do not set a value other than "1016", "2016", "4016", and "8016". See Figure 18. 7 6 5 4 3 2 1 0 Area CS1 start address register Area CS2 start address register Address 8C16 8E16 "0" at read. When mode 0 is selected, these bits determine A16 to A23 of the area CS1/CS2 start address. When mode 1 is selected, these bits determine A8 to A15 of the area CS1/CS2 start address. (Bit 0 is always "0" at read.) Note: The start address setting depends on the block size, which has been selected by the area CS1/CS2 block size select bits (bits 0 to 2 at address 8316, bits 0 to 2 at address 8516). See Figures 19 and 20. 7 6 5 4 3 2 1 0 Area CS3 start address register Address 9016 "0" at read. These bits determine A16 to A23 of the area CS3 start address. (Bit 0 is always "0" at read.) Note: The start address setting depends on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716). See Figure 20. Fig. 17 Bit configuration of area CS0/CS1/CS2/CS3 start address registers 35 Fig. 18 Area CS0 36 FFFFF16 7FFFF16 1FFFF16 016 100016 512 K bytes 1 Mbytes 128 K bytes 512 K bytes 1 Mbytes 400016 512 K bytes 1 Mbytes 800016 128 K bytes 512 K bytes Block size Value to be set to area CS0 start address register = "8016" Start address : 800016 : Area CS0 cannot be assigned here. 128 K bytes Block size Value to be set to area CS0 start address register = "4016" Start address : 400016 Note: When an area where area CS0 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS0 outputs "H" level. 128 K bytes 200016 Block size Value to be set to area CS0 start address register = "2016" Value to be set to area CS0 start address register = "1016" Block size Start address : 200016 1 Mbytes PR Start address : 100016 . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Block size : 4 Kbytes Addresses which can be start address (Address FFFF16 is not included; Note 1) Block size : 8 Kbytes Addresses which can be start address (Address FFFF16 is not included; Note 1) 016 016 4 Kbytes 8 Kbytes 100016 200016 200016 300016 400016 400016 500016 600016 600016 700016 800016 800016 E00016 F00016 (FFFF16) Notes 1: Only A8 to A15 of one of these addresses can be set to the area CS1/CS2 start address register. Do not set another address not shown here. 2: When an area where area CS1/CS2 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS1/CS2 outputs "H" level. (FFFF16) Fig. 19 Area CS1/CS2 (mode 1) 37 Block size : 128 Kbytes 38 Fig. 20 Area CS1/CS2 (mode 0) and area CS3 F0000016 (FF000016) (FFFFFF16) (FF000016) (FFFFFF16) FE000016 (FF000016) (FFFFFF16) Block size : 2 Mbytes E0000016 C0000016 A0000016 80000016 60000016 40000016 20000016 (016) Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) Block size : 4 Mbytes (FF000016) (FFFFFF16) C0000016 80000016 40000016 (016) Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) Block size : 8 Mbytes (FF000016) (FFFFFF16) 80000016 (016) Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) Notes 1: Only A16 to A23 of one of these addresses can be set to the area CS1/CS2/CS3 start address register. Do not set another address not shown here. 2: When an area where area CS1/CS2/CS3 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS1/CS2/CS3 outputs "H" level. : Reserved area. Do not access this area. : Area CS1/CS2/CS3 cannot be assigned here. (FF000016) (FFFFFF16) ;;; ;;;;;; ;;; ;;;;;; ;;; ; E0000016 FC000016 FC000016 (FF000016) (FFFFFF16) D0000016 FA000016 C0000016 F8000016 F8000016 F8000016 B0000016 A0000016 90000016 F6000016 12000016 80000016 10000016 10000016 10000016 70000016 E000016 60000016 C000016 C000016 50000016 A000016 40000016 8000016 8000016 8000016 30000016 6000016 20000016 4000016 (016) 4000016 (016) Block size : 1 Mbytes Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) 10000016 (016) Block size : 512 Kbytes Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) 2000016 (016) Block size : 256 Kbytes Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) PR Addresses which can be start address (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR (a) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 1 RD External address bus (A0 to A23) (b) Address Address Address Address External data bus (D0 to D7) Data Data Data Data (instruction) (instruction) (instruction) (instruction) External data bus (D8 to D15) Data Data Data Data (instruction) (instruction) (instruction) (instruction) 1 RD External address bus (A0 to A23) Address Address External data bus (D0 to D7) Data Data (instruction) (instruction) External data bus (D8 to D15) Data Data (instruction) (instruction) Note: The above is applied when 0 wait is selected. Fig. 21 Operating waveform example at burst ROM access 39 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION INTERRUPTS Table 13 shows the interrupt sources and the corresponding interrupt vector addresses. Reset is also described as a type of interrupt in this section, too. DBC and BRK instruction are interrupts used only for debugging. Therefore, do not use these interrupts. Interrupts other than reset, watchdog timer, zero divide, NMI, and address matching detection all have interrupt control registers. Table 14 shows the addresses of the interrupt control registers, and Figure 22 shows the bit configuration of the interrupt control register. The interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. Also, interrupt request bits other than watchdog timer and NMI can be cleared by software. Any of INT2 through INT0 interrupt requests is generated by an external input. INT2 to INT0 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected with the level/edge select bit. Furthermore, the polarity of the interrupt input can be selected with the polarity select bit. Timer and UART interrupts are described in the respective section. The priorities of interrupts when multiple interrupt requests are caused simultaneously are partially fixed by hardware, but, the other can be adjusted by software as shown in Figure 23. The hardware priority is fixed as the following: reset > NMI > watchdog timer > other interrupts 7 6 5 4 3 2 1 Table 13 Interrupt sources and interrupt vector addresses Interrupts Vector addresses DMA3 00FFC016 00FFC116 DMA2 00FFC216 00FFC316 DMA1 00FFC416 00FFC516 DMA0 00FFC616 00FFC716 Address matching detection interrupt 00FFCA16 00FFCB16 INT4 external interrupt 00FFD016 00FFD116 INT3 external interrupt 00FFD216 00FFD316 A-D conversion 00FFD416 00FFD516 UART1 transmit 00FFD616 00FFD716 UART1 receive 00FFD816 00FFD916 UART0 transmit 00FFDA16 00FFDB16 UART0 receive 00FFDC16 00FFDD16 Timer B2 00FFDE16 00FFDF16 Timer B1 00FFE016 00FFE116 Timer B0 00FFE216 00FFE316 Timer A4 00FFE416 00FFE516 Timer A3 00FFE616 00FFE716 Timer A2 00FFE816 00FFE916 Timer A1 00FFEA16 00FFEB16 Timer A0 00FFEC16 00FFED16 INT2 external interrupt 00FFEE16 00FFEF16 INT1 external interrupt 00FFF016 00FFF116 INT0 external interrupt 00FFF216 00FFF316 NMI external interrupt 00FFF416 00FFF516 Watchdog timer 00FFF616 00FFF716 DBC (Do not select.) 00FFF816 00FFF916 Break instruction (Do not select.) 00FFFA16 00FFFB16 Zero divide 00FFFC16 00FFFD16 Reset 00FFFE16 00FFFF16 0 Interrupt priority level Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested Bit configuration of interrupt control registers for DMA0 to DMA3, A-D converter, UART0, UART1, timers A0 to A4, and timers B0 to B2, and INT3, INT4. 7 6 5 4 3 2 1 0 Interrupt priority level Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. Level/Edge select bit 0 : Edge sense 1 : Level sense Bit configuration of interrupt control registers for INT0- INT2. Fig. 22 Bit configuration of interrupt control register 40 MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION tection interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 15. The interrupt request bit and the interrupt priority level of each interrupt source are sampled and latched at each operation code fetch cycle while is "H". However, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. The detection of an interrupt which has the highest priority is performed during that time. Priority is determined by hardware Table 14. Addresses of interrupt control registers Interrupt control registers Addresses INT3 interrupt control register 00006E16 INT4 interrupt control register 00006F16 A-D interrupt control register 00007016 UART0 transmit interrupt control register 00007116 UART0 receive interrupt control register 00007216 UART1 transmit interrupt control register 00007316 UART1 receive interrupt control register 00007416 Timer A0 interrupt control register 00007516 Timer A1 interrupt control register 00007616 Timer A2 interrupt control register 00007716 Timer A3 interrupt control register 00007816 Timer A4 interrupt control register 00007916 Timer B0 interrupt control register 00007A16 Timer B1 interrupt control register 00007B16 Timer B2 interrupt control register 00007C16 00007D16 INT0 interrupt control register INT1 interrupt control register 00007E16 INT2 interrupt control register 00007F16 DMA0 interrupt control register 0000B216 DMA1 interrupt control register 0000B316 DMA2 interrupt control register 0000B416 DMA3 interrupt control register 0000B516 Watchdog timer NMI Reset A-D converter, UART, etc. interrupts Priority can be changed by software inside . Fig. 23 Interrupt priority Level 0 DMA3 DMA2 Interrupts caused by the address matching detection and when dividing by zero are software interrupts and are not included in Figure 23. Other interrupts previously mentioned are A-D converter, UART, etc. interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by software. Figure 24 shows a diagram of the interrupt priority detection circuit. When an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority. This comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. Finally the selected interrupt is compared with the processor interrupt priority level (IPL) contained in the processor status register (PS) and the request is accepted if it is higher than IPL and the interrupt disable flag I is "0". The request is not accepted if flag I is "1". The reset, NMI, and watchdog timer interrupts are not affected by the interrupt disable flag I. When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable flag I is set to "1". Furthermore, the interrupt request bit of the accepted interrupt is cleared to "0" and the processor interrupt priority level (IPL) in the processor status register (PS) is replaced by the priority level of the accepted interrupt. Therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag I to "0" and enable further interrupts. For reset, watchdog timer, zero divide, NMI, and address match de- DMA1 DMA0 INT4 INT3 A-D Interrupt request UART1 transmit UART1 receive UART0 transmit UART0 receive Reset Timer B2 Timer B1 NMI Timer B0 Timer A4 Timer A3 Watchdog timer Timer A2 Timer A1 Timer A0 INT2 Interrupt disable flag I INT1 IPL INT0 Fig. 24 Interrupt priority detection 41 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION As shown in Figure 25, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been completed. The time is selected with bits 4 and 5 of the processor mode register 0 (address 5E16) shown in Figure 26. Table 16 shows the relationship between these bits and the number of cycles. After a reset, the processor mode register 0 is initialized to "0016." Therefore, the longest time is automatically set, however, the shortest time must be selected by software. Table 15. Value loaded in processor interrupt level (IPL) during an interrupt Interrupt types Reset Watchdog timer NMI Zero divide Address matching detection Table 16. Relationship between interrupt priority detection time select bit and number of cycles Priority detection time select bit Bit 5 Bit 4 0 0 0 1 1 0 Operation code fetch cycle Sampling pulse Priority detection time Select one between 0 to 2 with bits 4 and 5 of processor mode register 0 Fig. 25 Interrupt priority detection time 42 0 1 2 Setting value 0 7 7 Not change value of IPL. Not change value of IPL. Number of cycles (Note) 7 cycles of 4 cycles of 2 cycles of MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR 7 6 5 4 3 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 2 1 0 Processor mode register 0 Address 5E16 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. Software reset bit By a write of "1" to this bit, the microcomputer will be reset, and then, restarted. Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as a programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as the clock 1 output pin.) Fig. 26 Bit configuration of processor mode register 0 43 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION TIMER selected by bits 0 and 1 of this register. There are eight 16-bit timers. They are divided by type into timer A(5) and timer B(3). The timer I/O pins are multiplexed with I/O pins for port P5 and P6. To use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to "0" to specify input mode. TIMER A Figure 27 shows a block diagram of timer A. Timer A has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each of these modes is described below. Figure 28 shows the bit configuration of the timer A clock division select register. Timers A0 to A4 use the count source which has been Timer A clock division select bit f2 (1) Timer mode [00] Figure 29 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0, 1 and 5 of the timer Ai mode register must be "0" in timer mode. The timer A's count source is selected by bits 6 and 7 of the timer Ai mode register and the contents of the timer A clock division select register. (See Table 17.) The counting of the selected clock starts when the count start bit is "1" and stops when it is "0". Figure 30 shows the bit configuration of the count start bit. The counter is decremented, an interrupt is caused and the interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is transferred to the counter and count is continued. Count source select bits f1() f16 f64 Data bus (odd) f512 Data bus (even) f4096 (Low-order 8 bits) * Timer * One-shot pulse * Pulse width (High-order 8 bits) Reload register(16) Timer (gate function) Counter (16) TAiIN (i = 0-4) Polarity selection Event counter Count start register (Address 4016) External trigger Countdown Up-down register (Address 4416) Pulse output Toggle flip-flop TAiOUT (i = 0-4) Fig. 27 Block diagram of timer A 44 Countup/Countdown switching "Countdown" is always selected when not in the event counter mode. Addresses Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 4716 4916 4B16 4D16 4F16 4616 4816 4A16 4C16 4E16 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION When bit 2 of the timer Ai mode register is "1", the output is generated from TAiOUT pin. The output is toggled each time the contents of the counter reaches to 000016. When the contents of the count start bit is "0", "L" is output from TAiOUT pin. When bit 2 is "0", TAiOUT can be used as a normal port pin. When bit 4 is "0", TAiIN can be used as a normal port pin. When bit 4 is "1", counting is performed only while the input signal from the TAiIN pin is "H" or "L" as shown in Figure 31. Therefore, this can be used to measure the pulse width of the TAiIN input signal. Whether to count while the input signal is "H" or while it is "L" is determined by bit 3. If bit 3 is "1", counting is performed while the TAiIN pin input signal is "H" and if bit 3 is "0", counting is performed while it is "L". Note that, the duration of "H" or "L" on the TAiIN pin must be 2 or more cycles of the timer count source. When data is written to timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency division ratio is 1/(n+1). 7 6 5 0 4 3 2 1 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Timer A clock division select register Address 4516 Timer A clock division select bit (See Table 17.) "0" at read. Fig. 28 Bit configuration of timer A clock division select register Table 17. Relationship between timer A clock division select bits, clock source select bits, and count source Clock source select bits (bits 7 and 6 at addresses 5616 to 5A16) 00 01 10 11 Timer A clock division select bits (bits 1 and 0 at address 4516) 00 11 10 01 f2 f1() f1() f16 f64 f16 Do not f64 f512 select. f64 f4096 f4096 f512 Note: Timers A0 to A4 use the same clock, which is selected by the timer A clock division select bits. Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5616 5716 5816 5916 5A16 0 0 : Always "00" in timer mode 0 : No pulse output (TAiOUT is normal port pin.) 1 : Pulse output 0 x : No gate function (TAiIN is normal port pin.) 1 0 : Count only while TAiIN input is "L". 1 1 : Count only while TAiIN input is "H". 0 : Always "0" in timer mode. Clock source select bits See Table 17. Fig. 29 Bit configuration of timer Ai mode register during timer mode 45 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR 7 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 6 5 4 3 2 1 0 Count start register (Stop at "0", Start at "1") Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Fig. 30 Bit configuration of count start register Selected clock source fi TAiIN Timer mode register Bit 4 Bit 3 1 0 Timer mode register Bit 4 Bit 3 1 1 Fig. 31 Count waveform when gate function is available 46 Address 4016 MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (2) Event counter mode [01] Figure 32 shows the bit configuration of the timer Ai mode register during event counter mode. In event counter mode, bit 0 of the timer Ai mode register must be "1" and bits 1 and 5 must be "0". The input signal from the TAiIN pin is counted when the count start bit shown in Figure 30 is "1" and counting is stopped when it is "0". Count is performed at the fall of the input signal when bit 3 is "0" and at the rise of the signal when it is "1". In event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the TAiOUT pin. When bit 4 of the timer Ai mode register is "0", the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is "0" and increment when it is "1"). Figure 33 shows the bit configuration of the up-down register. When bit 4 of the timer Ai mode register is "1", the input signal from the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be "0" if bit 4 is "1." It is because if bit 2 is "1", TAiOUT pin becomes an output pin to output pulses. The count is decremented when the input signal from the TAiOUT pin is "L" and incremented when it is "H". Determine the level of the input signal from the TAiOUT pin before a valid edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 000016 (decrement count) or FFFF16 (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. When bit 2 is "1," each time the counter reaches 000016 (decrement count) or FFFF16(increment count), the waveform's polarity is reversed and is output from TAiOUT pin. If bit 2 is "0", TAiOUT pin can be used as a normal port pin. However, if bit 4 is "1" and the TAiOUT pin is used as an output pin, the output from the pin changes the count direction. Therefore, bit 4 must be "0" unless the output from the TAiOUT pin is to be used to select the count direction. 7 6 5 4 3 2 1 0 x x 0 0 1 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5616 5716 5816 5916 5A16 0 1 : Always "01" in event counter mode 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal 0 : Increment or decrement according to up/down bit 1 : Increment or decrement according to TAiOUT pin input signal level 0 : Always "0" in event counter mode x x : Not used in event counter mode Fig. 32 Bit configuration of timer Ai mode register during event counter mode 7 6 5 4 3 2 1 0 Up-down register Address 4416 Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Fig. 33 Bit configuration of up-down register 47 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time. In event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer A2, A3, or A4. There are two types of two-phase pulse processing operations. One uses timers A2 and A3, and the other uses timer A4. In both processing operations, two pulses described above are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively. When timers A2 and A3 are used, as shown in Figure 34, the count is incremented when a rising edge is input to the TAkIN pin after the level of TAkOUT(k=2, 3) pin changes from "L" to "H", and when the falling edge is input, the count is decremented. For timer A4, as shown in Figure 35, when a phase-related pulse with a rising edge input to the TA4IN pin is input after the level of TA4OUT pin changes from "L" to "H", the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase-related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from "H" to "L", the count is decremented at the respective rising edge and falling edge of the TA4IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, timer Aj mode register bit 0 and bit 4 must be set to "1" and bits 1, 2, 3, and 5 must be "0". Bits 6 and 7 are ig- nored. (See Figure 36.) Note that bits 5, 6, and 7 of the up-down register (address 4416) are the two-phase pulse signal processing select bits for timers A2, A3 and A4 respectively. Each timer operates in normal event counter mode when the corresponding bit is "0" and performs two-phase pulse signal processing when it is "1". Count is started by setting the count start bit to "1". Data write and read are performed in the same way as for normal event counter mode. Note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. Also, there can be no pulse output in this mode. 7 6 5 4 3 2 1 0 x x 0 1 0 0 0 1 0 1 0 0 : Always "0100" when processing two-phase pulse signal x x : Not used in event counter mode Fig. 36 Bit configuration of timer Aj mode register when performing two-phase pulse signal processing in event counter mode TAkIN (k = 2, 3) Incrementcount Incrementcount Decrementcount Decrementcount Decrementcount Fig. 34 Two-phase pulse processing operation of timers A2 and A3 TA4OUT Increment-count at each edge Decrement-count at each edge TA4IN Increment-count at each edge Decrement-count at each edge Fig. 35 Two-phase pulse processing operation of timer A4 48 Addresses 5816 5916 5A16 0 1 : Always "01" in event counter mode TAkOUT Incrementcount Timer A2 mode register Timer A3 mode register Timer A4 mode register MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (3) One-shot pulse mode [10] Figure 37 shows the bit configuration of the timer Ai mode register during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5 must be "0" and bit 1 and bit 2 must be "1". The trigger is enabled when the count start bit is "1". The trigger can be generated by software or it can be input from the TAiIN pin. Software trigger is selected when bit 4 is "0" and the input signal from the TAiIN pin is used as the trigger when it is "1". Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise of the trigger signal when it is "1". Software trigger is generated by setting "1" to a bit in the one-shot start register. Each bit corresponds to each timer. Figure 38 shows the bit configuration of the one-shot start register. As shown in Figure 39, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7 and the contents of the timer A clock division select register. (Set Table 17.) If the contents of the counter is not 000016, the TAiOUT pin goes "H" when a trigger signal is received. The count direction is decrement. When the counter reaches 000116, the TAiOUT pin goes "L" and count is stopped. The contents of the reload register is transferred to the counter. At the same time, an interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set. This is repeated each time a trigger signal is received. The output pulse width is 1 pulse frequency of the selected clock x (counter's value at the time of trigger). If the count start flag is "0", TAiOUT goes "L". Therefore, the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start bit. As shown in Figure 40, a trigger signal can be received before the operation for the previous trigger signal is completed. In this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. Except when retriggering while operating, the contents of the reload register are not transferred to the counter by triggering. When retriggering, there must be at least one timer count source cycle before a new trigger can be issued. Data write is performed in the same way as for timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. Undefined data is read when timer Ai is read. Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register 7 6 5 4 3 2 1 0 0 Addresses 5616 5716 5816 5916 5A16 1 1 0 1 0 : Always "10" in one-shot pulse mode 1 : Always "1" in one-shot pulse mode 0 x : Software trigger 1 0 : Trigger at the falling edge of TAiIN input 1 1 : Trigger at the rising edge of TAiIN input 0 : Always "0" in one-shot pulse mode Clock source select bits (See Table 17.) Fig. 37 Bit configuration of timer Ai mode register during one-shot pulse mode 7 6 5 4 3 2 1 0 0 One-shot start register Address 4216 Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Must be fixed to "0". Fig. 38 Bit configuration of one-shot start register 49 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000316 Fig. 39 Pulse output example when external rising edge is selected Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000416 Fig. 40 Example when trigger is re-issued during pulse output 50 MI ELI ge. ion. icat to chan ecif l sp ubject a in af es not mits ar li is is : Th metric e ic Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (4) Pulse width modulation mode [11] Figure 41 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to "1". Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is "0" and 8-bit length pulse width modulator is selected when it is "1". The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAiIN pin (external trigger). The software trigger mode is selected when bit 4 is "0". Pulse width modulator is started and a pulse is output from TAiOUT when the count start bit is set to "1". The external trigger mode is selected when bit 4 is "1". Pulse width modulation starts when a trigger signal is input from the TAiIN pin when the count start bit is "1". Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise when it is "1". When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the count start bit is set to "1" and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 42 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration "H" of pulse is 1 xm selected clock frequency The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6, 7, and the contents of the timer A clock division select register. (See Table 17.) A pulse is generated when the counter reaches 000016 as shown in Figure 43. At the same time, the contents of the reload register is transferred to the counter and count is continued. 7 6 5 4 3 2 1 0 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5616 5716 5816 5916 5A16 1 1 1 1 1 : Always "11" in pulse width modulation mode 1 : Always "1" in pulse width modulation mode 0 x : Software trigger 1 0 : Trigger at the falling of TAiIN input 1 1 : Trigger at the rising of TAiIN input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator Clock source select bits (See Table 17.) Fig. 41 Bit configuration of timer Ai mode register during pulse width modulation mode and the output pulse period is 1 x (216 -1). selected clock frequency An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is "1". The reload register and the counter are both divided into 8-bit halves. 51 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Therefore, if the low-order 8 bits of the reload register are n, the period of the generated pulse is high-order 8 bits of the reload register are m, the duration "H" of pulse is 1 x (n + 1) x m. selected clock frequency 1 x (n + 1). selected clock frequency The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the And the output pulse period is 1 selected clock frequency 1/fi x (216 - 1) Selected clock source fi TAiIN (rising edge) This trigger is not accepted 1/fi x (m) TAiOUT Example when the contents of the reload register is 000316 Fig. 42 16-bit length pulse width modulator output pulse example 1/fi x (n + 1) x (28 - 1) Selected clock source fi TAiIN (falling edge) 1/fi x (n + 1) Prescaler output (when n = 2) 1/fi x (n + 1) x (m) 8-bit length pulse width modulator output (when m = 2) Fig. 43 8-bit length pulse width modulator output pulse example 52 x (n + 1) x (28 - 1). MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION TIMER B Figure 44 shows a block diagram of timer B. Timer B has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. The mode is selected with bits 0 and 1 of the timer Bi mode register (i=0 to 2). Each of these modes is described below. (1) Timer mode [00] Figure 45 shows the bit configuration of the timer Bi mode register during timer mode. Bits 0 and 1 of the timer Bi mode register must always be "0" in timer mode. Bits 6 and 7 are used to select the clock source. The counting of the selected clock starts when the count start bit is "1" and stops when "0". As shown in Figure 30, the timer Bi count start bit is at the same address as the timer Ai count start bit. The count is decremented, an interrupt occurs, and the interrupt request bit in the timer Bi interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is stored in the counter and count is continued. Timer Bi does not have a pulse output function or a gate function like timer A. When data is written to timer Bi halted, it is written to the reload register and the counter. When data is written to timer Bi which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time. Data bus (odd) Data bus (even) (Low-order 8 bits) Count source select bits * Timer mode * Pulse period measurement/Pulse width measurement mode f2 f16 (High-order 8 bits) Reload register (16) f64 f512 Counter (16) TBiIN (i = 0 to 2) Polarity selection and edge pulse generator * Event counter mode Count start register Addresses Timer B0 5116 5016 Timer B1 5316 5216 Timer B2 5516 5416 (Address 4016) Counter reset circuit Note: Perform a write and read to/from timer Bi register in the condition of 16-bit data length : data length flag (m) = "0". Fig. 44 Block diagram of timer B 53 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (2) Event counter mode [01] Figure 46 shows the bit configuration of the timer Bi mode register during event counter mode. In event counter mode, bit 0 in the timer Bi mode register must be "1" and bit 1 must be "0". The input signal from the TBiIN pin is counted when the count start bit is "1" and counting is stopped when it is "0". Count is performed at the fall of the input signal when bits 2, and 3 are "0" and at the rise of the input signal when bit 3 is "0" and bit 2 is "1". When bit 3 is "1" and bit 2 is "0", count is performed at the rise and fall of the input signal. Data write, data read and timer interrupt are performed in the same way as for timer mode. 7 6 5 4 3 2 1 0 x x x 0 0 Timer B0 mode register Timer B1 mode register Timer B2 mode register Addresses 5B16 5C16 5D16 0 0 : Always "00" in timer mode x x : Not used in timer mode and may be any Not used in timer mode Clock source select bits 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 Fig. 45 Bit configuration of timer Bi mode register during timer mode (3) Pulse period measurement/Pulse width measurement mode [10] Figure 47 shows the bit configuration of the timer Bi mode register during pulse period measurement/pulse width measurement mode. In pulse period measurement/pulse width measurement mode, bit 0 must be "0" and bit 1 must be "1". Bits 6 and 7 are used to select the clock source. The selected clock is counted when the count start bit is "1" and counting stops when it is "0". The pulse period measurement mode is selected when bit 3 is "0". In pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBiIN pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. In this case, the reload register acts as a buffer register. When bit 2 is "0", the clock is counted from the fall of the input signal to the next fall. When bit 2 is "1", the clock is counted from the rise of the input signal to the next rise. In the case of counting from the fall of the input signal to the next fall, counting is performed as follows. As shown in Figure 48, when the fall of the input signal from TBiIN pin is detected, the contents of the counter is transferred to the reload register. Next, the counter is cleared and count is started from the next clock. When the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and the count is started. The period from the fall of the input signal to the next fall is measured in this way. After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer Bi interrupt control register is set. However, no interrupt request signal is generated when the contents of the counter is transferred first to the reload register after the count start bit is set to "1". When bit 3 is "1", the pulse width measurement mode is selected. Pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the TBiIN pin input signal to the next rise or from the rise of the input signal to the next fall as shown in Figure 49. 7 6 5 4 3 2 1 0 x x x 0 1 Timer B0 mode register Timer B1 mode register Timer B2 mode register Addresses 5B16 5C16 5D16 0 1 : Always "01" in event counter mode 0 0 : Count at the falling edge of input signal 0 1 : Count at the rising edge of input signal 1 0 : Count at the both falling edge and rising edge of input signal x x x : Not used in event counter mode Fig. 46 Bit configuration of timer Bi mode register during event counter mode 7 6 5 4 3 2 1 0 1 0 Timer B0 mode register Timer B1 mode register Timer B2 mode register Addresses 5B16 5C16 5D16 1 0 : Always "10" in pulse period measurement/pulse width measurement mode 0 0 : Count from the falling edge of input signal to the next falling one 0 1 : Count from the rising edge of input signal to the next rising one 1 0 : Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one Timer Bi overflow flag Clock source select bits 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 Fig. 47 Bit configuration of timer Bi mode register during pulse period measurement/pulse width measurement mode 54 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION When timer Bi is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to "1" when the timer Bi counter reaches 000016, which indicates that a pulse width or pulse period is longer than that which can be measured by a 16-bit length. This flag is cleared by writing data to the corresponding timer Bi mode register. This flag is set to "1" at reset. Selected clock source fi TBiIN Reload register Counter Counter 0 Count start bit Interrupt request signal Fig. 48 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) Selected clock source fi TBiIN Reload register Counter Counter 0 Count start bit Interrupt request signal Fig. 49 Pulse width measurement mode operation 55 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION SERIAL I/O PORTS Two independent serial I/O ports are provided. Figure 50 shows a block diagram of the serial I/O ports. Bits 0 to 2 of the UARTi(i = 0,1) transmit/receive mode register shown in Figure 51 are used to determine whether to use port P8 as a programmable I/O port, clock synchronous serial I/O port, or asyn- chronous (UART) serial I/O port which uses start and stop bits. Figures 52 and 53 show the block diagrams of the receiver/transmitter. Figure 54 shows the bit configuration of the UARTi transmit/receive control register. Each communication method is described below. Data bus (odd) Data bus (even) Bit converter UARTi D7 D6 D5 D4 D3 D2 D1 D0 receive buffer register UART0 (Addresses 3716, 3616) UART1 (Addresses 3F16, 3E16) 0 0 0 0 0 0 0 D8 UARTi receive register RX D i BRG count source select bits f2 f16 BRGi f64 1/(n + 1) divider f512 1/16 divider UART Clock synchronous 1/16 divider UART Clock synchronous Receive control circuit Transmit control circuit Transfer clock Transfer clock Clock synchronous (Internal clock) 1/2 divider UARTi transmit register Clock synchronous (External clock) TX D i Clock synchronous (when internal clock selected) D8 CLK0 D 7 D6 D5 D 4 D3 D 2 D 1 D0 UARTi transmit buffer register UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) CLK1 CTS0/CLK1 CTS0 Bit converter CTS0/RTS0 Data bus (odd) n = a value set into the UARTi baud rate register (BRGi) Data bus (even) Fig. 50 Block diagram of serial I/O port 7 6 5 4 3 2 1 0 UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register Addresses 3016 3816 Serial I/O mode select bits 0 0 0 : Programmable I/O port (Serial I/O is invalid.) 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal/External clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit (Valid in UART mode.) 0 : 1 stop bit 1 : 2 stop bits Odd/Even parity select bit (Valid in UART mode with the parity enable bit = "1".) 0 : Odd parity 1 : Even parity Parity enable bit (Valid in UART mode) 0 : No parity 1 : With parity Sleep select bit (Valid in UART mode) 0 : No sleep 1 : Sleep Fig. 51 Bit configuration of UARTi transmit/receive mode register 56 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Data bus (odd) Data bus (even) UARTi receive buffer register 0 0 0 0 0 2SP R XD i PAR D7 D6 D5 D4 D3 D2 D1 D0 8-bit UART 9-bit UART Synchronous UART No parity 1SP D8 0 9-bit UART Parity SP SP 0 7-bit UART 7-bit UART 8-bit UART Synchronous UARTi receive register Synchronous SP : Stop bit PAR : Parity bit Fig. 52 Block diagram of receiver Data bus (odd) Data bus (even) UARTi receive transmit register D8 2SP SP SP D6 D5 D4 D3 D2 D1 D0 8-bit UART 7-bit UART 9-bit UART 9-bit UART Synchronous Synchronous Parity TXDi UART PAR 8-bit UART 1SP D7 No parity 7-bit UART UARTi transmit register Synchronous 0 SP : Stop bit PAR : Parity bit Fig. 53 Block diagram of transmitter 57 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR 7 6 5 4 MSB CPL /LSB 3 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 2 TX R/C EPTY 1 0 CS1 CS0 UART0 transmit/receive control register 0 UART1 transmit/receive control register 0 Address 34 16 3C16 BRG count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS/RTS function select bit (Note 1) 0 : CTS function is selected. 1 : RTS function is selected. Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) CTS/RTS enable bit (Note 2) 0 : CTS, RTS function is enabled. 1 : CTS, RTS function is disabled. UART receive interrupt mode select bit 0 : Reception interrupt 1 : Reception error interrupt CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3) 0 : At the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. When not in transfer, pin CLK's level is "H". 1 : At the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. When not in transfer, pin CLK's level is "L". Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3) 0 : LSB (Least Significant Bit) first 1 : MSB (Most Significant Bit) first 7 6 5 4 SUM PER FER OER 3 2 1 0 RI RE TI TE UART0 transmit/receive control register 1 UART1 transmit/receive control register 1 Address 3516 3D16 Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Note 4) Parity error flag (Note 4) Error sum flag (Note 4) Notes 1: Valid when the CTS/RTS enable bit = "0". 2: Fix this bit to "1" in UART1 transmit/receive control register 0. (UART1 is not equipped with the CTS/RTS function.) 3: Fix this bit to "0" in UART mode or when serial I/O is invalid. 4: Valid in UART mode. Fig. 54 Bit configuration of UARTi transmit/receive control register 58 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CLOCK SYNCHRONOUS SERIAL COMMUNICATION A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 55 will be described. (The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/receive mode register must be set to "1" and bits 1 and 2 must be "0". The length of the transmission data is fixed at 8 bits. Bit 3 of the UARTj transmit/receive mode register of the clock sending side is cleared to "0" to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to "1" to select the external clock. Bits 4, 5 and 6 are ignored in clock synchronous mode. Bit 7 must always be "0". The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the clock-sending-side UARTj transmit/receive control register 0. As shown in Figure 50, the selected clock is divided by (n + 1), then by 2, is passed through a transmission control circuit, and is output as transmission clock CLKj. Therefore, when the selected clock is fi, Bit Rate = fi/ {(n + 1) x 2} On the clock receiving side, the CS0 and CS1 bits of the UARTk transmit/receive control register 0 are ignored because an external TxDj clock is selected. UART0 is equipped with the CTS and RTS functions. UART1 is not equipped with the CTS/RTS function. Bit 4 of the UART0 transmit/receive control register 0 is used to determine whether to use CTS0 or RTS0 signal. Bit 4 must be "0" when CTS0 or RTS0 signal is used. Bit 4 must be "1" when CTS0 and RTS0 signals are not used. When CTS0 and RTS0 signals are not used, CTS0/RTS0 pin can be used as a normal port pin. When using this pin as pin CTS0/RTS0, : * If bit 2 of the UART0 transmit/receive control register 0 is cleared to "0", CTS0 input is selected. * If bit 2 is set to "1", RTS0 output is selected. Figure 56 shows the bit configuration of the CTS/RTS separate select register. By using bit 0 of the CTS/RTS separate select register (CTS/RTS separate select bit), the function of the CTS0/RTS0 pin can be separated into two functions. When bit 0 = "1", the above separation is performed. When bit 0 = "0", no separation is performed. When the CTS0/RTS0 pin is separated, RTS0 function is selected. When the CTS0/CLK1 pin is separated, CTS0 function is selected. The following describes the case where the CTS and RTS signals are used. When the CTS and RTS signals are not used, however, the CTS input is not necessary, and there is no RTS output. Since UART1 is not equipped with the CTS/RTS function, UART1 is regarded as the case where the CTS and RTS signals are not used. TxDk UARTj transmit register UARTk transmit register UARTj transmit buffer register UARTk transmit buffer register UARTj receive buffer register UARTk receive buffer register RxDj RxDk UARTk receive register UARTj receive register UARTk Transmit/Receive mode register UARTj Transmit/Receive mode register 0 0 0 0 0 1 CLKj RE TI 0 1 UARTk Transmit/Receive control register 0 TX MSB /LSB CPL EPTY 1 CTSj RTSk UARTk Transmit/Receive control register 1 UARTj Transmit/Receive control register 1 RI 0 CLKk UARTj Transmit/Receive control register 0 TX MSB CS1 CS0 /LSB CPL EPTY 0 SUM PER FER OER 1 TE SUM PER FER OER RI RE TI TE Fig. 55 Clock synchronous serial communication 59 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 0 CTS/RTS separate select register Address AC16 CTS/RTS separate select bit (Note) 0 : CTS/RTS are multiplexed. 1 : CTS/RTS are separate. Must be "0". Note: Valid when the CTS/RTS enable bit (bit 4 at address 3416) = "0". Fig. 56 Bit configuration of CTS/RTS separate select register Transmission Transmission is started when bit 0 (TEj flag: transmit enable bit) of UARTj transmit/receive control register 1 is "1", bit 1 (TIj flag) of one is "0", and CTSj input is "L". The TIj flag indicates whether the transmit buffer register is empty or not. It is cleared to "0" when data is written in the transmit buffer register ; it is set to "1" when the contents of the transmit buffer register is transferred to the transmit register and the transmit buffer register becomes empty. When all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. As shown in Figure 57, data is output from TXDj pin each time when transmission clock CLKj changes from "H" to "L". (In the clock synchronous serial I/O mode, the polarity of a transfer clock can be changed. For details, refer to the section on the selection of the transfer clock polarity.) The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. The next transmission is performed succeedingly. Once transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission is not interrupt when CTSj input is changed to "H" during transmission. The transmission start condition indicated by TEj flag, TIj flag, and CTSj is checked while the TENDj signal (shown in Figure 57) is "H". Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIj flag is cleared to "0" before theTENDj signal goes "H". Bit 3 (TXEPTYj flag) of UARTj transmit/receive control register 0 changes to "1" at the next cycle just after the TENDj signal goes "H" and changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission has completed. When the TIj flag changes from "0" to "1", the interrupt request bit in the UARTj transmit interrupt control register is set to "1". Receive When bit 2 of the UARTk transmit/receive control register 1 is set to "1", reception becomes enabled. In this case, when the CLKk signal is input, the receive operation starts simultaneously with this signal. The RTSk output is "H" when the REK flag is "0". When the REK flag is set to "1", the RTSk output becomes "L". This informs the transmitter side that reception becomes enabled. When the receive opera- 60 tion starts, the RTSk output automatically becomes "H". When the receive operation starts, the receiver takes data from pin RxDk each time when the transmit clock (CLKj) turns from "L" to "H". Simultaneously with reception, the contents of the receiver register is shifted bit by bit. (Note that, in the clock synchronous serial communication, the polarity of a transfer clock can be inverted. For details, refer to the section on the polarity of the transfer clock.) When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (RIk flag) of UARTk transmit/receive control register 1 is set to "1". In other words, the setting "1" to the RIk flag indicates that the receive buffer register contains the received data. At this time, if the low-order byte of the UARTk receive buffer register is read out, the RTSk output turns back to "L". This indicates that the next data reception becomes enabled. Bit 4 (OERk flag) of UARTk transmit/receive control register 1 is set to "1" when the next data is transferred from the receive register to the receive buffer register while RIk flag is "1", and indicates that the next data was transferred to the receive register before the contents of the receive buffer register was read. (In other words, this indicates that an overrun error has occurred.) RIk flag is automatically cleared to "0" when the low-order byte of the receive buffer register is read or when the REk flag is cleared to "0". The OERk flag is cleared when the REk flag is cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode. As shown in Figure 50, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no need to sent data from UARTk to UARTj. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 1/fi x (n + 1) x 2 Transmission clock TEj TIj Write in transmit buffer register Transmit register Transmit buffer register CTSj 1/fi x (n + 1) x 2 Stopped because TEj = "0" CLKj TENDj TXDj D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TXEPTYj Fig. 57 Clock synchronous serial I/O timing Interrupt request at completion of reception Polarity of transfer clock When the RIk flag changes from "0" to "1", in other words, when the receive operation is completed, the interrupt request bit of the UARTk receive interrupt control register can be set to "1". The timing when this interrupt request bit is to be set to "1" can be selected from the following: * Each reception * When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UARTk receive interrupt mode select bit) is cleared to "0", the interrupt request bit is set to "1" at each reception. If bit 5 is set to "1", the interrupt request bit is set to "1" only when an error occurs. (In the clock synchronous serial communication, only when an overrun error occurs, the interrupt request bit is set to "1".) Note that a DMA request is affected by the UART receive interrupt mode select bit if the UARTi reception is selected as a DMA request source of the DMA controller. When the UARTk receive interrupt mode select bit is cleared to "0", a DMA request is generated at each UART reception. When the UARTk receive interrupt mode select bit is set to "1", a DMA request is generated only at normal UART reception. (In other words, no DMA request is generated when an error has occurred.) In the clock synchronous serial communication, by bit 6 of the UARTj transmit/receive control register 0 (CPL), the polarity of a transfer clock can be selected. As shown in Figure 58, when bit 6 = "0", the polarity is as follows: * In transmission, transmit data is output at the falling edge of CLKj. * In reception, receive data is input at the rising edge of CLKk. * When not in transfer, CLKi is at "H" level. When bit 6 = "1", the polarity is as follows: * In transmission, transmit data is output at the rising edge of CLKj. * In reception, receive data is input at the rising edge of CLKk. * When not in transfer, CLKi is at "L" level. 61 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CLK polarity select bit = 0 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 Transmit data is output to pin TxDi at the falling edge of transfer clock, and receive data is input from pin RxDi at the rising edge of transfer clock. When not in transfer, pin CLKi's level is "H". CLK polarity select bit = 1 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 Transmit data is output to pin TxDi at the rising edge of transfer clock, and receive data is input from pin RxDi at the falling edge of transfer clock. When not in transfer, pin CLKi's level is "L". Fig. 58 Polarity of transfer clock 62 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Selection of transfer format In clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. When bit 7 is "0", transfer format is LSB first. When bit 7 is "1", transfer format is MSB first. This function is realized by changing connection relation between Bit 7 in transmit/receive control register 0 Write to transmit buffer register Data bus 0 (LSB first) Read from receive buffer register Transmit buffer register Data bus Receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D0 DB0 D0 Data bus 1 (MSB first) the transmit buffer register and the receive buffer register when writing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter's operation is the same in both transfer formats. Figure 59 shows the connection relation. Transmit buffer register Data bus Receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D0 DB0 D0 Fig. 59 Connection relation between transmit buffer register, receive buffer register, and data bus 63 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION ASYNCHRONOUS SERIAL COMMUNICATION contents (n) of the bit rate generator. If the selected clock is an internal clock Pfi or an external clock fEXT, Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, bit 0 of UARTi transmit/receive mode register is "1", bit 1 is "0", and bit 2 is "1". Bit 3 is used to select an internal clock or an external clock. If bit 3 is "0", an internal clock is selected and if bit 3 is "1", then external clock is selected. If an internal clock is selected, bit 0 (CS0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal I/O pin. The selected internal or external clock is divided by (n + 1), then by 16, and is passed through a control circuit to create the UART transmission clock or UART receive clock. Therefore, the transmission speed can be changed by changing the Bit Rate = (fi or fEXT) / {(n + 1) x 16} Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. Bit 5 is a select bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. Bit 6 is the parity bit select bit which indicates whether to add parity bit or not. Bits 4 to 6 must be set or reset according to the data format used in the communicating devices. Bit 7 is the sleep select bit. The sleep mode is described later. The function and select method of the CTS/RTS pin are the same as those of the clock synchronous serial communication mode. (1/fi or 1/fEXT) x (n + 1) x 16 Transmission clock TEi TIi Transmit register Transmit buffer register Written in transmit buffer register CTSi TENDi Start bit TXDi Stopped because TEi = "0" Parity bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TXEPTYi Fig. 60 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected (1/fi or 1/fEXT) x (n + 1) x 16 Transmission clock TEi TIi Transmit register Transmit buffer register Written in transmit buffer register TENDi Start bit TX Di Stop bit Stop bit Stopped because TEi = "0" ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP TXEPTYi Fig. 61 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected 64 ST D0 D1 D2 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Transmission ________ Transmission is started when bit 0 (TEi flag transmit enable flag) of UARTi transmit/receive control register 1 is "1", bit 1 (TIi flag) is "0", ________ and CTSi input (in other words, transmit enable signal input from receiver) is "L." The TIi flag indicates whether the transmit buffer is empty or not. It is cleared to "0" when data is written in the transmit buffer; it is set to "1" when the contents of the transmit buffer register is transferred to the transmit register. When all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. As shown in Figures 60 and 61, data is output from the TXDi pin with the stop bit or parity bit specified by bits 4 to 6 of UARTi transmit/receive mode register. The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condition is satisfied. Then, the next transmission is performed succeedingly. Once transmission has started, the TEi flag, TIi flag, and CTSi signal are ignored until data transmission is completed. Therefore, transmission does not stop until it completes event if, during transmission, the TEi flag is cleared to "0" or CTSi input is set to "1". The transmission start condition indicated by TEi flag, TIi flag, and ________ CTSi is checked while the TENDi signal shown in Figure 60 is "H". Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIi flag is cleared to "0" before the TENDi signal goes "H". Bit 3 (TXEPTYi flag) of UARTi transmit/receive control register 0 changes to "1" at the next cycle just after the TENDi signal goes "H" and changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from "0" to "1", the interrupt request bit of the UARTi transmit interrupt control register is set to "1". fi or fEXT REi Stop bit RXDi Start bit Check to be "L" level Receive clock D1 D0 Start bit D7 Data fetched Starting at the falling edge of start bit RIi RTSi Fig. 62 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected 65 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Receive Sleep mode Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive control register 1 is set to "1." As shown in Figure 62, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. If RTSi output is selected by setting bit 2 of UARTi transmit/receive control register 0 to "1", the RTSi output is "H" when the REi flag is "0". When the REi flag changes to "1", the RTSi output goes "L" to inform the receiver that reception has become enabled. When the receive operation starts, the RTSi output automatically becomes "H". The entire transmission data bits are received when the start bit passes the final bit of the receive block shown in Figure 52. At this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (Rli flag) of UARTi transmit/receive control register 1 is set to "1." In other words, the RIi flag indicates that the receive buffer register contains data when it is set to "1." At this time, when the low-order byte of the UARTk receive buffer register is read out, RTSi output goes back to "L" to indicate that the register is ready to receive the next data. Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to "1" when the next data is transferred from the receive register to the receive buffer register while the RIi flag is "1", in other words, when an overrun error occurs. If the OERi flag is "1", it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. Bit 5 (FERi flag) is set to "1" when the number of stop bits is less than required (framing error). Bit 6 (PERi flag) is set to "1" when a parity error occurs. Bit 7 (SUMi flag) is set to "1" when either the OERi flag, FERi flag, or the PERi flag is set to "1." Therefore, the SUMi flag can be used to determine whether there is an error. The RIi, OERi, FERi, and PERi flags are set to "1" while transferring the contents of the receive register into the receive buffer register. The FERi, PERi, and SUMi flags are cleared to "0" when the low-order byte of the receive buffer register has been read out or when "0" has been written to the REi flag. The OERi flag is cleared to "0" when "0" has been written to the REi flag. The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial I/O. The microcomputer enters the sleep mode when bit 7 of UARTi transmit/receive mode register is set to "1." The operation of the sleep mode for an 8-bit asynchronous communication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asynchronous communication) of the received data is "0". Also the RIi, OERi, FERi, PERi, and the SUMi flags are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is "1". The following is an example of how the sleep mode can be used. The main microcomputer first sends data: bit 7 is "1" and bits 0 to 6 are set to the address of the subordinate microcomputer to be communicated with. Then all subordinate microcomputers receive this data. Each subordinate microcomputer checks the received data, clears the sleep bit to "0" if bits 0 to 6 are its own address and sets the sleep bit to "1" if not. Next, the main microcomputer sends data with bit 7 cleared. Then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to "1" will not. In this way, the main microcomputer is able to communicate only with the designated microcomputer. Interrupt request at completion of reception When the RIk flag changes from "0" to "1", in other words, when the receive operation is completed, the interrupt request bit of the UARTk receive interrupt control register can be set to "1". The timing when this interrupt request bit is to be set to "1" can be selected from the following: * Each reception * When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UART receive interrupt mode select bit) is cleared to "0", the interrupt request bit is set to "1" at each reception. If bit 5 is set to "1", the interrupt request bit is set to "1" only when an error occurs. (In the clock asynchronous serial communication, when an overrun error, framing error, or parity error occurs, the interrupt request bit is set to "1".) 66 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION A-D CONVERTER address are "0000002" when read. When the conversion result is used as 8-bit data, the conversion result are stored in even-numbered address of the corresponding A-D register. In this case, the value at the A-D register's odd-numbered address is "0016" when read. The A-D converter is a 10-bit successive approximation converter. Figure 63 shows the block diagram of the A-D converter, Figure 64 shows the bit configuration of the A-D control register 0 (address 1E16), and the bit configuration of the A-D control register 1 (address 1F16). A-D conversion frequency An operation clock (AD) of an A-D converter can be selected with bit 7 of the A-D control register 0 and bit 4 of the A-D control register 1. When bit 4 of the A-D control register 1 is "0", AD becomes f2/4 when bit 7 of the A-D control register 0 is "0", AD becomes f2/2 when bit 7 of the A-D control register 0 is "1". When bit 4 of the A-D control register 1 is "1", AD becomes f2 when bit 7 of the A-D control register 0 is "0", AD becomes f1 when bit 7 of the A-D control register 0 is "1". Note that AD = f1 (in other words, the fastest speed) can be selected only in the 8-bit mode. AD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. A-D conversion accuracy Bit 3 of A-D control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. The conversion result is regarded as 10-bit data when bit 3 is "1" and as 8-bit data when bit 3 is "0". When the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even-numbered address of the corresponding A-D register and the high-order 2 bits are stored in bits 0 and 1 at the odd-numbered address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd-numbered A-D conversion frequency selection VREF connection select bit VREF f2 AD 1/2 1/2 f1 Resistor ladder network Vref AVSS Successive approximation register A-D control register 1 (Address 1F16) A-D control register 0 (Address 1E16) A-D register 0 (Address 2116)A-D register 0 (Address 2016) A-D register 1 (Address 2316) A-D register 1 (Address 2216) A-D register 2 (Address 2516) A-D register 2 (Address 2416) Decoder A-D register 3 (Address 2716) A-D register 3 (Address 2616) Data bus (odd) Comparator Data bus (even) AN0 AN1 AN2 AN3/ADTRG Selector Fig. 63 Block diagram of A-D converter 67 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Trigger external trigger is selected, even when the A-D conversion is completed, the A-D conversion start bit keeps "1". Also, a retrigger can be available even when A-D conversion is in progress. A-D conversion can be started by software trigger or by an external input trigger. Software trigger is selected when bit 5 of A-D control register 0 is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to "1." When an external trigger is selected, the polarity of a trigger input can be selected by bit 5 of the A-D control register 1. When bit 5 = "0", a falling edge is selected, and when bit 5 = "1", a rising edge is selected. A-D conversion starts when the A-D conversion start bit is "1" and the ADTRG input changes from "H" to "L" (or "L" to "H.") In this case, the pins that can be used for A-D conversion are AN0 to AN2 because the ADTRG pin is multiplexed with an analog voltage input pin, AN3. If an 7 6 5 4 3 2 0 1 0 A-D control register 0 Address 1E16 VREF connection Whether to connect the reference voltage input (VREF) with the resistor ladder network or not depends on bit 6 of the A-D control register 1. The VREF pin is connected when bit 6 is "0" and is disconnected when bit 6 is "1" (High impedance state). When A-D conversion is not performed, current from the VREF pin to the resistor ladder network can be cut off by disconnecting resistor ladder network from the VREF pin. Before starting A-D conversion, wait for 1 s or more after clearing bit 6 to "0". 7 6 5 4 3 2 1 0 0 0 A-D control register 1 A-D sweep pin select bit (Valid in the single sweep mode and repeat sweep mode.) 0 : AN0, AN1 (2 pins) 1 : AN0-AN3 (4 pins) Must be "0". Resolution select bit 0: 8-bit mode 1: 10-bit mode A-D conversion frequency (AD) select bit 1 External trigger polarity select bit (Valid when external trigger is selected.) 0: Falling edge 1: Rising edge VREF connection select bit 0 : VREF is connected. 1 : VREF is not connected. "0" at read. Analog input select bits (Valid in the one-shot and repeat modes.) 0 0 : Select AN0 0 1 : Select AN1 1 0 : Select AN2 1 1 : Select AN3 Must be "0". A-D operation mode select bits 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode Trigger select bit 0 : Software trigger 1 : External trigger due to ADTRG input A-D conversion start bit (Note 7) 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency (AD) select bit 0 A-D conversion frequency (AD) select bit Bit 1 Bit 0 0 0 1 0 Fig. 64 Bit configuration of A-D control register 0 68 Address 1F16 1 0 1 1 AD f2/4 f2/2 f2 f1 (Selectable only in 8-bit mode) MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Operation mode The operation mode is selected by bits 3 and 4 of A-D control register 0. The available operation modes are one-shot, repeat, single sweep, and repeat sweep. Analog input port pins are multiplexed with port P7 pins. Therefore, bits which correspond to pins for A-D conversion must be "0" (input mode). (1) One-shot mode One-shot mode is selected when bits 3 and 4 of A-D control register 0 are "0" is "0". The A-D conversion pins are selected with bits 0 and 1 of A-D control register 0. When a software trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to "1". When bit 3 of the A-D control register 1 is "1", A-D conversion ends after 59 AD cycles, and the interrupt request bit of the A-D interrupt control register is set to "1". At the same time, bit 6 of A-D control register 0 (A-D conversion start bit) is cleared to "0" and A-D conversion stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D conversion start bit is "1" and a valid edge is input to the ADTRG pin, This operation is the same as that for software trigger except that the A-D conversion start bit is not cleared after A-D conversion and a retrigger can be available during A-D conversion. (2) Repeat mode same time, A-D conversion start bit is cleared to "0" and A-D conversion stops. When an external trigger is selected, A-D conversion starts when the A-D conversion start bit is "1" and a valid edge is input to the ADTRG pin. In this case, the A-D conversion result which is stored in the A-D register 3 becomes invalid. The operation by external trigger is the same as that by a software trigger except that the A-D conversion start bit is not cleared to "0" after A-D conversion and that a retrigger can be available during A-D conversion. (4) Repeat sweep mode Repeat sweep mode is selected when bit 3 of A-D control register 0 is "1" and bit 4 is "1". The difference from the single sweep mode is that A-D conversion does not stop after conversion for all selected pins, but repeats again from the AN0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if a software trigger is selected, the A-D convension start bit is not cleared. The A-D register can be read at any time. Precautions for A-D conversion interrupt function Clear the interrupt request bit of the A-D interrupt control register (bit 3 at address 7016) before using an A-D interrupt. It is because this interrupt request bit is undefined just after reset. Repeat mode is selected when bit 3 of A-D control register 0 is "1" and bit 4 is "0". The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is generated in this mode. Furthermore, if a software trigger is selected, the A-D conversion start bit is not cleared. The contents of the A-D register can be read at any time. (3) Single sweep mode Single sweep mode is selected when bit 3 of A-D control register 0 is "0" and bit 4 is "1". In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pin is selected by bit 0 of the AD control register 1 (address 1F16). Two pins, or four pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with a software trigger or with an external trigger input. A software trigger is selected when bit 5 of the AD control register 0 (address 1E16) is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion is started when bit 6 of A-D control register 0 (A-D conversion start bit) is set to "1". When A-D conversion of all selected pins end, the interrupt request bit of the A-D conversion interrupt control register is set to "1". At the 69 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DMA CONTROLLER Pin description The DMA (direct memory access) controller is a 4-channel controller which provides high-speed data transfers from memory to memory, memory to input/output ports of external devices (herein referred to as external I/O), and external I/O to memory without using the CPU. Figure 65 shows the block diagram of the DMA controller, Figure 66 shows the DMA control-related register memory map, and Figure 67 shows the bit configuration of the DMAC control registers L and H. DMA transfers are performed by the DMA control circuit via the bus interface unit (BIU). Each of DMAC control registers L and H consists of 8 bits. For DMAC control register L, bit 0 is the priority select bit, and bit 1 is the TC pin validity bit. Bits 4 to 7 are DMAi request bits (i = 0 to 3). Reading these bits indicates whether a DMA request for each channel has occurred or not. For DMAC control register H, bits 0 to 3 are software DMA request bits, and each of them is used to generate a DMA request by software. Bits 4 to 7 are DMAi enable bits (i = 0 to 3). The DMA request is accepted only when the corresponding DMAi enable bit is set to "1". All of these DMAi enable bits are cleared to "0" after reset removal. Figure 68 shows the bit configuration of the DMAi control register (i = 0 to 3). Each channel of the DMAi control register consists of 8 bits. Bits 0 to 3 are DMA request source select bits. Bit 4 determines whether the edge or level sense function is to be used for selecting a request source from pin DMAREQi (DMA request input). Bit 5 is the DMAACKi validity bit. When bit 5 is "0", pin DMAACKi (the DMA acknowledge signal output pin) is invalid; when "1", pin DMAACKi is valid. Figure 69 shows the bit configuration of the DMAi mode registers L and H. Each channel of both registers consists of 8 bits. Refer to the corresponding section for more details. Pins DMAREQi, DMAACKi, TC are used for DMA transfers. Pin DMAREQi is a DMA request input pin. Port pins P61, P63, P65, and P6 6 are multiplexed with pins DMAREQ 0 , DMAREQ 1 , DMAREQ2 and DMAREQ3, respectively. These pins are used in order to request a DMA transfer from the external. When the DMA request source select bits (bits 0 to 3) of the DMAi control register are set to "0001", the input signal from this pin becomes the DMA request signal. In order to use any of the above pin as pin DMAREQi, be sure to set the corresponding bit of the port P6 direction register to the input mode. Pin DMAACKi is the DMA acknowledge signal output pin. Port pins P60, P62, P64 are multiplexed with pins DMAACK0, DMAACK1, and DMAACK2, respectively. When bit 5 (DMAACKi validity bit) of the DMAi control register for each channel is set to "1", pin DMAACKi serves as the output-only pin for signal DMAACKi. (DMA3 is not equipped with pin DMAACKi.) During DMA transfer, the operating channel acknowledge signal is output regardless of the data transfer method (the 1-bus cycle transfer or 2-bus cycle transfer). When the acknowledge signal is not needed, clear the DMAACKi validity bit to "0", so that pin DMAACKi can serve as an I/O pin. Pin TC is a terminal count pin and is multiplexed with port pin P42. Pin TC is valid when "1" has been written to bit 1 of the DMAC control register L. At this time, pin TC serves as the N-channel open drain output pin. When the value of the transfer counter register or transfer block counter is "0", pin TC outputs "L" level for 1 cycle of 1. Furthermore, when the TC pin validity bit is "1", any ongoing channel DMA transfer can be cancelled by changing the input level at pin TC from "H" to "L". 70 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Data transfer method Two different data transfer methods are available: 2-bus cycle transfer, effective for memory-to-memory data transfer, and 1-bus cycle transfer, effective for memory-to-I/O or I/O-to-memory data transfer. Both methods are described in detail below. (1) 2-bus cycle transfer When bit 1 of the DMAi mode register L, as shown in Figure 69, is cleared to "0", the 2-bus cycle transfer method is selected. This method makes data to be transferred by the "1 transfer unit", by using 1 read bus cycle and 1 write bus cycle. The "1 transfer unit" refers to the number of bits which can be transferred in 1 DMA transfer operation, and it is determined by bit 0 of the DMAi mode register L. When bit 0 is cleared to "0", "1 transfer unit" consists of 16 bits (2 bytes); when "1", "1 transfer unit" consists of 8 bits (1 byte). In the 2-bus cycle transfer, be sure to clear bit 0 of the DMAi mode register H to "0". Figure 70 shows an connection example with external memories in 2-bus cycle transfer. In the read cycle, the transfer source address is output to the address bus, and the data at this address is read out by the "1 transfer unit" and then stored into the BIU's data buffer. When 16-bit data is read out from an odd-numbered address or when 16bit data is read out with the external data bus width = 8 bits, the microcomputer will enter the write cycle after the above 16-bit data is stored into the BIU's data buffer in 2 accesses. In the write cycle, the transfer destination address is output to the address bus, and the data which has been stored in the BIU's data buffer is written to the transfer destination address. When 16-bit data is read out from an odd-numbered address or when 16-bit data is read out with the external data bus width = 8 bits, the microcomputer will preforms the write operation in 2 accesses. tween an external I/O and the external memory, this method allows the memory to be read at the same time the data is written to the external I/O, and vice versa, resulting in fast data transfer. Bit 0 of the DMAi mode register H determines whether the 1-bus cycle transfer is to be made from the external memory to the external I/O or from the external I/O to the external memory. When the bit is "1", the data transfer is made from the external I/O to the external memory. Figure 71 shows an connection example with external memories and external I/Os in 1-bus cycle transfer (the external data bus width = 16 bits and "1 transfer unit" = 16 bits). For the transfer from the external memory to external I/O, the external-memory-side address (transfer source address) is output to the address bus, pin RD goes to "L", and the read operation will be performed. This ensures that the data is read out from the external memory. At the same time, pin DMAACKi corresponding to the operating DMAi channel (i = 0 to 2) goes to "L", the external I/O is selected, and the data read from the external memory is directly fetched at the rising of signal RD. In this manner, data is transferred from external memory to external I/O in 1 bus cycle. For the transfer from the external I/O to the external memory, the data is read out from the external I/O, selected by the acknowledge signal from pin DMAACKi, to the data bus. At the same time, the external-memory-side address (transfer destination address) is output to the address bus, pin BLW (write signal for even-numbered addresses) and pin BHW (write signal for odd-numbered addresses) go to "L", and the write operation to the external memory is performed. The 1-bus cycle transfer cannot perform operations for a read from or a write to the internal memory. In order to perform the transfer from the internal memory to the external I/O or from the external I/O to the internal memory, be sure to select the 2-bus cycle transfer method. (2) 1-bus cycle transfer When bit 1 of the DMAi mode register L is set to "1", the 1-bus cycle transfer method is selected. When data transfer is to be made be- Internal address bus Incrementer/Decrementer Source address register 0 (SAR0) Destination address register 0 (DAR0) Source address register 1 (SAR1) Decrementer Destination address register 1 (DAR1) Transfer counter register 0 (TCR0) Source address register 2 (SAR2) Transfer counter register 1 (TCR1) Destination address register 2 (DAR2) Transfer counter register 2 (TCR2) Source address register 3 (SAR3) Transfer counter register 3 (TCR3) Destination address register 3 (DAR3) Bus Interface Unit (BIU) Internal address bus : DMA controller's bus : Internal bus Fig. 65 Block diagram of DMA controller 71 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address (Hexadecimal notation) Address (Hexadecimal notation) 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000C016 0000C116 0000C216 0000C316 0000C416 0000C516 0000C616 0000C716 0000C816 0000C916 0000CA16 0000CB16 0000CC16 0000CD16 0000CE16 0000CF16 0000D016 0000D116 0000D216 0000D316 0000D416 0000D516 0000D616 0000D716 0000D816 0000D916 0000DA16 0000DB16 0000DC16 0000DD16 0000DE16 0000DF16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA16 0000EB16 0000EC16 0000ED16 0000EE16 0000EF16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA16 0000FB16 0000FC16 0000FD16 0000FE16 0000FF16 DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register Fig. 66 DMA controll-related register memory map 72 Source address register 0 L M H Destination address register 0 L M H Transfer counter register 0 L M H DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 L M H Destination address register 1 L M H Transfer counter register 1 L M H DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 L M H Destination address register 2 L M H Transfer counter register 2 L M H DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 L M H Destination address register 3 L M H Transfer counter register 3 L M H DMA3 mode register L DMA3 mode register H DMA3 control register MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR 7 6 5 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 3 2 1 0 DMAC control register L Address B016 Priority select bit 0: Fixed. 1: Rotating. TC pin validity bit 0: Invalid. Pin P42 functions as a programmable I/O port (CMOS) pin. 1: Valid. Pin P42 functions as pin TC (N-channel open-drain). DMA0 request bit 0: No request. 1: Requested (Note). DMA1 request bit 0: No request. 1: Requested (Note). DMA2 request bit 0: No request. 1: Requested (Note). DMA3 request bit 0: No request. 1: Requested (Note). Note: Even when "1"s are written to bits 4 to 7 by software, these bits' status do not change. 7 6 5 4 3 2 1 0 DMAC control register H Address B116 Software DMA0 request bit 1: DMA request. Valid when the software DMA source is selected. The value is "0" at reading. Software DMA1 request bit 1: DMA request. Valid when the software DMA source is selected. The value is "0" at reading. Software DMA2 request bit 1: DMA request. Valid when the software DMA source is selected. The value is "0" at reading. Software DMA3 request bit 1: DMA request. Valid when the software DMA source is selected. The value is "0" at reading. DMA0 enable bit 0: Disabled. 1: Enabled. DMA1 enable bit 0: Disabled. 1: Enabled. DMA2 enable bit 0: Disabled. 1: Enabled. DMA3 enable bit 0: Disabled. 1: Enabled. Fig. 67 Bit configuration of DMAC control registers L and H 73 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL 7 6 0 0 5 4 3 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 2 1 0 DMA0 control register DMA1 control register DMA2 control register DMA3 control register Address CE16 DE16 EE16 FE16 DMA request source select bits 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note 1) (Used when both of the external source and burst transfer mode are selected.) 0 : Edge sense (Rising edge) 1 : Level sense ("L" level) DMAACKi validity bit (Note 2) 0 : Invalid. Pin DMAACKi functions as a programmable I/O port pin. 1 : Valid. Functions as pin DMAACKi are valid. The value is "0" at reading. Notes 1: Be sure to fix this bit to "0" in any of the following cases: * When the external source is selected by using bits 0 to 3 * In the cycle steal transfer mode Level sense can be selected only when both of the external source and burst transfer mode are selected. 2: DMA3 is not equipped with the DMAACK output function. For the DMA3 control register, be sure to clear this bit to "0". Fig. 68 Bit configuration of DMAi control register 74 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR 7 6 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 4 3 2 1 0 0 DMA0 mode register L DMA1 mode register L DMA2 mode register L DMA3 mode register L Address CC16 DC16 EC16 FC16 Transfer-unit-bit-number select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer (Note) Transfer mode select bit 0 : Burst transfer mode 1 : Cycle steal transfer mode Fix this bit to "0". Transfer-source-address-direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer-destination-address-direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Note: For the DMA3 mode register L, be sure to fix this bit to "0" (2-bus cycle transfer). In this case, 1-bus cycle transfer cannot be used. Additionally, be sure to fix this bit to "0" when either transfer source or transfer destination is in an internal area. In this case, also, 1-bus cycle transfer cannot be used. 7 6 5 4 3 2 1 0 0 0 0 0 0 DMA0 mode register H DMA1 mode register H DMA2 mode register H DMA3 mode register H Address CD16 DD16 ED16 FD16 Transfer destination select bit (Used in 1-bus cycle transfer.) (Note) 0 : From memory to I/O 1 : From I/O to memory The value is "0" at reading. Fix this bit to "0". The value is "0" at reading. Operating mode select bits 0 0 : Single transfer 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer Note: Be sure to fix this bit to "0" in 2-bus cycle transfer. Fig. 69 Bit configuration of DMAi control registers L and H 75 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION M37920 Address bus Data bus (D8 to D15) Data bus (D0 to D7) Transfer destination memory (odd-numbered address) Transfer destination memory (even-numbered address) Transfer source memory (odd-numbered address) Transfer source memory (even-numbered address) Address (Transfer source) Address (Transfer destination) RD BLW, BHW Data (Read) Data (Write) DMAACKi RD BHW BLW Note: External circuits are not considered. Fig. 70 Connection example with external memories in 2-bus cycle transfer M37920 Address bus Data bus (D8 to D15) Data bus (D0 to D7) Memory (odd-numbered address) Memory (even-numbered address) I/O Write/Read I/O DMA DMA acknowledge request Write/Read DMA DMA acknowledge Address (Memory) request RD RD BHW BLW DMAACKj DMAREQj Data (Read) DMAACKi Notes 1: External circuits are not considered. 2: When the external data bus width = 16 bits and "1 transfer unit" = 8 bits, 1-bus cycle transfer cannot be used for the transfer between a memory and I/O if they are connected to the different data buses (D0 to D7, D8 to D15), one for one. j = 0 to 2 Fig. 71 Connection example with external memories and external I/Os in 1-bus cycle transfer 76 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DMA request sources One out of fifteen DMA request sources can be selected for each channel. There are a total of fifteen DMA request sources. Thirteen internal request sources (A-D conversion, UART0 transmit/receive, UART1 transmit/receive, timers A0 to A4, timers B0 to B2), one software DMA source issued by programs, and one external source by input to pin DMAREQi. For DMA request source selection, use the DMAi control register's DMAi request source select bits (bits 0 to 3) as shown in Figure 68. Table 18 lists the relationship between DMA request source select bits (bits 0 to 3) and DMA request sources. The request timing is the same as that for interrupts. When the software DMA request source is selected with the DMA request source select bits, by writing "1" to any of the DMAC control register H's software DMA request bits (bits 0 through 3), the correspomding DMA request bit is set to "1". When a DMA request bit has been set to "1", the software DMA request bits are automatically cleared to "0". When the external source is selected with the DMA request source select bits, the input from pin DMAREQi sets the correspomding DMA request bit to "1". The DMA transfer request will not be accepted until both of the DMA request bit and DMA enable bit of the DMAC control registers L and H are "1". Therefore, if the DMA enable bit is "0", no DMA request will be accepted even when the DMA request bit is "1". Note that the DMA enable bit is "0" at reset. Therefore, after the DMA transfer parameter and other data have been setup, be sure to set the DMA enable bit of the DMA channel to be rendered valid to "1". This assures that the transfer request of that channel becomes valid, making the DMA transfer enabled. Transfer mode Two DMA transfer modes are available: burst transfer mode and cycle steal transfer mode. Mode selection is made variously for each channele, using bit 2 of the DMAi mode register L. When this bit is cleared to "0", the burst transfer mode is selected. This mode is automatically selected after reset removal. (1) Burst transfer mode In the burst transfer mode, either the edge sense or level sense mode can be selected only when the input from pin DMAREQi (ex- ternal source) is selected as a request source. When the DMAi control register's bit 4 is cleared to "0", the edge sense mode is selected. The edge sense mode is automatically selected after reset removal. In the edge sense mode, the DMA request bit is set to "1" at the falling edge of the input from pin DMAREQi. In the burst transfer's edge sense mode, the DMA request bit is cleared to "0" when any of the following conditions is satisfied. 1. Channel i's DMA enable bit is cleared to "0" (forced termination of transfer). 2. Channel i's DMA request bit is cleared to "0". 3. All of channel i's DMA transfers are completed (normal termination of transfer). 4. "L" level is input to pin TC during channel i's transfer (forced termination of transfer). Figure 72 shows a burst transfer example in edge sense mode. When a DMA request is received from a certain channel in the edge sense mode's burst transfer, no DMA request from the other channels will be accepted until the DMA transfer on the former channel is completed. In this example, pin DMAREQi's input (external source) is selected as the DMA request source. When pin DMAREQi's input changes from the "H" to "L" level during CPU operation, the DMA request bit will be set to "1" and the DMA controller will acquire the right to use bus and initiate transfer. From high to low, the bus use priority is for DRAM refresh, HOLD, DMA controller, and CPU. Therefore, if a request is made by the DRAM refresh, which has a higher priority than the DMA controller, the DMA controller halts any ongoing transfer operation at the end of the current transfer bus cycle and passes the right to use bus to the DRAM controller as shown in Figure 72. Upon getting the right, the DRAM controller generates the refresh cycle. When refreshing is terminated, the DMA controller resumes the execution of the interrupted DMA transfer at the point of interruption. Once a DMA request is accepted in the burst transfer mode, no request from the other channels is accepted until the DMA transfer is entirely completed or the transfer operation is brought to a forced stop. Therefore, even when the request bit of channel 0, which has a high priority, is set to "1" in the middle of transfer as shown in Figure 72, such a request will not be accepted. (The priority is explained in the next section.) Table 18. Relationship between DMA request source select bits (bits 3 to 0) and DMA request sources b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DMA request source Do not select. External source (DMAREQi) Software DMA source Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion 77 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION When channel 1's DMA transfer is entirely completed, the right to use bus is once passed to the CPU, and the DMA transfer request from channel 0 is later accepted at the end of the current bus cycle. When bit 4 of the DMAi control register is set to "1", the level sense mode is selected. The level sense mode can be used only for the DMA request from pin DMAREQi. When selecting another source, be sure to select the edge sense mode. In the level sense mode, the DMAi request bit is set to "1" to initiate the DMA transfer only while pin DMAREQi's input level is "L". If pin DMAREQi's input level returns to "H" in the middie of transfer, the DMA operation is interrupted at the end of the current transfer bus cycle or next transfer bus cycle so that the right to use bus is returned to the CPU. At this time, the DMA enable bit is not cleared. When pin DMAREQi's input level returns to "L", the transfer operation is resumed at the address which is next to the point of interruption. In the level sense mode, the DMA request bit varies only with the input level at pin DMAREQi. Therefore, while pin DMAREQi's input level is "L", the DMA request bit remains to be "1" even if the transfer is completed. Figure 73 shows a burst transfer example in level sense mode. When pin DMAREQi's input level for channel 1 changes from "H" to "L" during CPU operation, the DMA1 request bit will be set to "1" so that the DMA controller will acquire the right to use bus and initiate transfer. When pin DMAREQi's input level returns to "H", the DMA1 request bit is cleared to "0". This causes the DMA transfer operation to be interrupted and returns the right to use bus to the CPU. DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user (CPU) DMA1 DRAM refresh DMA1 Channel 1 entire data transfer DMA0 (CPU) Channel 0 entire data transfer The above example applies on the following conditions : * DMA request sources of DMA0 and DMA1: external source (edge sense) * Channel priority : fixed (channel 0 > channel 1) Fig. 72 Burst transfer example (in edge sense mode) DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user (CPU) DMA1 DRAM (CPU) refresh DMA0 DMA1 The above example applies on the following conditions : * DMA request sources of DMA0 and DMA1: external source (level sense) * Channel priority : fixed (channel 0 > channel 1) Fig. 73 Burst transfer example (in level sense mode) 78 (CPU) MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (2) Cycle steal transfer mode When bit 2 of the DMAi mode register L is set to "1", the cycle steal transfer mode is selected. In the cycle steal transfer mode, be sure to select the edge sense mode. When a DMA request occurs in the cycle steal transfer mode, the corresponding DMA request bit is set to "1" as in the burst transfer mode. When the DMA request from the channel is accepted, DMA transfer starts. However, the DMA request bit is automatically cleared to "0" at the start of the first DMA transfer cycle. Therefore, if there is no DMA request from any channel when 1-transfer-unit data has been transferred, the DMA controller returns the right to use bus to the CPU. If there is a DMA request from a channel, the DMA controller continues to use the bus and initiates DMA transfer for the channel. In the cycle steal transfer mode, the priorities of the channels are detected at all times to assure that the DMA request from a channel having the highest priority is accepted to initiate the DMA transfer execution. The DMA request bit is cleared to "0", at each time when 1-transfer-unit data has been transferred. At this time, however, the DMA enable bit will not be cleared to "0" although the DMA request bit is cleared to "0" at each transfer of 1 transfer unit. Therefore, when the DMA request bit is set to "1" next, transfer is resumed at the point of interruption. When the transfer counter register's value is "0" in the single transfer, or when both of the transfer counter register's value and transfer block counter's value are "0" in the array chain transfer, the DMA enable bit will be cleared to "0" to terminate the whole DMA transfer operation. Figure 74 shows an example of cycle steal transfer. When pin DMAREQi's input level changes from "H" to "L", the DMA1 request bit will be set to "1" and the DMA controller will acquire the right to use bus and initiate DMA transfer. The DMA1 request bit is cleared to "0" when the channel 1 transfer cycle starts. Therefore, if there is no DMA transfer request from the other channels, the DMA controller returns the right to use bus to the CPU at the end of 1 transfer cycle. In the example shown in Figure 74, however, DMA0 transfer cycle execution continues because the channel 0's request bit is set to "1". When the DMA0 transfer cycle is terminated, the DMA request bits of all channels are cleared to "0" so that the DMA controller returns the right to use bus to the CPU. When the DMA1 request bit is set to "1", only one cycle of transfer operation is performed. Even if the DMA1 request bit is cleared to "0" at this time, the DMA1 request bit is set to "1" again to perform continuous transfer, as long as pin DMAREQi's input level goes "L" before the end of the next transfer cycle. In the cycle steal transfer, the priorities of individual channels are detected at the end of each transfer cycle. Therefore, if the request is issued from channel 0, which has a higher priority than channel 1, channel 0 transfer is executed first. Furthermore, if a request to use bus which has a higher priority (for example, a refresh request from the DRAM controller) is generated, this request takes the precedence. DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user (CPU) DMA1 DMA0 (CPU) DMA1 DMA1 DMA0 DRAM refresh DMA1 (CPU) The above example applies on the following conditions : * DMA request sources of DMA0 and DMA1: external source * Channel priority : fixed (channel 0 > channel 1) Fig. 74 Example of cycle steal transfer 79 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Priority Priorities are assigned to all DMA channels. Either the fixed or rotative priority can be selected. When bit 0 (priority select bit) of the DMAC control register is cleared to "0", the fixed priority is selected. Note that the fixed priority is automatically selected after the reset removal. In the fixed priority, the channels are given fixed priorities and DMA transfer is executed in the order of priority. From high to low, the priorities are assigned to channels 0, 1, 2, and 3. As indicated in Figure 76, the priorities are detected at each cycle in the cycle steal transfer mode or when the first DMA request is accepted in the burst transfer mode. When bit 0 of the DMAC control register is set to "1", the rotative pri- ority is selected. From high to low, the initial priorities are assigned to channels 0, 1, 2, and 3 as is the case with the fixed priority. When a DMA transfer for one channel is normally terminated with the rotative priority employed, the priorities are rotated in such a manner that the channel, for which transfer has just been completed, has the lowest priority. For example, when channel 0's transfer is normally terminated as shown in Figure 75, the priorities are rotated upon completion of transfer so that the new priorities are, in decreasing order, channel 1, channel 2, channel 3, and channel 0. The priorities remain unchanged when DMA transfer is forcibly terminated by pin TC's input or the DMA enable bit clearance, etc. (1) Before start of transfer (after reset removal) Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 3 Channel 0 Channel 1 Channel 2 (2) After completion of channel 0's transfer (3) After completion of channel 2's transfer Fig. 75 Rotative priority 80 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Priority level: fixed 1 DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority :0>1>2>3 1 DMA-transfer-executing channel 2 0 1 3 (None) 0 2 1 1 0 3 Priority level: rotating 1 DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 3 0>1>2>3 2 2>3>0>1 0 0>1>2>3 (None) 3>0>1>2 3 1>2>3>0 1 0>1>2>3 3 0>1>2>3 2 2>3>0>1 1 0>1>2>3 3>0>1>2 2>3>0>1 DMA-transfer-executing channel 0>1>2>3 Channel priority 1 3 3 The above applies on the following conditions : * No DRAM refresh request, no Hold request. * All of DMAi enable bits are "1". Fig. 76 Example of channel priority detection 81 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Transfer address direction The address direction in DMA transfers can be designated independently for the transfer source and destination. These directions are available: "forward", "backward", and "fixed". When the forward direction is selected, the address increments. When the backward direction is selected, the address decrements. When the fixed direction is selected, the address is fixed (2 bytes when 1 transfer unit consists of 16 bits, or 1 byte when 1 transfer unit consists of 8 bits) and does not change. Use bits 4 and 5 of the DMAi mode register L shown in Figure 69 to specify the transfer address direction for the transfer source. For the transfer destination, use bits 6 and 7. Figure 77 shows an example of transfer address direction in the 2bus cycle transfer (1 transfer unit = 16 bits). Figure 77-(1) shows an example when the transfer source address direction is "forward" and the destination addresses are "fixed". In this setup, the transfer source memory's data is called up in the forward address direction and written to the transfer destination memory's fixed address by the "1 transfer unit". Figure 77-(2) shows an example when both the transfer source and destination address directions are set to "forward" by using the DMAi mode register L. In this type of setup, data are transferred from the transfer source memory to the transfer destination memory in the sequence of , , , .... Figure 77-(3) shows an example when the transfer source address direction is "forward" and the destination address direction is "backward". Figure 77-(4) shows an example when the transfer source address direction is "backward" and the destination address is "fixed". In this setup, the transfer source memory's data is written to the fixed transfer destination memory's address by the "1 transfer unit" in the sequence of , , and .... As explained above, in 2-bus cycle transfer, three different address directions are selectable for each of the transfer source and destination. A total of nine different address direction combinations are available. In 1-bus cycle transfer, the memory side's address direction depends on the memory bits. For data transfer from memory to external I/O, therefore, use bits 4 and 5 (transfer-source-address-direction select bits) of the DMAi mode register L to determine the memory side's (transfer source) address direction. This is not affected by bits 6 and 7 (transfer-destination-address-direction select bits). For data transfer from external I/O to memory, use bits 6 and 7 of the DMAi mode register L to determine the memory side's (transfer destination) address direction. This is not affected by bits 4 and 5. 82 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION External data bus width: 16 bits or 8 bits Address direction Transfer unit: 16 bits (Note) Transfer source (1) Forward Data arrangement Transfer in transfer source destination memory Transfer order Data arrangement in transfer destination memory (transfer result) Transfer unit: 8 bits Data arrangement in transfer source memory Low order 1 High order 2 Low order 3 Low order Data 1 1 Data 2 2 Data 3 3 Data 1 to 3 High order Data 2 High order Data 4 Low order Data 5 Data 3 5 6 Forward Low order 1 Data 1 High order Low order Low order 2 High order Low order Low order 3 High order Data 2 Low order Low order Data 4 Low order 5 Data 5 Data 3 6 Data 2 Data 3 Data 4 Data 5 High order Data 6 Low order Data 1 1 Data 6 Data 2 2 Data 5 Data 3 3 Data 4 High order Data 4 4 5 Data 3 Low order Data 5 6 Data 2 High order Low order 2 Data 2 High order Data 3 4 Data 1 Data 6 Data 3 1 High order Data 2 3 Data 3 (3) Forward Backward Low order 2 Data 2 High order Data 3 1 Data 1 Data 1 High order Data 2 Data 1 Data 1 to 6 4 Data 6 High order 3 Data 1 High order (4) Backward Data arrangement in transfer destination memory (transfer result) Fixed Data 1 (2) Forward Transfer order High order Data 6 Low order Data 6 Data 1 Fixed Low order Data 3 High order Low order 3 2 1 Data 1 to 3 High order Data 5 Data 4 Data 2 High order Data 3 Low order Data 2 Data 1 High order 6 5 4 3 Data 1 to 6 2 1 Data 1 Note: The relationship of position between 16-bit data's high-order byte and its low-order byte is fixed, regardless of the address direction. (Data is transferred by the 16 bits.) Fig. 77 Example of address directions and transfer results in 2-bus cycle transfer (1 transfer unit = 16 bits) 83 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DMA continuous transfer (1) Single transfer mode In the single transfer mode, only the preselected number of bytes are transferred. As shown in Figure 69, first, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the DMAi mode registers L and H. Then, write the transfer source block's first transfer address (the block's lowest address in the forward or fixed transfer address direction, or the block's highest address in the backward address direction) into the source address register (hereinafter referred to as SAR). Further, write the destination block's first transfer address (the lowest address in the forward or fixed transfer address direction, or the highest address in the backward transfer address direction) into the destination address register (hereinafter referred to as DAR). Also write the desired number of bytes to be transferred, into the transfer counter register (hereinafter referred to as TCR). Write the value 1 or more into TCR. Each of SAR, DAR, and TCR consists of 24 bits, therefore, be sure to write into all these bits. The SAR, DAR, and TCR are located at the addresses shown in Figure 66. The next is to set a DMA source and others by the DMAi control register shown in Figure 68. Set up bit 0 (priority select bit) and bit 1 (TC pin validity bit) of the DMAC control register L shown in Figure 67, and finally set the DMAC control register H's DMA enable bit to "1" so as to make the DMA request acceptable. When the contents of TCR are cleared to "0", the terminal count signal (TC) is output, and at the same time, the interrupt request bit of the DMA interrupt control register is set to "1". To forcedly terminate the DMA transfer, input "L" level to pin TC or write the value "0" to the DMA enable bit. At this time, the interrupt request bit of the DMA interrupt control register is not set to "1". Figure 78 shows a timing diagram example in the single transfer mode on the following conditions: * Transfer unit: 16 bits * Transfer method: 2-bus cycle transfer * Transfer mode: Burst transfer mode (edge sense) * Transfer source address direction: Forward. * Transfer destination address direction: Forward. * Transfer source wait: 0 wait * Transfer destination wait: 0 wait 84 As 2-bus cycle transfer mode is selected, a read operation is performed in the first bus cycle. First, the address written into the SAR is output to the address bus and then inputted into the incrementor/ decrementor (hereinafter referred to as I/D). The I/D adds 1 or 2 to the inputted address and outputs the result back to the SAR. If one 16-bit transfer operation is not enough to complete the read operation, the read operation is performed within 2 bus cycles to achieve the purpose. The operation is performed in the next bus cycle. First, the address written in the DAR is output to the address bus and then inputted into the I/D. The I/D adds 1 or 2 to the inputted address and outputs the result back to the DAR. If one 16-bit transfer operation is not enough to complete the write operation, the write operation is performed within 2 bus cycles to achieve the purpose. The operation performed so far is called the write cycle. The data stored in the BIU's data latch in the read cycle is output to the data bus in the write cycle and written into the destination memory or external I/O. The operations performed so far complete the transfer of 1 transfer unit. In the 2-bus cycle transfer, the read and write cycle combination is called the DMA transfer cycle. DMA transfer is executed by repeating the DMA transfer cycle. In the 2-bus cycle transfer, the TCR varies in the read cycle. The remaining transfer bytes are read from the TCR in concurrence with address output from SAR in the read cycle and inputted into the decrementor (hereinafter referred to as D). The D subtracts 1 or 2 from the number of remaining bytes and outputs the result back to the TCR. In this manner, the contents of the TCR decrease each time when 1-transfer-unit data has been transferred. When the number of remaining bytes, which was read from the TCR, becomes "0", the DMA controller outputs the terminal count signal (TC) to pin TC, and at the same time, sets the interrupt request bit of the DMA interrupt control register to "1". At this time, the DMA enable bit is cleared to "0". As the burst transfer mode is selected in this example, the DMA request bit is also cleared to "0". To forcedly terminate transfer, input "L" level to pin TC (P42) or write the value "0" to the DMA enable bit. In the single transfer, the first values written in the SAR, DAR, and TCR are retained in the internal latches. Therefore, if DMA transfer is to be performed under the same conditions, it can be initiated simply by setting the DMA enable bit to "1". MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 1 ALE RD BLW BHW A0-A23 (CPU) sar dar sar + 2 dar + 2 sar + 4 dar + 4 D0-D7 Data0L Data0L Data1L Data1L Data2L Data2L D8-D15 Data0H Data0H Data1H Data1H Data2H Data2H (CPU) DMAACKi TC Read cycle Terminate processing Write cycle Transfer of 1 transfer unit This example applies on the following conditions: Transfer source memory External data bus width : 16 bits Transfer unit : 16 bits sar L Transfer method : 2-bus cycle transfer Data0 Transfer source address direction : Forward H Transfer destination address direction : Forward Transfer source area's wait : 0 wait L Data1 Transfer destination area's wait : 0 wait H : Value which has been set to SARi (even) sar dar : Value which has been set to DARi (even) L Data2 Value which has been set to TCR :6 H Bus user : CPU DMAC CPU sar + 5 Transfer destination memory dar Data0 L H Transfer Data1 L H Data2 L H dar + 5 Fig. 78 Timing diagram example in single transfer mode (burst transfer mode) 85 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (2) Repeat transfer mode In the repeat transfer mode, the single transfer is repeated. First, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the DMAi mode register L. Next, write the transfer source block's transfer start address in the SAR and the transfer destination block's transfer start address in the DAR. Further, write the desired number of bytes to be transferred, into the TCR, and set up the DMAi control register and DMAC control register. The DMA request is now acceptable. When the DMA request occurs in this state, DMA transfer starts. Even when the number of remaining bytes, which was read from the TCR, becomes 0, the DMA enable bit is not cleared to "0". When the burst transfer mode is selected, the DMA request bit is not cleared to "0", also. When the cycle steal transfer mode is selected, the DMA request bit is cleared to "0" each time when 1-transfer-unit data has been transferred. The values written in the SAR, DAR, and TCR first are retained in the internal latches. The contents of the latches are transferred to the SAR, DAR and TCR at the end of the last transfer cycle. Therefore, when the burst transfer mode is selected, the transfer operation is repeated starting with the values written first. When the cycle steal transfer mode is selected, these values are used as the initial values and transfer is performed each time the DMA request bit is set to "1". To forcedly terminate transfer, input "L" level to the pin TC or write the value "0" to the DMA enable bit. In the repeat transfer mode, TC signal output and the setting the interrupt request bit of the DMA interrupt control register to "1" are not performed. Figure 78 shows the timing diagram example in the repeat transfer mode. 1 ALE RD BLW BHW A0-A23 (CPU) sar dar sar + 4 dar + 4 sar dar D0-D7 Data0L Data0L Data2L Data2L Data0L D8-D15 Data0H Data0H Data2H Data2H Data0H DMAACKi TC H Transfer of 1 transfer unit Transfer of entire data (first) This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source area's wait : 0 wait Transfer destination area's wait : 0 wait sar : Value which has been set to SARi (even) dar : Value which has been set to DARi (even) Value which has been set to TCR :6 Bus user : CPU DMAC Fig. 79 Timing diagram example in repeat transfer mode (burst transfer mode) 86 Transfer of entire data (second) Transfer source memory sar Data0 Transfer destination memory dar L Data0 H Data1 L Transfer Data1 H Data2 L H L Data2 H sar + 5 L H L H dar + 5 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Transfer source's transfer start address 1 4 bytes Transfer destination's transfer start address 1 4 bytes Number of transfer bytes 1 4 bytes Transfer source's transfer start address 2 Transfer destination's transfer start address 2 Number of transfer bytes 2 Transfer source's transfer start address 3 Transfer destination's transfer start address 3 Number of transfer bytes 3 Transfer source's transfer start address 4 Transfer destination's transfer start address 4 Number of transfer bytes 4 Fig. 80 Parameter memory map example in array chain transfer mode Transfer source's transfer start address (L) Transfer source's transfer start address (M) Even-numbered address Transfer parameters for 1 block Transfer source's transfer start address (H) Dummy byte Transfer destination's transfer start address (L) Transfer destination's transfer start address (M) Transfer destination's transfer start address (H) Number of transfer bytes (L) Number of transfer bytes (M) Number of transfer bytes (H) Transfer parameter address (L) Transfer parameter address (M) Transfer parameter address (H) Necessary only in link array chain transfer. (H) = High order, (M) = Middle order, (L) = Low order Fig. 81 Parameter memory format Transfer parameters for 1 block In the array chain transfer mode, one channel is used for the data transfer for two or more memory blocks. Three parameters necessary for transfer, that is, the transfer source's transfer start address, transfer destination's transfer start address, and the number of transfer bytes, must be sequentially written into the transfer parameter memory. The transfer parameter memory can be located in an arbitrary position in the memory space. Figure 80 shows a transfer parameter memory map example in the array chain transfer mode. All of the transfer parameters of the memory blocks to be transferred must be written into the transfer parameter memory. The transfer parameter memory format is shown in Figure 81. For 1-bus cycle transfer, the external I/O side's parameters are not needed. For transfer from external memory to external I/O, for instance, consecutively write the transfer source start addresses and the number of transfer bytes only, as shown in Figure 82. As the transfer destination's transfer start addresses need not be written, it is possible to save the transfer time and transfer parameter memory area. In the single and repeat transfer modes, the values written in the SAR, DAR, and TCR first are retained in the internal latches. In the array chain transfer and link array chain transfer modes, however, these latches perform different functions. The SAR latch serves as the transfer parameter register (hereinafter referred to as TPR), which indicates the start address of the transfer parameter memory. The TCR latch serves as the transfer block counter (hereinafter referred to as TBC), which indicates the number of transfer blocks. In the array chain transfer and link array chain transfer modes, writing a value to an SAR address causes that value to be written in the TPR, and writing a value to a TCR address causes that value to be written in the TBC. The array chain transfer operations are detailed below. In the array chain transfer mode, also, first, set up the DMAi mode register, DMAi control register, and DMAC control register. Write the start address of the transfer parameter memory into the SAR. This value is then written into the TPR. Be sure that an even-numbered address is set to the start address. Nothing needs to be written into the DAR. Into the TCR, write the desired number of memory blocks to be transferred. This number is then written into the TBC. When the DMA enable bit is set to "1" after completion of the above setup, DMA transfer becomes enabled. Transfer parameters for 1 block (3) Array chain transfer mode Transfer source's transfer start address 1 4 bytes Number of transfer bytes 1 4 bytes Transfer source's transfer start address 2 Number of transfer bytes 2 Transfer source's transfer start address 3 Number of transfer bytes 3 Transfer source's transfer start address 4 Number of transfer bytes 4 Fig. 82 Transfer parameter memory in 1 bus cycle transfer 87 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION In the array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the SAR, DAR, and TCR. This operations state is called the "array state". Figures 83 and 84 show timing diagram examples in the array chain transfer mode (burst transfer mode). The DMA controller outputs the start address of the transfer parameter memory to the address bus, and sequentially stores the read data into the SAR, DAR, and TCR. When the transfer parameters for 1 block are completely stored, the contents of the TBC are decremented by 1, and then, the first DMA transfer starts in accordance with the stored parameters. These operations for storing parameters are called "array state". In contrast to the array state, the state in which DMA transfer is active is called "transfer state". In the transfer state, the same operations are performed as in the single transfer mode. Each time when 1-transfer-unit data has been transferred, the contents of the TCR are decremented by 1 in 8-bit transfer or by 2 in 16-bit transfer. Even when the contents of the TCR become 0, the DMA request bit and DMA enable bit are not cleared to "0" and the array state of the next block starts. When the contents of the TBC are 0 at the start of the array state, the entire transfer operation is considered to be completed, and "L" level is output into pin TC to clear the DMA request bit and DMA enable bit and terminate array chain transfer. At the same time, the interrupt request bit of the DMA interrupt control register is set to "1". In the cycle steal transfer at the array chain transfer mode, one array state and transfer cycle of 1 transfer unit are made by one DMA request. 88 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Continue to Figure 84. 1 ALE RD BLW BHW A0-A23 (CPU) tp tp + 2 tp + 4 tp + 6 tp + 8 tp + 10 sa1 da1 da1 + m - 2 D0-D7 sa1L sa1H da1L da1H mL mH DataL DataL DataL D8-D15 sa1M Dummy data da1M Dummy data mM Dummy data DataH DataH DataH DMAACKi TC H Transfer of 1 transfer parameter Transfer of 1 transfer unit Array state This example applies on the following conditions: : 16 bits External data bus width : 16 bits Transfer unit : 2-bus cycle transfer Transfer method : Forward Transfer source address direction Transfer destination address direction : Forward : 1 wait Transfer source area's wait : 1 wait Transfer destination area's wait : 0 wait Transfer parameter memory's wait : Transfer parameters (even) sa1, sa2, da1, da2 : Start address of first block's transfer tp parameter memory :2 Transfer block's number : CPU DMAC CPU Bus user Transfer state Memory tp sa1 tp + 4 da1 tp + 8 m tp + 12 sa2 tp + 16 da2 tp + 20 n Memory First block's transfer parameters Memory sa1 da1 First block transfer sa1 + m - 1 sa1 + m Second block's transfer parameters da1 + m - 1 da1 + m sa2 da2 Second block transfer sa2 + n - 1 sa2 + n da2 + n - 1 da2 + n The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is "1", and is accepted. Fig. 83 Timing diagram example in array chain transfer mode (burst transfer mode) (1) From proceeding Figure 83. 1 ALE RD BLW BHW A0-A23 tp + 12 tp + 20 tp + 22 sa2 da2 + n - 4 sa2 + n - 2 da2 + n - 2 D0-D7 sa2L nL nH DataL DataL DataL DataL D8-D15 sa2M nM Dummy data DataH DataH DataH DataH (CPU) DMAACKi TC Terminate Processing Array state Transfer state Fig. 84 Timing diagram example in array chain transfer mode (burst transfer mode) (2) 89 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Figure 85 shows the perameter memory map in the link array chain transfer mode. As shown in this figure, not only the transfer source's transfer start address, transfer destination's transfer start address, and number of transfer bytes, but also the start address of the memory block which contains the next transfer parameters is stored. In the transfer parameter of the last block, be sure to set "00000016" as the start address of the next transfer parameter. For 1-bus cycle transfer, the external I/O side's parameters are not needed. In the link array chain transfer, also, the DMAi mode registers L and H, DMAi control register, and DMAC control registers L and H must be set up. Into the SAR, write the start address of the memory block that stores the parameters for the first transfer. This value is then written into the TPR. Be sure that an even-numbered address is set to the start address. Nothing needs to be written in the DAR. Write the value 1 or more into the TCR. When the DMA enable bit is set to "1" after completion of the above setup, DMA transfer becomes enabled. In the link array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the SAR, DAR, and TCR. Further, the start address of the memory block that contains the next parameters has been written into the TPR. In the link array chain transfer mode, the state so far is referred to as the array state. The DMA controller sequentially outputs the transfer parameters to the address bus, beginning with the start address of the memory block, storing the transfer parameters. The read data are sequentially stored into the SAR, DAR, and TCR, and then the start address of the memory block, containing the next parameters, is written into the TPR. A DMA transfer is made in accordance with the parameters read from the transfer parameter memory. The transfer state is the same as in the single transfer mode. The contents of the TCR are decremented by 1 or 2 each time when 1-transfer-unit data has been transferred. Even when the contents of the TCR become 0, the DMA request bit and DMA enable bit are not cleared to "0" but the array state starts again. When the contents of the TPR are 0 at this time, however, "L" level is output into pin TC to clear the DMA request bit and DMA enable bit to "0" and terminate the link array chain transfer. At the same timing, the interrupt request bit of the DMA interrupt control register is set to "1". In the cycle steal transfer at the link array chain transfer mode, one array state and the transfer cycle of 1 transfer unit are made by one DMA request. Figures 86 and 87 show timing diagram examples in the link array chain transfer mode (burst transfer mode). 90 Transfer parameters for 1 block (4) Link array chain transfer mode Transfer parameter address 4 Transfer source's transfer start address 1 Transfer destination's transfer start address 1 Number of transfer bytes 1 Transfer parameter address 2 Transfer source's transfer start address 4 Transfer destination's transfer start address 4 Number of transfer bytes 4 Transfer parameter address 5 Transfer parameter address 3 Transfer source's transfer start address 3 Transfer destination's transfer start address 3 Number of transfer bytes 3 Transfer parameter address 4 Transfer parameter address 2 Transfer source's transfer start address 2 Transfer destination's transfer start address 2 Number of transfer bytes 2 Transfer parameter address 3 Fig. 85 Parameter memory map example in link array chain transfer mode MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Continue to Figure 87. 1 ALE RD BLW H BHW A0-A23 tp1 (CPU) D0-D7 D8-D15 DMAACKi sa1L sa1H sa1M Dummy data tp1 + 4 tp1 + 6 da1L da1H da1M Dummy data tp1 + 8 tp1 + 10 mL mH mM Dummy data tp1 + 12 tp1 + 14 (tp1+8) tp2LM tp2H (tp1 tp2M Dummy data H H TC tp1 + 2 Transfer of 1 transfer parameter Array state This example applies on the following conditions: Memory : 16 bits External data bus width sa1 tp1 : 16 bits Transfer unit : 2-bus cycle transfer Transfer method tp1 + 4 da1 : Forward Transfer source address direction tp1 + 8 m Transfer destination address direction : Forward tp2 tp1 + 12 : 0 wait Transfer source area's wait : 0 wait Transfer destination area's wait : Transfer parameters (even) sa1, sa2, da1, da2 sa2 tp2 : Start address of first block's tp1 da2 tp2 + 4 transfer parameter memory tp2 + 8 n :2 Transfer block's number : CPU DMAC CPU Bus user tp2 + 12 00000016 Memory Memory da1 sa1 First block transfer First block's transfer parameter da1 + m - 1 da1 + m sa1 + m - 1 sa1 + m da2 sa2 Second block transfer Second block's transfer parameter da2 + n - 1 da2 + n sa2 + n - 1 sa2 + n Fig. 86 Timing diagram example in link array chain transfer mode (burst transfer mode) (1) From preceding Figure 86. 1 ALE RD BLW BHW A0-A23 sa1 da1 da1 + m - 2 tp2 tp2 + 14 sa2 da2 + n - 4 sa2 + n - 2 da2 + n - 2 D0-D7 DataL DataL DataL sa2L 0016 DataL DataL DataL DataL D8-D15 DataH DataH DataH sa2M Dummy data DataH DataH DataH DataH (CPU) DMAACKi TC Terminate processing Transfer of 1 transfer unit Transfer state Array state Transfer state Fig. 87 Timing diagram example in link array chain transfer mode (burst transfer mode) (2) 91 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DRAM CONTROLLER The DRAM controller directly accesses the DRAM located in the external chip select area (CS1, CS2, CS3). Figure 88 shows the block diagram of the DRAM controller. Table 19 shows the functions of the DRAM-related signals, and Table 20 shows the relationship between the external data bus width and the multiplexed addresses. The start address, block size, external data bus width, and DRAM space of the chip select area, which is to be accessed by the DRAM controller, are specified by the CSj control register L, CSj control register H, and the area CSj start address register in the chip select wait controller. For more details, refer to the section on the chip select wait controller. Figure 89 shows the bit configuration of the CSj control register L with use of the DRAM controller. Bit 4 is the DRAM space designation bit. When bit 4 is set to "1", pins A8/MA0 to A16/MA8, A18/MA9, A20/MA10, A22/MA11, and P94 to P96, become the output pins for the DRAM control signals. Figure 90 shows the bit configuration of the DRAM control register. Bit 0 is the byte control select bit. When the device type of DRAM to be connected is 1CAS/2W, be sure to clear this bit to "0", and when the device type of DRAM to be connected is 2CAS/1W, be sure to set this bit to "1". When the external data bus width = 8 bits, however, be sure to clear this bit to "0". Table 21 shows the relationship between the byte control select bit and the pin functions. Each of Figures 91 and 92 shows an operating waveform example of the DRAM control signals, address bus, and data buses with 1CAS/2W or 2CAS/1W selected. Bit 4 of the DRAM control register is the self-refresh operation select bit and controls the DRAM self-refresh operation in the stop mode; "0" disables the self-refresh operation in the stop mode, and "1" enables the self-refresh operation. Bit 7 is the refresh timer count start bit. The refresh timer starts counting when this bit is set to "1". Figure 94 shows an operating waveform example of the DRAM control signals at refresh. This refreshing method, as shown in Figure 94, is the "CAS before RAS refresh". This method makes signal CAS falls before signal RAS falls. The refresh interval is determined by the refresh timer (address A916). The refresh timer is an 8-bit timer performing a repetitive count with the reload register. The clock source is internal clock f32. The refresh time issues a refresh request to the BIU each time when the refresh timer's count value reaches 0016. Therefore, the relationship between the value to be loaded into the refresh timer, n (n = 0116 to FF16), and DRAM refresh interval, m (s), is as follows: n = {m f(XIN) / 32} - 1 Once the BIU accepts a refresh request, it performs the bus arbitration for the CPU and DMAC and outputs the refresh enable signal to the DRAM controller. Accordingly, the DRAM controller makes the refresh cycle (CAS before RAS refresh). In the stop mode, since the refresh timer stops counting and the DRAM controller cannot perform the refresh operation (CAS before RAS refresh). For DRAM supporting the self-refresh operation, by setting the selfrefresh operation select bit to "1" before going into the stop mode, the self-refresh operation in the stop mode can be enabled. 92 Figure 95 shows an operating waveform example of the DRAM control signals at self-refresh. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Bus Interface Unit (BIU) Refresh request Chip select wait controller 1/16 Address DRAM space designation bit Valid/Invalid 1/2 (Address A916) Refresh timer 1/ (n + 1) DRAM control register (Address A816) b7 RASj CAS (UCAS/LCAS) DRAM control signal generating circuit W (WRH/WRL) Address multiplexer b0 MA0-MA11 DRAM controller DRAM space designation bit: bit 4 at addresses 8216, 8416, 8616 j = 1 to 3 Fig. 88 Block diagram of DRAM controller Table 19. Functions of DRAM-related signals Functions External data bus width = 8 bits External data bus width = 16 bits Multiplexed address output MA0-MA11 RASj (j = 1 to 3) "L" when a row address is output. LCAS "L" when a column address at an even-numbered address is output. "L" when a row address is output. CAS UCAS "L" when a column address at an odd-numbered address is output. "H" output (Fixed) "L" when data at an even-numbered address is written. "L" when data is written. WRL W WRH "L" when data at an odd-numbered address is written. "H" output (Fixed) Signal Table 20. Relationship between external data bus width and multiplexed addresses Output signal Pin name External data Row address bus width = 8 bits Column address Row address External data bus width = 16 bits Column address A8/MA0 A9/MA1 A10/MA2 A11/MA3 A12/MA4 A13/MA5 A14/MA6 A15/MA7 A16/MA8 A18/MA9 A20/MA10 A22/MA11 A8 A0 A8 A9 A1 A9 A10 A2 A10 A11 A3 A11 A12 A4 A12 A13 A5 A13 A14 A6 A14 A15 A7 A15 A16 A17 A16 A18 A19 A18 A20 A21 A20 A22 A23 A22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A19 A21 : These signals are not used. 93 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL 7 6 5 4 3 1 0 0 1 X SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 2 1 0 0 1 CS1 control register L CS2 control register L CS3 control register L Address 8216 8416 8616 Area CSj wait number select bits 0 1 : 1 wait External data bus width select bit 0 : 16-bit width 1 : 8-bit width Invalid. (It may be "0" or "1".) DRAM space designation select bit 1: DRAM space Burst ROM access select bit 0 : Normal access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CSj. CSj output select bit 1 : CSj output is enabled. (Port pin P9j functions as pin CSj. RAS output is enabled.) Note: In order to use the DRAM controller, setup for bits 0, 1, 4 to 7 are necessary as above. Fig. 89 Bit configuration of CSj control register L with use of DRAM controller (j = 1 to 3) 94 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR 7 6 5 0 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 4 3 2 1 0 0 0 0 DRAM control register Address A816 Byte control select bit (Note) 0 : 1CAS/2W 1 : 2CAS/1W The value is "0" at reading. Fix this bit to "0". The value is "0" at reading. Self-refresh operation select bit (Self-refresh operation in the stop mode is controlled.) 0 : Disabled. 1 : Enabled. The value is "0" at reading. Refresh timer count start bit 0 : Counting stopped. 1 : Counting started. Note: When the external data bus width = 8 bits, be sure to set this bit to "0" (1CAS/2W). Fig. 90 Bit configuration of DRAM control register Table 21. Relationship between byte control select bit and pin functions Byte control select bit Pin 1 (2CAS/1W) 0 (1CAS/2W) P94 CAS W P95 WRL LCAS P96 UCAS WRH 95 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address (Note) 1 RASj(CSj) CAS Row address Address Column address Column address Row address WRL WRH D0-D7 RD (even) WD (even) D8-D15 RD (odd) WD (odd) At reading At writing Note: When DRAM is continuously accessed with the fast page access OFF, 1 cycle of 1 will be inserted between bus cycles. Fig. 91 Operating waveform example of DRAM control signals, address bus, and data buses with 1CAS/2W selected Operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address (Note) 1 RASj(CSj) LCAS UCAS Address Row address Column address Row address Column address W D0-D7 RD (even) WD (even) D8-D15 RD (odd) WD (odd) At reading At writing Note: When DRAM is continuously accessed with the fast page access OFF, 1 cycle of 1 will be inserted between bus cycles. Fig. 92 Operating waveform example of DRAM control signals, address bus, and data buses with 2CAS/1W selected 96 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Bus request (DRAMC) sampled 1 RASj CAS H W j = 1 to 3 (Preceding bus cycle) Refresh cycle (Next bus cycle) Fig. 94 Operating waveform example of DRAM control signals at CAS before RAS refresh Stop mode f(XIN) 1 BIU Interrupt request to be used for stop mode termination (Interrupt request bit) Wf32 2048 counts FFF16 Value of watchdog timer 7FF16 RASj CAS H W (Preceding bus cycle) Refresh cycle (Interrupt request which has been used for stop mode termination) Fig. 95 Operating waveform example of DRAM control signals at self-refresh 97 I MITSUBISHI MICROCOMPUTERS Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION REAL-TIME OUTPUT Each of these microcomputers is equipped with the 8-bit real-time output function. Whether to use the real-time output function is decided by the waveform output select bits of the 8-bit real-time output control register (bits 0 and 1 at address A016). (See Figure 96.) Also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address A016) and is used in one of the following ways: * 4 bits 2 channels * 6 bits 1 channel + 2 bits 1 channels (low-order 4 bits at address A216), which corresponds to RTP03 to RTP00, is output to these ports each time when the contents of timer A0 counter becomes "000016". When "0" is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter contents of the timer which corresponds to the bit becomes "000016": when "1" is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing. 7 (1) Pulse mode 0 When the pulse output mode select bit is cleared to "0", the microcomputer enters pulse output port is controlled by 2 groups of 4 bits. Figures 97 and 98 show the pulse output data register 0/1 (address A216/A416) bit configuration and real-time output structure in pulse mode 0, respectively. When the waveform output select bits are set to "01" (bit 1 = "0" and bit 0 = "1"), RTP03 to RTP00 become pulse output port pins, in other words, RTP0 is selected. When the waveform output select bits are set to "10" (bit 1 = "1" and bit 0 = "0"), RTP13 to RTP10 become pulse output port pins, in other words, RTP1 is selected. When the waveform output select bits are set to "11" (bit 1 = "1" and bit 0 = "1"), two groups consisting of RTP13 to RTP10 and RTP03 to RTP00 become pulse output port pins, in other words, RTP1 and RTP0 are selected. When the waveform output select bits are set to "00" (bit 1 = bit 0 = "0"), port P5 pins become normal programmable I/O port pins. The contents of the pulse output data register 1 (high-order 4 bits at address A416), which corresponds to RTP13 to RTP10, is output to these ports each time when the contents of timer A1 counter becomes "000016". The contents of the pulse output data register 0 7 6 5 4 3 2 1 Address 0 Pulse output data register 0 A216 RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit (Note 1) RTP03 pulse output data bit (Note 1) Note 1: Used only in pulse mode 0 2: Used only in pulse mode 1 Fig. 97 Bit configuration of pulse output data register 98 6 5 4 3 2 1 0 0 0 0 0 0 Real-time output register Address A016 Waveform output select bits 00 : Programmable I/O port 01 : RTP0 selected When pulse mode 0 is selected: RTP0 When pulse mode 1 is selected: RTP01, RTP00 10 : RTP1 selected When pulse mode 0 is selected: RTP1 When pulse mode 1 is selected: RTP1, RTP03, RTP02 11 : RTP1 and RTP0 selected When pulse mode 0 is selected: RTP1 and RTP0 When pulse mode 1 is selected: RTP1, RTP03, RTP02 and RTP01, RTP00 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 "0" at read. Fig. 96 Bit configuration of real-time output control register 7 6 5 4 3 2 1 Address 0 Pulse output data register 1 A416 RTP02 pulse output data bit (Note 2) RTP03 pulse output data bit (Note 2) RTP10 pulse output data bit RTP11 pulse output data bit RTP12 pulse output data bit RTP13 pulse output data bit MITSUBISHI MICROCOMPUTERS RY A N IMI M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer A2 Pulse output mode select bit (Address A016) Pulse output data register 1 (Address A416) D7 D6 Data bus (Even) D5 D4 T D Q T D Q T D Q T D Q 0 a P57/RTP13 a P56/RTP12 a P55/RTP11 a P54/RTP10 Waveform output select bit (Address A016) D3 D2 D1 D0 D Q T D Q T D Q T D Q T a P53/RTP03 a P52/RTP02 a P51/RTP01 a bit 1 P50/RTP00 Waveform output select bit (Address A016) bit 0 Pulse output data register 0 (Address A216) Timer A0 a Port P5i direction register (Address D16) "1" Port P5i latch (i = 7 to 0) (Address B16) "0" Fig. 98 Real-time output structure in pulse mode 0 (2) Pulse mode 1 When the pulse output mode select bit is set to "1", the microcomputer enters pulse mode 1, and a pulse output port pins are separately controlled (6 bits and 2 bits). Figure 99 shows the real-time output structure in pulse mode 1. When the waveform output select bits are set to "01" (bit 1 = "0" and bit 0 = "1"), RTP13 to RTP10, RTP03, and RTP02 become programmable I/O port pins. Simultaneously, RTP01 and RTP00 become pulse output port pins. When the waveform output select bits are set to "10" (bit 1 = "1" and bit 0 = "0"), RTP13 to RTP10, RTP03, and RTP02 become pulse output port pins. At this time, RTP01 and RTP00 become programmable I/O port pins. When the waveform output select bits are set to "11" (bit 1 = bit 0 = "1"), pulse output port pins are divided into two groups; one consists of RTP13 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00. When the waveform output select bits are set to "00" (bit 1 = bit 0 = "0"), port P5 pins become normal programmable I/O port pins. RTP13 to RTP10, RTP03, and RTP02 are controlled by timer A2. Also, RTP01 and RTP00 are controlled by timer A0. The contents of the pulse output data register 1 (high-order 6 bits at address A416), which corresponds to RTP13 to RTP10, RTP03, and RTP02, are output to this port each time when the contents of timer A2 counter becomes "000016". The contents of the pulse output data register 0 (low-order 2 bits at address A216), which corresponds to RTP01 and RTP00, are output to this port each time when the contents of timer A0 counter become "000016". 99 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer A2 Pulse output mode select bit (Address A016) Pulse output data register 1 (Address A416) D7 D6 D5 Data bus (Even) D4 D3 D2 T D Q T D Q T D Q T D Q T D Q T D Q 1 a P57/RTP13 a P56/RTP12 a P55/RTP11 a P54/RTP10 a P53/RTP03 a P52/RTP02 Waveform output select bit (Address A016) D1 D0 D Q T D Q T a P51/RTP01 a P50/RTP00 Pulse output data register 0 (Address A216) Timer A0 bit 1 Waveform output select bit (Address A016) a bit 0 Port P5i direction register (Address D16) "1" Port P5i latch (i = 7 to 0) "0" (Address B16) Fig. 99 Real-time output structure in pulse mode 1 Table 22 lists the port P5/RTP pin output when all of the port P5 direction registers are set to the output mode. Precautions for real-time output function After reset, the port P5 direction register is set to the input mode, and port P5i (i = 0 to 7) pins function as normal I/O port pins. When using these pins as real-time output port pins, set the corresponding bits of the port P5 direction register to the output mode. Additionally, by reading the real-time output port's value from the port P5 register, output level of pins can be read out. Table 22. Port P5/RTP pin output Real-time output control register (Address A016) bit bit bit 2 1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 Store address for port P5/RTP pin output data bit 7 0B 0B A4 A4 0B 0B A4 A4 bit 6 0B 0B A4 A4 0B 0B A4 A4 bit 5 0B 0B A4 A4 0B 0B A4 A4 bit 4 0B 0B A4 A4 0B 0B A4 A4 Address 0B16: Port P5 Address A216: Pulse output data register 0 Address A416: Pulse output data register 1 100 bit 3 0B A2 0B A2 0B 0B A4 A4 bit 2 0B A2 0B A2 0B 0B A4 A4 bit 1 0B A2 0B A2 0B A2 0B A2 bit 0 0B A2 0B A2 0B A2 0B A2 MITSUBISHI MICROCOMPUTERS RY A N IMI M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION WATCHDOG TIMER The watchdog timer is used to detect unexpected execution sequence caused by software runaway and others. Figure 100 shows the block diagram of the watchdog timer. The watchdog timer consists of a 12-bit binary counter. The watchdog timer counts clock Wf32, which is obtained by dividing the peripheral devices' clock f2 by 16; or clock Wf512, which is obtained by doing it by 256. The watchdog timer frequency select register (bit 0 = watchdog timer frequency select bit) shown in Figure 101 selects which clock is to be counted. Wf512 is selected when this bit 0 is "0", and Wf32 is selected when this bit 0 is "1". This bit 0 is cleared to "0" after reset. FFF16 is set in the watchdog timer when "L" level voltage is applied to pin RESET, STP instruction is executed, data is written to the watchdog timer register (address 6016), or the most significant bit of the watchdog timer becomes "0". After FFF16 is set in the watchdog timer, when the watchdog timer counts Wf32 or Wf512 by 2048 counts, the most significant bit of watchdog timer becomes "0", the watchdog timer interrupt request bit is set to "1", and FFF16 is set again in the watchdog timer. In program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes "0". If this routine is not executed owing to unexpected program execution or others, the most significant bit of the watchdog timer be- comes "0" and an interrupt is generated. The microcomputer can generate a reset pulse by writing "1" to bit 6 (software reset bit) of processor mode register 0 in an interrupt routine and can be restarted. The watchdog timer can also be used to return from the STP state, where a clock has stopped its operation owing to the STP instruction execution. For details, refer to the sections on the clock generating circuit. The watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled: * When the external area is accessed in the hold state * In the wait mode * In the stop mode 7 5 4 3 2 0 Address 6116 Watchdog timer frequency select bit 0 : W f512 is selected. 1 : W f32 is selected. Fig. 101 Bit configuration of watchdog timer frequency select register Watchdog timer frequency select bit f2 1 Watchdog timer frequency select register Access to external area HLDA DMA transfer Wait mode 6 Wf32 1 1/16 1/16 At the STP instruction execution, however, Wf32 is selected compulsorily. Watchdog timer interrupt request Watchdog timer Wf512 0 "FFF16" is set. Disables watchdog timer Writing to watchdog timer register RESET 1 STP instruction External clock input select bit 0 * Watchdog timer register : address 6016 * Watchdog timer frequency select register : bit 0 at address 6116 When the most significant bit of the watchdog timer becomes "0", this signal will be generated. Fig. 100 Block diagram of watchdog timer 101 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION How to disable watchdog timer When not using the watchdog timer, it can be disabled. When the watchdog timer is disabled, it's operation stops and no watchdog timer interrupt has been generated. Setting for disabling the watchdog timer is possible by writing "7916" and "5016" to the particular function select register 2 (address 6416) sequentially with the following instructions: * MOVMB/STAB instruction, or * MOVM/STA instruction (m = 1) If any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is performed. (Also, reset is the only one method to remove the setting for disabling the watchdog timer.) 102 MITSUBISHI MICROCOMPUTERS RY A N IMI M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Stop and Wait mode The stop (hereafter called STP) and the wait (hereafter called WIT) modes are used to save the power dissipation of the system, by stopping oscillation or system clock in the case that the CPU needs not be operating. The microcomputer enters the STP or WIT mode by executing the STP or WIT instruction, and either mode is terminated by acceptance of an interrupt request or reset. To terminate the STP or WIT mode by an interrupt request, the interrupt to be used for termination of the STP or WIT mode must be enabled in advance to execution of the STP or WIT instruction. The interrupt priority level of this interrupt is required to be higher than the processor interrupt priority level (IPL) of the routine where the STP or WIT instruction will be executed. Figures 102 and 103 show the bit configurations of the particular function select registers 0, 1. Setting the STP instruction invalidity select bit (bit 0 of the particular function select register 0) to "1" invalidates the STP instruction, and the STP instruction will be ignored. After reset is removed, since the above bit is cleared to "0", however, the STP instruction is valid. The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the particular function select register 1) is set to "1" by the execution of the STP or the WIT instruction, and so, after the STP or WIT mode has been terminated, each bit will indicate that the STP or WIT instruction has been executed. Accordingly, each of these bits must be cleared to "0" by software at termination of the STP or the WIT mode. Table 23 lists the microcomputer's operation in the STP and WIT modes. STP mode The execution of the STP instruction stops the oscillation circuit. It also stops clock source , 1, BIU, CPU, and divide clocks f1() to f4096, Wf32 and Wf512 in the "L" state. In the watchdog timer, "FFF16" is automatically set, and regardless the contents of watchdog timer frequency select bit (bit 0 at address 6116), the count source of the watchdog timer becomes Wf32. This setting is terminated by clearance of the most significant bit of the watchdog timer or reset, and the count source is back to the one which was selected with the watchdog timer frequency select bit. In the STP mode, the A-D converter, DMA controller, DRAM controller (Reflesh timer is also stopped.), and watchdog timer, which use divide clocks f1() to f4096, Wf32 and Wf512, are stopped. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active only while an external clock is selected. The STP mode is terminated by acceptance of an interrupt request or reset, and the oscillation restarts. Supply of clock source , 1, divide clocks f1() to f4096, Wf32 and Wf512 is also restarted. When the oscillation is restarted by the interrupt request acceptance, BIU and CPU are stopped at "L" level until the most significant bit of the watchdog timer, which is counted down with divide clock Wf32, is cleared to "0". Note that, when the oscillation is restarted, supply of BIU and CPU starts immediately after the oscillation restarts. Therefore, the reset input must be raised to "H" after the enough oscillation-stabilizing time has elapsed. The system where a stable clock is input from the external to pin XIN is equipped with the mode where an instruction can be executed immediately after the STP mode termination. For details, refer to the section on "Stop of oscillation circuit" of the power saving function. WIT mode When the WIT instruction is executed with the internal clock stop select bit at WIT (bit 3 of the particular function select register 1 in Figure 103) = "0", BIU, CPU, and divide clocks Wf32 and Wf512 are stopped in the "L" state. However, the oscillation circuit, clock source , 1, and divide clocks f1() to f4096 remain operating. Therefore, BIU, CPU, and DMA controller are stopped, whereas timers A and B, serial I/O, and the A-D converter, which use the divide clocks f1() to f4096, are still operating. Because the reflesh timer of the DRAM con- Table 23. Microcomputer's operation in STP and WIT modes Instruction STP Internal clock stop select bit at WIT Operations in WIT and STP modes Oscillation , 1, Wf32, Wf512 BIU, CPU Peripheral devices using f1() to f4096, Wf32, Wf512 circuit f1() to f4096 Timers A, B: Operation is enabled only in the event counter mode. Serial I/O: Operation is enabled only while an external clock is selected. A-D converter, DMA controller: Stopped. DRAM controller: Stopped. (Reflesh timer is also stopped.) (Watchdog timer: Stopped.) -- Stopped Stopped ("L") Stopped ("L") Stopped ("L") "0" Active Active Stopped ("L") Stopped ("L") Timers A, B, Serial I/O, A-D converter: Operation is enabled. DRAM controller: Reflesh timer is operated. DMA controller: Stopped. (Watchdog timer: Stopped.) Stopped ("L") Timers A, B: Operation is enabled only in the event counter mode. Serial I/O: Operation is enabled only while an external clock is selected. A-D converter, DMA controller: Stopped. DRAM controller: Reflesh timer is operated. (Watchdog timer: Stopped.) WIT "1" Active Stopped ("L") Stopped ("L") 103 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION troller is operating, DRAM reflesh is performed. Note that the watchdog timer is stopped. On the other hand, when the WIT instruction is executed with the internal clock stop select bit at WIT = "1", the oscillation circuit is operating, while BIU, CPU, and divide clocks f1() to f4096 stop operating. As a result, the A-D converter, DMA controller, and watchdog timer, which use divide clocks f1() to f4096, Wf32 and Wf512, are stopped. Because the reflesh timer of the DRAM controller is operating, DRAM reflesh is performed. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active 7 6 5 4 3 2 1 only while an external clock is selected. If the internal peripheral devices are not used in the WIT mode, the latter is better because the current dissipation is more saved. Note that the internal clock stop select bit at WIT is to be set to "1" immediately before execution of the WIT instruction and cleared to "0" immediately after the WIT mode is terminated. The WIT state is terminated by acceptance of an interrupt request, and then, supply of BIU and CPU will restart. Since the oscillation circuit is operating in the WIT mode, an interrupt processing can be executed just after the WIT mode termination. 0 Particular function select register 0 Address 6216 STP instruction invalidity select bit 0: STP instruction is valid. 1: STP instruction is invalid. External clock input select bit (Note) 0: Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1: Oscillation circuit is inactive. (Clock which is generated in the external is input.) Watchdog timer is not used at stop mode termination. "0" at read. Note: Writing to these bits requires the following procedure: * Write "5516" to this register. (The bit status does not change only by this writing.) * Succeedingly, write "0" or "1" to each bit. Fig. 102 Bit configuration of particular function select register 0 7 6 5 4 3 2 1 0 Particular function select register 1 Address 6316 STP-instruction-execution status bit (Note 1) 0: Normal operation. 1: STP instruction has been executed. WIT-instruction-execution status bit (Note 1) 0: Normal operation. 1: WIT instruction has been executed. Standby state select bit 0: External bus 1: Programmable I/O port Internal clock stop select bit at WIT (Note 2) 0: In wait mode, internal peripheral devices' operation clock is active. 1: In wait mode, internal peripheral devices' operation clock is stopped. "0" at read. Notes 1: At power-on reset, this bit becomes "0". At hardware reset or software reset, this bit retains the status just before reset. Even when "1" is written, the bit status will not change. 2: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the WIT state is terminated, this bit must be cleared to "0" immediately. Fig. 103 Bit configuration of particular function select register 1 104 MITSUBISHI MICROCOMPUTERS RY A N IMI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION POWER SAVING FUNCTION (3) Stop of oscillation circuit The following functions can save the power dissipation of the whole system. When an externally-generated-stable clock is input to pin XIN, the power dissipation can be saved if both of the following conditions are met: * the external clock input select bit (bit 1 of the particular function select register 0) = "1". * the oscillation driver circuit between pins XIN and XOUT stops its operation. At this time, the output level at pin XOUT is fixed to "H". When the STP mode is terminated by an interrupt request occurrence, the watchdog timer is not used. Therefore, an instruction can be executed just after the termination of the STP mode. For details, refer to the section on the clock generating circuit and stop and wait modes. (1) Bus fixation in STP and WIT modes By setting the standby state select bit (bit 2 of the particular function select register 1) to "1", in the stop or wait state, the I/O pins of the external buses and bus control signals can be switched to programmable I/O port pins. By setting these pins' state with the corresponding port registers and port direction registers, unnecessary current will not flow between the microcomputer and external devices. As a result, in the stop or wait mode, the power dissipation of the whole system can be saved. Table 24 lists the correspondence between the external buses, bus control signals, and programmable I/O port pins. This function is valid only in the stop or wait state. At termination of the stop or wait mode, the original functions of external buses and bus control signals become valid. Table 24. Correspondence between external buses, bus control signals, and programmable I/O port pins Standby state select bit External buses, Bus control signals 0 1 A0 to A7, A8 to A15, A16 to A23 A0 to A7, A8 to A15, A16 to A23 D0 to D7, D8 to D15 D0 to D7, P10 to P17 (Note 2), D8 to D15 (Note 1) P20 to P27 RD, BLW, BHW RD, BLW, BHW (Note 1) P31, P32 (Note 2), P33 CS0 CS0 P90 (Note 2) P100 to P107 (Note 2), P110 to P117 (Note 2), P00 to P07 (Note 2) (4) Disconnection from pin VREF When not using the A-D converter, by setting the VREF connection select bit (bit 6 of the A-D control register 1) to "1", the ladder network of the A-D converter will be disconnected from the reference voltage input pin (VREF). In this case, no current flows from pin VREF to the ladder network, and the power dissipation can be saved. Note that, after the VREF connection select bit changes from "1" (VREF disconnected) to "0" (VREF connected), be sure that the A-D conversion starts a period of 1 s or more has elapsed. For details, refer to the section on the A-D converter. Notes 1: When the external data bus width = 8 bits (BYTE = VCC level), this becomes a programmable I/O port pin, regardless of the standby state select bit's contents. 2: Pin functions of port pins P0, P1, P31, P32, P90, P10, P11 are not shown in the pin configuration. However, relationship with corresponding bus signals and ports is listed in Table 24. For the addresses of these port's registers and direction registers, refer to the location of the perpheral devices' control register (Figures 4 and 5). (2) Stop of internal clock in wait mode In the WIT mode, if the internal peripheral devices need not to be operated, be sure to set the internal clock stop select bit at WIT (bit 3 of the particular function select register 1) to "1". As a result, the clock source for each internal peripheral device is stopped, and the power dissipation of the microcomputer can be saved. For details, refer to the section on the Stop and Wait modes. 105 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address Address Port P0 direction register (0416)*** 0016 Processor mode register 0 (5E16)*** (Note 2) 0 0 0 1 0 Port P1 direction register (0516)*** 0016 Processor mode register 1 (5F16)*** 0 0 Port P2 direction register (0816)*** 0016 Watchdog timer Port P3 direction register (0916)*** 0 0 0 0 Port P4 direction register (0C16)*** Port P5 direction register (0D16)*** Port P6 direction register (1016)*** Port P7 direction register (Note 2) (6016)*** (Note 2) 0 1 (Note 2) 0 0 FFF16 Watchdog timer frequency select register (6116)*** 0 0 0 0 0 0 Particular function select register 0 (6216)*** 0 0 0016 Particular function select register 1 (6316)*** 0 0 (Note 3) 0 0 0 0 0 0 0 Debug control register 0 (6616)*** 1 (Note 3) (1116)*** 0 0 0 0 Debug control register 1 (6716)*** 0 0 0 (Note 3) Port P8 direction register (1416)*** 0 0 0 0 0 0 0 INT3 interrupt control register (6E16)*** 0 0 0 0 Port P9 direction register (1516)*** 0 0 0 0 0 0 0 INT4 interrupt control register (6F16)*** 0 0 0 0 Port P10 direction register (1816)*** 0016 A-D conversion interrupt control register (7016)*** ? 0 0 0 Port P11 direction register (1916)*** 0016 UART 0 transmit interrupt control register (7116)*** 0 0 0 0 Port P12 direction register (1C16)*** 0 0 0 UART 0 receive interrupt control register (7216)*** 0 0 0 0 A-D control register 0 (1E16)*** 0 0 0 0 0 ? ? ? UART 1 transmit interrupt control register (7316)*** 0 0 0 0 A-D control register 1 (1F16)*** UART 1 receive interrupt control register (7416)*** 0 0 0 0 UART 0 Transmit/Receive mode register (3016)*** 0016 Timer A0 interrupt control register (7516)*** 0 0 0 0 UART 1 Transmit/Receive mode register (3816)*** 0016 Timer A1 interrupt control register (7616)*** 0 0 0 0 UART 0 Transmit/Receive control register 0 (3416)*** 0 0 0 0 1 0 0 0 Timer A2 interrupt control register (7716)*** 0 0 0 0 UART 1 Transmit/Receive control register 0 (3C16)*** 0 0 0 0 1 0 0 0 Timer A3 interrupt control register (7816)*** 0 0 0 0 UART 0 Transmit/Receive control register 1 (3516)*** 0 0 0 0 0 0 1 0 Timer A4 interrupt control register (7916)*** 0 0 0 0 UART 1 Transmit/Receive control register 1 (3D16)*** 0 0 0 0 0 0 1 0 Timer B0 interrupt control register (7A16)*** 0 0 0 0 Count start register (4016)*** 0016 Timer B1 interrupt control register (7B16)*** 0 0 0 0 One-shot start register (4216)*** 0 0 0 0 0 0 Timer B2 interrupt control register (7C16)*** 0 0 0 0 Up-down register (4416)*** 0 0 0 0 0 0 0 0 INT0 interrupt control register (7D16)*** 0 0 0 0 0 0 Timer A clock division select register (4516)*** INT1 interrupt control register (7E16)*** 0 0 0 0 0 0 Timer A0 mode register (5616)*** 0016 INT2 interrupt control register (7F16)*** 0 0 0 0 0 0 Timer A1 mode register (5716)*** 0016 Processor status register PS 0 0 0 ? ? 0 0 0 1 ? ? Timer A2 mode register (5816)*** 0016 Program bank register PG Timer A3 mode register (5916)*** 0016 Program counter PCH Contents at address FFFF16 Timer A4 mode register (5A16)*** 0016 Program counter PCL Contents at address FFFE16 Timer B0 mode register (5B16)*** 0 0 ? 0 0 0 0 Direct page registers DPR0 to DPR3 Timer B1 mode register (5C16)*** 0 0 ? 0 0 0 0 Data bank register DT Timer B2 mode register (5D16)*** 0 0 ? 0 0 0 0 Stack pointer 0 0 0 0 0 0 1 0 0 0 0 0 (Note 3) 0016 000016 0016 FFF16 Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: At power-on reset, these bits are clear to "0". At hardware or software reset, on the other hand, these bits retain the state just before reset. Fig. 104 Microcomputer internal register's status just after reset (1) 106 MITSUBISHI MICROCOMPUTERS RY A N IMI M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address Address CS0 control register L (8016)*** CS0 control register H (8116)*** CS1 control register L (8216)*** 0 1 0 0 0 CS1 control register H (8316)*** 0 CS2 control register L (8416)*** 0 1 0 0 0 CS2 control register H (8516)*** 0 CS3 control register L (8616)*** 0 1 0 0 0 CS3 control register H (8716)*** Area CS0 start address register DMAC control register H (B116)*** 0 0 0 0 0 0 0 0 0 0 1 DMA0 interrupt control register (B216)*** 0 0 0 0 1 0 DMA1 interrupt control register (B316)*** 0 0 0 0 0 0 0 DMA2 interrupt control register (B416)*** 0 0 0 0 1 0 DMA3 interrupt control register (B516)*** 0 0 0 0 0 0 0 DMA0 mode register L (CC16)*** 0 0 0 0 0 0 0 0 1 0 DMA0 mode register H (CD16)*** 0 0 0 0 0 0 0 0 DMA0 control register (CE16)*** 0 0 0 0 0 0 0 0 (8A16)*** 0 0 0 1 0 0 0 0 DMA1 mode register L (DC16)*** 0 0 0 0 0 0 0 0 Area CS1 start address register (8C16)*** 0 0 0 0 0 0 0 0 DMA1 mode register H (DD16)*** 0 0 0 0 0 0 0 0 Area CS2 start address register (8E16)*** 0 0 0 0 0 0 0 0 DMA1 control register (DE16)*** 0 0 0 0 0 0 0 0 Area CS3 start address register (9016)*** 0 0 0 0 0 0 0 0 DMA2 mode register L (EC16)*** 0 0 0 0 0 0 0 0 Flash memory control register (9E16)*** DMA2 mode register H (ED16)*** 0 0 0 0 0 0 0 0 Real-time output control register (A016)*** 0 0 0 0 0 0 0 0 DMA2 control register (EE16)*** 0 0 0 0 0 0 0 0 DRAM control register (A816)*** 0 0 0 0 0 0 0 0 DMA3 mode register L (FC16)*** 0 0 0 0 0 0 0 0 CTS/RTS separate select register (AC16)*** 0 0 0 0 0 0 0 0 DMA3 mode register H (FD16)*** 0 0 0 0 0 0 0 0 DMAC control register L (B016)*** 0 0 0 0 0 0 0 0 DMA3 control register (FE16)*** 0 0 0 0 0 0 0 0 (Note 2) 1 0 0 (Note 3) (Note 3) (Note 3) (Note 3) 1 0 0 0 0 0 0 0 0 0 1 Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: While Vss level voltage is applied to pin BYTE, these bits are "0". While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are "1". Fig. 105 Microcomputer internal register's status just after reset (2) RESET CIRCUIT While the power source voltage satisfies the recommended operating condition, reset state is removed if pin RESET's level returns from the stabilized "L" level to the "H" level. As a result, program execution starts from the reset vector address. This reset vector address is expressed as shown below: * A23 to A16 = 0016 * A15 to A8 = Contents at address FFFF16 * A7 to A0 = Contents at address FFFE16 Figures 104 and 105 show the microcomputer internal register's status just after reset, and Figure 106 shows an operation example of the reset circuit. Apply "L" level voltage to pin RESET for a period (2 s or more) under the following conditions: * Pin Vcc's level satisfies the recommended operating condition. * Oscillator's operation has been stabilized. VCC level VCC 0V RESET 0.2VCC level 2 s 0V f(XIN) 0V Power on Oscillation stabilized Fig. 106 Operation example of reset circuit (Note that proper evaluation is necessary in the system development stage.) 107 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION INPUT/OUTPUT PINS Each of ports P0 to P12 has an direction register, and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is "1", and an input pin when it is "0". When a pin is programmed as an output pin, the data written to its port latch is output to the output pin. When a pin is programmed as an output pin, the contents of the port latch are read out instead of the value of the pin. Accordingly, a previously output value can be read out correctly even when the output "H" voltage is lowered or the output "L" voltage is raised, owing to an external load, etc. A pin programmed as an input pin is placed in the flooting state, and the value input to the pin can be read out correctly. When a pin is programmed as an input pin, the data can be written only in the port latch, and the pin remains floating. Each of Figures 107 and 108 shows the block diagram for each port pin. 108 MITSUBISHI MICROCOMPUTERS RY A N IMI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION [Inside dotted-line not included] P00 to P07, P10 to P17, P20 to P27, P31 to P33, P100 to P107, P110 to P117 [Inside dotted-line included] P30/RDY, P43/HOLD, P61/TA1IN/DMAREQ0, P63/TA3IN/DMAREQ1, P65/TA4IN/DMAREQ2, P66/DMAREQ3, P81/RxD1, P85/RxD0, P120/INT0/TB0IN, P121/INT1/TB1IN, P122/INT2/TB2IN Direction register Data bus Port latch Direction register P40/ALE, P41/1, P44/HLDA, P60/TA1OUT/DMAACK0, P62/TA3OUT/DMAACK1, P64/TA4OUT/DMAACK2, P80/TxD1, P84/TxD0, P90/CS0, P91/CS1/RAS1, P92/CS2/RAS2, P93/CS3/RAS3, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS "1" Output (Internal peripheral devices) Data bus Direction register [Inside dotted-line not included] P52/RTP02, P53/RTP03, P54/RTP10, P55/RTP11 [Inside dotted-line included] P51/TA0IN/RTP01, P57/TA2IN/RTP13 Port latch Data bus Port latch Latch Timer underflow signal P50/TA0OUT/RTP00, P56/TA2OUT/RTP12 Q T CK Direction register "1" Output (Internal peripheral devices) Data bus Port latch Latch Timer underflow signal T Q CK Fig. 107 Block diagram for each port pin (1) 109 I . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION [Inside dotted-line not included] P70/AN0, P71/AN1 [Inside dotted-line included] P72/AN2/INT3, P73/AN3/ADTRG/INT4 Direction register Data bus Port latch Analog input "1" "0" P82/CTS0/CLK1, P83/CTS0/RTS0, P86/CLK0 Direction register Output (Internal peripheral devices) Data bus P42/TC Port latch Direction register "0" Data bus Fig. 108 Block diagram for each port pin (2) 110 Output (TC) Port latch MITSUBISHI MICROCOMPUTERS RY A N IMI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CLOCK GENERATING CIRCUIT In the clock generating circuit, the basic clock which is used to operate the CPU and each internal peripheral device is made by a clock input from pin XIN. Figure 111 shows the block diagram of the clock generating circuit. The clock which is input from the external clock input pin, XIN, generates the following; * , which is used to operate the microcomputer * BIU, which is used to operate the BIU * CPU, which is used to operate the CPU is stopped only when the external clock input is disabled by STP instruction. BIU is stopped when to STP or WIT instruction is executed. Also, CPU is stopped when STP or WIT instruction is executed or when a CPU wait request is issued by the BIU. f1() is the basic clock for internal peripheral devices. This basic clock is divided furthermore in the divide circuit, as shown in Figure 111, and some frequency types are generated. Serial I/O communication and timer B can use any of four clocks (f2, f16, f64, f512), respectively. Timer A can use any of six clocks (f2, f16, f64, f512, and f1() and f4096). "f2" indicates that this clock is f1() divided by 2. For operation of the watchdog timer, refer to section on the watchdog timer. When the STP instruction is executed, , BIU, and CPU stop at the "L" state. The STP mode is terminated by acceptance of an interrupt, and the oscillation is started. Simultaneously, supply of is started. When the watchdog timer starts to count down with Wf32 and the most significant bit of the watchdog timer is cleared to "0", supply of BIU and CPU is restarted. The count source of the watchdog timer is back to the count source which was selected before execution of the STP instruction, and the generated interrupt request is accepted. When the WIT instruction is executed, BIU and CPU stops at the "L" state. However, is not stopped. Immediately after the interrupt request is accepted, BIU and CPU start their operations. In order to terminate the STP or WIT mode by a non-maskable interrupt, it is necessary to make the interrupt request acceptable before execution of the STP or WIT instruction. For setting method, refer to the section on interrupts. Figure 109 shows a circuit example with an external ceramic resonator or a quartz crystal oscillator. The constants such as capacitance etc. depend on a resonator. Therefore, for these constants, adopt the oscillator/resonator manufacturer's recommended values. Figure 110 shows a circuit e example with an external clock source. XIN XOUT Rf CIN Rd COUT Fig. 109 Circuit example with external ceramic resonator or quartz crystal oscillator XIN XOUT Left open. External oscillation circuit Vcc Vss Fig. 110 Circuit example with external clock source 111 112 Fig. 111 Block diagram of clock generating circuit Reset R S R Q Q Q CPU wait request from BIU Internal clock stop select bit at WIT CPU BIU 1 1/2 1/8 1/4 External clcok input select bit f2 Reflesh counter DMA transfer 1/32 Access to external area HLDA CPU : Central Processing Unit BIU : Bus Interface Unit : Signal generated when the watchdog timer's most significant bit becomes "0". Watchdog timer frequency select bit : bit 0 at address 6116 External clock input select bit : bit 1 at address 6216 Internal clock stop select bit at WIT : bit 3 at address 6316 WIT instruction S R S XOUT 0 1 1/16 1/8 1/16 Wf32 1/8 Operating clock for timer A A-D conversion frequency (AD) clock source Operating clock for serial I/O, timer B Wf512 0 1 Watchdog timer Watchdog timer frequency select bit f4096 f1() f2 f16 f64 f512 I STP instruction Interrupt request External clock input select bit XIN P . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som IM REL Y NAR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS RY A N IMI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T met ice: Not e para Som PRE L M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DEBUG FUNCTION When the CPU fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of PG and PC). The decision whether this condition is satisfied or not is called address matching detection, and the interrupt generated by this detection is called an address matching detection interrupt. (For interrupt vector addresses, refer to the section on interrupts.) In the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. The debug function provides the following two modes: * the address matching detection mode, which is used to avoid the area where program exists or modify a program. * the out-of-address-area detection mode, which is used to detect a program runaway. Figure 112 shows the block diagram of the debug function. Figures 113 and 114 show the bit configurations of the debug control registers 0, 1, and address compare registers 0,1, respectively. The detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. When the selected address condition is satisfied, an address matching detection interrupt request will be generated: (1) Address matching detection 0 The contents of PG and PC match with the address which has been set in the address compare register 0. (2) Address matching detection 1 The contents of PG and PC match with the address which has been set in the address compare register 1. (3) Address matching detection 2 The contents of PG and PC match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) Out-of-address-area detection The contents of PG and PC are less than the address which has been set in the address compare register 0 or larger than the address which has been set in the address compare register 1. By setting the detect enable bit of the debug control register 0 to "1", an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. Clearing the detect enable bit to "0" generates no interrupt request even if any of the above address conditions is satisfied. The address compare register access enable bit of the debug control register 1 must be set to "1" by the instruction just before the access operation (read/write). Then, this bit must be cleared to "0" (disabled) by the next instruction. While this bit = "0", the address compare registers 0, 1 cannot be accessed. The address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of PG, PC, when the address matching detection 2 is selected. The contents of this bit is invalid when address matching detection 0 or 1 is selected. In order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. As a result, the contents of PG, PC, PS at acceptance of an address matching detection interrupt request (i.e. the address at which an address matching detection condition is satisfied) have been pushed on to the stack. If a return destination address after the interrupt processing is to be altered, rewrite the contents of the stack, and then return by the RTI instruction. To use the debug function to detect a program runaway, set an address area where no program exists into the address compare registers 0 and 1 by using the out-of-address-area detection. When the CPU fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be generated. The above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is running. Internal data bus (DB0 to DB15) Debug control register 0 Address compare register 0 Address compare register 1 Debug control register 1 Matching * Compare register Matching * Compare register Address matching detect circuit Address matching detection interrupt CPU bus (Address) Fig. 112 Block diagram of debug function 113 I MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som P IM REL 7 6 1 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 5 4 3 0 0 2 1 0 Debug control register 0 Address 6616 Detect condition select bits (Note 1) 000: Do not select. 001: Address matching detection 0 010: Address matching detection 1 011: Address matching detection 2 100: Do not select. 101: Out-of-address-area detection 110: Do not select. 111: Do not select. Fix this bit to "0" (Note 1). Detect enable bit (Note 1) 0: Detection disabled. 1: Detection enabled. Fix this bit to "0" (Note 1). "1" at read. 7 0 6 5 4 3 0 1 2 1 0 Debug control register 1 0 Address 6716 Fix this bit to "0" (Note 1). "0" at read (Note 1). Address compare register access enable bit (Note 2) 0: Disabled 1: Enabled Fix this bit to "1" when using the debug function. Fix this bit to "0" (Note 1). While debugger is not used, "0" at read. While debugger is used, "1" at read. Address-matching-detection 2 decision bit Valid when address matching detection 2 is selected. 0: Matches with the contents of the address compare register 0. 1: Matches with the contents of the address compare register 1. "0" at read. Notes 1: At power-on reset, these bits = "0"; at hardware reset or software reset, these bits retain the value just before reset. 2: Set this bit to "1" with the instruction just before the address compare register 0, 1 (addresses 6816 to 6D16) is accessed. And then, clear this bit to "0" with the instruction just after the access. Fig. 113 Bit configuration of debug control register 0, 1 (23) 7 (16) (15) 0 7 (8) 0 7 0 Address compare register 0 Address compare register 1 Address 6816, 6916, 6A16 6B16, 6C16, 6D16 The address to be detected (in other words, the start address of instruction) is set here. Fig. 114 Bit configuration of address compare register 0, 1 114 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION FLASH MEMORY MODE These microcomputers contain the DINOR (DIvided bit line NOR)type flash memory; and single-power-supply reprogramming is available to this. These microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory: * Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external programmer. * CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figures 116 and 117, the flash memory is divided into several blocks, and erasure per block is possible. Each of these blocks is provided with a lock bit, which determines the validity of erasure/program execution. Therefore, data protection per block is possible. This internal flash memory has the boot ROM area storing the reprogramming control software for reprogramming in the CPU reprogramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal operation in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on shipment, the user-original reprogramming control software which is more appropriate for the user's system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode. User ROM area Boot ROM area Byte Address Word Address Byte Addresses 00200016 00100016 00000016 00000016 003FFF16 00400016 005FFF16 00600016 007FFF16 00800016 001FFF16 00200016 002FFF16 00300016 003FFF16 00400016 003FFF16 001FFF16 8 Kbytes 8 Kbytes 007FFF16 00800016 64 Kbytes 01FFFF16 16 Kbytes 8 Kbytes 32 Kbytes 00FFFF16 01000016 Word Addresses 00FFFF16 Total 120 Kbytes Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016-00FFFF16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016-FFBF16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area. Fig. 116 M37920FCCGP, M37920FCCHP: block configuration of internal flash memory 115 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION User ROM area Boot ROM area Byte Address Word Address Byte Addresses 00200016 00100016 00000016 00000016 003FFF16 00400016 005FFF16 00600016 007FFF16 00800016 001FFF16 00200016 002FFF16 00300016 003FFF16 00400016 003FFF16 001FFF16 8 Kbytes 8 Kbytes 007FFF16 00800016 64 Kbytes 01FFFF16 02000016 16 Kbytes 8 Kbytes 32 Kbytes 00FFFF16 01000016 00FFFF16 01000016 Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016-00FFFF16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016-FFBF16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area. 64 Kbytes 02FFFF16 03000016 017FFF16 01800016 64 Kbytes 03FFFF16 01FFFF16 Total 248 Kbytes Fig. 117 M37920FGCGP, M37920FGCHP: block configuration of internal flash memory 116 Word Addresses MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Flash Memory Parallel I/O Mode User ROM Area and Boot ROM Area The flash memory parallel I/O mode is used to manipulate the internal flash memory with a parallel programmer. This parallel programmer uses the software commands listed in Table 25 to do the flash memory manipulations, such as read/programming/erase operations. In the flash memory parallel I/O mode, each block can be protected from erasing/programming (in other words, block lock). The user ROM area and boot ROM area can be reprogrammed in the flash memory parallel I/O mode. The programming and block erase operations can be performed only to these areas. The boot ROM area, 16 Kbytes in size, is assigned to addresses 000016-3FFF16 (byte addresses), so that programming and block erase operations can be performed only to this area. (Access to any address out of this area is prohibited). The erasable block in the boot ROM area is only one block, consisting of 16 Kbytes. The reprogramming control firmware to be used in the flash memory serial I/O mode has been stored to this boot ROM area on our shipment. Therefore, do not reprogram the boot ROM area if the user uses the flash memory serial I/O mode. Addresses FFB016 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. Note that, when the boot ROM area is read out from the CPU in the CPU reprogramming mode, described later, its addresses will be shifted to C00016--FFFF16 (byte addresses). Table 25. Software commands (flash memory parallel I/O mode) Software Command Read Array Read Status Register Clear Status Register Page Programming (Note) Block Erase Erase All Unclocked Block Lock Bit Programming Read Lock Bit Status Note: Programming is performed in a unit of 256 bytes, with the low-order address assigned in the range of 0016--FF16 (byte addresses). 117 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) Pin Name Input /Output VCC, VSS MD0 MD1 RESET XIN XOUT BYTE AVcc, AVss VREF P00-P07 P10-P17 P20-P27 P30-P33 P40, P41 Power supply input MD0 MD1 Reset input Clock input Clock output BYTE Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 SDA I/O BUSY output SCLK input Input port P5 Input port P6 Input port P7 Input port P8 Input port P9 Input port P10 Input port P11 Input port P12 Non-maskable interrupt -- Input Input Input Input Output Input -- Input Input Input Input Input Input I/O Output Input Input Input Input Input Input Input Input Input Input P42 P43 P44 P50-P57 P60-P66 P70-P73 P80-P86 P90-P96 P100-P107 P110-P117 P120-P122 NMI 118 Functions Apply 5 V 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 k to 100 k. The reset input pin. Connect a ceramic resonator between the XIN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.) Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS-VCC. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 k). This is an output pin for the BUSY signal. This is an input pin for a serial clock. Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H" or "L", or leave them open. (This is not used in the flash memory serial I/O mode.) Input "H", or leave this pin open. MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figures 118 and 119 show the pin connections in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an external pullup resistor (about 1 k). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes "H" during BUSY periods owing to a certain operation, such as transmit, receive, erase, programming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FFB016 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. 119 MI ELI Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P101/A1 P102/A2 P103/A3 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8/MA0 P111/A9/MA1 P112/A10/MA2 P113/A11/MA3 P114/A12/MA4 P115/A13/MA5 P116/A14/MA6 P117/A15/MA7 P00/A16/MA8 P01/A17 P02/A18/MA9 P03/A19 P04/A20/MA10 P05/A21 P06/A22/MA11 P07/A23 VSS MD1 P10/D0 P11/D1 P12/D2 P13/D3 P14/D4 PR MITSUBISHI MICROCOMPUTERS 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M37920FCCGP M37920FGCGP P15/D5 P16/D6 P17/D7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET NMI BYTE P30/RDY VSS RESET SDA SCLK BUSY P66/DMAREQ3 P65/TA4IN/DMAREQ2 P64/TA4OUT/DMAACK2 P63/TA3IN/DMAREQ1 P62/TA3OUT/DMAACK1 P61/TA1IN/DMAREQ0 P60/TA1OUT/DMAACK0 P57/TA2IN/RTP13 P56/TA2OUT/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P96/WRH/UCAS P95/WRL/LCAS P94/CAS/W P93/CS3/RAS3 P92/CS2/RAS2 P91/CS1/RAS1 P90/CS0 P44/HLDA P43/HOLD P42/TC P41/1 P40/ALE P33/BHW P32/BLW P31/RD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VCC P100/A0 81 P86/CLK0 82 P85/RXD0 83 P84/TXD0 84 P83/CTS0/RTS0 85 P82/CTS0/CLK1 86 P81/RXD1 87 P80/TXD1 88 VCC 89 AVCC 90 VREF 91 AVSS 92 VSS 93 P73/AN3/ADTRG/INT4 94 P72/AN2/INT3 95 P71/AN1 96 P70/AN0 97 P122/INT2/TB2IN 98 P121/INT1/TB1IN 99 P120/INT0/TB0IN 100 : Connect to the ceramic oscillation circuit. Output 100P6S-A Fig.118 Pin connection of M37920FxCGP in flash memory serial I/O mode 120 MI ELI Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8/MA0 P111/A9/MA1 P112/A10/MA2 P113/A11/MA3 P114/A12/MA4 P115/A13/MA5 P116/A14/MA6 P117/A15/MA7 P00/A16/MA8 P01/A17 P02/A18/MA9 P03/A19 P04/A20/MA10 P05/A21 P06/A22/MA11 P07/A23 VSS MD1 P10/D0 P11/D1 P12/D2 PR MITSUBISHI MICROCOMPUTERS 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 M37920FCCHP M37920FGCHP P13/D3 P14/D4 P15/D5 P16/D6 P17/D7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET NMI BYTE P30/RDY P31/RD P32/BLW P33/BHW VSS RESET SDA SCLK BUSY P64/TA4OUT/DMAACK2 P63/TA3IN/DMAREQ1 P62/TA3OUT/DMAACK1 P61/TA1IN/DMAREQ0 P60/TA1OUT/DMAACK0 P57/TA2IN/RTP13 P56/TA2OUT/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P96/WRH/UCAS P95/WRL/LCAS P94/CAS/W P93/CS3/RAS3 P92/CS2/RAS2 P91/CS1/RAS1 P90/CS0 P44/HLDA P43/HOLD P42/TC P41/1 P40/ALE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VCC P103/A3 76 P102/A2 77 P101/A1 78 P100/A0 79 P86/CLK0 80 P85/RXD0 81 P84/TXD0 82 P83/CTS0/RTS0 83 P82/CTS0/CLK1 84 P81/RXD1 85 P80/TXD1 86 VCC 87 AVCC 88 VREF 89 AVSS 90 VSS 91 P73/AN3/ADTRG/INT4 92 P72/AN2/INT3 93 P71/AN1 94 P70/AN0 95 P122/INT2/TB2IN 96 P121/INT1/TB1IN 97 P120/INT0/TB0IN 98 P66/DMAREQ3 99 P65/TA4IN/DMAREQ2 100 : Connect to the ceramic oscillation circuit. Output 100P6Q-A Fig.119 Pin connection of M37920FxCHP in flash memory serial I/O mode 121 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CPU Reprogramming Mode Boot Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU reprogramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU reprogramming mode, the above software must be transferred to the internal RAM in advance to be executed. The user-original reprogramming control software for the CPU reprogramming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 0000 16 to 3FFF16 (byte address). On the other hand, when accessing with the CPU, these addresses will be shifted to C00016 to FFFF16 (byte address). Reset removal with both of the MD0 and MD1 pins held "L" invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not accessible. Removing reset with the MD0 pin held "L" and the MD1 pin "H", the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also reprogram the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. 7 6 5 4 3 2 1 0 0 Flash memory control register Address 9E16 RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Lock bit invalidity select bit (Note 3) 0: Block lock by lock bit data is valid. 1: Block lock by lock bit data is invalid. Flash memory reset bit (Note 4) 0: Normal operation 1: Reset Must be "0". User ROM area select bit (Note 5) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Notes 1: The contents of the flash memory control register after reset is removed are "XX0000012". 2: To set "1", writing of "0" to bit 1 and subsequent writing of "1" to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: To set "1", writing of "0" to bit 2 and subsequent writing of "1" to bit 2 are necessary while bit 1 = "1". 4: Valid only when bit 1 = "1". Set bit 3 to "1" (reset), and then clear to "0". This bit 3 must be controlled with the CPU reprogramming mode select bit (bit 1) = "1". 5: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM. Fig. 120 Bit configuration of flash memory control register 122 MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Function overview (CPU reprogramming mode) The CPU reprogramming mode is available in the single-chip mode, memory expansion mode, and boot mode to reprogram the user ROM area only. In the CPU reprogramming mode, the CPU erases, programs, and reads the internal flash memory by writing software commands. Note that the user-original reprogramming control software must be transferred to the internal RAM in advance to be executed. The CPU reprogramming mode becomes active when "1" is written into the flash memory control register's bit 1 (the CPU reprogramming mode select bit) shown in Figure 120, and software commands become acceptable. In the CPU reprogramming mode, software commands and data are all written to and read from even addresses (Note that address A0 in byte addresses = "0".) 16 bits at a time. Therefore, a software command consisting of 8 bits must be written to an even address; therefore, any command written to an odd address will be invalid. Since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. The write state machine (WSM) in the flash memory controls the erase and programming operations. What the status of the WSM operation is and whether the programming or erase operation has been completed normally or terminated by an error can be examined by reading the status register. Figure 120 shows the bit configuration of the flash memory control register. Bit 0 (the RY/BY status bit) is a read-only bit for indicating the WSM operation. This bit goes to "0" (BUSY) while the automatic programming/erase operation is active and goes to "1" (READY) during the other operations. Bit 1 serves as the CPU reprogramming mode select bit. Writing of "1" to this bit selects the CPU reprogramming mode, and software commands will be acceptable. Because the CPU cannot directly access the internal flash memory in the CPU reprogramming mode, writing to this bit 1 must be performed by the user-original reprogramming control software which has been transferred to the internal RAM in advance. To set bit 1 to "1", it is necessary to write "0" and "1" to this bit 1 successively. On the other hand, to clear this bit to "0", it is sufficient only to write "0". Bit 2 serves as the lock bit invalidity select bit, and setting this bit to "1" invalidates the protection by a lock bit against erasing and programming (block lock). The lock bit invalidity select bit can invalidates the lock bit function but set no lock bit itself. However, if erasing is performed with this bit = "1", a lock bit with value "0" (the locked state) will be set to "1" (the unlocked state) after the erasing has been completed. To set the lock bit invalidity select bit to "1", write "0" and "1" to this bit 2 successively with the CPU reprogramming mode select bit = "1". The manipulation of bit 2 is allowed only when the CPU reprogramming mode select bit = "1". Bit 3 (the flash memory reset bit) resets the control circuit of the internal flash memory and is used when the CPU reprogramming mode is terminated or when an abnormal access to the flash memory happens. Writing of "1" to bit 3 with the CPU reprogramming mode select bit = "1" preforms the reset operation. To remove the reset, write "0" to bit 3 subsequently. Bit 5 serves as the user ROM area select bit and is valid only in the boot mode. Setting this bit to "1" in the boot mode switches an acces- sible area from the boot ROM area to the user ROM area. To use the CPU reprogramming mode in the boot mode, set this bit to "1". Note that when the microcomputer is booted up in the user ROM area, only the user ROM area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the CPU reprogramming mode. To rewrite bit 5, execute the user-original reprogramming control software transferred to the internal RAM in advance. Figure 121 shows the CPU reprogramming mode set/termination flowchart, and be sure to follow this flowchart. As shown in Note 1 of Figure 121, before selecting the CPU reprogramming mode, set the processor mode register 1's bit 7 (the internal ROM bus cycle select bit) to "0" and set flag I to "1" to avoid an interrupt request input. When an NMI interrupt or a watchdog timer interrupt request is generated in the CPU reprogramming mode, when an input to the RESET pin is "L", or when the software reset is performed, the flash memory control circuit and flash memory control register will be reset. When the flash memory is reset during the erase or programming operation, this operation is cancelled and the target block's data will be invalid. Just before writing a software command related to the erase/programming operation, be sure to write to the watchdog timer. Also, be sure to set the NMI pin to "H" to avoid an NMI interrupt request occurrence. In the CPU reprogramming mode, be sure not to use the STP and WIT instructions. 123 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Software Commands Start Single-chip mode, Memory expansion mode, or Boot mode The processor mode register is set (Note 1). Flag I is set to "1". Table 26 lists the software commands. By writing a software command after the CPU reprogramming select bit has been set to "1", erasing, programming, etc. can be specified. Note that, at software commands' input, the high-order byte (D8- D15) is ignored. (Except for the write data at the 2nd cycle of a page programming command.) Software commands are explained as below. Read Array Command (FF16) The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. By writing command code "FF16" at the 1st bus cycle, the microcomputer enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified address are output to the data bus (D0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) Read Status Register Command (7016) (Only in the boot mode.) The user ROM area select bit is set to "1". Writing command code "7016" at the 1st bus cycle outputs the contents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. Clear Status Register Command (5016) Writing of "1" to the CPU reprogramming mode select bit. (Writing of "0" Writing of "1") Operations such as erasing, programming are executed by using software commands. (If necessary, the lock bit invalidity select bit is set.) Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of "1" Writing of "0") (Note 2) Writing of "0" to the CPU reprogramming mode select bit. (Only in the boot mode.) Writing of "0" to user ROM area select bit (Note 3). Completed Notes 1: The processor mode register 1's bit 7 (address 5F16, the internal ROM access wait bit) must be "0" (1 wait). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain "1". However, if this bit is "1", the user ROM area access is specified. Fig. 121 CPU reprogramming mode set/termination flowchart 124 This command clears three status bits (SR.3-5) each of which is set to "1" to indicate that the operation has been terminated by an error. To clear these bits, write command code "5016" at the 1st bus cycle. Page Programming Command (4116) Page programming facilitates quick programming of 128 words (a page = 256 bytes) at a time. To initiate page programming, write command code "4116" at the 1st bus cycle; then, program a series of data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus cycle. It is necessary, at this time, to increment address A0-A7 from "0016" to "FE16" by +2. (Programmed to even addresses.) Upon completion of data loading, automatic programming (data programming and verification) operation is started. The completion of the automatic programming operation is recognized by a read of the status register or a read of the flash memory control register. As the automatic programming operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. Bit 7 of the status register (SR.7) is cleared to "0" simultaneously with the start of the automatic programming operation; and also, bit 7 returns to "1" by the end of it. Until writing of the read array command (FF16), writing of the read lock bit status command (7116), or performing the reset operation with the flash memory reset bit, this read status register mode is maintained. In continuous programming, if there is no programming error, page programming commands can be executed with the read status register mode kept. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Table 26. Software commands (CPU reprogramming mode) 1st cycle Command Read Array Read Status Register Clear Status Register Page Programming (Note 3) Block Erase Erase All Unclocked Block Lock Bit Programming Read Lock Bit Status 3rd cycle 2nd cycle Mode Address Data (D0 to D7) Mode Address Write Write Write Write Write Write Write Write X (Note 2) X X X X X X X FF16 7016 5016 4116 2016 A716 7716 7116 -- Read -- Write Write Write Write Read -- X -- Data -- SRD (Note 3) -- WA0 (Note 4) WD0 (Note 4) BA (Note 5) D016 X D016 BA D016 BA D6 (Note 6) Mode Address Data -- -- -- -- -- WA1 -- -- -- -- -- -- -- WD1 -- -- -- -- -- Write -- -- -- -- Notes 1: At software commands' input, the high-order byte of data (D8-D15) is ignored. 2: X = An arbitrary address in the user ROM area. (Note that A0 = "0".) 3: SRD = Status register data. 4: WA = Write address, WD = Write data (16 bits). WA and WD must be set from "0016" to "FE16". (Byte addresses. Incremented by +2. Address A0 = "0".) Page size = 128 words (128 16 bits). 5: Block address: the maximum address of each block must be input. Note that address A0 = "0". 6: D6 indicates the block lock status. "1" = unlocked. "0" = locked. The RY/BY status bit of the flash memory control register goes "0" during the automatic programming operation; and also, it goes "1" after the end of it, the same way as bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to "1" (READY). During the automatic programming operation, writing of commands and access to the flash memory must not be performed. Reading out the status register after the automatic programming operation is completed reports the result of it. For details, refer to the section on the status register. Figure 122 shows an example of the page programming flowchart. Note that each block can be protected from programming by using a lock bit. For details, refer to the section on the data protect function. Additional programming to any page that has already been programmed is prohibited. the status register (SR.7) or the RY/BY status bit is set to "1" (READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed. Reading out the status register after the automatic erase operation is completed reports the result of it. For details, refer to the section on the status register. Figure 123 shows an example of the block erase flowchart. Note that each block can be protected from erasing by using a lock bit. For details, refer to the section on the data protect function. Block Erase Command (2016/D016) Writing command code "2016" at the 1st bus cycle and writing verify command code "D016" and the maximum address of the block (Note that address A0 = "0".) at the subsequent 2nd bus cycle initiate the automatic erase (erasing and erase verification) operation for the specified block. The completion of the automatic erase operation is verified by a read of the status register or a read of the flash memory control register. As the automatic erase operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. Bit 7 of the status register (SR.7) is cleared to "0" simultaneously with the start of the automatic erase operation; and also, it returns to "1" by the end of it. The read status register mode is maintained until writing of the read array command (FF16), writing of the read lock bit status command (7116), or performing the reset operation with the flash memory reset bit. The RY/BY status bit of the flash memory control register goes "0" during the automatic erase operation; and also, it goes "1" after the end of it, the same way as bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of 125 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Start Start Write 4116 Write 7716 n=0 Write Addressn, Datan n = FE16 n=n+2 Write D016 Block Address NO SR.7 = 1? YES Status Register Read NO YES SR.4 = 0? SR.7 = 1? NO NO Lock Bit Programming Error YES YES Lock Bit Programming Completed Full status check Page programming completed Fig.122 Page programming flowchart Fig.124 Lock bit programming flowchart Start Write 2016 Start Write D016 Block Address Write 7116 Status Register Read Block Address SR.7 = 1? NO YES Full Status Check D6 = 0? NO YES Block: locked Block Erase Completed Fig.123 Block erase flowchart 126 Fig.125 Read lock bit status flowchart Block: unlocked MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Erase All Unlocked Block Command (A716/D016) Writing command code "A716" at the 1st bus cycle and writing verify command code "D016" at the subsequent 2nd bus cycle initiate the continuous block erase (chip erase) operations for all the blocks. The completion of the chip erase operation, as well as of the block erase operation, is verified by a read of the status register or a read of the flash memory control register. The result of the automatic erase operation is also reported by a read of the status register. During the automatic erase operation (when the RY/BY status bit = "0"), writing of commands and access to the flash memory must not be performed. When the lock bit invalidity select bit = "1", all the blocks are erased regardless of the status of their lock bits. When the lock bit invalidity select bit = "0", on the contrary, the status of each lock bit becomes valid, so only the blocks in the unlocked state (lock bit = "1") are erased. Lock Bit Programming Command (7716/D016) By writing of command code "7716" at the 1st bus cycle and writing of verify command code "D016" and the block's maximum address (Note that address A0 = "0".) at the subsequent 2nd bus cycle, "0" (the locked state) is written into the lock bit of the specified block. Figure 124 shows an example of the lock bit programming flowchart. The status of the lock bit can be read out by the read lock bit status command. The completion of the lock bit programming operation, as well as of the page programming operation, is verified by a read of the status register or a read of the flash memory control register. For details of the lock bit's function and the method of reset, refer to the section on the data protect function. completion of the erase operation, and the locked state by the lock bit is terminated. To perform erase or programming, be sure to do one of the following. * By executing the read lock bit status command, verify that the lock of the target block is invalid. * Set the lock bit invalidity select bit to "1" to invalidate the lock. When the block erase or programming is performed with the lock valid, the erase status bit (SR.5) and programming status bit (SR.4) are set to "1" (terminated by error). Status Register The status register is used to indicate what the status of the write state machine (WSM) operation is and whether the programming/ erase operation has been completed normally or terminated by an error. By writing the read status register command (7016), the contents of the status register can be read out; by writing the clear status register command (5016), the contents of the status register can be cleared. Table 27 lists the definition of each bit of the status register. The status register outputs "8016" after reset is removed. The status of each bit is described below. Read Lock Bit Status Command (7116) By writing of command code "7116" at the 1st bus cycle and writing of the block's maximum address (Note that address A0 = "0".) at the subsequent 2nd bus cycle, the status of the lock bit of the specified block is output to the data bus (D6). Figure 125 shows an example of the read lock bit programming flowchart. Data Protect Function (Block Lock) Each block is implemented with a nonvolatile lock bit to protect the block from erasing/programming (block lock). A "0" (the locked state) can be written to a lock bit using the lock bit programming command, and the lock bit of each block can be read out by using the read lock bit status command. Whether a block lock is valid or invalid is determined by the status of the lock bit and the lock bit invalidity select bit of the flash memory control register. (1) When the lock bit invalidity select bit = "0", a lock bit determines whether to lock or unlock the corresponding block. A block with its lock bit = "0" is locked and inhibited from erasing and programming. On the other hand, a block with its lock bit = "1" remains unlocked and allows to be erased/programmed. (2) When the lock bit invalidity select bit = "1", all the blocks are unlocked and allows to be erased/programmed regardless of the values of their lock bits. In this case, a lock bit with a value "0" (the locked state) is set to "1" (the unlocked state) after 127 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Write State Machine (WSM) Status Bit (SR.7) This bit reports the operation status of the WSM. This bit is set to "1" (READY) after the system power is turned on or after reset is removed. During the automatic programming or erase operation, this bit is cleared to "0" (BUSY), however, set to "1" upon completion of them. Erase Status Bit (SR.5) This bit reports the status of the automatic erase operation. This bit is set to "1" if an erase error occurs and returns to "0" if one of the following conditions is satisfied: * the system power is turned on. * reset is removed. * the clear status register command (5016) is executed. Under the condition that any of SR.5, SR.4 and SR.3 = "1", none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (5016) to clear the status register. Both of SR.4 and SR.5 are set to "1" under the following conditions (Command Sequence Error): (1) when data other than "D016" and "FF16" is written to the data in the 2nd bus cycle of the lock bit programming command (7716/ D016) (2) when data other than "D016" and "FF16" is written to the data in the 2nd bus cycle of the block erase command (2016/D016) (3) when data other than "D016" and "FF16" is written to the data in the 2nd bus cycle of the erase all unlocked block command (A716/D016) Programming Status Bit (SR.4) This bit reports the status of the automatic programming operation. This bit is set to "1" if a programming error occurs and returns to "0" if one of the following conditions is satisfied: * the system power is turned on. * reset is removed. * the clear status register command (5016) is executed. Note that, writing of "FF16" forces the microcomputer into the read array mode. Simultaneously with this, the command written in the 1st bus cycle will be canceled. Block Status After Programming Bit (SR.3) Full Status Check This bit is set to "1", upon completion of the page programming operation, if the excessive programming (Note) occurs. That is, the status register becomes "8016" when the programming operation is terminated normally, "9016" when the programming operation is failed, and "8816" when the excessive programming occurs. The full status check reports the results of the erase or programming operation. Figure 126 shows the full status check flowchart and actions to be taken if an error has occurred. Note: The excessive programming means the status that memory cells are too depleted, so data cannot be read out correctly. Table 27. Bit definition of status register Symbol SR.7 (D7) SR.6 (D6) SR.5 (D5) SR.4 (D4) SR.3 (D3) SR.2 (D2) SR.1 (D1) SR.0 (D0) 128 Status Write State Machine (WSM) Status Reserved Erase Status Programming Status Block Status After Programming Reserved Reserved Reserved Definition "1" "0" Ready Busy Terminated by error. Terminated by error. Terminated by error. Terminated normally. Terminated normally. Terminated normally. MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Status Register Read SR.4 = 1 and SR.5 = 1 ? YES Command Sequence Error Execute the clear status register command (5016) to clear the status register. After verifying the command to be correctly input, start the operation again. NO NO Block Erase Error SR.5 = 0? YES NO SR.4 = 0? Programming Error (Page, Lock bit) YES NO SR.3 = 0? Programming Error (Block) Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform block erase again. If the same error still occurs, this page cannot be used. Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform programming again. If the same error still occurs, this page cannot be used. After erasing the block where an error has occured, perform programming again. If the same error still occurs, this block cannot be used. YES End (Block erase, Programming) Note: Under the condition that any of SR.5, SR.4 and SR.3 = "1", none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (5016). Fig.126 Full status check flowchart and actions to be taken if an error has ocurred DC Electrical Characteristics (VCC = 5 V 0.5 V, Ta = 0 to 60 C, f(XIN) = 20 MHz (Note)) Symbol Icc1 Icc2 Icc3 Icc4 Parameter Min. VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) Limits Typ. 30 Max. 48 48 54 54 Unit mA mA mA mA Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(XIN) indicates the system clcok (XIN) frequency. AC Electrical Characteristics (VCC = 5 V 0.5 V, Ta = 0 to 60 C, f(XIN) = 20 MHz (Note)) Parameter Min. Page programming time Block erase time Erase all unlocked block time Lock bit programming time Limits Typ. Max. 8 120 50 600 50 n 600 n 8 120 Unit ms ms ms ms n = Number of blocks to be erased The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(XIN) indicates the system clock (XIN) frequency. 129 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI VO Pd Topr Tstg Parameter Power source voltage Analog power source voltage Input voltage D0-D7, D8/P20-D15/P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P100-P107, P110-P117, P120-P122, VREF, XIN, RESET, BYTE, MD0, MD1, NMI Output voltage D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P100-P107, P110-P117, P120-P122, XOUT Power dissipation Operating ambient temperature Storage temerature Ratings -0.3 to 6.5 -0.3 to 6.5 Unit V V -0.3 to VCC+0.3 V -0.3 to VCC+0.3 V 300 -20 to 85 -40 to 150 mW C C RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter VCC AVCC VSS AVSS VIH Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage VIH VIH High-level input voltage High-level input voltag VIL Low-level input voltage VIL VIL Low-level input voltage Low-level input voltage IOH (peak) High-level peak output current IOH (avg) High-level average output current IOL (peak) Low-level peak output current IOL (avg) Low-level average output current f(XIN) External clock input frequency P00-P07, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P101-P107, P111-P117, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI P10-P17, P20-P27 (In single-chip mode) P10-P17, P20-P27 (In memory expansion and microprocessor modes) P00-P07, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P101-P107, P111-P117, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI P10-P17, P20-P27 (In single-chip mode) P10-P17, P20-P27 (In memory expansion and microprocessor modes) P00-P07, P10-P17, P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P96, P100-P107, P110-P117, P120-P122 P00-P07, P10-P17, P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P96, P100-P107, P110-P117, P120-P122 P00-P07, P10-P17, P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P96, P100-P107, P110-P117, P120-P122 P00-P07, P10-P17, P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P96, P100-P107, P110-P117, P120-P122 Min. Typ. Max. 4.5 5 VCC 0 0 5.5 Unit 0.8VCC VCC V V V V V 0.8VCC 0.5VCC VCC VCC V V 0 0.2VCC V 0 0 0.2VCC 0.16VCC V V -10 mA -5 mA 10 mA 5 mA 20 MHz Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P3-P7, P9, and P12 must be 80 mA or less, the sum of IOH(peak) for ports P3-P7, P9, and P12 must be 80 mA or less. 130 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol VOH VOH VOH VOL VOL VOL VT+ --VT- VT+ --VT- VT+ --VT- IIH IIL VRAM ICC Parameter Test conditions IOH = -10 mA High-level output voltage P00-P07, P10-P17, P20-P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P93, P100-P107, P110-P117, P120-P122 High-level output voltage P00-P07, P10-P17, IOH = -400 A P20-P27, P40, P44, P90-P93, P100-P107, P110-P117 High-level output voltage P31-P33, P94-P96 IOH = -10 mA IOH = -400 A Low-level output voltage P00-P07, P10-P17, IOL = 10 mA P20-P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P90-P93, P100-P107, P110-P117, P120-P122 Low-level output voltage P00-P07, P10-P17, IOL = 2 mA P20-P27, P40, P44, P90-P93, P100-P107, P110-P117 Low-level output voltage P31-P33, P94-P96 IOL = 10 mA IOL = 2 mA Hysteresis TA0IN-TA4IN, TB0IN-TB2IN, INT0-INT4, DMAREQ0-DMAREQ3, ADTRG, CTS0, CLK0, CLK1, RxD0, RxD1, NMI, RDY, HOLD Hysteresis RESET Hysteresis XIN High-level input current P00-P07, P10-P17, VI = 5.0 V P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P100-P107, P110-P117, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input current P00-P07, P10-P17, VI = 0 V P20-P27, P30-P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P100-P107, P110-P117, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI RAM hold voltage When clock is stoped. At reset in micro- f(XIN) = 20 MHz. Power source current processor mode, output-only pins Ta = 25 C when are open, and the clcock is stopped. other pins are con- Ta = 80 C when nected to Vss. clcock is stopped. Min. 3 Limits Typ. Max. Unit V 4.7 V 3.4 4.8 V 0.4 0.5 0.1 2 V 0.45 V 1.6 0.4 1 V 1.5 0.3 5 V V A -5 A 50 V mA A 2 25 1 V 20 131 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V 0.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---------- ---------- RLADDER Parameter Resolution Test conditions VREF = VCC Absolute accuracy VREF = VCC Ladder resistance VREF = VCC tCONV Conversion time VREF VIA Reference voltage Analog input voltage f(XIN) 20 MHz Note: This is applied when A-D conversion freguency (AD) = f1(). 132 Limits Min. 10 3 2 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode Max. 5 5.9 2.45 (Note) 2.7 0 Unit Bits LSB LSB k s VCC VREF V V MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V 0.5 V, VCC = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz unless otherwise noted) For limits depending on f(XIN), their calculation formulas are shown below. Also, the values at f(XIN) = 20 MHz are shown in ( ). Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Limits Parameter Min. 80 40 40 TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time f(XIN) 20 MHz tw(TAH) TAiIN input high-level pulse width f(XIN) 20 MHz tw(TAL) TAiIN input low-level pulse width f(XIN) 20 MHz Limits Min. 16 x 109 (800) f(XIN) 8 x 109 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz. Timer A input (External trigger input in one-shot pulse mode) Symbol Limits Parameter tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Min. f(XIN) 20 MHz 8 x 109 f(XIN) Max. (400) Unit ns 80 80 ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input and Count input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns 133 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Limits Parameter Min. 800 200 200 TAiIN input cycle time TAjIN input setup time TAjOUT input setup time * Gating input in timer mode * Count input in event counter mode * External trigger input in one-shot pulse mode * External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) * Up-down and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) TAiIN input (When count by falling) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by rising) * Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Test conditions * VCC = 5 V0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V 134 Max. Unit ns ns ns MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer B input (Count input in event counter mode) Symbol Parameter tc(TB) TBiIN input cycle time (one edge count) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(XIN) 20 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 20 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 20 MHz Limits Min. 16 x 109 (800) f(XIN) 8 x 109 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz. Timer B input (Pulse width measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(XIN) 20 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 20 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 20 MHz Limits Min. 16 x 109 (800) f(XIN) 8 x 109 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width Limits Min. 1000 125 Max. Unit ns ns 135 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Limits Parameter Min. 200 100 100 CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Max. 80 0 20 90 Unit ns ns ns ns ns ns ns External interrupt (INTi) input, NMI input Symbol tw(INH) tw(INL) Limits Parameter Min. 250 250 INTi input/NMI input high-level pulse width INTi input/NMI input low-level pulse width tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C - Q) TxDi output td(C - Q) tsu(D - C) RxDi input tw(INL) INTi input, NMI input Test conditions * Vcc = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 136 tw(INH) th(C - D) Max. Unit ns ns MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION READY, HOLD TIMING Timing requirements (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD) Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Limits Min. 40 40 0 0 Max. Switching characteristics (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Limits Symbol Parameter Max. Min. td(1-HLDAL) HLDA output delay time 20 td(RDH-HLDAL) HLDA low-level output delay time after read tc -15 (Note) td(BXWH-HLDAL) HLDA low-level output delay time after write tc -15 (Note) 10 tpxz(HLDAL-RDZ) Floating start delay time -15 10 tpxz(HLDAL-BXWZ) Floating start delay time -15 10 tpxz(HLDAL-CSiZ) Floating start delay time -15 10 tpxz(HLDAL-ALEZ) Floating start delay time -15 10 tpxz(HLDAL-AZ) Floating start delay time -15 tpzx(HLDAL-RDZ) Floating release delay time 0 tpzx(HLDAL-BXWZ) Floating release delay time 0 tpzx(HLDAL-CSiZ) Floating release delay time 0 tpzx(HLDAL-ALEZ) Floating release delay time 0 tpzx(HLDAL-AZ) Floating release delay time 0 Unit ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note: tc = 1/f(XIN). 137 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION RDY input 1 RD, BLW, BHW tsu (RDY-1) th (1-RDY) RDY input : Wait inserted by software (The above is applied when 1 wait is selected.) : Wait inserted by Ready function HOLD input 1 tsu (HOLD-1) th (1-HOLD) HOLD input td (1-HLDAL) td (1-HLDAL) HLDA output td (RDH-HLDAL) tpxz (HLDAL-RDZ) tpzx (HLDAL-RDZ) Hi-Z RD td (BXWH-HLDAL) tpxz (HLDAL-BXWZ) tpzx (HLDAL-BXWZ) Hi-Z BLW BHW tpxz (HLDAL-CSiZ) tpzx (HLDAL-CSiZ) Hi-Z CSi tpxz (HLDAL-ALEZ) tpzx (HLDAL-ALEZ) Hi-Z ALE tpxz (HLDAL-AZ) A0-A23 output Test conditions * VCC = 5 V 0.5 V, Ta= -20 to 85 C * RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V * HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 138 tpzx (HLDAL-AZ) Hi-Z MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION External bus timing For limits depending on f(XIN), their calculation formulas are shown below. W = 0 (0 wait) W = 1 (1 wait) W = 2 (2 wait) tc = 1/f(XIN). Timing Requirements (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol Limits When 0/1/2 wait is selected When ALE expansion wait is selected Unit Parameter Min. tc tw(half) tw(H) tw(L) tr tf ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Max. 50 0.45 tc 0.5tc-8 0.5tc-8 Min. 50 0.45tc 0.5tc-8 0.5tc-8 0.55tc 0.55tc 8 8 4tc-45 3.5tc-35 2tc-30 8 8 (2 + W)tc-45 (1.5 + W)tc-35 (1 + W)tc-30 15 0 Max. 15 0 2tc-35 (1 + W)tc-35 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns External clock input tw(L) tw(H) tr tf tc tw(half) f(XIN) Test conditions * Vcc = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) * Output timing voltage : 2.5 V (tc, tw(half)) 139 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Switching characteristics (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Limits Symbol td(1-RDL) td(1-RDH) td(1-BXWL) td(1-BXWH) tw(ALEH) td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Parameter Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time ALE pulse width ALE completion delay time after address stabilization Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read Address hold time after read (Note 3) ALE completion delay time after read start Read disable valid time after ALE completion Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write Address hold time after write (Note 3) ALE completion delay time after write start Write disable valid time after ALE completion Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write Floating start delay time after write When 0/1/2 wait is selected When ALE expansion wait is selected Unit Min. Max. Min. Max. -10 -10 -10 -10 0.5tc-20 tc-30 (1+W)tc-15 tc-15 tc-15 tc-30 8 15 10 15 10 -10 -10 -10 -10 tc-20 1.5tc-30 2tc-15 2tc-15 tc-15 2tc-30 8 15 10 15 10 20 0.5tc-20 0.5tc-20 (1.5 + W)tc-20 0.5tc-20 tc-15 1.5tc-20 3.5tc-20 0.5tc-20 tc-15 (1 + W)tc-15 tc-15 tc-15 tc-30 8 2tc-15 2tc-15 tc-15 2tc-30 8 20 0.5tc-20 1.5tc-20 3.5tc-20 0.5tc-20 2tc-20 0.5tc-10 0.5tc-20 (1.5 + W)tc-20 0.5tc-20 (1 + W)tc-20 0.5tc-10 0.5tc+10 0.5tc+10 Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). However, except for the case at instruction prefetch. 140 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MI ELI . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Normal access : 0/1/2 wait tc f(XIN) Bus cycle <At read> 1 td(1-RDL) td(1-RDH) tw(ALEH) ALE td(A-ALEL) tw(RDL) tw(RDH) RD td(RDH-ALEL) td(RDH-BXWH) BLW BHW th(RDH-A) td(A-RDH) A0-A23 td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) CSi ta(A-D) ta(CSiL-D) ta(RDL-D) td(RDH-D) tsu(D-RDL) th(RDH-D) D0-D7, D8-D15 Bus cycle <At write> 1 td(1-BXWL) td(1-BXWH) tw(ALEH) ALE td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW td(A-BXWH) td(BXWH-ALEL) th(BXWH-A) A0-A23 td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) CSi td(D-BXWL) th(BXWH-D) D0-D7, D8-D15 tpxz(BXWH-DZ) Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.5 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 141 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Normal access : ALE expansion wait tc f(XIN) Bus cycle <At read> 1 td(1-RDL) tw(ALEH) td(1-RDH) td(ALEL-RDH) ALE td(A-ALEL) tw(RDH) tw(RDL) RD td(RDH-BXWH) BLW BHW th(RDH-A) td(A-RDH) A0-A23 td(CSiL-RDH) th(RDH-CSiL) td(CSiL-RDL) CSi ta(A-D) td(RDH-D) tsu(D-RDL) th(RDH-D) ta(CSiL-D) ta(RDL-D) D0-D7, D8-D15 Bus cycle <At write> 1 tw(ALEH) ALE td(1-BXWL) td(1-BXWH) td(ALEL-BXWH) td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW th(BXWH-A) td(A-BXWH) A0-A23 td(CSiL-BXWH) th(BXWH-CSiL) td(CSiL-BXWL) CSi td(D-BXWL) th(BXWH-D) D0-D7, D8-D15 tpxz(BXWH-DZ) Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.5 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 142 ta(A-D) ta(RDL-D) ta(CSiL-D) td(A-RDH) td(A-ALEL) tw(RDH) td(CSiL-RDH) td(RDH-ALEL) th(BA-D) ta(BA-D) Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.5 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) D0-D7, D8-D15 CSi A0-A23 BLW BHW RD ALE tw(ALEH) Burst ROM access : 0/1/2 wait at instruction prefetch th(BA-D) ta(BA-D) th(BA-D) ta(BA-D) th(RDH-D) th(RDH-CSiL) th(RDH-A) td(RDH-BXWH) PR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 143 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DRAM access Timing Requirements (VCC = 5 V 0.5 V, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Parameter Symbol ta(RASL-D) ta(CASL-D) th(CASH-D) RAS access time CAS access time Data input hold time after CAS Limits Min. Max. 2.5tc-35 tc-30 0 Unit ns ns ns Switching characteristics (VCC = 5 V 0.5 V, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(RASH) td(CASH-RASH) th(RASL-CASH) th(CASL-RASL) tw(CASL) td(RA-RASH) th(RASL-RA) td(CA-CASH) th(CASH-CA) td(WH-CASH) td(WL-CASH) th(CASL-WL) td(D-CASH) th(CASL-D) tpxz(CASH-D) tpxz(WH-D) 144 Parameter RAS high-level pulse width CAS high-level valid time before RAS CAS high-level hold time after RAS's low level RAS hold time after CAS's low level CAS low-level pulse width Row address valid time before RAS Row address hold time after RAS's low level Column address valid time before CAS Column address hold time after CAS's high level W high-level valid time before CAS W low-level valid time before CAS W hold time after CAS's low level Data output valid time before CAS Data output hold time after CAS's low level Floating start delay time after CAS Floating start delay time after write Limits Min. Max. 1.5tc-20 1.5tc-20 1.5tc-20 tc-15 tc-15 0.5tc-25 tc-40 0.5tc-20 0 3tc-15 tc-15 tc-15 tc-20 1.5tc-15 0.5tc+10 0.5tc+10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DRAM access 1 <At read> tw(RASH) RASi th(RASL-CASH) td(CASH-RASH) th(CASL-RASL) tw(CASL) LCAS,UCAS (CAS) td(RA-RASH) td(CA-CASH) th(CASH-CA) Row address A0-A23 Column address Row address Column address th(RASL-RA) td(WH-CASH) W (WRL,WRH) ta(RASL-D) th(CASH-D) ta(CASL-D) D0-D7, D8-D15 <At write> tw(RASH) RASi th(RASL-CASH) td(CASH-RASH) th(CASL-RASL) tw(CASL) LCAS,UCAS (CAS) td(RA-RASH) td(CA-CASH) th(CASH-CA) A0-A23 Row address Column address th(RASL-RA) td(WL-CASH) Row address Column address th(CASL-WL) W (WRL,WRH) td(D-CASH) th(CASL-D) D0-D7, D8-D15 tpxz(CASH-D) Test conditions * VCC = 5 V 0.5 V, Ta = 0 to 70 C * Input timing voltage : VIL=0.8 V, VIH=2.5 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (RASi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for RASi) 145 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DRAM refresh Switching characteristics (VCC = 5 V 0.5 V, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(RASCBRL) tw(CASCBRL) td(CASCBRL-RASCBRH) td(RASCBRL-CASCBRL) td(CASSLFRL-RASSLFRH) th(RASSLFRH-CASSLFRL) 146 Parameter RAS low-level pulse width (At CAS before RAS refresh) CAS low-level pulse width (At CAS before RAS refresh) RAS high-level valid time after CAS's low level start (At CAS before RAS refresh) CAS low-level valid time after RAS's low level start (At CAS before RAS refresh) RAS high-level valid time after CAS's low level start (At selfrefresh) CAS low-level hold time after RAS's high level (At selfrefresh) Limits Min. 2tc-15 2tc-15 tc-15 tc-15 tc-15 -15 Max. 15 Unit ns ns ns ns ns ns MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DRAM refresh : CAS before RAS refresh 1 tw(RASCBRL) RASi td(CASCBRL-RASCBRH) td(RASCBRL-CASCBRL) tw(CASCBRL) LCAS,UCAS (CAS) W (WRL,WRH) Refresh cycle DRAM refresh : selfrefresh 1 RASi td(CASSLFRL-RASSLFRH) th(RASSLFRH-CASSLFRL) LCAS,UCAS (CAS) W (WRL,WRH) Refresh cycle Test conditions * VCC = 5 V 0.5 V, Ta = 0 to 70 C * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (RASi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for RASi) 147 MI ELI . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DMA transfer timing Timing Requirements (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) tsu(TCINL-1) tw(TCINL) tsu(DRQL-1) tw(DRQL) Limits Parameter Symbol Max. Min. TC input setup time TC input pulse width DMAREQi input setup time DMAREQi input pulse width Unit ns ns ns ns 40 tc + 20 40 tc Switching characteristics (VCC = 5 V 0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(TCL) td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Limits Parameter Min. TC output pulse width TC output start delay time after read TC output start delay time after write DMAACK low-level output valid time after TC output start tc-20 tc-15 tc-15 2.5tc-20 Max. Unit ns ns ns ns 3 k TC 50 pF Test circuit for TC output 148 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR * TC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION input 1 tsu(TCINL-1) tw(TCINL) TC input * DMAREQi input 1 tsu(DRQL-1) tw(DRQL) DMAREQi input Test conditions * Vcc = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF * Transfer terminate timing Final transfer cycle Terminate processing (Next bus cycle) ALE RD BLW BHW A0-A23 CSi D0-D7, D8-D15 tw(TCL) TC td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) DMAACKi Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 149 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP . . nge tion ifica t to cha pec al s subjec in f are ot a is n limits his e: T ametric ic t No e par Som PR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PACKAGE OUTLINE 100P6S-A Plastic 100pin 1420mm body QFP EIAJ Package Code QFP100-P-1420-0.65 Weight(g) 1.58 Lead Material Alloy 42 MD e JEDEC Code - ME HD D 81 b2 100 1 80 I2 E HE Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y 51 30 50 A L1 c A2 31 b F A1 e b2 I2 MD ME L Detail F y 100P6Q-A Dimension in Millimeters Max Nom Min 3.05 - - 0.1 0.2 0 2.8 - - 0.4 0.3 0.25 0.2 0.15 0.13 14.2 14.0 13.8 20.2 20.0 19.8 0.65 - - 17.1 16.8 16.5 23.1 22.8 22.5 0.8 0.6 0.4 1.4 - - 0.1 - - 10 0 - 0.35 - - - - 1.3 - 14.6 - - 20.6 - Plastic 100pin 1414mm body LQFP EIAJ Package Code LQFP100-P-1414-0.50 Weight(g) Lead Material Cu Alloy MD e JEDEC Code - b2 ME HD D 100 76 I2 75 1 Symbol HE E Recommended Mount Pad 51 25 26 50 A L1 F b y A1 c A2 e L Detail F 150 A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max - 1.7 - 0.1 0.2 0 1.4 - - 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - - 0.1 - 0 10 - - 0.225 - 1.0 - - - 14.4 - - 14.4 - MI ELI Y NAR . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR MITSUBISHI MICROCOMPUTERS M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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No. M37920FCCGP/HP, M37920FGCGP/HP Datasheet Revision Description Rev. date 1.0 First Edition 990602 2.0 Refer to Corrections and Supplementary Explanation for "M37920FxCGP/HP Datasheet (REV.A)". 000628 (1/1) Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.1 Page All pages, Header Page 1 DESCRIPTI ON; Lines 11, 12 Page 1 DISTI NCTIVE FEAT URES ; Memory Page 1 DISTI NCTIVE FEAT URES ; Interrupts Page 2, Error Correction M37920F8CGP, M37920F8CHP, M37920FCCGP, M37920FCCHP, M37920FGCGP, M37920FGCHP M37920FCCGP, M37920FCCHP, M37920FGCGP, M37920FGCHP These microcomputers include the 4-channel DMA controller and the DRAM controller with enhanced fast page mode. These microcomputers include the 4-channel DMA controller and the DRAM controller. [M37920F8CGP, M37920F8CHP] Flash memory (User ROM area) ......................60 Kbytes RAM.................................................................2048 bytes Interrupts ......................6 external sources, 17 internal sources, 7 levels (Type) Page 120, Interrupts ......................6 external sources, 20 internal sources, 7 levels (Type) M37920F8CGP M37920FCCGP M37920FGCGP PIN CONFIGURATION (Deleted) M37920FCCGP M37920FGCGP Fig. 118, Pin connection of M37920FxCGP in flash memory Page 3, (Type) (Type) M37920F8CHP M37920FCCHP M37920FGCHP PIN CONFIGURATION Page 121, M37920FCCHP M37920FGCHP Fig. 119, Pin connection of M3792 0FxCHP in flash memory Page 4, Note: Note: BLOCK DIAGRAM Note: Flash memory 60 Kbytes M37920F8CGP,M37920F8CHP M37920FCCGP,M37920FCCHP 120 Kbytes M37920FGCGP,M37920FGCHP 248 Kbytes Page 5, DRAM controller 1 channel Supports fast page access mode. Incorparates 8-bit refresh timer. Supports CAS before RAS refresh method ****** Page 5, Chip-select wait control Page 5, Interrupts Page 5, Parameter Page 5, Note: Page 6, N o te RAM 2048 bytes 4096 bytes 6144 bytes M37920FCCGP,M37920FCCHP M37920FGCGP,M37920FGCHP Flash memory 120 Kbytes 248 Kbytes RAM 4096 bytes 6144 bytes 1 channel Incorparates 8-bit refresh timer. Supports CAS before RAS refresh method ****** Chip select area 4 (CS0-CS3). A wait number and bus width can be set for each chip select area. Chip select area 4 (CS0-CS3). A bus cycle type and bus width can be set for each chip select area. 6 external types, 17 internal types. Each interrupt ****** 6 external types, 20 internal types. Each interrupt ****** Operating temperature range ****** Note: ***** Note: Flash memory (User ROM area) RAM M37920F8C GP,M37920F8C HP M37920FC CGP,M3792 0FCCHP M37920FGCGP, M37920FG CHP M37920F8C GP,M37920F8C HP M37920FC CGP,M3792 0FCCHP M37920FGCGP, M37920FG CHP 60 Kbytes 120 Kbytes 248 Kbytes 2048 bytes 4096 bytes 6144 bytes Note: User ROM area Operating ambient temperature range Flash memory M37920FCCGP,M37920FCCHP (User ROM M37920FGCGP,M37920FGCHP area) M37920FCCGP,M37920FCCHP RAM M37920FGCGP,M37920FGCHP 120 Kbytes 248 Kbytes 4096 bytes 6144 bytes Note: M37920F8C GP, M37920F8CH P 4 blocks ****** M37920FC CGP, M37920FCC HP 5 blocks ****** M37920FGCGP, M37920 FGCHP 7 blocks ****** (1/6) User ROM area M37920FC CGP, M37920FCC HP 5 blocks ****** M37920FGCGP, M37920 FGCHP 7 blocks ****** Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.2 Page Error Correction Memory map of M37920F8CGP and M37920F8CHP (Single-chip mode) (Deleted) Page 9, Fig. 1 Fig. 2. Memory map of M37920FCCGP and M37920FCCHP (Single-chip mode) Fig. 1. Memory map of M37920FCCGP and M37920FCCHP (Single-chip mode) Page 10, Fig. 2 Fig. 3. Memory map of M37920FGCGP and M37920FGCHP (Single-chip mode) Fig. 2. Memory map of M37920FGCGP and M37920FGCHP (Single-chip mode) Page 11, Fig. 4; address 0016, 0116 Page 18, Table 1 00000016 00000016 00000116 00000116 Reserved area (Note) Reserved area (Note) Temporarity stores an instruction which ********. Temporarily stores an instruction which ********. Temporarity stores data which has been ********, and external areas by the BIU or which is to be writeen to internal memory, ******** . Temporarily stores data which has been ********, and external areas by the BIU; or temporarily stores data which is to be written to internal memory, ******** . Instruction queue buffer Data buffer Page 18, Fig. 8 The final page of Selection of "processor mode" Page 28, Fig. 12 b31 b0 b31 b0 Data buff er DB Data buff er DQ (this contents is published for one page) ALE is an address latch enable signal. ******** ******** Note: The chip select wait controller, ******** by the chip select wait controller. 7 6 0 5 4 3 2 1 0 0 (Deleted) 7 Processor mode register 1 6 0 5 4 3 2 1 0 0 Processor mode register 1 * * * * Direct page register switch bit **** Direct page register switch bit (Note 1) **** RDY input select bit RDY input select bit (Notes 2 to 4) **** **** ALE output select bit **** ALE output select bit (Notes 2 and 3) Recovery cycle insert select bit **** HOLD input, HLDA output select bit 0: ***** (P40 and P44 function as ***) 1: ******** Internal ROM access wait bit **** **** Recovery cycle insert select bit (Notes 2 and 3) **** HOLD input, HLDA output select bit (Notes 2 to 4) 0: ***** (P43 and P44 function as ***) 1: ******** Internal ROM access wait bit (Note 5) **** (2/6) Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.3 Page Error Correction Page 28, Fig. 12 Page 35, Fig. 17, Notes 1: After reset, this bit's contents can be switched only once. During the software execution, be sure not to switch this bit's contents. 2: In the single-chip mode, these bits' functions are disabled regardless of these bits' contents. 3: While VSS level voltage is applied to pin MD0, each of these bits is "0" at reset. While VCC level voltage is applied to pin MD0, on the other hand, each of these bits is "1" at reset. 4: In the memory expansion or microprocessor mode, if this bit's contents is switched from "1" to "0", this bit will be cleared to "0". After this clearance, this bit cannot return to "1". If it is necessary to set this bit to "1", be sure to reset the microcomputer. 5: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to "0". 2 1 0 Area CSx st art address regi ster (x = 0 to 3) 2 Area CSx start address register (x = 0, 3) 1 0 These bits determine ***** Area CS3 start address register (x = 0, 3) "0" at read. * * These bits determine ***** * * 2 1 0 2 Area CSx start address register (x = 1, 2) 1 0 When mode 0 is ***** Area CSx start address register (x = 1, 2) "0" at read. * * When mode 0 is ***** * * Page 51, Left column, Lines 14, 17, 22 Page 61, Interrupt request at completion of reception ***** timer Ai start bit ***** (Line 9) Page 68, (Line 9) ***** control register 0 (UART receive interrupt mode select bit) ***** (Lines 18, 20) ***** control register 0 (UARTk receive interrupt mode select bit) ***** (Lines 18, 20) ***** UARTi receive interrupt mode select bit ***** Page 67, Fig. 63 VREF connection ***** count start bit ***** ***** UARTk receive interrupt mode select bit ***** Ladder network Resistor ladder network (Lines 2, 3) (Lines 2, 3) ******* the ladder network or not *********** ******* the resistor ladder network or not *********** (Line 7) (Line 7) the ladder network can be cut off by disconnecting ladder network ******* the resistor ladder network can be cut off by disconnecting resistor ladder network ******* (3/6) Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.4 Page Page 92, Left column, Lines 28, 29 Page 95, Fig. 90 Error Correction ******* selected. Bit 2 of the DRAM control register is the access mode select bit. When bit 2 is "0", normal access is selected, when it is "1", fast page access is selected. When the fast page access is selected, the access supporting the fast page access mode of DRAM is performed, if the range which can be specified with the same row address is continuously accessed. If the row address changes during the fast page access, the new row addresses will be output again after that fast page access is terminated. Then, the fast page access will restart. Figure 93 shows an operating waveform example of the DRAM control signals and address bus in the fast page access. Bit 4 of the DRAM ******* 2 1 0 0 DRAM control register ******* selected. Bit 4 of the DRAM ******* 2 1 0 0 0 Access mode select bit 0: Normal access 1: Fast page access Page 99, Right column, Lines 1 to 3 Page 117, Right column, Lines 15 to 17 When the waveform output select bits are set to "11" (bit 1 = bit 0 = "1"), RTP13 to RTP10, RTP03, and RTP02 become pulse output port pins. When the waveform output ********* DRAM control register Fix this bit to "0". When the waveform output select bits are set to "11" (bit 1 = bit 0 = "1"), pulse output port pins are divided into two groups; one consists of RTP13 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00. When the waveform output ********* Operating waveform example of DRAM control signals and address bus in fast page access (Deleted) M37920F8CGP, M37920F8CHP : block configuration of internal flash memory (Deleted) area if the user uses the flash memory serial I/O mode. Note that, when the boot ROM area is read ********* area if the user uses the flash memory serial I/O mode. Addresses FFB016 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. Note that, when the boot ROM area is read ********* The reset input pin. Input "H" after "L" is input. The reset input pin. P42; [Function] This is an I/O pin for serial data. This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 k). P44; [Function] This is an input pin for a serial clock. Connect this pin to VCC via a resistor (about 1 k). This is an input pin for a serial clock. NMI; [Function] Input "H". Input "H", or leave this pin open. Page 118 RESET; [Function] Page 122, Boot mode (Lines 22, 23) (Lines 22, 23) program the user ROM area. program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. Page 122, Fig. 120, Note 4 4: Valid only when bit 1 = "1". Set bit 3 to "1" (reset), and then clear to "0". 4: Valid only when bit 1 = "1". Set bit 3 to "1" (reset), and then clear to "0". This bit 3 must be controlled with the CPU reprogramming mode select bit (bit 1) = "1". (4/6) Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.5 Page Error Correction Page 123, Left column, Lines 15 to 19 Therefore, a software command consists of 8-bit units must be written only to an even address; therefore, any data written to an odd address will be invalid. The write state ****** Therefore, a software command consisting of 8 bits must be written to an even address; therefore, any command written to an odd address will be invalid. Since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. The write state ****** Page 123, Right column, After line 24 request occurrence. request occurrence. In the CPU reprogramming mode, be sure not to use the STP and WIT instructions. Page 124, Fig. 121 The CPU reprogramming mode select bit is set to "1". (Writing of "0" Writing of "1") Page 124, Software Commands Page 124, Page program Command Page 125, Page program Command Writing of "1" to the CPU reprogramming mode select bit. (Writing of "0" Writing of "1") (Lines 6, 7) (Lines 6, 7) ******* (D8-D15) is ignored. ******* (D8-D15) is ignored. (Except for the write data at the 2nd cycle of a page programming command.) (Titlle) (Titlle) Page Program Command (4116) Page Programming Command (4116) (After line 20) (After line 20) ******* mode is maintained. ******* mode is maintained. In continuous programming, if there is no programming error, page programming commands can be executed with the read status register mode kept. (Lines 4 to 7) (Lines 4 to 7) *******, the same way as bit 7 of the status register. Reading out the ******* *******, the same wayas bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to "1" (READY). During the automatic programming operation, writing of commands and access to the flash memory must not be performed. Reading out the ******* Page 125, (Lines 20 to 23) (Lines 20 to 23) Block Erase Command *******, the same way as bit 7 of the status register. Reading out the ******* *******, the same way as bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to "1" (READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed. Reading out the ******* Page 127, (Lines 9 to 11) (Lines 9 to 11) ******* is also reported by a read of the status register. When the lock bit ******* ******* is also reported by a read of the status register. During the automatic erase execution (when the RY/BY status bit = "0" ), writing of commands and access to the flash memory must not be performed. When the lock bit ******* (After line 20) (After line 20) lock bit is terminated. lock bit is terminated. To perform erase or programming, be sure to do one of the following. * By executing the read lock bit status command, verify that the lock of the target block is invalid. * Set the lock bit invalidity select bit to "1" to invalidate the lock. When the block erase or programming is performed with the lock valid, the erase status bit (SR.5) and programming status bit (SR.4) are set to "1" (terminated by error). Erase All Unlocked Block Command Page 127, Data Protect Function (Block Lock) (5/6) Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.6 Page Page 130, ABSOLUTE MAXIMUM RATINGS; Topr Error Correction Operating temperature ****** Page 144, Switching characteristics Symbol Limits Min. Max. Unit Symbol ns tpxz(CASH-D) Floating start delay time after CAS td(CAF-CASH) Column address valid time before tc-40 ns tpxz(WH-D) Floating start delay time after write td(WFL-CASH) W low-level valid time before CAS 0.5tc-20 ns tpxz(CASH-D) Parameter Floating start delay time after CAS 0.5tc+10 CAS (When fast page access ON is selected) (When fast page access ON is selected) Page 145, DRAM access Operating ambient temperature td(DF-CASH) Data output valid time before CAS 0.5tc-20 (When fast page access ON is selected) tpxz(WH-D) Floating start delay time after write Parameter ns 0.5tc+10 ns (Title) (Title) DRAM access : fast page access OFF DRAM access Timing of DRAM access : fast page access OFF (6/6) (Deleted) ***** Limits Min. Max. 0.5tc+10 Unit ns 0.5tc+10 ns