15-output DB1900Z Low-Power Derivative 9ZXL1550 DATASHEET Description Features/Benefits The 9ZXL1550 is a DB1900Z derivative buffer utilizing Low-Power HCSL (LP-HCSL) outputs to increase edge rates on long traces, reduce board space, and reduce power consumption more than 50% from the original 9ZX21501. It is pin-compatible to the 9ZXL1530 and has the output terminations integrated. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications. * LP-HCSL outputs; up to 90% IO power reduction, better * * * * * Recommended Application * Buffer for Romley, Grantley and Purley Servers * * * Key Specifications * * * * * Cycle-to-cycle jitter: < 50ps Output-to-output skew: <75ps Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI 9.6GB/s < 0.2ps rms * * signal integrity over long traces Direct connect to 85 transmission lines; eliminates 60 termination resistors, saves 103mm2 area Pin compatible to the 9ZXL1530; easy upgrade to reduced board space 64-VFQFPN package; smallest 15 output Z-buffer Fixed feedback path: ~ 0ps input-to-output delay 9 Selectable SMBus addresses; multiple devices can share same SMBus segment Separate VDDIO for outputs; allows maximum power savings PLL or bypass mode; PLL can dejitter incoming clock 100MHz & 133.33MHz PLL mode; legacy QPI/UPI support Selectable PLL BW; minimizes jitter peaking in downstream PLL's Spread spectrum compatible; tracks spreading input clock for EMI reduction SMBus Interface; unused outputs can be disabled Output Features * 15 - LP-HCSL Differential Output Pairs w/integrated terminations (Zo = 85) Block Diagram FBOUT_NC Z-PLL (SS Compatible) DIF_IN DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri DIF(14:0) Logic SMBDAT SMBCLK 9ZXL1550 REVISION E 11/20/15 1 (c)2015 Integrated Device Technology, Inc. 9ZXL1550 DATASHEET DIF10 DIF10# VDDIO GND DIF11 DIF11# DIF12 DIF12# GND VDD DIF13 DIF13# DIF14 DIF14# VDDIO GND Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA GNDA 100M_133M# HIBW_BYPM_LOBW# CKPWRGD_PD# GND VDDR DIF_IN DIF_IN# SMB_A0_tri SMBDAT SMBCLK SMB_A1_tri FBOUT_NC# FBOUT_NC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 9ZXL1550 EPAD is Pin 65 VDDIO GND DIF9# DIF9 DIF8# DIF8 GND VDD DIF7# DIF7 DIF6# DIF6 VDDIO GND DIF5# DIF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDDIO DIF4# DIF4 DIF3# DIF3 VDD GND DIF2# DIF2 DIF1# DIF1 GND VDDIO DIF0# DIF0 9x9 mm 64-pin VFQFPN Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm Power Management Table Inputs CKPWRGD_PD# 0 DIF_IN/ DIF_IN# X 1 Running Outputs Control Bits SMBus DIFx/ FBOUT_NC/ EN bit DIFx# FBOUT_NC# X Low/Low Low/Low 0 Low/Low Running 1 Running Running Power Connections GND 2 6 16,20,25,32, 19,31,36,48,5 26, 41, 58 35,42,47,52, 1,63 57,64 HiBW_BypM_LoBW# Byte0, bit (7:6) Low ( PLL Low BW) 00 Mid (Bypass) 01 High (PLL High BW) 11 NOTE: PLL is off in Bypass mode Description Analog PLL Analog Input DIF clocks Tri-Level Input Thresholds Level Low Mid High Functionality at Power-up (PLL mode) 100M_133M# 1 0 OFF ON ON PLL Operating Mode Pin Number VDDIO VDD 1 7 PLL State DIF_IN (MHz) 100.00 133.33 DIFx (MHz) DIF_IN DIF_IN 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2 Voltage <0.8V 1.2<Vin<1.8V Vin > 2.2V REVISION E 11/20/15 9ZXL1550 DATASHEET Pin Descriptions PIN # PIN NAME 1 VDDA 2 GNDA 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TYPE DESCRIPTION PWR Power for the PLL core. GND Ground pin for the PLL core. 3.3V Input to select operating frequency. 100M_133M# IN See Functionality Table for Definition Trilevel input to select High BW, Bypass or Low BW mode. HIBW_BYPM_LOBW# IN See PLL Operating Mode Table for Details. 3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down CKPWRGD_PD# IN Mode on subsequent assertions. Low enters Power Down Mode. GND GND Ground pin. 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and VDDR PWR filtered appropriately. DIF_IN IN HCSL True input DIF_IN# IN HCSL Complementary Input SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMB_A0_tri IN SMBus Addresses. SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMB_A1_tri IN SMBus Addresses. Complementary half of differential feedback output. This pin should NOT be connected to anything outside FBOUT_NC# OUT the chip. It exists to provide delay path matching to get 0 propagation delay. True half of differential feedback output. This pin should NOT be connected to anything outside the chip. FBOUT_NC OUT It exists to provide delay path matching to get 0 propagation delay. GND GND Ground pin. DIF0 OUT Differential true clock output DIF0# OUT Differential Complementary clock output VDDIO PWR Power supply for differential outputs GND GND Ground pin. DIF1 OUT Differential true clock output DIF1# OUT Differential Complementary clock output DIF2 OUT Differential true clock output DIF2# OUT Differential Complementary clock output GND GND Ground pin. VDD PWR Power supply, nominal 3.3V DIF3 OUT Differential true clock output DIF3# OUT Differential Complementary clock output DIF4 OUT Differential true clock output DIF4# OUT Differential Complementary clock output VDDIO PWR Power supply for differential outputs GND GND Ground pin. REVISION E 11/20/15 3 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Pin Descriptions (cont.) PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 PIN NAME DIF5 DIF5# GND VDDIO DIF6 DIF6# DIF7 DIF7# VDD GND DIF8 DIF8# DIF9 DIF9# GND VDDIO DIF10 DIF10# VDDIO GND DIF11 DIF11# DIF12 DIF12# GND VDD DIF13 DIF13# DIF14 DIF14# VDDIO GND EPAD TYPE OUT OUT GND PWR OUT OUT OUT OUT PWR GND OUT OUT OUT OUT GND PWR OUT OUT PWR GND OUT OUT OUT OUT GND PWR OUT OUT OUT OUT PWR GND GND DESCRIPTION Differential true clock output Differential Complementary clock output Ground pin. Power supply for differential outputs Differential true clock output Differential Complementary clock output Differential true clock output Differential Complementary clock output Power supply, nominal 3.3V Ground pin. Differential true clock output Differential Complementary clock output Differential true clock output Differential Complementary clock output Ground pin. Power supply for differential outputs Differential true clock output Differential Complementary clock output Power supply for differential outputs Ground pin. Differential true clock output Differential Complementary clock output Differential true clock output Differential Complementary clock output Ground pin. Power supply, nominal 3.3V Differential true clock output Differential Complementary clock output Differential true clock output Differential Complementary clock output Power supply for differential outputs Ground pin. Epad should be connected to GND 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 4 REVISION E 11/20/15 9ZXL1550 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9ZXL1550. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA, R VDD VDDIO VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP MAX 4.6 4.6 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins VDD+0.5V 5.5V -65 Human Body Model 150 125 2000 UNITS NOTES V V V V V V C C V 1,2 1,2 1,2 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. 2 Electrical Characteristics-DIF_IN Clock Input Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN VCROSS Cross Over Voltage 150 V SWING Differential value 300 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 Input Leakage Current IIN V IN = VDD , V IN = GND -5 Input Duty Cycle dtin Measurement from differential wavefrom Input Jitter - Cycle to Cycle J DIFIn Differential Measurement Input Crossover Voltage DIF_IN Input Swing - DIF_IN TYP MAX 900 UNITS NOTES mV 1 mV 1 8 V/ns 1,2 5 uA 45 55 % 1 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero 2 REVISION E 11/20/15 5 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Electrical Characteristics-Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Ambient Operating Temperature TCOM Commmercial range 0 35 70 C Input High Voltage VIH 2 VDD + 0.3 V Input Low Voltage VIL GND - 0.3 0.8 V -5 5 uA Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA V DD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode VDD = 3.3 V, 133.33MHz PLL mode 33 90 120 CINDIF_IN Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 150 110 147 7 5 2.7 MHz MHz MHz nH pF pF 2 2 2 1 1 1,4 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 0.65 1 ms 2 Input SS Modulation Frequency fMODIN Allowable Frequency (Triangular Modulation) 31.5 33 kHz Tdrive_PD# tDRVPD 25 300 us Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, V IN = VDD IIN Input Current Input Frequency Pin Inductance Capacitance IINP Fibyp Fipll Fipll Lpin CIN Tfall tF DIF output enable after PD# de-assertion Fall time of control inputs Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tR Rise time of control inputs VILSMB VIHSMB V OLSMB IPULLUP V DDSMB tRSMB tFSMB @ IPULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) fMINSMB Maximum SMBus operating frequency 30 2.1 4 2.7 100 100.00 133.33 UNITS NOTES 1,3 5 ns 1,2 5 0.8 ns V V V mA V ns ns 1,2 kHz 5 VDDSMB 0.4 5.5 1000 300 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 6 REVISION E 11/20/15 9ZXL1550 DATASHEET Electrical Characteristics-DIF LP-HCSL Differential Outputs TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate Slew rate matching Trf Trf Scope averaging on Slew rate matching. 1.5 2.7 8.8 4 20 Voltage High VHigh 660 787 850 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) -150 33 150 Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vcross_abs -Vcross Single ended signal using absolute value. Includes 300mV of over/undershoot. (Scope Scope averaging off Scope averaging off 845 9 471 14 1150 -300 250 V/ns % 1, 2, 3 1, 2, 4 mV 550 140 mV mV mV 1, 5 1, 6 Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 27 for Zo = 85 differential trace impedance. 1 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute. Electrical Characteristics-Current Consumption TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS IDDVDD All outputs 100MHz, CL = 2pF; Zo = 85 All outputs 100MHz, CL = 2pF; Zo = 85 All outputs 100MHz, CL = 2pF; Zo = 85 All differential pairs low-low All differential pairs low-low All differential pairs low-low Operating Supply Current IDDVDDA/R IDDVDDIO IDDVDDPD Powerdown Current IDDVDDA/RPD IDDVDDIOPD MIN TYP MAX UNITS NOTES 17 15 112 2.1 4.4 0.0 30 20 150 4 7 1.5 mA mA mA 1 1 1 1 1 1 mA mA mA 1 Guaranteed by design and characterization, not 100% tested in production. REVISION E 11/20/15 7 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Electrical Characteristics-Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS Input-to-Output Skew in PLL mode nominal value @ 35C, 3.3V, 100MHz Input-to-Output Skew in Bypass mode nominal value @ 35C, 3.3V Input-to-Output Skew Varation in PLL mode across voltage and temperature MIN TYP MAX UNITS NOTES CLK_IN, DIF[x:0] t SPO_PLL -150 -117 -50 ps 1,2,4,5,8 CLK_IN, DIF[x:0] t PD_BYP 2.5 4 4.5 ns 1,2,3,5,8 CLK_IN, DIF[x:0] t DSPO_PLL -50 0 50 ps 1,2,3,5,8 CLK_IN, DIF[x:0] t DSPO_BYP Input-to-Output Skew Varation in Bypass mode across temperature for a given voltage -250 0 250 ps 1,2,3,5,8 CLK_IN, DIF[x:0] t DTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode 1 5 ps (rms) 1,2,3,5,8 CLK_IN, DIF[x:0] t DSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 5 75 ps 1,2,3,5,8 DIF[x:0] tSKEW_ALL Output-to-Output Skew across all outputs (Common to Bypass and PLL mode). 100MHz 53 75 ps 1,2,3,8 PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Duty Cycle jpeak-hibw jpeak-lobw pllHIBW pllLOBW t DC 0 0 2 0.7 45 1.8 0.7 3.3 1.2 50 2.5 2 4 1.4 55 dB dB MHz MHz % 7,8 7,8 8,9 8,9 1 Duty Cycle Distortion tDCD 0 1 2 % 1,10 Jitter, Cycle to cycle t jcyc-cyc 12 0 50 50 ps ps 1,11 1,11 LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 Measured differentially, PLL Mode Measured differentially, Bypass Mode @100MHz PLL mode Additive Jitter in Bypass Mode Notes for preceding table: 1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. 6. t is the period of the input clock 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. 10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 11 Measured from differential waveform 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 8 REVISION E 11/20/15 9ZXL1550 DATASHEET Electrical Characteristics-Phase Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions PARAMETER SYMBOL t jphPCIeG1 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) t jphPCIeG2 Phase Jitter, PLL Mode t jphPCIeG3 t jphQPI_SMI t jphPCIeG1 t jphPCIeG2 Additive Phase Jitter, Bypass mode t jphPCIeG3 t jphQPI_SMI MIN TYP 34 MAX 86 1.2 3 2.1 3.1 0.5 1 0.2 0.5 0.1 0.3 0.1 0.2 0.1 10 0.1 0.3 0.1 0.7 0.0 0.3 0.0 0.3 0.0 0.1 0.0 0.1 UNITS ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) 1 Applies to all outputs. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final ratification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4 6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2 Notes 1,2,3 1,2 1,2 1,2,4 1,5 1,5 1,5 1,2,3 1,2,6 1,2,6 1,2,4,6 1,5,6 1,5,6 1,5,6 Test Loads Differential Output Terminations Rs () DIF Zo () 85 Internal 7 100 (External) 9ZXL1550 Differential Test Loads 10 in., Differential Zo=85 2pF 2pF LP-HCSL Differential Output REVISION E 11/20/15 9 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Driving LVDS Driving LVDS inputs Value Receiver does Receiver has not have termination termination Note 10K ohm 140 ohm 5.6K ohm 75 ohm 0.1 uF 0.1 uF 1.2 volts 1.2 volts Component R7a, R7b R8a, R8b Cc Vcm 3.3V Driving LVDS Cc R7a R7b R8a R8b Rs Zo Cc Rs LVDS Clock input Device Clock Periods-Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 133.33 1 Clock 1us 0.1s -SSC - ppm -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94900 9.99900 7.44925 7.49925 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.00000 10.00100 7.50000 7.50075 1us +SSC Short-Term Average Max 1 Clock +c2c jitter AbsPer Max 10.05100 7.55075 Units Notes ns ns 1,2,3 1,2,4 Clock Periods-Differential Outputs with Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 133.00 1 Clock 1us 0.1s -SSC - ppm -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94906 9.99906 10.02406 7.44930 7.49930 7.51805 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.02506 10.02607 7.51880 7.51955 1us +SSC Short-Term Average Max 10.05107 7.53830 1 Clock +c2c jitter AbsPer Max 10.10107 7.58830 Units Notes ns ns 1,2,3 1,2,4 Notes: 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy requirements (+/-100ppm). The 9ZXL1550 itself does not contribute to ppm error. 3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode 4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 10 REVISION E 11/20/15 9ZXL1550 DATASHEET General SMBus Serial Interface Information How to Write * * * * * * * * * * How to Read Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit * * * * * * * * * * * * * * Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite WR ACK WRite ACK Beginning Byte = N Beginning Byte = N ACK ACK Data Byte Count = X RT ACK Beginning Byte N RD ACK X Byte O O O Repeat starT Slave Address ReaD ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit X Byte P O O O O O O Byte N + X - 1 REVISION E 11/20/15 11 N Not acknowledge P stoP bit 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET 9ZXL1550 SMBus Addressing SMB_A(1:0)_tri Address (Rd/Wrt bit = 0) (Hex) 00 D8 0M DA 01 DE M0 C2 MM C4 M1 C6 10 CA 1M CC 11 CE SMBusTable: PLL Mode, and Frequency Select Register Byte 0 Pin # Name Control Function 4 PLL Mode 1 PLL Operating Mode Rd back 1 Bit 7 PLL Mode 0 PLL Operating Mode Rd back 0 4 Bit 6 Reserved Bit 5 DIF_14_En Output Enable 61/62 Bit 4 DIF_13_En Output Enable 59/60 Bit 3 Reserved Bit 2 Reserved Bit 1 100M_133M# Frequency Select Readback 3 Bit 0 Type R R 0 1 See PLL Operating Mode Readback Table RW RW Low/Low Low/Low Enable Enable R 133MHz 100MHz Control Function Output Enable Reserved Output Enable Output Enable Output Enable Output Enable Output Enable Reserved Type RW 0 Low/Low 1 Enable RW RW RW RW RW Low/Low Enable SMBusTable: Output Control Register Byte 2 Pin # Name DIF_12_En 55/56 Bit 7 53/54 DIF_11_En Bit 6 49/50 DIF_10_En Bit 5 Bit 4 DIF_9_En 45/46 Bit 3 43/44 DIF_8_En Bit 2 39/40 DIF_7_En Bit 1 37/38 DIF_6_En Bit 0 Control Function Output Enable Output Enable Output Enable Reserved Output Enable Output Enable Output Enable Output Enable Type RW RW RW 0 1 Low/Low Enable RW RW RW RW Low/Low Enable SMBusTable: Reserved Register Byte 3 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 SMBusTable: Output Control Register Byte 1 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 39/40 DIF_5_En 29/30 29/30 23/24 21/22 17/18 DIF_4_En DIF_3_En DIF_2_En DIF_1_En DIF_0_En 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 12 Default Latch Latch 1 1 1 0 0 Latch Default 1 1 1 1 1 1 1 1 Default 1 1 1 1 1 1 1 1 Default 0 0 0 0 0 0 0 0 REVISION E 11/20/15 9ZXL1550 DATASHEET SMBusTable: Reserved Register Pin # Name Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBusTable: DEVICE ID Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SMBusTable: Byte Count Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBusTable: Reserved Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REVISION E 11/20/15 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 Control Function Type R R R R R R R R 0 1 - - Default 0 0 0 1 0 0 0 1 Type R R R R R R R R 0 1 REVISION ID VENDOR ID Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Control Function Reserved Reserved Reserved Writing to this register configures how many bytes will be read back. Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 13 Type RW RW RW RW RW Type B Rev = 0000 1550 is 155 decimal or 9B Hex 0 1 Default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. 0 1 Default 1 0 0 1 1 0 1 1 Default 0 0 0 0 1 0 0 0 Default 0 0 0 0 0 0 0 0 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Marking Diagram ICS 9ZXL1550BKL LOT COO YYWW Notes: 1. "L" denotes RoHS compliant package. 2. "LOT" denotes the lot number. 2. "COO" denotes country of origin. 3. "YYWW" is the last two digits of the year and week that the part was assembled. 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 14 REVISION E 11/20/15 9ZXL1550 DATASHEET Package Outline and Package Dimensions (NLG64 REVISION E 11/20/15 15 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 9ZXL1550 DATASHEET Package Outline and Package Dimensions (NLG64), cont. 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 16 REVISION E 11/20/15 9ZXL1550 DATASHEET Ordering Information Part / Order Number 9ZXL1550BKLF 9ZXL1550BKLFT Shipping Package Trays Tape and Reel Package Temperature 64-pin VFQFPN 0 to +70C 64-pin VFQFPN 0 to +70C "LF" suffix denotes Pb-Free configuration, RoHS compliant. "B" is the device revision designator (will not correlate with the datasheet revision). Revision History Rev. C D Issuer Issue Date Description 1. Cleaned up output pin names to be DIFxx instead of DIF_xx 2. Updated electrical tables with characterized data RDW 2/27/2015 3. Updated ordering info to B rev along with Rev ID. 4. Updated termination schemes for driving LVDS. 5. Minor cleanup and move to final 1. Updated Data sheet Title, General Description and Recommended Application text. RDW 3/6/2015 2. Corrected tSPO_PLL parameter in Skew and Differential Jitter Parameters table. RDW 3/16/2015 1.Changed max IDDVDDIOPD limit from 0.5mA to 1.5mA. RDW 6/16/2015 Added landing pattern from POD drawing. E RDW A B 11/20/2015 REVISION E 11/20/15 1. Updated QPI references to QPI/UPI 2. Updated DIF_IN table to match PCI SIG specification, no silicon change 17 Page # Various 1,8 7 16 1,5 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE Corporate Headquarters Sales Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. 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