TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization...32768 by 8 Bits
D
Single 5-V Power Supply
D
Pin Compatible With Existing 256K MOS
ROMs, PROMs, and EPROMs
D
All Inputs /Outputs Fully TTL Compatible
D
Max Access/Min Cycle Time
VCC ± 10%
’27C/PC256-10 100 ns
’27C/PC256-12 120 ns
’27C/PC256-15 150 ns
’27C/PC256-17 170 ns
’27C/PC256-20 200 ns
’27C/PC256-25 250 ns
D
Power Saving CMOS Technology
D
Very High-Speed SNAP! Pulse
Programming
D
3-State Output Buffers
D
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Lines
D
Low Power Dissipation (VCC = 5.5 V)
– Active...165 mW Worst Case
– Standby...1.4 mW Worst Case
(CMOS Input Levels)
D
Temperature Range Options
D
256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
description
The TMS27C256 series are 32768 by 8-bit
(262144-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
The TMS27PC256 series are 32768 by 8-bit
(262144-bit), one-time programmmable (OTP)
electrically programmable read-only memories
(PROMs).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3213231
14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
430
15 16 17 18 19 20
PIN NOMENCLATURE
A0–A14 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
EChip Enable/Powerdown
GOutput Enable
GND Ground
NC No Internal Connection
NU Make No External Connection
VCC 5-V Power Supply
VPP 13-V Power Supply†
J PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
DQ1
DQ2
NU
DQ3
DQ4
A7
A12
V
NU
V
A14
A13
FM PACKAGE
(TOP VIEW)
DQ5
CC
GND PP
†Only in program mode
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is supplied in a 32-lead
plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffixes) and – 40°C to 85°C (JE and FME suffixes). See Table 1.
All package styles conform to JEDEC standards.
Table 1. Temperature Range Suffixes
EPROM
AND SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE RANGES
OTP PROM 0°C TO 70°C–40°C TO 85°C
TMS27C512-xxx JL JE
TMS27PC512-xxx FML FME
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming . All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
Table 2. Operation Modes
MODE†
FUNCTION READ OUTPUT
DISABLE STANDBY PROGRAMMING VERIFY PROGRAM
INHIBIT SIGNATURE
MODE
E VIL VIL VIH VIL VIH VIH VIL
G VIL VIH X VIH VIL X VIL
VPP VCC VCC VCC VPP VPP VPP VCC
VCC VCC VCC VCC VCC VCC VCC VCC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X VIL VIH
CODE
DQ0–DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DEVICE
97 04
†X can be VIL or VIH.
‡VH = 12 V ±0.5 V.
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity × exposure time) is 15-W•s/cm2. A typical 12-mW/cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
initializing (TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when VPP = 13 V , VCC = 6.5 V , G = VIH, and E = VIL. More than one device
can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V.
program inhibit
Programming can be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL and E = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V . T wo identifier bytes are accessed by toggling A0. All other addresses must
be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 04, as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
PINS
IDENTIFIER†
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
MANUFACTURER CODE VIL 1001011197
DEVICE CODE VIH 0000010004
†E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, VPP = VCC, PGM = VIH or VIL.
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Start
Address = First Location
VCC = 6.5 V, VPP = 13 V
Last
Address?
Address = First Location
X = 0
VCC = VPP = 5 V ±10%
Compare
All Bytes
To Original
Data
Device Passed
Increment Address
Increment
Address Verify
One Byte
Program One Pulse = tw = 100 µs
X = 10?X = X + 1
Last
Address?
Device Failed
Pass
No
Yes Yes
No
Fail
Fail
Pass
No
Program
Mode
Interactive
Mode
Final
Verification
Yes
Program One Pulse = tw = 100 µs
Figure 1. SNAP! Pulse Programming Flowchart
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol†
14
[PWR DWN]
&EN
A
A
A
A
A
A
A
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
G
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
EPROM
32 768 × 8
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0
32 767
0
A0
32 767
A
A
A
A
A
A
A
A
14
[PWR DWN]
&EN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
G
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
OTP PROM
32 768 × 8
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
0
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC (see Note 1) : –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VPP : –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (see Note 1): All inputs except A9 : –0.6 V to VCC + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A9 : –0.6 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (see Note 1) : –0.6 V to VCC + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range (’27C256-_ _JL, ’27PC256-_ _FML) TA :0°C to 70°C. . . . . . . . . . . . . .
Operating free-air temperature range (’27C5256-_ _JE, ’27PC256-_ _FME) TA : –40°C to 85°C. . . . . . . . . . .
Storage temperature range, Tstg : –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to GND.
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
recommended operating conditions
MIN NOM MAX UNIT
VCC
Su
pp
ly voltage
Read mode (see Note 2) 4.5 5 5.5
V
V
CC
S
u
ppl
y v
oltage
SNAP! Pulse programming algorithm 6.25 6.5 6.75
V
VPP
Su
pp
ly voltage
Read mode VCC–0.6 VCC+0.6
V
V
PP
S
u
ppl
y v
oltage
SNAP! Pulse programming algorithm 12.75 13 13.25
V
VIH
High level dc in
p
ut voltage
TTL 2 VCC+1
V
V
IH
High
-
le
v
el
dc
inp
u
t
v
oltage
CMOS VCC – 0.2 VCC+1
V
VIL
Low level dc in
p
ut voltage
TTL – 0.5 0.8
V
V
IL
Lo
w-
le
v
el
dc
inp
u
t
v
oltage
CMOS – 0.5 0.2
V
TAOperating free-air temperature ’27C256-_ _JL
’27PC256-_ _FML 0 70 °C
TAOperating free-air temperature ’27C256-_ _JE
’27PC256-_ _FME –40 85 °C
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
electrical characteristics over recommended ranges of operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH
High level dc out
p
ut voltage
IOH = – 2.5 mA 3.5
V
V
OH
High
-
le
v
el
dc
o
u
tp
u
t
v
oltage
IOH = – 20 µA VCC – 0.1
V
VOL
Low level dc out
p
ut voltage
IOL = 2.1 mA 0.4
V
V
OL
Lo
w-
le
v
el
dc
o
u
tp
u
t
v
oltage
IOL = 20 µA0.1
V
IIInput current (leakage) VI = 0 V to 5.5 V ±1µA
IOOutput current (leakage) VO = 0 V to VCC ±1µA
IPP1 VPP supply current VPP = VCC = 5.5 V 1 10 µA
IPP2 VPP supply current (during program pulse) VPP = 13 V 35 50 mA
ICC1
V
supply current TTL-input level VCC = 5.5 V, E = VIH 250 500
µA
I
CC1
(standby) CMOS-input level VCC = 5.5 V, E = VCC 100 250 µ
A
ICC2 VCC supply current (active) VCC = 5.5 V, E = VIL,
tcycle = minimum cycle time,
outputs open 15 30 mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz†
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
CiInput capacitance VI = 0, f = 1 MHz 6 10 pF
CoOutput capacitance VO = 0, f = 1 MHz 10 14 pF
†Capacitance measurements are made on a sample basis only.
‡Typical values are at TA = 25°C and nominal voltages.
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
switching characteristics over recommended range of operating conditions
PARAMETER TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C256-10
’27PC256-10 ’27C256-12
’27PC256-12 ’27C256-15
’27PC256-15 UNIT
(SEE
NOTES
3
AND
4)
MIN MAX MIN MAX MIN MAX
ta(A) Access time from address 100 120 150 ns
ta(E) Access time from chip enable 100 120 150 ns
ten(G) Output enable time from G CL = 100 pF,
1 Series 74 TTL Load
55 55 75 ns
tdis Output disable time from G or E, whichever
occurs first†
1
Series
74
TTL
Load
,
Input tr ≤ 20 ns,
Input t
f
≤ 20 ns 045 0 45 0 60 ns
tv(A) Output data valid time after change of
address, E, or G, whichever occurs first†
f
0 0 0 ns
PARAMETER TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C256-17
’27PC256-17 ’27C256-20
’27PC256-20 ’27C256-25
’27PC256-25 UNIT
(SEE
NOTES
3
AND
4)
MIN MAX MIN MAX MIN MAX
ta(A) Access time from address 170 200 250 ns
ta(E) Access time from chip enable 170 200 250 ns
ten(G) Output enable time from G CL = 100 pF,
1 Series 74 TTL Load
75 75 100 ns
tdis Output disable time from G or E, whichever
occurs first†
1
Series
74
TTL
Load
,
Input tr ≤ 20 ns,
Input t
f
≤ 20 ns 060 0 60 0 60 ns
tv(A) Output data valid time after change of
address, E, or G, whichever occurs first†
f
0 0 0 ns
†Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. T iming measurements are made at 2 V for logic high and
0.8 V for logic low) (see Figure 2).
4. Common test conditions apply for the tdis except during programming.
switching characteristics for programming: VCC = 6.50 V and VPP = 13 V (SNAP! Pulse), T A = 25°C
(see Note 3)
PARAMETER MIN MAX UNIT
tdis(G) Output disable time from G 0 130 ns
ten(G) Output enable time from G 150 ns
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low).
timing requirements for programming
MIN NOM MAX UNIT
th(A) Hold time, address 0 µs
th(D) Hold time, data 2 µs
tw(IPGM) Pulse duration, initial program 95 100 105 µs
tsu(A) Setup time, address 2 µs
tsu(G) Setup time, G 2 µs
tsu(E) Setup time, E 2 µs
tsu(D) Setup time, data 2 µs
tsu(VPP) Setup time, VPP 2µs
tsu(VCC) Setup time, VCC 2µs
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
NOTE A: CL includes probe and fixture capacitance.
ac testing input/output wave forms
2.4 V
0.4 V 0.8 V 0.8 V
2 V 2 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. T iming measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
Figure 2. AC Testing Output Load Circuit
A0–A14
E
Addresses Valid
ta(E)
G
DQ0–DQ7 Hi-Z
ten(G) tv(A)
tdis
Output Valid
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Hi-Z
ta(A)
Figure 3. Read-Cycle Timing
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Program Verify
VIH
VIL
VIH /V
OH
VIL /V
OH
VPP‡
VCC
VCC‡
VCC
VIH
VIL
VIH
VIL
A0–A14
VPP
VCC
E
G
tsu(A)
tsu(D)
ten(G)†
tdis(G)†
Data-In Stable Data-Out Valid
tsu(VPP)
tsu(VCC) th(D)
tsu(E)
tw(IPGM) tsu(G)
Address Stable
Hi-Z
Address
N+1
DQ0–DQ7
th(A)
†tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer
‡13-V VPP and 6.5-V VCC for SNAP! Pulse programming
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER
4040201-4/B 03/95
0.020 (0,51)
0.015 (0,38)
Seating Plane
0.140 (3,56)
0.132 (3,35)
0.123 (3,12)
0.129 (3,28)
0.043 (1,09)
0.049 (1,24)
0.008 (0,20) NOM
0.595 (15,1 1)
0.553 (14,05)
0.585 (14,86)
TYP
0.030 (0,76)
0.547 (13,89)
301
0.495 (12,57)
0.453 (11,51)
0.485 (12,32)
0.447 (11,35)
5
4
20
13
14
29
21
0.050 (1,27)
0.004 (0,10)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
TMS27C256 32768 BY 8-BIT UV ERASABLE
TMS27PC256 32768 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS256H– SEPTEMBER 1984 – REVISED NOVEMBER 1997
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
4040084/B 04/95
B
C
0.018 (0,46) MIN
0.125 (3,18) MIN
0.022 (0,56) 0.012 (0,30)
0.014 (0,36) 0.008 (0,20)
Seating Plane
A
WIDE
24
A
PINS**
DIM
MAX
MIN
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
1.235(31,37) 1.235(31,37)
1.265(32,13) 1.265(32,13)
MIN
MAX
B
CMAX
MIN
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
0.541(13,74) 0.598(15,19)
1.668(42,37) 1.668(42,37)
1.632(41,45) 1.632(41,45)
0.590(14,99) 0.590(14,99)
0.624(15,85) 0.624(15,85)
NARR 32 WIDE
0.514(13,06) 0.571(14,50)
0.541(13,74) 0.598(15,19)
1.465(37,21) 1.465(37,21)
1.435(36,45) 1.435(36,45)
0.590(14,99) 0.590(14,99)
0.624(15,85) 0.624(15,85)
NARR 28 WIDE WIDE
40
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
2.032(51,61) 2.032(51,61)
2.068(52,53) 2.068(52,53)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
24 PIN SHOWN
112
24 13
0.045 (1,14)
0.065 (1,65)
0.090 (2,29)
0.060 (1,53)
Lens Protrusion
0.010 (0,25) MAX
0.175 (4,45)
0.140 (3,56)
0.100 (2,54)
0°–10°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
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