AT84AD001C Dual 8-bit 1 Gsps ADC Datasheet 1. Features * * * * * * * * * Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format (100) 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50 PECL/LVDS Compatible Clock Inputs Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output) LQFP144 or LQFP-ep 144L Green Packages Temperature Range: - 0C < Tamb < 70C (Commercial Grade) - -40C < Tamb < 85C (Industrial Grade) * 3-wire Serial Interface - 16-bit Data, 3-bit Address - 1:2 or 1:1 Output Demultiplexer Ratio Selection - Full or Partial Standby Mode - Analog Gain ( 1.5 dB) Digital Control - Input Clock Selection - Analog Input Switch Selection - Synchronous Data Ready Reset - Data Ready Delay Adjustable on Both Channels - Interleaving Functions: * Offset and Gain (Channel to Channel) Calibration * Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel - Internal Static or Dynamic Built-In Test (BIT) 2. Performance * * * * * Low Power Consumption: 0.75W Per Channel Power Consumption in Standby Mode: 120 mW 1.5 GHz Full Power Input Bandwidth (-3 dB) Flat ENOB (DC to 1 GHz) SNR = 45 dB Typ (7.2 bit ENOB), THD = -51 dBc, SFDR = -54 dBc at Fs = 1 Gsps Fin = 500 MHz * 2-tone IMD3: -54 dBc (499 MHz, 501 MHz) at 1 Gsps * DNL = 0.25 LSB, INL = 0.5 LSB * Low Bit Error Rate (10-13) at 1 Gsps Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2009 1006C-BDC-04/10 AT84AD001C 3. Application * * * * Digital Oscilloscopes Communication Receivers (I/Q) Direct RF Down Conversion High Speed Data Acquisition 4. Description The AT84AD001C is a monolithic dual 8-bit analog-to-digital converter, offering low 1.56W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 1 Gsps and an input frequency bandwidth of over 1.5 GHz. The dual concept, the integrated demultiplexer and the easy interleaving mode make this device user-friendly for all dual channel applications, such as direct RF conversion or data acquisition. The smart function of the 3-wire serial interface eliminates the need for external components, which are usually necessary for gain and offset tuning and setting of other parameters, leading to space and power reduction as well as system flexibility. 5. Functional Description The AT84AD001C is a dual 8-bit 1 Gsps ADC based on advanced high-speed BiCMOS technology. Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100). Two over-range bits are provided for adjustment of the external gain control on each channel. A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments: * Analog input range adjustment (1.5 dB) with 8-bit data control using a 3-wire bus interface (steps of 0.011 dB) * Analog input switch: both ADCs can convert the same analog input signal I or Q * Output format: DMUX 1:1 or 1:2 with control of the output frequency on the data ready output signal * Partial or full standby on channel I or channel Q * Clock selection: - Two independent clocks: CLKI and CLKQ - One master clock (CLKI) with the same phase for channel I and channel Q - One master clock but with two phases (CLKI for channel I and CLKIB for channel Q) * ISA: Internal Settling Adjustment on channel I and channel Q * FiSDA: Fine Sampling Delay Adjustment on channel Q (in interleaving mode) * Adjustable Data Ready Output Delay on both channels * Test mode: decimation mode (by 16), Built-In Test A calibration phase is provided to set the two DC offsets of channel I and channel Q close to code 127.5 and calibrate the two gains. This calibration might be launched several times before the optimum is reached. The offset and gain error can also be set externally via the 3-wire serial interface. The AT84AD001C operates in fully differential mode from the analog inputs up to the digital outputs. The AT84AD001C features a full-power input bandwidth of 1.5 GHz. 2 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 5-1. Simplified Block Diagram CLKI Divider 2 to16 Clock Buffer DDRB DoirI + Vini S/H Vinib - 8bit ADC I DRDA I DMUX 1:2 or 1:1 I 8 Gain control I Calibration Gain/offset ISA I LVDS Clock Buffer LVDS Buffer I 2 16 DOAI DOAIN 16 DOBI DOBIN 2 Data BIT 3-wire Serial Interface 3WSI Gain control Q Calibration Gain/offset ISA Q & FiSDA + S/H Vinqb - Clock Ldn DMUX control Mode 2 DoirQ Vinq DOIRI DOIRIN DMUX control Input switch INPUT MUX CLKIO 8bit ADC Q 8 DMUX 1: 2 or 1: 1 Q LVDS buffe r Q DOIRQ DOIRQN 16 DOAQ DOAQN 16 DOBQ DOBQN CLKQ Clock Buffer DDRB Divider 2 to 16 DRDA Q LVDS Clock Buffer 2 CLKQO 3 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 6. Typical Applications Figure 6-1. Satellite Receiver Application Satellite Low Noise Converter (Connected to the Dish) Bandpass Amplifier Dish Satellite Tuner Low Pass Filter Bandpass Amplifier 11..12 GHz Tunable Band Filter IF Band Filter AGC 1..2 GHz Synthesizer 1.5 ... 2.5 GHz Local oscillator I I I Local Oscillator Control Functions: AT84AD001C Clock and Carrier 90 Q Recovery... Q 0 Q Clock Q Quadrature Demodulation 4 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 6-2. Dual Channel Digital Oscilloscope Application DAC Gain Channel B ADC B Analog switch A Channel A DAC Offset FISO RAM DAC Offset A Display P ADC A DAC Gain Channel Mode Selection Clock selection Timing circuit DACs Smart dual ADC DACs 5 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 6-1. Absolute Maximum Ratings Parameter Symbol Value Unit Analog positive supply voltage VCCA 3.6 V Digital positive supply voltage VCCD 3.6 V Output supply voltage VCCO 3.6 V VCCA to VCCD 0.8 V VCCO 1.6 V Analog input voltage VINI or VINIB VINQ or VINQB 1/-1 V Digital input voltage VD -0.4 to VCCD + 0.4 V Clock input voltage VCLK or VCLKB -0.4 to VCCD + 0.4 V Maximum difference between VCLK and VCLKB VCLK - VCLKB -2 to 2 V Maximum junction temperature TJ 125 C Storage temperature Tstg -55 to 150 C Tleads 300 C Maximum difference between VCCA and VCCD Minimum VCCO Lead temperature (soldering 10s) Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. Table 6-2. Recommended Conditions of Use Parameter Symbol Comments Recommended Value Unit Analog supply voltage VCCA 3.3 V Digital supply voltage VCCD 3.3 V Output supply voltage VCCO 2.25 V VINi - VIniB or VINQ - VINQB 500 mVpp Vinclk 600 mVpp 1:1 DMUX 0 ps 1:2 DMUX -100 ps Commercial grade Industrial grade 0 < Tamb < 70 -40 < Tamb < 85 C Differential analog input voltage (full-scale) Differential clock input level Internal Settling Adjustment (ISA) with a 3-wire serial interface for channel I and channel Q Operating temperature range ISA TAmbient 6 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 7. Electrical Operating Characteristics Unless otherwise specified: * VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V * VINI - VINB or VINQ - VINQB = 500 mVpp full-scale differential input * LVDS digital outputs (100) * Tamb (typical) = 25C * Full temperature range: 0C < Tamb < 70C (commercial grade) Table 7-1. Electrical Operating Characteristics in Nominal Conditions Parameter Symbol Min Resolution Typ Max 8 Coding Unit Bits Binary Power Requirements Positive supply voltage - Analog - Digital -Output digital (LVDS) and serial interface VCCA VCCD 3.15 3.3 3.45 3.15 3.3 3.45 VCCO 2.0 2.25 2.5 V V V Supply current (1:1 DMUX mode, 1 clock) - Analog - Digital - Output Supply current (1:2 DMUX mode, 2 clocks) - Analog - Digital - Output Supply current (1:2 DMUX mode, 1 clock) - Analog - Digital - Output Supply current (1:1 DMUX mode, partial standby) - Analog - Digital - Output Supply current (1:2 DMUX mode, partial standby) - Analog - Digital - Output Supply current (Full Standby) - Analog - Digital - Output ICCA 145 179 mA ICCD 248 274 mA ICCO 88 119 mA ICCA 145 179 mA ICCD 296 349 mA ICCO 158 214 mA ICCA 145 179 mA ICCD 272 309 mA ICCO 154 209 mA ICCA 79 94 mA ICCD 170 189 mA ICCO 48 64 mA ICCA 79 94 mA ICCD 157 204 mA ICCO 81 109 mA ICCA 14 19 mA ICCD 20 38 mA ICCO 4.3 6.5 mA Nominal dissipation (1 clock, 1:1 DMUX mode, 2 channels) PD 1.5 W Nominal dissipation (full standby mode) stbpd 120 mW PD 1.7 W Nominal Power dissipation (1 clock, 1:2 DMUX) 7 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 7-1. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Symbol Min Typ Max Unit VDp-p 450 500 550 mV Analog Inputs Full-scale differential analog input voltage to obtain full scale with no gain adjust (mode 0)(1) Analog input common mode Analog input capacitance I and Q Full power input bandwidth (-3 dB) 0 V 2 CIN FPBW Gain flatness (-0.5 dB) pF 1.5 GHz 500 MHz Clock Input Logic compatibility for clock inputs and DDRB reset (pins 124,125,126,127,128,129) in AC coupling mode PECL/LVDS clock inputs and DDRB input voltages (VCLKI/IN or VCLKQ/QN) PECL/ECL/LVDS VIL - VIH 600 mV Differential logical level Clock input and DDRB input power level -9 0 Clock input capacitance 6 2 dBm pF Digital Outputs (including DOIRI, DOIRIN, DOIRQ and DOIRQN signals) Logic driving compatibility for digital outputs (depending on the value of VCCO) Differential output voltage swings (assuming VCCO = 2.25V) LVDS VOD 220 270 350 mV Output levels (assuming VCCO = 2.25V) 100 differentially terminated Logic 0 voltage Logic 1 voltage VOL VOH 1.0 1.25 1.1 1.35 1.2 1.48 V V Output offset voltage (assuming VCCO = 2.25V) 100 differentially terminated VOS 1125 1250 1340 mV Output impedance RO 50 Output current (shorted output) 12 mA Output current (grounded output) 30 mA Output level drift with temperature 1.3 mV/C Digital Input (Serial Interface) Maximum clock frequency (input clk) Fclk 50 MHz Input logical level 0 (clk, mode, data, ldn) -0.4 0 0.4 V Input logical level 1 (clk, mode, data, ldn) VCCO - 0.4 VCCO VCCO + 0.4 V Output logical level 0 (cal) -0.4 0 0.4 V Output logical level 1 (cal) VCCO - 0.4 VCCO VCCO + 0.4 V 15 pF Maximum output load (cal) Notes: 1. See Figure 7-1 on page 13 for more information. 2. The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off. 8 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 7-2. Electrical Operating Characteristics Parameter Symbol Min Typ Max Unit DC Accuracy No missing code Guaranteed over specified temperature range Differential non-linearity (peak +/-) DNL 0.25 0.78 LSB Integral non-linearity (peak +/-) INL 0.5 1 LSB Gain error (single channel I or Q) with calibration -2 0 2 % Input offset matching (single channel I or Q) with calibration -2 0 2 LSB Gain error drift against temperature Gain error drift against VCCA 0.062 0.064 Mean output offset code with calibration 126 127.5 LSB/C LSB/mV 129 LSB Transient Performance Bit Error Rate Fs = 1 GHz Fin = 250 MHz ADC settling time channel I or Q (between 10% - 90% of output response) VIni - ViniB = 500 mVpp Notes: BER(1) 10-13 Error/ sample TS 170 ps 1. BER with sinewave at -1 dBFS at Fin = 250 MHz. 2. Gain setting is 0 dB, two clock inputs, no standby mode [full power mode], 1:2 DMUX, calibration on. 9 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 7-3. AC Performances Parameter Symbol Min Typ Max Unit 42 45 dBc 40 45 dBc 43 dBc 7 7.3 Bits 6.5 7.2 Bits 7 Bits 48 55 dBc 45 51 dBc 45 dBc 50 56 dBc 48 54 dBc 50 dBc -54 dBc 0.5 dB AC Performance Signal-to-noise Ratio Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1 GHz SNR Effective Number of Bits Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1 GHz ENOB Total Harmonic Distortion (First 9 Harmonics) Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1 GHz |THD| Spurious Free Dynamic Range Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1 GHz |SFDR| Two-tone Inter-modulation Distortion (Single Channel) FIN1 = 499 MHz, FIN2 = 501 MHz at Fs = 1 Gsps IMD Band flatness from DC up to 600 MHz Phase matching using auto-calibration and FiSDA in interleaved mode (channel I and Q) Fin = 250 MHz Fs = 1 Gsps d Crosstalk channel I versus channel Q Fin = 250 MHz, Fs = 1 Gsps(2) Cr Notes: -0.7 0 -65 0.7 dB 1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode, 1:1 DMUX, ISA = 0 ps. 2. Measured on the AT84AD001TD-EB Evaluation Board. 10 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 7-4. AC Performances over Full Industrial Temperature Range (-40C < Tamb < 85C) Parameter Symbol Min Typ Max Unit 39 45 dBc 6.0 7.2 Bits 39 51 dBc 42 54 dBc AC Performance Signal-to-noise Ratio Fs = 1 Gsps Fin = 500 MHz Effective Number of Bits Fs = 1 Gsps Fin = 500 MHz Total Harmonic Distortion (First 9 Harmonics) Fs = 1 Gsps Fin = 500 MHz Spurious Free Dynamic Range Fs = 1 Gsps Table 7-5. Fin = 500 MHz AC Performances in Interleaved Mode Parameter Symbol Min Typ Max Unit Maximum equivalent clock frequency Fint = 2 x Fs Where Fs = external clock frequency Fint 2 Minimum clock frequency Fint 20 Msps Differential non-linearity in Interleaved mode intDNL 0.25 LSB Integral non-linearity in Interleaved mode intINL 0.5 LSB 42 dBc 40 dBc 7.1 Bits 6.8 Bits 52 dBc 49 dBc 54 dBc 52 dBc -54 dBc Interleaved Mode Gsps Signal-to-noise Ratio in Interleaved Mode Fint = 2 Gsps Fin= 20 MHz iSNR Fint = 2 Gsps Fin = 250 MHz Effective Number of Bits in Interleaved Mode Fint = 2 Gsps Fin = 20 MHz iENOB Fint = 2 Gsps Fin = 250 MHz Total Harmonic Distortion in Interleaved Mode Fint = 2 Gsps Fin = 20 MHz |iTHD| Fint = 2 Gsps Fin = 250 MHz Spurious Free Dynamic Range in Interleaved Mode Fint = 2 Gsps Fin = 20 MHz |iSFDR| Fint = 2 Gsps Fin = 250 MHz Two-tone Inter-modulation Distortion (Single Channel) in Interleaved Mode FIN1 = 249 MHz , FIN2 = 251 MHz at Fint = 2 Gsps Note: iIMD One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration phase is necessary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment. 11 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 7-6. Switching Performances Parameter Symbol Min Typ Max Unit Switching Performance and Characteristics - See "Timing Diagrams" on page 13. Maximum operating clock frequency Maximum operating clock frequency in BIT and decimation modes FS 1 FS (BIT, DEC) 1 Minimum clock frequency (no transparent mode) Minimum clock frequency (with transparent mode) Gsps FS Gsps 10 Msps 1 Ksps Minimum clock pulse width [high] (No transparent mode) TC1 0.4 0.5 50 ns Minimum clock pulse width [low] (No transparent mode) TC2 0.4 0.5 50 ns Aperture delay: nominal mode with ISA & FiSDA TA 0.8 ns Aperture uncertainty Jitter 0.4 ps (rms) Data output delay between input clock and data TDO 2.8 ns Data Ready Output Delay TDR 3 ns Data Ready Reset to Data Ready Data Ready (CLKO) Delay Adjust (85 ps steps) 2 clock cycles TRDR Tdrda range Output skew -340 to 255 50 ps 100 ps Output rise/fall time for DATA (20% - 80%) TR/TF 300 350 500 ps Output rise/fall time for DATA READY (20% - 80%) TR/TF 300 350 500 ps Data pipeline delay (nominal mode) DMUX 1:1 Port A: 5 Data pipeline delay (nominal mode) DMUX 1:2 Port A: 5.5 Port B: 4.5 Clock cycles TPD Data pipeline delay in S/H transparent mode DMUX 1:1 Port A: 4.5 Data pipeline delay in S/H transparent mode DMUX 1:2 Port A: 5.0 Port B: 4.0 DDRB recommended pulse width Notes: 2 clock cycles 1. All timing characteristics are specified at ambient temperature but also apply to the specified temperature range (the variation over the specified temperature range is negligible). 2. Data Ready signal is centered on Data by TOD-TDR ns. 12 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-1. Differential Inputs Voltage Span (Full-scale) VIN mV VINB 500 mV Full-scale Analog Input -250 mV +250 mV +125 0V -125 t The analog input full-scale range is 0.5V peak-to-peak (Vpp), or -2 dBm into the 50 (100 differential) termination resistor. In differential mode input configuration, this means 0.25V on each input, or 125 mV around common mode voltage. 7.1 Timing Diagrams Figure 7-2. 1:1 DMUX Mode, Clock I ADC I, Clock Q ADC Q TA VIN N N+3 N+2 N+1 CLKI or CLKQ 5 clock cycles (TPD) + TOD DOIA[0:7] or DOQA[0:7] N-4 N-3 N-2 N-1 N N+1 N+2 N+3 Programmable delay (DRDA) CLKOI OR CLKOQ Notes: 1. VIN = VINI or VINQ depending on setting of bits D4 and D5 of 3WSI control register at address 000 2. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 3. DOIB[0:7] and DOQB[0:7] are high impedance. 4. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 1 X X 0 1 0 0 13 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-3. 1:1 DMUX Mode, Clock I ADC Q ADC I, Clock I ADC Q, analog I ADC I, Analog Q TA VINI N N+1 N+2 N+3 M+2 M+3 TA VINQ M M+1 CLKI 5 clock cycles (TPD) + TOD N-4 DOIA[0:7] N-3 N-2 N-1 N N+1 N+2 N+3 M-1 M M+1 M+2 M+3 5 clock cycles (TPD) + TOD DOQA[0:7] M-4 M-3 M-2 Programmable delay (DRDA) CLKOI Notes: 1. CLKOQ is high impedance. 2. DOIB[0:7] and DOQB[0:7] are high impedance. 3. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 4. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 1 0 1 0 0 5. In the case of the following settings: - Analog I ADC I, analog I ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 0 0 1 0 0 Then, DOQA[0:7] will output the same data as DOIA[0:7], ie data N, N+1, N+2... synchronously. - Analog Q ADC I, analog Q ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 0 X 0 1 0 0 Then, DOQA[0:7] will output the same data as DOIA[0:7], ie data M, M+1, M+2... synchronously. 14 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-4. 1:1 DMUX Mode, Clock I ADC Q TA VINI ADC I, Clock IN ADC Q, Analog I ADC I, Analog Q N+1 N TA VIN Q M+1 M CLKI CLKIN 5 clock cycles (TPD) + TOD N-2 DOQA[0:7] N-1 N N+1 N+2 M-2 M-1 M M+1 5.5 clock cycles (TPD) + TOD DOIA[0:7] M-3 Programmable delay (DRDA) CLKOI Notes: 1. CLKOQ is high impedance. 2. DOIB[0:7] and DOQB[0:7] are high impedance. 3. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 4. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 1 0 1 0 0 15 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-5. 1:1 DMUX Mode, Clock I TA VINx N ADC I, Clock IN ADC Q N+2 N+1 N+3 CLKI CLKIN 5.5 clock cycles (TPD) + TOD N-5 DOQA[0:7] N-3 N -1 N+1 N+3 N-2 N N+2 N+4 5 clock cycles (TPD) + TOD DOIA[0:7] N-4 Programmable delay (DRDA) CLKOI Notes: 1. CLKOQ is high impedance. 2. DOIB[0:7] and DOQB[0:7] are high impedance. 3. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 4. VINx = VINI or VINQ with the following 3WSI settings: - VINx = VINI, then, Analog I ADC I, analog I ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 0 0 1 0 0 - VINx = VINQ, then, Analog Q ADC I, analog Q ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 0 X 0 1 0 0 16 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-6. 1:2 DMUX Mode, Clock I ADC I, Clock Q ADC Q TA VIN N+2 N+1 N N+3 CLKI or CLKQ 5.5 clock cycles (TPD) + TOD DOIA[0:7] or DOQA[0:7] N-4 N-2 N N+2 N+1 N+3 4.5 clock cycles (TPD) + TOD DOIB[0:7] or DOQB[0:7] N-3 N-1 Programmable delay (DRDA) CLKOI OR CLKOQ (= CLKI/2) Programmable delay (DRDA) CLKOI OR CLKOQ (= CLKI/4) Notes: 1. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to Section 10. "Test and Control Features" on page 32. 2. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 1 X X 1 1 0 0 17 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-7. 1:2 DMUX Mode, Clock I ADC 1, Clock I ADC Q TA VINI N+1 N N+2 N+3 M+2 M+3 TA VINQ M+1 M CLKI 5.5 clock cycles (TPD) + TOD DOIA[0:7] N-4 N-2 N N+2 N-1 N+1 N+3 M-2 M M+2 M+1 M+3 4.5 clock cycles (TPD) + TOD DOIB[0:7] N-3 5.5 clock cycles (TPD) + TOD DOQA[0:7] M-4 4.5 clock cycles (TPD) + TOD DOQB[0:7] M-3 M-1 Programmable delay (DRDA) CLKOI (= CLKI/2) Programmable delay (DRDA) CLKOI (= CLKI/4) Notes: 1. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 2. CLKOQ is high impedance. 3. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 1 1 1 0 0 18 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 4. In the case of the following settings: - Analog I ADC I, analog I ADC Q, 3WSI setting at address `000' is: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 0 0 1 0 0 Then, DOQx[0:7] will output the same data as DOIx[0:7], with x = A or B - Analog Q ADC I, analog Q ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 0 X 0 1 0 0 Then, DOQx[0:7] will output the same data as DOIx[0:7], with x = A or B 19 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-8. 1:2 DMUX Mode, Clock I ADC Q ADC I, Clock IN ADC Q, Analog I ADC I, Analog Q TA VINI N+1 N TA VINQ M+1 M CLKI CLKIN 5.5 clock cycles (TPD) + TOD DOIA[0:7] N-4 N N+2 N-1 N+1 N+3 M-2 M M+2 M-1 M+1 M+3 N-2 4.5 clock cycles (TPD) + TOD DOIB[0:7] N-3 6 clock cycles (TPD) + TOD M-4 DOQA[0:7] 5 clock cycles (TPD) + TOD M-3 DOQB[0:7] Programmable delay (DRDA) CLKOI (= CLKI/2) Programmable delay (DRDA) CLKOI (= CLKI/4) Notes: 1. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 2. CLKOQ is high impedance. 3. 3WSI Setting at address `000': D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 1 1 1 0 0 20 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-9. 1:2 DMUX Mode, Clock I N ADC Q N+2 TA VIN x ADC I, Clock IN N+1 N+3 CLKI CLKIN 5.5 clock cycles (TPD) + TOD DOIA[0:7] N-7 N-3 N+1 N+5 N-1 N+3 N+7 N-4 N N+4 N-2 N+2 N+6 4.5 clock cycles (TPD) + TOD DOIB[0:7] N-5 6 clock cycles (TPD) + TOD N-8 DOQA[0:7] 5 clock cycles (TPD) + TOD N-6 DOQB[0:7] Programmable delay (DRDA) CLKOI (= CLKI/2) Programmable delay (DRDA) CLKOI (= CLKI/4) Notes: 1. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G datasheet. 2. CLKOQ is high impedance. 3. VINx = VINI or VINQ with the following 3WSI settings: - VINx = VINI, then, Analog I ADC I, analog I ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 1 0 0 1 0 0 - VINx = VINQ, then, Analog Q ADC I, analog Q ADC Q, 3WSI setting at address `000' is D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 1 0 0 X 0 1 0 0 21 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor) Address: D7 D6 D5 D4 D3 D2 D1 D0 1 0 X X 0 X 0 0 N - 16 VIN N + 16 N N + 32 16 clock cycles CLKI DOIA[0:7] N - 16 N N + 16 N + 32 N + 48 DOQA[0:7] N - 16 N N + 16 N + 32 N + 48 CLKOI DOIB[0:7] and DOQB[0:7] are high impedance CLKOQ is high impedance Notes: 1. The maximum clock input frequency in decimation mode is 750 Msps. 2. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16. Figure 7-11. Data Ready Reset 500 ps CLKI or CLKQ 500 ps 1 ns min DDRB FORBIDDEN FORBIDDEN ALLOWED ALLOWED 22 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-12. Data Ready Reset 1:1 DMUX Mode TA N VIN N+1 Clock in Reset CLKI or CLKQ Pipeline Delay + TDO DOIA[0:7] or DOQA[0:7] N TDR CLKOI or CLKOQ TDR TRDR = 2 clock cycles DDRB 2 clock cycles Notes: 1. The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes the output clock return to normal mode (after TDR). 2. DDRB reset is needed whenever the following functions are changed: DMUX mode, FS/2 - FS/4 function, clock frequency. BIT function (Test mode) in DMUX 1:2. 23 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-13. Data Ready Reset 1:2 DMUX Mode TA N VIN N+1 Clock in Reset CLKI or CLKQ Pipeline Delay + TDO DOIA[0:7] or DOQA[0:7] N DOIB[0:7] or DOQB[0:7] N+1 TDR TDR CLKOI or CLKOQ (= CLKI/2) TDR + 2 cycles CLKOI or CLKOQ (= CLKI/4) TDR + 2 cycles TRDR = 2 clock cycles DDRB 2 clock cycles Notes: 1. In 1:2 DMUX, Fs/2 mode: The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset occurs when it is low, it goes high only when its half cycle is complete; if the reset occurs when it is high, it remains high) and then only, remains in reset state (frozen to a high level in 1:2 DMUX Fs/2 mode). The next rising edge of the input clock after reset makes the output clock return to normal mode (after TDR). 2. In 1:2 DMUX, Fs/4 mode: The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then only, remains in reset state (frozen to a low level in 1:2 DMUX Fs/4 mode). The next rising edge of the input clock after reset makes the output clock return to normal mode (after TDR). If you don't respect the RESET forbidden zone, The output Data and Data Ready have an uncertainty.If you interleave several ADC, you are not sure that all ADC outputs are synchronized. 24 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 7-14. Data Ready Reset with bad Timings TA N VIN N+ 1 Clock created RESET? CLKI or CLKQ DO IA[0:7] or DOQA[0:7] N CLKOI or CLKOQ 2 ns DDRB 1 ns min Clock restart? CLKI or CLKQ Pipeline delay + TDO DOIA[0:7] or DOQA[0:7] N TDR CLKOI or CLKOQ TDR TRDR = 2 clock cycles DDRB 2 clock cycles Note: You don't know exactly the clock in RESET edge and the clock in RESTART edge. For the clock CLKOI and CLKOQ, you are not sure that this two output clocks start at the same time. Maybe CLKOI starts with the first clock in edge and CLKOQ starts with the second clock in edge. The CLKOI and CLKOQ are in opposite phase (in same condition before the reset). 25 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 7.2 Functions Description Table 7-7. Description of Functions Name Function VCCA Positive analog power supply VCCD Positive digital power supply VCCO Positive output power supply GNDA Analog ground GNDD Digital ground GNDO Output ground VINI, VINIB Differential analog inputs I VINQ, VINQB Differential analog inputs Q VCCA = 3.3V VCCD = 3.3V VCCO = 2.25V VINI 32 D0AI0 D0AI0N D0BI0 D0BI0N DOAI7 DOAI7N DOBI7 DOBI7N 32 D0AQ0 D0AQ0 DOAQ7 DOAQ7 VINIB VINQ DOQBQ7 DOBQ0 DOBQ0N DOQBQ7N VINQB CLKOI, CLKOIN, CLKOQ, CLKOQN Differential output data ready I and Q CLKI, CLKIN, CLKQ, CLKQN Differential clock inputs I and Q DDRB, DDRBN Synchronous data ready reset I and Q Mode Bit selection for 3-wire bus or nominal setting Clk Input clock for 3-wire bus interface Data Input data for 3-wire bus Ldn Beginning and end of register line for 3-wire bus interface <D0AI0:DOAI7> <D0AI0N:DOAI7N> <D0BI0:DOBI7> <D0BI0N:DOBI7N> Differential output data port channel I 4 DOIRI, DOIRIN DOIRQ, DOIRQN CLKQ 4 CLOCKOI, CLOCKOIB CLOCKOQ, CLOCKOQB CLKQB 2 VtestI VtestQ CLKIB Vdiode GNDA GNDD GNDO mode DOIRI, DOIRIN DOIRQ, DOIRQN clk data ldn Differential output IN range data I and Q Test voltage output for ADC Q VtestQ <D0AQ0:DOAQ7> <D0AQ0N:DOAQ7N> <D0BQ0:DOBQ7> <D0BQ0N:DOBQ7N> 7.3 AT84AD001C CLKI (to be left open) VtestI Test voltage output for ADC I (to be left open) Cal Output bit status internal calibration or Test Chip version indicator Vdiode Test diode voltage for TJ measurement Differential output data port channel Q Digital Output Coding (Nominal Settings) Table 7-8. Digital Output Coding (Nominal Setting, MSB = bit 7 and LSB = bit 0) Differential Analog Input Voltage Level Digital Output I or Q (Binary Coding) Out-of-range Bit > 250 mV > Positive full-scale + 1/2 LSB 11111111 1 250 mV 248 mV Positive full-scale + 1/2 LSB Positive full-scale - 1/2 LSB 11111111 11111110 0 0 1 mV -1 mV Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB 10000000 01111111 0 0 -248 mV -250 mV Negative full-scale + 1/2 LSB Negative full-scale - 1/2 LSB 00000001 00000000 0 0 < -250 mV < Negative full-scale - 1/2 LSB 00000000 1 26 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 8. Pin Description Table 8-1. AT84AD001C Pin Description Symbol Pin number Function GNDA, GNDD, GNDO 10, 12, 22, 24, 36, 38, 40, 42, 44, 46, 51, 54, 59, 61, 63, 65, 67, 69, 85, 87, 97, 99, 109, 111, 130, 142, 144 Ground pins. To be connected to external ground plane VCCA 41, 43, 45, 60, 62, 64 Analog positive supply: 3.3V typical VCCD 9, 21, 37, 39, 66, 68, 88, 100, 112, 123, 141 3.3V digital supply VCCO 11, 23, 86, 98, 110, 143 2.25V output and 3-wire serial interface supply VINI 57, 58 In-phase (+) analog input signal of the sample & hold differential preamplifier channel I VINIB 55, 56 Inverted phase (-) of analog input signal (VINI) VINQ 47, 48 In-phase (+) analog input signal of the sample & hold differential preamplifier channel Q VINQB 49, 50 Inverted phase (-) of analog input signal (VINQ) CLKI 124 In-phase (+) clock input signal CLKIN 125 Inverted phase (-) clock input signal (CLKI) CLKQ 129 In-phase (+) clock input signal CLKQN 128 Inverted phase (-) clock input signal (CLKQ) DDRB 126 Synchronous data ready reset I and Q DDRBN 127 Inverted phase (-) of input signal (DDRB) DOAI0, DOAI1, DOAI2, DOAI3, DOAI4, DOAI5, DOAI6, DOAI7 117, 113, 105, 101, 93, 89, 81, 77 In-phase (+) digital outputs first phase demultiplexer (channel I) DOAI0 is the LSB. D0AI7 is the MSB DOAI0N, DOAI1N, DOAI2N, DOAI3N, DOAI4N, DOAI5N, DOAI6N, DOAI7N, 118, 114, 106, 102, 94, 90, 82, 78 Inverted phase (-) digital outputs first phase demultiplexer (channel I) DOAI0N is the LSB. D0AI7N is the MSB DOBI0, DOBI1, DOBI2, DOBI3, DOBI4, DOBI5, DOBI6, DOBI7 119, 115, 107, 103, 95, 91, 83, 79 In-phase (+) digital outputs second phase demultiplexer (channel I) DOBI0 is the LSB. D0BI7 is the MSB DOBI0N, DOBI1N, DOBI2N, DOBI3N, DOBI4N, DOBI5N, DOBI6N, DOBI7N 120, 116, 108, 104, 96, 92, 84, 80 Inverted phase (-) digital outputs second phase demultiplexer (channel I) DOBI0N is the LSB. D0BI7N is the MSB DOAQ0, DOAQ1, DOAQ2, DOAQ3, DOAQ4, DOAQ5, DOAQ6, DOAQ7 136, 140, 4, 8, 16, 20, 28, 32 In-phase (+) digital outputs first phase demultiplexer (channel Q) DOAI0 is the LSB. D0AQ7 is the MSB DOAQ0N, DOAQ1N, DOAQ2N, DOAQ3N, DOAQ4N, DOAQ5N, DOAQ6N, DOAQ7N 135, 139, 3, 7, 15, 19, 27, 31 Inverted phase (-) digital outputs first phase demultiplexer (channel Q) DOAI0N is the LSB. D0AQ7N is the MSB DOBQ0, DOBQ1, DOBQ2, DOBQ3, DOBQ4, DOBQ5, DOBQ6, DOBQ7 134, 138, 2, 6, 14, 18, 26, 30 In-phase (+) digital outputs second phase demultiplexer (channel Q) DOBQ0 is the LSB. D0BQ7 is the MSB DOBQ0N, DOBQ1N, DOBQ2N, DOBQ3N, DOBQ4N, DOBQ5N, DOBQ6N, DOBQ7N 133, 137, 1 ,5, 13, 17, 25, 29 Inverted phase (-) digital outputs second phase demultiplexer (channel Q) DOBQ0N is the LSB. D0BQ7N is the MSB 27 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 8-1. AT84AD001C Pin Description (Continued) Symbol Pin number Function DOIRI 75 In-phase (+) out-of-range bit input (I phase) combined demultiplexer out-of-range is high on the leading edge of code 0 and code 256 DOIRIN 76 Inverted phase of output signal DOIRI DOIRQ 34 In-phase (+) out-of-range bit input (Q phase) combined demultiplexer out-of-range is high on the leading edge of code 0 and code 256 DOIRQN 33 Inverted phase of output signal DOIRQ MODE 74 Bit selection for 3-wire bus interface or nominal setting CLK 73 Input clock for 3-wire bus interface DATA 72 Input data for 3-wire bus LND 71 Beginning and end of register line for 3- wire bus interface CLKOI 121 Output clock in-phase (+) channel I CLKOIN 122 Inverted phase (-) output clock channel I CLKOQ 132 Output clock in-phase (+) channel Q, 1/2 input clock frequency CLKOQN 131 Inverted phase (-) output clock channel Q VtestQ, VtestI 52, 53 Pins for internal test (to be left open) Cal 70 Calibration output bit status or Test Chip version indicator Vdiode 35 Positive node of diode used for die junction temperature measurements 28 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 8-1. AT84AD001C Pinout (Top View) LQFP 144 20 by 20 by 1.4 mm Dual 8-bit 29 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 9. Typical Characterization Results Nominal conditions (unless otherwise specified): * VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V * VINI - VINB or VINQ to VINQB = 500 mVpp full-scale differential input * LVDS digital outputs (100) * TA (typical) = 25C * Full temperature range: 0C < TA < 70C (commercial grade) or -40C < TA < 85C (industrial grade) 9.1 Typical Full Power Input Bandwidth * Fs = 500 Msps * Pclock = 0 dBm * Pin = -1 dBFS * Gain flatness (0.5 dB) from DC to > 500 MHz * Full power input bandwidth at -3 dB > 1.5 GHz Figure 9-1. Full Power Input Bandwidth 0 -1 -2 -3 dB Bandwidth -3 dBFS -4 -5 -6 -7 -8 -9 -10 -11 100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 Fin (MHz) 30 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 9.2 Typical DC, INL and DNL Patterns 1:2 DMUX mode, Fs/4 DR type Figure 9-2. Typical INL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input) 0,6 0,4 INL (Lsb) 0,2 0 -0,2 -0,4 -0,6 1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256 Codes Figure 9-3. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input) 0,3 0,2 DNL (Lsb) 0,1 0 -0,1 -0,2 -0,3 1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256 Codes 31 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 10. Test and Control Features 10.1 3-wire Serial Interface Control Setting Table 10-1. 3-wire Serial Interface Control Settings Mode Characteristics Mode = 1 (2.25V) 3-wire serial bus interface activated Mode = 0 (0V) 3-wire serial bus interface deactivated Nominal setting: Dual channel I and Q activated One clock I 0 dB gain DMUX mode 1:1 DRDA I & Q = 0 ps ISA I & Q = 0 ps FiSDA Q = 0 ps Cal = 0 Decimation test mode OFF Calibration setting OFF Data Ready = Fs/4 Note: In the AT84AD001C, the default setting is Fs/4 mode for DMUX 1:2 mode (it was Fs/2 in previous versions of the device AT84AD001Bxxx series). 32 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 10.1.1 3-wire Serial Interface and Data Description The 3-wire bus is activated with the control bit mode set to 1. The length of the word is 19 bits: 16 for the data and 3 for the address. The maximum clock frequency is 50 MHz. Table 10-2. 3-wire Serial Interface Address Setting Description Address Setting 000 Standby Chip version indicator 1:1 or 1:2 DMUX mode Analog input MUX Clock selection Auto-calibration Decimation test mode Data Ready Delay Adjust 001 Analog gain adjustment Data7 to Data0: gain channel I Data15 to Data8: gain channel Q Code 00000000: -1.5 dB Code 10000000: 0 dB Code 11111111: 1.5 dB Steps: 0.011 dB 010 Offset compensation Data7 to Data0: offset channel I Data15 to Data8: offset channel Q Data7 and Data15: sign bits Code 11111111b: 31.75 LSB Code 10000000b: 0 LSB Code 00000000b: 0 LSB Code 01111111b: -31.75 LSB Steps: 0.25 LSB Maximum correction: 31.75 LSB 011 Gain compensation Data6 to Data0: channel I/Q (Q is matched to I for interleaving adjustment) Code 11111111b: -0.315 dB Code 10000000b: 0 dB Code 0000000b: 0 dB Code 0111111b: 0.315 dB Steps: 0.005 dB Data6: sign bit Data15 to Data7 = XXX 100 Internal Settling Adjustment (ISA) Data2 to Data0: channel I Data5 to Data3: channel Q Data15 to Data6: 1000010000 Code 000 = -200 ps Code 100 = 0 ps Code 111 = 150 ps DMUX 1:1 recommended value code 100 = 0 ps DMUX 1:2 recommended value code 010 = -100 ps 33 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 10-2. 3-wire Serial Interface Address Setting Description (Continued) Address Setting 101 Testability Data3 to Data0 = 0000 Mode S/H transparent Data7 = 0 Data8 = 0 Data5 to Data6 = XXX Data15 to Data9 = XXX 110 Built-In Test (BIT) Data0 = 0 BIT Inactive Data0 = 1 BIT Active Data1 = 0 Static BIT Data1 = 1 Dynamic BIT If Data1 = 1, then Ports BI & BQ = Rising Ramp Ports AI & AQ = Decreasing Ramp If Data1 = 0, then Data2 to Data9 = Static Data for BIT Ports BI & BQ = Data2 to Data9 Ports AI & AQ = NOT (Data2 to Data9) Data15 to Data10 = XXX 111 Data Ready Delay Adjust (DRDA) Data2 to Data0: clock I Data5 to Data3: clock Q Steps: 85 ps 000: -340 ps 100: 0 ps 111: +255 ps Fine Sampling Delay Adjustment (FiSDA) on channel Q Data10 to Data6: channel Q Steps: 4 ps Data4: sign bit 11000: -60 ps Code 10000: 0 ps Code 00000: 0 ps Code 01111: +60 ps Data15 to Data11 = XXX Notes: OFF: Data4 = 0 ON: Data4 = 1 1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and Q) of the sample/hold (with a fixed digital sampling time) with steps of 50 ps: Nominal mode will be given by Data2...Data0 = 100 or Data5...Data3 = 100. Data5...Data3 = 000 or Data2...Data0 = 000: sampling time is -200 ps compared to nominal. Data2...Data0 = 111 or Data5...Data3 = 111: sampling time is 150 ps compared to nominal. We recommend setting the ISA to 0 ps in 1:1 DMUX mode and to -100 ps in 1:2 DMUX mode to optimize the ADC's dynamic performance. 2. The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of 4 ps) on channel Q more precisely, particularly in the interleaved mode. 3. A Built-In Test (BIT) function is available to rapidly test the device's I/O by either applying a defined static pattern to the dual ADC or by generating a dynamic ramp at the output of the dual ADC. This function is controlled via the 3-wire bus interface at the address 110. The maximum clock frequency in dynamic BIT mode is 1 Gsps. Please refer to "Built-In Test (BIT)" on page 41 for more information about this function. Dynamic BIT works on channel I when Clock I is applied and on channel Q when clock Q is applied. 4. The decimation mode enables you to lower the output bit rate (including the output clock rate) by a factor of 16, while the internal clock frequency remains unchanged. The maximum clock frequency in decimation mode is 1 Gsps. 5. The "S/H transparent" mode (address 101, Data4) enables bypassing of the ADC's track/hold. This function optimizes the ADC's performances at very low input frequencies (Fin < 50 MHz) with an increase of 2 dB in SNR. 34 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 6. If bit D2 "Chip version Test bit" is set to "0", the output bit Cal should change to high level when the ADC corresponds to AT84AD001C version (this function is not implemented in previous AT84AD001 and AT84AD001B versions). 7. With DRDA adjustment, you can shift the Output clock signal (shift the falling and rising edges) from -200 to +150 ps around its default value. 8. DDRB reset is needed whenever the following functions are changed: DMUX mode, FS/2 - FS/4 function, clock frequency. BIT function (Test mode) in DMUX 1:2. 35 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 10-3. 3-wire Serial Interface Data Setting Description D15 D14 D13 D12 D11 D10 D9(1) D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 X X X X X X X 1 1 X X X X X X 0 X X X X X X X 0 1 X X X X X X 0 X X X X X X X 1 0 No standby mode X X X X X X 0 X X X X X X X 0 0 Chip Version Test bit inactivated(7) X X X X X X 0 X X X X X X 1 X X Chip Version Test bit activated(7) X X X X X X 0 X X X X X X 0 X X DMUX 1:2 mode X X X X X X 0 X X X X X 1 X X X DMUX 1:1 mode X X X X X X 0 X X X X X 0 X X X Analog selection mode Input I ADC I Input Q ADC Q X X X X X X 0 X X X 1 1 X X X X Analog selection mode Input I ADC I Input I ADC Q X X X X X X 0 X X X 1 0 X X X X Analog selection mode Input Q ADC I Input Q ADC Q X X X X X X 0 X X X 0 X X X X X Clock Selection mode CLKI ADC I CLKQ ADC Q X X X X X X 0 X 1 1 X X X X X X Clock selection mode CLKI ADC I CLKI ADC Q X X X X X X 0 X 1 0 X X X X X X Clock selection mode CLKI ADC I CLKIN ADC Q X X X X X X 0 X 0 X X X X X X X Decimation OFF mode X X X X X X 0 0 X X X X X X X X Decimation ON mode X X X X X X 0 1 X X X X X X X X Keep last calibration calculated value(4) No calibration phase X X X X 0 1 0 X X X X X X X X X No calibration phase(5) No calibration value X X X X 0 0 0 X X X X X X X X X Start a new calibration phase X X X X 1 1 0 X X X X X X X X X Setting for Address: 000 Full standby mode Standby channel I (2) Standby channel Q (3) 36 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 10-3. 3-wire Serial Interface Data Setting Description (Continued) D15 D14 D13 D12 D11 D10 D9(1) D8 D7 D6 D5 D4 D3 D2 D1 D0 Control wait bit calibration(6) X X a b X X 0 X X X X X X X X X In 1:2 DMUX FDataReady I & Q = Fs/4 (9) X 0 X X X X 0 X X X X X X X X X In 1:2 DMUX FDataReady I & Q = Fs/2 (9) X 1 X X X X 0 X X X X X X X X X Setting for Address: 000 Notes: 1. D9 must be set to "0" 2. Mode standby channel I: use analog input I Vini, Vinib and Clocki. 3. Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq. 4. Keep last calibration calculated value - no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The values taken into account for the gain and offset are either from the last calibration phase or are default values (reset values). 5. No calibration phase - no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation and at address 011 for the gain compensation. 6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase: For high clock rates (> 500 Msps) use a = b = 1. For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0. For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1. For low clock rates < 125 Msps use a = 0 and b = 0. 7. If bit D2 "Chip version Test bit" is set to "0", the output bit Cal should change to high level when the ADC corresponds to AT84AD001C version (this function is not implemented in previous AT84AD001 and AT84AD001B versions). 8. When Channel I is in standby (D1 = 0, D0 = 1), the following modes are forbidden: Clock I I & Q (D7 = 1, D6 = 0) Clock I I & Clock IN Q (D7 = 0, D6 = X) 9. Default mode for AT84AD001C is now Fs/4 (previously Fs/2 for AT84AD001Bxxx series). 10.1.2 3-wire Serial Interface Timing Description The 3-wire serial interface is a synchronous write-only serial interface made of three wires: * sclk: serial clock input * sldn: serial load enable input * sdata: serial data input The 3-wire serial interface gives write-only access to as many as 8 different internal registers of up to 16 bits each. The input format is always fixed with 3 bits of register address followed by 16 bits of data. The data and address are entered with the Most Significant Bit (MSB) first. The write procedure is fully synchronous with the rising clock edge of "sclk" and described in the write chronogram (Figure 10-1 on page 38). * "sldn" and "sdata" are sampled on each rising clock edge of "sclk" (clock cycle). * "sldn" must be set to 1 when no write procedure is performed. * A minimum of one rising clock edge (clock cycle) with "sldn" at 1 is required for a correct start of the write procedure. * A write starts on the first clock cycle with "sldn" at 0. "sldn" must stay at 0 during the complete write procedure. 37 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C * During the first 3 clock cycles with "sldn" at 0, 3 bits of the register address from MSB (a[2]) to LSB (a[0]) are entered. * During the next 16 clock cycles with "sldn" at 0, 16 bits of data from MSB (d[15]) to LSB (d[0]) are entered. * An additional clock cycle with "sldn" at 0 is required for parallel transfer of the serial data d[15:0] into the addressed register with address a[2:0]. This yields 20 clock cycles with "sldn" at 0 for a normal write procedure. * A minimum of one clock cycle with "sldn" returned at 1 is requested to close the write procedure and make the interface ready for a new write procedure. Any clock cycle where "sldn" is at 1 before the write procedure is completed interrupts this procedure and no further data transfer to the internal registers is performed. * Additional clock cycles with "sldn" at 0 after the parallel data transfer to the register (done at the 20th consecutive clock cycle with "sldn" at 0) do not affect the write procedure and are ignored. It is possible to have only one clock cycle with "sldn" at 1 between two following write procedures. * 16 bits of data must always be entered even if the internal addressed register has less than 16 bits. Unused bits (usually MSBs) are ignored. Bit signification and bit positions for the internal registers are detailed in Table 10-2 on page 33. To reset the registers, the Pin mode can be used as a reset pin for chip initialization, even when the 3wire serial interface is used. Figure 10-1. Write Chronogram Mode 1 2 3 4 a[1] a[0] d[15] 5 13 14 15 16 17 18 19 d[1] d[0] 20 sclk sldn sdata Internal register value a[2] d[8] d[7] d[6] d[5] d[4] d[3] d[2] New d Reset setting Reset Write procedure Figure 10-2. Timing Definition Twlmode Mode Tsclk Twsclk Tdmode Tdmode sclk Tssldn Thsldn Tssdata Thsdata sldn sdata 38 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 10-4. Timing Description Value 10.1.3 Name Parameter Min Typ Max Unit Tsclk Sclk period 20 ns Twsclk High or low time of sclk 5 ns Tssldn Setup time of sldn before rising edge of sclk 4 ns Thsldn Hold time of sldn after rising edge of sclk 2 ns Tssdata Setup time of sdata before rising edge of sclk 4 ns Thsdata Hold time of sdata after rising edge of sclk 2 ns Twlmode Minimum low pulse width of mode 5 ns Tdmode Minimum delay between an edge of mode and the rising edge of sclk 10 ns Calibration Description The AT84AD001C offers the possibility of reducing offset and gain matching between the two ADC cores. An internal digital calibration may start right after the 3-wire serial interface has been loaded (using data D12 of the 3-wire serial interface with address 000). This calibration might be launched several times before the optimum is reached. The beginning of calibration disables the two ADCs and a standard data acquisition is performed. The output bit CAL goes to a high level during the entire calibration phase. When this bit returns to a low level, the two ADCs are calibrated with offset and gain and can be used again for a standard data acquisition. If only one channel is selected (I or Q) the offset calibration duration is divided by two and no gain calibration between the two channels is necessary. Figure 10-3. Internal Timing Calibration 3-wire Serial Interface LDN CAL Tcal The Tcal duration is a multiple of the clock frequency ClockI (master clock). Even if a dual clock scheme is used during calibration, ClockQ will not be used. The control wait bits (D13 and D14) give the possibility of changing the calibration's setting depending on the clock's frequency: * For high clock rates (> 500 Msps) use a = b = 1, Tcal = 10112 clock I periods. * For clock rates > 250 Msps and < 500 Msps use a = 1, b = 0, Tcal = 6016 clock I periods. * For clock rates > 125 Msps and < 250 Msps use a = 0, b = 1 ,Tcal = 3968 clock I periods. * For low clock rates (< 125 Msps) use a = 0, b = 0 , Tcal = 2944 clock I periods. 39 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C The calibration phase is necessary when using the AT84AD001C in Interleaved mode, where one analog input is sampled at both ADC cores on the common input clock's rising and falling edges. This operation is equivalent to converting the analog signal at twice the clock frequency. Table 10-5. Matching Between Channels Value Parameter Min Typ -2 0 Gain error (single channel I or Q) without calibration Gain error (single channel I or Q) with calibration 2 % % 0 -2 0 126 127.5 Mean offset code without calibration (single channel I or Q) Mean offset code with calibration (single channel I or Q) Unit 0 Offset error (single channel I or Q) without calibration Offset error (single channel I or Q) with calibration Max LSB 2 LSB 127.5 129 During the ADC's auto-calibration phase, the dual ADC is set with the following: * Decimation mode ON * 1:1 DMUX mode * Binary mode Any external action applied to any signal of the ADC's registers is inhibited during the calibration phase. 10.1.4 Gain and Offset Compensation Functions It is also possible for the user to have external access to the ADC's gain and offset compensation functions: * Offset compensation between I and Q channels (at address 010) * Gain compensation between I and Q channels (at address 011) To obtain manual access to these two functions, which are used to set the offset to middle code 127.5 and to match the gain of channel Q with that of channel I (if only one channel is used, the gain compensation does not apply), it is necessary to set the ADC to "manual" mode by writing 0 at bits D11 and D10 of address 000. 40 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 10.1.5 Built-In Test (BIT) A Built-In Test (BIT) function is available to allow rapid testing of the device's I/O by either applying a defined static pattern to the ADC or by generating a dynamic ramp at the ADC's output. The dynamic ramp can be used with a clock frequency of up to 1 Gsps. This function is controlled via the 3-wire bus interface at address 101. * The BIT is active when Data0 = 1 at address 110. * The BIT is inactive when Data0 = 0 at address 110. * The Data1 bit allows choosing between static mode (Data1 = 0) and dynamic mode (Data1 = 1). When the static BIT is selected (Data1 = 0), it is possible to write any 8-bit pattern by defining the Data9 to Data2 bits. Port B then outputs an 8-bit pattern equal to Data9 ... Data2, and Port A outputs an 8-bit pattern equal to NOT (Data9 ... Data2). Note: In 1:1 DMUX mode, the ramp test mode works with the same output rate as in 1:2 DMUX mode, ie. The change stays at the same code during 2 clock cycles instead of 1" Example: Address = 110 Data = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 1 0 1 0 1 0 1 0 1 One should then obtain 01010101 on Port B and 10101010 on Port A. When the dynamic mode is chosen (Data1 = 1) port B outputs a rising ramp while Port A outputs a decreasing one. Note: In dynamic mode, use the DRDA function to align the edges of CLKO with the middle of the data. Dynamic BIT works on channel I when Clock I is applied and on channel Q when clock Q is applied. 10.1.6 Decimation Mode The decimation mode can be used with a clock frequency of up to 1 Gsps. In decimation mode, one data out of 16 is output, thus leading to a maximum output rate of 62.5 Msps. Note: Frequency (CLKO) = frequency (Data) = Frequency (CLKI)/16. 41 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 10.2 Die Junction Temperature Monitoring Function A die junction temperature measurement setting is included on the board for junction temperature monitoring. The measurement method forces a 1 mA current into a diode-mounted transistor. Caution should be given to respecting the polarity of the current. In any case, one should make sure the maximum voltage compliance of the current source is limited to a maximum of 1V or use a resistor serial-mounted with the current source to avoid damaging the transistor device (this may occur if the current source is reverse-connected). The measurement setup is illustrated in Figure 10-5 on page 42. Figure 10-4. Die Junction Temperature Monitoring Setup VDiode (Pin 35) 1 mA GNDD (Pin 36) Protection Diodes The VBE diode's forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure 11-1. Figure 10-5. Diode Characteristics Versus TJ 860 840 820 Diode Voltage (mV) 800 780 760 740 720 700 680 660 640 620 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Junction Temperature (C) 10.3 VtestI, VtestQ VtestI and VtestQ pins are for internal test use only. These two signals must be left open. 42 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 11. Equivalent Input/Output Schematics Figure 11-1. Simplified Input Clock Model VCCD CLKI or CLKQ 100 50 VCCD/2 50 100 CLKIN or CLKQN) GNDD Figure 11-2. Simplified Data Ready Reset Buffer Model VCCD DDRB 100 50 VCCD/2 50 100 DDRBN GNDD 43 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 11-3. Analog Input Model Vcca Vcca DC Coupling (Common Mode = Ground = 0V) Vinl Reverse Termination 50 Sel Input I ESD GND VinI VinI Double Pad GND - 0.4V MAX ESD GND 50 VinQ Reverse Termination GND GND VinQ VinQ Double Pad Sel Input Q Figure 11-4. Data Output Buffer Model VCCO DOAIO, DOAI7 DOBIO, DOBI7 DOAION, DOAI7N DOBION, DOBI7N GNDO 44 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 12. Definitions of Terms Table 12-1. Definitions of Terms Abbreviation Definition Description BER Bit Error Rate The probability of an error occurring on the output at a maximum sampling rate. DNL Differential Non-Linearity The differential non-linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). A DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic ENOB Effective Number of Bits FPBW Full Power Input Bandwidth The analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at full-scale -1 dB (-1 dBFS) IMD Inter-Modulation Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either of the two input tones to the worst third order intermodulation products INL Integral Non-Linearity The integral non-linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs and is the maximum value of all |INL (i)| JITTER Aperture uncertainty The sample-to-sample variation in aperture delay. The voltage error due to jitters depends on the slew rate of the signal at the sampling point NPR Noise Power Ratio The NPR is measured to characterize the ADC's performance in response to broad bandwidth signals. When applying a notch-filtered broadband white noise signal as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test ORT Overvoltage Recovery Time The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale PSRR Power Supply Rejection Ratio The ratio of input offset variation to a change in power supply voltage SFDR Spurious Free Dynamic Range The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS value of the highest spectral component (peak spurious spectral component). The peak spurious component may or may not be a harmonic. It may be reported in dB (related to the converter -1 dB full-scale) or in dBc (related to the input signal level) SINAD Signal to Noise and Distortion Ratio The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (-1 dBFS) to the RMS sum of all other spectral components including the harmonics, except DC SNR Signal to Noise Ratio The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS sum of all other spectral components excluding the first 9 harmonics SSBW Small Signal Input Bandwidth The analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at full-scale -10 dB (-10 dBFS) TA Aperture delay The delay between the rising edge of the differential clock inputs (CLKI, CLKIN) [zero crossing point] and the time at which VIN and VINB are sampled TC Encoding Clock period TC1 = minimum clock pulse width (high) TC = TC1 + TC2 TC2 = minimum clock pulse width (low) TD1 Time delay data to clock Time delay between Data transition (Port A or B) channel I or Q to Output Clock CLKXO (channel I or Q) TD2 Time delay clock to data Time delay between Output Clock CLKXO (channel I or Q) to Data transition (Port A or B) channel I or Q A SINAD - 1,76 + 20 log ----------Fs/2 ENOB = ----------------------------------------------------------------------------6,02 Where A is the actual input amplitude and Fs is the full scale range of the ADC under test If Output Clock CLKXO is in the middle to data TD1 = Tdata/2 If Output Clock CLKXO is in the middle to data TD2 = Tdata/2 45 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table 12-1. Abbreviation Definitions of Terms (Continued) Definition Description This difference TD1-TD2 gives an information if Output Clock CLKXO (channel I or Q) is centered on the output data If Output Clock CLKXO is in the middle to data TD2=TD1=Tdata/2 TD1-TD2 TDO Digital Data Output Delay The delay from the rising edge of the differential clock inputs (CLKI, CLKIN) [zero crossing point] to the next point of change in the differential output data (zero crossing) with a specified load TDR Data Ready Output Delay The delay from the falling edge of the differential clock inputs (CLKI, CLKIN) [zero crossing point] to the next point of change in the differential output data (zero crossing) with a specified load TF Fall Time The time delay for the output data signals to fall from 20% to 80% of delta between the low and high levels THD Total Harmonic Distortion The ratio expressed in dB of the RMS sum of the first 9 harmonic components to the RMS input signal amplitude, set at 1 dB below full-scale. It may be reported in dB (related to the converter -1 dB full-scale) or in dBc (related to the input signal level) TPD Pipeline Delay The number of clock cycles between the sampling edge of an input data and the associated output data made available (not taking into account the TDO) TR Rise Time The time delay for the output data signals to rise from 20% to 80% of delta between the low and high levels TRDR Data Ready Reset Delay The delay between the falling edge of the Data Ready output asynchronous reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR) TS Settling Time The time delay to rise from 10% to 90% of the converter output when a full-scale step function is applied to the differential analog input VSWR Voltage Standing Wave Ratio The VSWR corresponds to the ADC input insertion loss due to input power reflection. For example, a VSWR of 1.2 corresponds to a 20 dB return loss (99% power transmitted and 1% reflected) 46 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 13. Using the AT84AD001C Dual 8-bit 1 Gsps ADC 13.1 Decoupling, Bypassing and Grounding of Power Supplies The following figures show the recommended bypassing, decoupling and grounding schemes for the dual 8-bit 1 Gsps ADC power supplies. Figure 13-1. VCCD and VCCA Bypassing and Grounding Scheme L PC Board 3.3V VCCD 1 mF L VCCA 100 pF PC Board GND C C Figure 13-2. VCCO Bypassing and Grounding Scheme L VCCO PC Board 2.25V 1F 100 pF PC Board GND C Note: L and C values must be chosen in accordance with the operation frequency of the application. Figure 13-3. Power Supplies Decoupling Scheme VCCA VCCA 100 pF 10 nF GNDA GNDA GNDO VCCD VCCO VCCO 100 pF 10 nF GNDO 100 pF 10 nF GNDD Note: The bypassing capacitors (1 F and 100 pF) should be placed as close as possible to the board connectors, whereas the decoupling capacitors (100 pF and 10 nF) should be placed as close as possible to the device. 47 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 13.2 Analog Input Implementation The analog inputs of the dual ADC have been designed with a double pad implementation as illustrated in Figure 13-5 on page 49. The reverse pad for each input should be tied to ground via a 50 resistor. The analog inputs must be used in differential mode only. Figure 13-4. Termination Method for the ADC Analog Inputs in DC Coupling Mode 50 VinI VinI 50 Source Channel I VinIB GND 50 VinIB Dual ADC 50 VinQ VinQ 50 Source Channel Q VinQB GND 50 VinQB 48 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 13-5. Termination Method for the ADC Analog Inputs in AC Coupling Mode 50 VinI 50 Source VinI Channel I GND VinIB GND 50 VinIB Dual ADC 50 VinQ 50 Source VinQ Channel Q GND VinQB GND 50 VinQB 13.3 Clock Implementation The ADC features two different clocks (I or Q) that must be implemented as shown in Figure 13-6. Each path must be AC coupled with a 100 nF capacitor. Figure 13-6. Differential Termination Method for Clock I or Clock Q ADC Package 50 VCCD/2 100 nF CLKIN or CLKQN Note: 50 Differential Buffer 100 nF CLKI or CLKQ When only clock I is used, it is not necessary to add the capacitors on the CLKQ and CLKQN signal paths; they may be left floating. 49 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 13-7. Single-ended Termination Method for Clock I or Clock Q AC coupling Capacitor CLKI or CLKQ 50 Source 50 50 AC coupling Capacitor VCDD CLKIN or CLKQN 50 13.4 Reset Implementation DDRB may be implemented as described in the following figure. A pull-up resistor is implemented to maintain the DDRB signal inactive in normal mode. The Data Ready Reset command (it might be a pulse) is active on the high level. Figure 13-8. Reset Implementation DDRB inactive R = 1.4 K DDRB DDRB AT84AD001C C = 100 nF DDRBN DDRBN R = 1.5 K VCCD Note: The external pull and pull down resistors are needed to bias the differential pair in AC coupling. They are of no use in DC coupling (when used with an LVDS driver). 50 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 13.5 Output Termination in 1:1 Ratio When using the integrated DMUX in 1:1 ratio, the valid port is port A. Port B remains unused. Port A functions in LVDS mode and the corresponding outputs (DOAI or DOAQ) have to be 100 differentially terminated as shown in Figure 13-9. The pins corresponding to Port B (DOBI or DOBQ pins) must be left floating (in high impedance state). Figure 13-9 shows the example of a 1:1 ratio of the integrated DMUX for channel I (the same applies to channel Q). Figure 13-9. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused) DOBI0 / DOBI0N DOBI1 / DOBI1N DOBI2 / DOBI2N Port B DOBI3 / DOBI3N Floating (High Z) DOBI4 / DOBI4N DOBI5 / DOBI5N DOBI6 / DOBI6N DOBI7 / DOBI7N Dual ADC Package DOAI0 / DOAI0N DOAI1 / DOAI1N VCCO DOAI2 / DOAI2N DOAI3 / DOAI3N Port A DOAI4 / DOAI4N DOAI5 / DOAI5N DOAI0 Z0 = 50 DOAI0N Z0 = 50 LVDS In DOAI6 / DOAI6N DOAI7 / DOAI7N 100 LVDS In Note: If the outputs are to be used in single-ended mode, it is recommended that the true and false signals be terminated with a 50 resistor. 51 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 13.6 Using the Dual ADC With and ASIC/FPGA Load Figure 13-10 illustrates the configuration of the dual ADC (1:2 DMUX mode, independent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential additional DMUXes used to halve the speed of the dual ADC outputs. Figure 13-10. Dual ADC and ASIC/FPGA Load Block Diagram Data rate = FsI/2 Port A Channel I DEMUX 8 :16 Data rate = FsQ/2 Data rate = FsQ/4 CLKI/CLKIN @ FsI Port A Dual 8-bit 1 Gsps ADC Channel Q DMUX 8 :16 ASIC / FPGA Port B Channel I DMUX 8 :16 CLKQ/CLKQN @ FsQ Port B DMUX 8 :16 Channel Q Note: The demultiplexers may be internal to the ASIC/FPGA system. 52 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 14. Thermal Characteristics 14.1 Simplified Thermal Model for LQFP 144 20 x 20 x 1.4 mm The following model has been extracted from the ANSYS FEM simulations. Assumptions: no air, no convection and no board. Figure 14-1. Simplified Thermal Model for LQFP Package 8.3C/watt Silicon Junction Package top 355 m silicon die 25 mm 2 = 0.95 W/cm/C 0.6C/watt 40 m Epoxy/Ag glue = 0.02 W/cm/C 1.4C/watt Copper paddle = 2.5 W/cm/C Resin = 0.007 W/cm/C 0.1C/watt 6.1C/watt 1.5C/watt 5.5C/watt Leads tip Aluminium paddle Resin Copper alloy leadframe = 0.007 W/cm/C = 25 W/cm/C Aluminium paddle = 0.75 W/cm/C 0.1C/watt Resin bottom = 0.007 W/cm/C 4.3C/watt Package bottom Assumptions: Die 5.0 x 5.0 = 25 mm 2 40 m thick Epoxy/Ag glue Package bottom connected to: (user dependent) 100 m air gap = 0.00027 W/cm/C 11.4C/watt 100 m thermal grease gap diamater 12 mm Top of user boa = 0.01 W/cm/C 1.5C/watt Note: The above are typical values with an assumption of uniform power dissipation over 2.5 x 2.5 mm2 of the top surface of the die. 53 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 14.1.0.1 Thermal Resistance from Junction to Bottom of Leads Assumptions: no air, no convection and no board. The thermal resistance from the junction to the bottom of the leads is 15.2C/W typical. 14.1.0.2 Thermal Resistance from Junction to Top of Case Assumptions: no air, no convection and no board. The thermal resistance from the junction to the top of the case is 8.3C/W typical. 14.1.0.3 Thermal Resistance from Junction to Bottom of Case Assumptions: no air, no convection and no board. The thermal resistance from the junction to the bottom of the case is 6.4C/W typical. 14.1.0.4 Thermal Resistance from Junction to Bottom of Air Gap The thermal resistance from the junction to the bottom of the air gap (bottom of package) is 17.9C/W typical. 14.1.0.5 Thermal Resistance from Junction to Ambient The thermal resistance from the junction to ambient is 25.2C/W typical. Note: In order to keep the ambient temperature of the die within the specified limits of the device grade (that is Tamb max = 70C in commercial grade and 85C in industrial grade) and the die junction temperature below the maximum allowed junction temperature of 105C, it is necessary to operate the dual ADC in air flow conditions (1m/s recommended). In still air conditions, the junction temperature is indeed greater than the maximum allowed TJ. - TJ = 25.2 C/W x 1.4W + Tamb = 35.28 + 70 = 105.28 C for commercial grade devices - TJ = 25.2 C/W x 1.4W + Tamb = 35.28 + 85 = 125.28 C for industrial grade devices 14.1.0.6 14.2 14.2.1 Thermal Resistance from Junction to Board The thermal resistance from the junction to the board is 13C/W typical. LQFP-ep 144L Green Package Thermal Characteristics Thermal Resistance from Junction to Ambient Simulations (JEDEC JESD51 standard) were held with the following assumptions: * Board with 76.2 mm x 114.3 mm dimensions * Still air * Exposed pad (5.8 x 5.8 mm) soldered to the board The thermal resistance from the junction to ambient is 25.0 C/W. Note: when the exposed pad is not soldered to the board, the Rthj-a becomes 58.8C/W. 54 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 14.2.2 Exposed pad Board layout recommendation This recommendation is done for the AT84AD001CXEPW (LQFP-ep 144L green package). Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence; special attention is require to the heat transfer below the package to provide a good thermal bond to the PCB. A Copper (Cu) fill is to be designed into PCB as a thermal pad under the package. Heat from devices, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 6.5 array of via. The LQFP metal died paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The diameter of solder Mask needs to be higher than diameter of via (diameter of via+ 0.2 mm) The diameter of solder Mask is 0.3 mm + 0.1 mm + 0.1 mm = 0.5 mm) The Solder Paste template needs to de designed to allow at least 50% solder coverage. The Solder Paste is place between the balls (diamond area) and not covers all the copper. 6.5 mm Via. 6.5 mm 6.5 mm 0.3 mm, typ. 6.5 mm To GND 0.5 mm, typ. 6.5 mm 6.5 mm 1.25 mm, typ. Solder Mask Copper + Via (White area) Solder Paste Mask (Grey Area) The thermal via is connected to inner layer (GND layer) with complete connection. 55 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 15. Ordering Information Table 15-1. Ordering Information Part Number Package AT84AD001CCTD LQFP 144 AT84AD001CVTD LQFP 144 AT84XAD001CEPW LQFP-ep 144L Temperature Range C grade 0C < Tamb < 70C V grade -40C < Tamb < 85C Screening Comments Standard Please contact your local sales office Standard Please contact your local sales office Ambient Prototype green (RoHS compliant) C grade 0C < Tamb < 70C Standard AT84AD001CVEPW LQFP-ep 144L green (RoHS compliant) V grade -40C < Tamb < 85C Standard AT84AD001TD-EB LQFP 144 Ambient Prototype AT84AD001CCEPW green (RoHS compliant) LQFP-ep 144L Evaluation Kit 56 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 16. Packaging Information Figure 16-1. LQFP 144 Package N 1 B E1 A Body +2.00 mm footprint Tols. Leads 144L max. 1.60 0.05 min./0.15 max. +/- 0.05 1.40 +/-0.20 22.00 +/-0.10 20.00 +/-0.20 22.00 +/-0.10 20.00 +0.15/-0.10 0.60 basic 0.50 +/-0.05 0.22 0.08 max. 0.08 o 0 o- 5 Dims. A A1 A2 D D1 E E1 L e b ddd ccc o E Notes: D D1 1. All dimensions are in millimeters 2. Dimensions shown are nominal with tolerances as indicated 3. L/F: eftec 64T copper or equivalent 4. Foot length: "L" is measured at gauge plane at 0.25 mm above the seating plane D 12 o TYP. A2 e A1 A 12 o TYP. 0.20 RAD max. 0.20 RAD nom. 6o A C Stand off A1 0.25 Seating plane C Lead coplanarity 0 0.17 max b L Note: + 4o - ddd e c A-B e De ccc c Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm. 57 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 16-2. LQFP-ep 144L Green Package PIN 1 1 144 D 7.000 REF. D D1 H REF. (4X) 14.000 REF. D 19.9000.100 20.0000.100 (D1) 5.800 REF. 14.000 REF. B X (4X) 19.9000.100 Y bbb H A-B E EXPOSED PAD AREA D SEATING PLANE b b1 SECTION N-N C T1 b e ddd C A-B D DETAIL Y DETAIL X C0.800X45 (4X) L 0 0.20 00~ H N N R0.100~0.200 R0.1 0.200 Min. L1 0 Min. R0.300 TYP ALL AROUND a A C A-B 12 ALL AROUND 12 ALL AROUND 1 144 C ccc . (4X) aaa BACK PIN 1 A2 A1 E1 5.800 REF. 14.000 REF. 14.000 REF. 20.0000.100 (E1) A T 0.250 BASE GAGE PLANE 58 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Figure 16-3. Dimensions DIMENSION LIST (FOOTPRINT: 2.00) S/N SYM DIMENSIONS REMARKS 1 A MAX. 1.600 OVERALL HEIGHT 2 A1 0.1000.050 STANDOFF 3 A2 1.4000.050 PKG THICKNESS 4 D 22.0000.200 LEAD TIP TO TIP 5 D1 20.0000.100 PKG LENGTH 6 E 22.0000.200 LEAD TIP TO TIP 7 E1 20.0000.100 PKG WIDTH 8 L 0.6000.150 FOOT LENGTH 9 L1 1.000 REF. LEAD LENGTH 10 T 0.150 -0.060 LEAD THICKNESS 11 T1 0.1270.030 LEAD BASE METAL THICKNESS 12 a 0~7 FOOT ANGLE 13 b 0.2200.050 LEAD WIDTH 14 b1 0.2000.030 LEAD BASE METAL WIDTH 15 e 0.500 BASE LEAD PITCH 16 H (REF.) (17.500) 17 aaa 0.200 18 bbb 0.200 PROFILE OF MOLD SURFACE 19 ccc 0.080 FOOT COPLANARITY 20 ddd 0.080 FOOT POSITION +0.050 CUM. LEAD PITCH PROFILE OF LEAD TIPS NOTES : S/N DESCRIPTION SPECIFICATION 1 GENERAL TOLERANCE. DISTANCE ANGLE 0.100 2.5 2 MATTE FINISH ON PACKAGE BODY SURFACE EXCEPT EJECTION AND PIN 1 MARKING. ALL MOLDED BODY SHARP CORNER RADII UNLESS OTHERWISE SPECIFIED. Ra0.8~2.0 um 4 PACKAGE/LEADFRAME MISALIGNMENT ( X, Y ): MAX. 0.127 5 TOP/BTM PACKAGE MISALIGNMENT ( X, Y ): MAX. 0.127 6 DRAWING DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OR CUTTING BURR. 7 COMPLIANT TO JEDEC STANDARD: 3 FOR HIGH DENSITY STRIP LAYOUT MAX. R0.200 MS-026 59 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 60 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C Table of Contents 1 Features .................................................................................................... 1 2 Performance ............................................................................................. 1 3 Application ............................................................................................... 2 4 Description ............................................................................................... 2 5 Functional Description ............................................................................ 2 6 Typical Applications ................................................................................ 4 7 Electrical Operating Characteristics ...................................................... 7 7.1 Timing Diagrams .................................................................................................. 13 7.2 Functions Description ........................................................................................... 26 7.3 Digital Output Coding (Nominal Settings) ............................................................. 26 8 Pin Description ...................................................................................... 27 9 Typical Characterization Results ......................................................... 30 9.1 Typical Full Power Input Bandwidth ..................................................................... 30 9.2 Typical DC, INL and DNL Patterns ....................................................................... 31 10 Test and Control Features .................................................................... 32 10.1 3-wire Serial Interface Control Setting .................................................................32 10.2 Die Junction Temperature Monitoring Function .................................................. 42 10.3 VtestI, VtestQ ...................................................................................................... 42 11 Equivalent Input/Output Schematics ................................................... 43 12 Definitions of Terms .............................................................................. 45 13 Using the AT84AD001C Dual 8-bit 1 Gsps ADC .................................. 47 13.1 Decoupling, Bypassing and Grounding of Power Supplies ................................. 47 13.2 Analog Input Implementation ............................................................................... 48 13.3 Clock Implementation .......................................................................................... 49 13.4 Reset Implementation ......................................................................................... 50 13.5 Output Termination in 1:1 Ratio .......................................................................... 51 13.6 Using the Dual ADC With and ASIC/FPGA Load ................................................ 52 i 1006C-BDC-04/10 e2v semiconductors SAS 2010 AT84AD001C 14 Thermal Characteristics ........................................................................ 53 14.1 Simplified Thermal Model for LQFP 144 20 x 20 x 1.4 mm ............................................................................................ 53 14.2 LQFP-ep 144L Green Package Thermal Characteristics .................................... 54 15 Ordering Information ............................................................................. 56 16 Packaging Information .......................................................................... 57 Table of Contents ...................................................................................... i ii 1006C-BDC-04/10 e2v semiconductors SAS 2010 How to reach us Home page: www.e2v.com Sales offices: Europe Regional sales office Americas e2v ltd e2v inc 106 Waterhouse Lane 520 White Plains Road Chelmsford Essex CM1 2QU Suite 450 Tarrytown, NY 10591 England USA Tel: +44 (0)1245 493493 Tel: +1 (914) 592 6050 or 1-800-342-5338, Fax: +44 (0)1245 492492 Fax: +1 (914) 592-5148 mailto: enquiries@e2v.com mailto: enquiries-na@e2v.com e2v sas Asia Pacific 16 Burospace e2v ltd F-91572 Bievres Cedex 11/F., France Onfem Tower, Tel: +33 (0) 16019 5500 29 Wyndham Street, Fax: +33 (0) 16019 5529 Central, Hong Kong mailto: enquiries-fr@e2v.com Tel: +852 3679 364 8/9 Fax: +852 3583 1084 e2v gmbh mailto: enquiries-ap@e2v.com Industriestrae 29 82194 Grobenzell Germany Tel: +49 (0) 8142 41057-0 Fax: +49 (0) 8142 284547 mailto: enquiries-de@e2v.com Product Contact: e2v Avenue de Rochepleine BP 123 - 38521 Saint-Egreve Cedex France Tel: +33 (0)4 76 58 30 00 Hotline: mailto: hotline-bdc@e2v.com IMPORTANT NOTICE Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no liability for the consequences any use thereof and also reserves the right to make corrections, modifications, enhancements, improvements, and other changes of its products without prior notice. Users of e2v products should obtain the latest relevant information before placing orders and should verify that such information is current and complete. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of data converters or other devices in accordance with information contained herein. e2v semiconductors SAS 2010 1006C-BDC-04/10 AT84AD001C iv 1006C-BDC-04/10 e2v semiconductors SAS 2010