F10173 F10573 QUAD MULTIPLEXER/LATCH DESCRIPTION The F10173 and F10573 are Quad 2-Channel Multiplexers with latches. They incorporate a common Enable and a common Data Select Input. The Select input determines which Data input is enabled. A HIGH input enables Data inputs Doa, Dob, Doc, and Dod, and a LOW enables Data inputs D1a, Dib, Dic, Dia. Any change on the Data input appears at the outputs while the Enable is LOW. The outputs are latched on the positive transition of the enable. While the Enable input is in the HIGH state, a change in the information present at the Data inputs does not affect the output information. PIN NAMES s Dn E Qn Data Select Data tnputs Enable (Active LOW) Outputs LOGIC DIAGRAM Note that this diagram is provided for understanding of togic operation only. it should not be used for evaluation of propagation delays as many gate functions are achieved internally without incurring a full gate delay. LOGIC SYMBOL (9G) 19) (8) U7} TF 16) (15) 114) 6 5 4 3. 13=120~11~10 tives | | Ooa Dia Don D Bic Dog an? go02 Dia Ob 1b Doc Bic Dog Dig QUAD MULTIPLEXER/LATCH (13) 93-448 Ds % % og , i J 3 1 2 15 14 (5) i) 13) (2} Voc = 16 (4) VEE =8 (12) ( ) = Fiatpak CONNECTION DIAGRAM DIP (TOP VIEW) PACKAGE OUTLINE 6B FAIRCHILD ECL F10173 F10573 TRUTH TABLE s E | Qn+4 H L { Doa L L Dia x H | Qh L=LOW Voltage Level H= HIGH Voltage Levelt X = Don't Care DC CHARACTERISTICS: Veg = 5.2 V, Vcc = GND LIMITS SYMBOL CHARACTERISTIC UNITS TA CONDITIONS B TYP A WH Input Current HIGH pA 25C VIN=VIHA Enable and Select 245 Data 290 lee Power Supply Current 66 mA 25C Inputs and Outputs Open SWITCHING CHARACTERISTICS: Veg = 5.2 V, Ta = 25C ' SYMBOL CHARACTERISTIC LIMITS UNITS CONDITIONS B TYP A tPLH Propagation Delay 4.0 45 5.2 ns Enable to Output tPHL: Propagation Delay 1.0 2.5 3.8 ns tPLH Data to Output {tPLH. Propagation Delay 1.9 35 5.2 ns tPHL Select to Output {TLH: Output Transition Time 15 2.0 3.3 ns See Figure 1 {THL LOW to HIGH, HIGH to LOW (20% to 80%) (80% to 20%) ts Set-Up Time Data 1.5 ns Select 2.5 th Hold Time Data 0.0 ns Select -0.5 7-91 FAIRCHILD ECL F10173 F10573 SWITCHING TEST CIRCUIT AND WAVEFORMS Voc YouT 25 .F 0.1 WF LEADLESS Ly and Lg = equal length 50 2 impedance line Ry = 50 termination of scope CL = Jig and stray capacitance < 5.0 pF Decoupling 0.1 uF from gnd to Veg and Voc Voc =2.0V Veg=-3.2V +tAV NOTE: 50% D or $ INPUT 40.31 tg is the minimum time before the positive transition of the enable pulse (E) that Information must be present at the input (D) or (S). F1A1TV th is the minimum time after the positive transition of the enable pulse -+0.31 (E) that information must remain unchanged at the data input (D) or (S). D INPUT J \ Sf tog = 1.0 MHz E D INPUT frag = 1.0 MHz Q OUTPUT frog = 9.0 MHz ttun| j~<=+ | [HHL Q OUTPUT Fig.1 7-92