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GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace

Equalization and Output De-Emphasis

Data Sheet

55972 - 0 March 2012

GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace Equalization and Output

De-Emphasis

www.gennum.com

Key Features

• 2 x 2 crosspoint switch architecture

• Integrated CDR with 9.95 to 11.3Gb/s and 14.025Gb/s

reference-free operation

• Automatic rate detect

• Dynamic on-chip power management control

• Multiple user-programmable power-down saving

modes

• Independent programmable input trace equalization to

reduce deterministic jitter (ISI)

• Independent programmable output pre-emphasis for

driving long board traces

• Digital control through I2C interface

• Integrated analog-to-digital converter, which provides

access to digital diagnostic information on supply

voltage and die temperature

• Integrated eye monitor and PRBS7 generator/checker

• Polarity invert, output mute functions available

• Single 3.3V supply (±5%)

• On-chip I/O termination

• Low power consumption: 600mW typical

Low power option for 4.25 & 8.5Gb/s operation:

415mW typical

• 5mm x 5mm 32-pin QFN package

• -40°C to +100°C case operation

• RoHS-compliant

Applications

• Enterprise and carrier applications

• 10GbE, Fibre Channel and InfiniBand networks

•Redundancy switching

• Retimer for 10Gb/s and 14Gb/s backplane and

linecards

Description

The GX4002 is a low-power, high-speed 2 x 2 crosspoint

switch, with robust signal conditioning circuits for driving

and receiving high-speed signals through backplanes.

The device consumes as low as 600mW of power (typical)

with all channels operational. Unused portions of the chip

can be turned off in order to further reduce power

consumption.

The signal conditioning features of the GX4002 include

per-input clock and data recovery (CDR), programmable

equalization and per-output programmable de-emphasis.

The input equalizer removes ISI jitter—typically caused by

PCB trace losses—by opening the input data eye in

applications where long PCB traces are used. The

integrated CDR “resets” the jitter budget, effectively

erasing the signal distortion that can occur during

transmission.

Output pre-emphasis capability provides a boost of the

high-frequency content of the output signal, such that the

data eye remains open after passing through a long

interconnect of PCB traces and connectors.

The GX4002 features an integrated analog-to-digital

converter, which, through the serial interface, provides

digital diagnostic information about supply voltage and die

temperature.

The GX4002 device is packaged in a small-outline 5mm ×

5mm 32-pin, high-frequency QFN package with exposed

pad.

The GX4002 is Pb-free, and the encapsulation compound

does not contain halogenated flame retardant. This

component and all homogeneous sub components are

RoHS-compliant.

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Equalization and Output De-Emphasis

Data Sheet

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Figure A: GX4002 Functional Block Diagram

Ch0

Driver

Trace

Digital Core

I2C

2 x 2

Differential

Cross-point

Switch Matrix

SDO0/SDO0

SDO1/SDO1

Trace

Ch1

Driver

SDI1/SDI1

SDI0/SDI0

CDR with

Eye Monitor

CDR with

Eye Monitor

PRBS 7

Generator

PRBS 7

Checker

Temp Sensor

Supply Sensor

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Revision History

Contents

Key Features ........................................................................................................................................................1

Applications.........................................................................................................................................................1

Description...........................................................................................................................................................1

1. Pin Out...............................................................................................................................................................5

1.1 Pin Assignment ..................................................................................................................................5

1.2 Pin Descriptions ................................................................................................................................6

2. Electrical Characteristics ............................................................................................................................8

2.1 Absolute Maximum Ratings ..........................................................................................................8

2.2 DC Electrical Characteristics ........................................................................................................8

2.2.1 Power Features......................................................................................................................9

2.3 AC Electrical Characteristics ..................................................................................................... 10

2.4 Required Initialization Settings ................................................................................................ 12

3. Detailed Description.................................................................................................................................. 13

3.1 Multirate CDR Functionality ...................................................................................................... 13

3.1.1 Rate Selection and Rate Detection............................................................................... 13

3.1.2 Auto Retimer Bypass ........................................................................................................ 16

3.2 Channel 0 Path (Ch0) .................................................................................................................... 17

3.2.1 Ch0 Equalization................................................................................................................ 17

3.2.2 Ch0 PLL Variable Loop Bandwidth.............................................................................. 18

3.2.3 Channel 0 Output Polarity Invert................................................................................. 18

3.3 Channel 1 Path (Ch1) .................................................................................................................... 19

3.3.1 Integrated Limiting Amplifier ....................................................................................... 19

3.3.2 Ch1 Equalization................................................................................................................ 19

3.3.3 Ch1 PLL Variable Loop Bandwidth.............................................................................. 20

Version ECR Date Changes and / or Modifications

0 157889 March 2012 Ability to propagate loss of lock to Ch0FAULT pin

was added.

C157185 November

2011

Converted document to a Data Sheet. Updates

throughout. Removed typical temperature

monitor accuracy. Removed typical voltage

monitor accuracy. Added AC common-mode

channel characteristics. Added register 101 bits

[5:3] to Table 7-1: Configuration and Status

B 155955 March 2011 Correction to pin 21 and 23 in Table 1-1: Pin

Descriptions.

A 155765 February 2011 New document.

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Equalization and Output De-Emphasis

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3.3.4 Pre-Emphasis Driver with Auto-Mute........................................................................ 21

3.3.5 Channel 1 Output Polarity Invert................................................................................. 22

3.4 Crosspoint ........................................................................................................................................ 23

3.5 Status Indicators ............................................................................................................................ 27

3.5.1 Ch0 Loss Of Signal (LOS) ................................................................................................. 27

3.5.2 Ch1 Loss Of Signal............................................................................................................. 29

3.5.3 Loss Of Lock (LOL) ............................................................................................................. 32

3.5.4 Ch0FAULT - Channel 0 Fault......................................................................................... 33

3.6 Test Features ................................................................................................................................... 33

3.6.1 PRBS Generator and Checker........................................................................................ 34

3.6.2 Eye Monitor & Peak Detector......................................................................................... 36

3.7 Digital Diagnostics ........................................................................................................................ 38

3.7.1 Analog to Digital Converter (ADC) .............................................................................. 38

3.8 Power Control Options ................................................................................................................ 48

3.9 Device Reset .................................................................................................................................... 49

3.9.1 Reset State During Power-up......................................................................................... 49

3.9.2 RESET Timing...................................................................................................................... 50

3.9.3 I/O and Register States During and After Reset ...................................................... 51

3.10 Digital Control Interface ........................................................................................................... 51

3.10.1 I2C Host Interface Mode................................................................................................ 51

4. Typical Application Circuit ..................................................................................................................... 53

4.1 Power Supply Filter Recommendations ................................................................................ 53

4.2 Power Supply Domains ............................................................................................................... 54

5. Layout Considerations.............................................................................................................................. 55

6. Input/Output Equivalent Circuits......................................................................................................... 56

7. Package and Ordering Information...................................................................................................... 59

7.1 Package Dimensions ..................................................................................................................... 59

7.2 Recommended PCB Footprint ................................................................................................... 59

7.3 Packaging Data ............................................................................................................................... 60

7.4 Solder Reflow Profile .................................................................................................................... 60

7.5 Marking Diagram ........................................................................................................................... 61

7.6 Ordering Information ................................................................................................................... 61

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Data Sheet

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1. Pin Out

1.1 Pin Assignment

Figure 1-1: GX4002 Pin Assignment

Ground Pad

(bottom of package)

32 25

9 16

Ch1LOS 8

SDO0VCC

SDI1

RS1

SDO0VEE

Ch0VCC

GND

Ch0VEE

SDI0

Ch0VCOFILT

Ch0VCOVEE

Ch0LF

GX4002

32-pin QFN

(top view)

Ch0FAULT

SDO0

RS0

DIGVSS

VREG

SCL

SDA

Ch1LF

Ch1VCOVEE

Ch1VCOFILT

Ch1VEE

Ch1VCC

SDO1

RESET

31 30 29 28 27 26

10 11 12 13 14 15

SDI1

SDO1

SDI0

SDO0

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1.2 Pin Descriptions

Table 1-1: Pin Descriptions

Pin # Name Typ e Description

1SDO0VCC Power Power supply for channel 0 path output.

2SDO0VEE Ground Ground for channel 0 path output.

3, 4 NC—No connect.

5RS1Digital

Input

Input Digital LVTTL/LVCMOS-compliant input.

Rate Select Input for the Ch1 Signal Path.

See Section 3.1 Multirate CDR Functionality for more details.

6, 7 SDI1, SDI1 Input High-speed input for the channel 1 signal path.

8Ch1LOSDigital

Output

SFP+-compliant active-high digital output. Open-collector Loss-Of-Signal indicator for

the channel 1 signal path. Requires an external pull-up resistor.

When Ch1LOS is LOW, a valid channel 1 input signal has been detected.

When Ch1LOS is high-impedance, a valid channel 1 input signal has not been detected.

Configurable as LVTTL/LVCMOS-compliant output.

9Ch1LF Passive Loop filter capacitor connection for the channel 1 signal path.

10 Ch1VCOVEE Ground Ground for the channel 1 signal path VCO.

11 Ch1VCOFILT Passive Filter for the channel 1 signal path VCO supply.

12 Ch1VEE Ground Ground for the channel 1 signal path and output.

13 Ch1VCC Power Power supply for the channel 1 signal path and output.

14, 15 SDO1,

SDO1 Output High-speed differential output for the channel 1 signal path.

16 RESET Digital

Input

Digital active-low LVTTL/LVCMOS-compliant Schmitt-trigger input.

Device reset control pin.

Includes an internal pull-down resistor to hold the device in a reset state during

power-up, should this pin be externally disconnected.

17 Ch0VCC Power Power supply for the channel 0 signal path.

18 Ch0VEE Ground Ground for the channel 0 signal path.

19, 20 SDI0, SDI0 Input High-speed input for the channel 0 signal path.

21 Ch0VCOFILT Passive Filter for the channel 0 signal path VCO supply.

22 Ch0VCOVEE Ground Ground for the channel 0 signal path VCO.

23 Ch0LF Passive Loop filter capacitor connection for the Ch0 signal path.

24 GND Ground Connect to GND.

25 SDA

Digital

Input/

Output

Digital active-high serial data signal for the host interface.

Bi-directional, I2C-compliant, open-drain driver/receiver.

26 SCLDigital

Input Digital active-high clock input signal for the serial host interface.

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27 VREGPassive LDO regulator capacitor connection. (1.8V)

28 DIGVSS Ground Ground for low-speed digital I/O and internal logic.

29 RS0Digital

Input

Input Digital LVTTL/LVCMOS-compliant input.

Rate Select Input for the Ch0 Signal Path.

See Section 3.1 Multirate CDR Functionality for more details.

30, 31 SDO0,

SDO0 Output High-speed differential output for the channel 0 signal path.

32 Ch0FAULT Digital

Output

SFP+-compliant active-high digital output. Open-collector Ch0FAULT indicator. Requires

an external pull-up resistor.

When Ch0FAULT is LOW, the channel 0 path output is operating properly.

When Ch0FAULT is high-impedance, the device has detected a fault condition.

The Ch0FAULT is latched, and may be cleared via the host interface or by strobing the

Ch0DSBL pin.

Can be configured as a LVTTL/LVCMOS compatible output.

Table 1-1: Pin Descriptions (Continued)

Pin # Name Typ e Description

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2. Electrical Characteristics

2.1 Absolute Maximum Ratings

2.2 DC Electrical Characteristics

Parameter Value

Supply Voltage -0.5 to +3.8VDC

Input ESD Voltage2kV

Storage Temperature Range -50°C < TA < 125°C

Input Voltage Range (any input pin) -0.3 to 3.8VDC*

Solder Reflow Temperature 260°C

*NOTE: Stress above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only, and functional operation of the device at

these or any other conditions above those listed in the operational sections of this

specification is not applied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Table 2-1: DC Electrical Characteristics

VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.

Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s

Note: mApp refers to mA peak-to-peak value.

Parameter Conditions Symbol Min Typ Max Units Notes

Supply VoltageVCC 2.8 3.3 3.47 V —

Power — 600 800 mW 1, 2

Control Logic Input Specifications

Input Low VoltageVIL 0—0.4V—

Input High VoltageVIH 2.0 — VCC V—

Input Low Current VIL = 0V IIL — -100 — μA—

Input High Current VIH = 3.3V,

VCC = 3.3V IIH — 100 — μA—

Status Indicator Output Specifications

Indicator Output Logic

LOW ISINK(max) = 3mA VOL —0.20.4V—

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2.2.1 Power Features

Channel 0 Specifications

Input Termination (SDI0) Differential 80 100 120 Ω—

Output Termination (SDO0) — 50 — Ω—

Channel 1 Specifications

Input Termination

(Ch1SDIP/N) Differential 80 100 120 Ω—

Output Termination

(Ch1SDOP/N) Differential 80 100 120 Ω—

NOTES:

1. Typical Conditions: T = 25°C, V = 3.3V. Maximum Conditions: T = 100°C, V = 3.467V.

2. Each output terminated.

Table 2-1: DC Electrical Characteristics (Continued)

VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.

Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s

Note: mApp refers to mA peak-to-peak value.

Parameter Conditions Symbol Min Typ Max Units Notes

Table 2-2: Power Features

Configuration

Typi ca l

Baseline

Power

(mW)

Typi ca l

Incremental

Power

(mW)

Description Feature

Section

GX4002 Base 600

SDO1 Pre-emphasis = 3dB @ 600mVppd — 20 — 3.3.4

PRBS7 Generator — 115 Path for PRBS7 generator to

Ch1SDO is on. 3.6.1

PRBS7 Checker — 125 PRBS7 checker is on. 3.6.1

Diag + ADC— 14 Temperature, Supply Sensor, ADC. 3.7

Eye Monitor + ADC—50

All, Ch0 and Ch1 horizontal and

vertical eye monitors are on. 3.6.2

Ch0 EQ Boost — 0 — 3.2.1

GX4002 with Ch0 CDR bypassed and

powered-down —-90mW — —

GX4002 with Ch1 & Ch0 CDR bypassed and

powered-down —-185mW — —

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2.3 AC Electrical Characteristics

Table 2-3: AC Electrical Characteristics

VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.

Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s

Parameter Conditions Symbol Min Typ Max Units Notes

Data Rate

10G configuration 9.95 — 11.3 Gb/s 1

16GFC configuration — 14.025 — Gb/s 1

Channel 0 Specifications

Input Amplitude Range differential 120 — 850 mVppd —

LOS Threshold Level Setting

Range20 — 100 mVppd —

Equalization Gain — 6 — dB 6

Jitter Transfer Bandwidth

Setting RangePRBS31 data 1 — 23 MHz —

Total Output Jitter — 0.1 0.25 UIpp —

Ch0 CDR Lock Time 16G FC mode: loop

filter cap = 100nF ——0.5ms—

Ch0SDO Output Rise/Fall

Time (minimum) 20% - 80% tr, tf——20ps7

Ch0SDO Output Rise/Fall

Time (maximum) 20% - 80% tr, tf40 — — ps 8

Channel 1 Specifications

Input Sensitivity — — 10 mVppd —

Input Overload 1200 — — mVppd —

Limiting Amplifier

Equalization maximum EQ setting14 — — dB 2

Jitter Transfer Bandwidth

Setting Range1—23MHz—

Ch1SDO Output Total Jitter PRBS31 data TJ — 0.1 0.25 UIpp —

Ch1SDO Output Rise/Fall

time 20% - 80% tr, tf20 — — ps —

Ch1SDO Output AC

Common Mode Voltage——7.5mVrms3

Ch1LOS De-assert

Threshold Level Setting

Range

minimum

programmable

setting

— 5 — mVppd —

maximum

programmable

setting

— 400 — mVppd —

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Ch1LOS Threshold Level

Variation

1 sigma, IC to IC—1.50—mVrms—

over VCC Range—+

0.5 — dB —

over temperature

range -40°C to

+100°C

—+

0.5 — dB —

Ch1LOS Threshold Level

Hysteresis Setting Rangeelectrical 0 — 6 dB —

Ch1LOS Response Time 3 5 20 μs—

Ch1 CDR Lock Time 16G FC mode: loop

filter cap = 100nF ——0.5ms4

Differential Output Voltage

Setting Range

minimum swing

setting— 100 — mVppd —

maximum swing

setting— 850 — mVppd —

Output Pre-emphasis

Setting Rangemaximum setting3——dB5

NOTES:

1. See Table 3-1 for details.

2. At 7GHz.

3. 600mVppd swing.

4. For loop bandwidth = 13MHz (as detailed in Table 3-4).

5. 600mVppd swing.

6. At 7GHz (dielectric loss).

7. Reg89[7:0] = "11001000" = Reg110[7:0]. Reg90[1:0] = "00" = Reg111[7:0]. Reg102[1:0] = "00". Reg118[4:3] = "11" = Reg119[4:3].

Reg80[7:0] = "11101110". Reg81[4:0] = "11100" = Reg103[4:0]. Reg82[4:0] = "11010" = Reg104[4:0].

8. Reg89[7:0] = "11111111" = Reg110[7:0]. Reg90[1:0] = "11" = Reg111[7:0]. Reg102[1:0] = "00". Reg118[4:3] = "00" = Reg119[4:3].

Reg80[7:0] = "01000100". Reg81[4:0] = "01000" = Reg103[4:0]. Reg82[4:0] = "10000" = Reg104[4:0].

Table 2-3: AC Electrical Characteristics (Continued)

VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.

Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s

Parameter Conditions Symbol Min Typ Max Units Notes

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2.4 Required Initialization Settings

The GX4002 configuration registers must be set as described in Table 2-4 below to meet

the power specification listed in Table 2-1. The AC parametric specifications in Table 2-3

are also based on these settings:

Table 2-4: Required Initialization Settings

Name

Address

(decimal)

Parameter Name Bit

Position

New

Value

(binary)

Valid

Range

(decimal)

Function

CH1_REG17 64 CH1PWR1 4:0 10101 0-31 Channel 1 power control

CH1_REG18 65 CH1PWR2 6:5 10 0-3 Channel 1 power control

CH0_REG15 45 CH0PWR1 4:0 10101 0-31 Channel 0 power control

CH0_REG16 46 CH0PWR2 4:3 10 0-3 Channel 0 power control

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3. Detailed Description

3.1 Multirate CDR Functionality

There are two data rate ranges available for selection, so that a single part can be used

for multiple applications. The GX4002 does not require a reference clock. Some example

applications are as follows:

• 10Gb/s Ethernet (10.3Gb/s)

• 10Gb/s Ethernet with FEC (11.1Gb/s)

• 10G Fibre Channel (10.5Gb/s)

• 10G Fibre Channel with FEC (11.3Gb/s)

• Fibre Channel over Ethernet (10.3Gb/s)

• 16G Fibre Channel (14.025Gb/s)

3.1.1 Rate Selection and Rate Detection

The GX4002 has three different methods to select the data rate. The rate can be selected

through the use of the RS0/RS1 pins, through the use of registers, or through automatic

detection. The rate selection methods are described in more detail below.

The GX4002 also contains a set of data-dependent registers. This enables parameters

such as rise and fall times to be automatically configured based on the data rate. There

are two profiles, one for low data rates such as 4G or 8G Fibre Channel, and one for high

data rates such as 10GbE or 16G Fibre Channel. The register map (Appendix:

Configuration and Status Register Map) shows which registers contain both low data

rate and high data rate options.

A configuration profile is invoked by one of three methods:

1. Using input pins RS0 and RS1 to invoke a “hard” rate select for either the Ch0 path

or Ch1 path respectively (CH0PLLRATESELVAL is HIGH and/or

CH1PLLRATESELVAL is HIGH).

2. Using host interface commands to invoke a “soft” rate select for either the Ch1 or

Ch0 path, or for both Ch1 and Ch0 paths together using the CH1PLLRATESEL and

CH0PLLRATESEL bits (CH1PLLRATESELVAL is HIGH and/or

CH0PLLRATESELVAL is HIGH).

Table 3-1: Mode Details

Mode Description

10GThe part will retime in a continuous range from 9.95Gb/s to 11.3Gb/s.

14G

Through the serial interface, the part can be placed in 14G mode. In this

mode, the CDRs will retime at 14.025Gb/s, and is intended for use in 16G Fibre

Channel applications. An automatic rate detect circuit can be used that will

determine if the incoming data rate is a legacy Fibre Channel rate, and will

automatically bypass the CDRs. By using the automatic rate detect feature,

RS0 and RS1 pins are not required. The automatic rate detect feature is not

enabled by default when the device is configured in 14G mode.

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3. Using on-chip automatic rate detection circuitry to detect the new data rate, and to

invoke an internal rate select in either the Ch1 or Ch0 path independently. The

application is defined using the RATEDETFCGBEN bits (CH1PLLRATESELVAL is

LOW and/or CH0PLLRATESELVAL is LOW).

3.1.1.1 Hard Rate Select (Rate Select Pins)

The RS0 pin controls the rate-dependent profile of the Ch0 path, and the RS1 pin

controls the rate-dependent profile of the Ch1 path. The rate select valid bit,

CH0PLLRATESELVAL (or CH1PLLRATESELVAL), must be HIGH for RS0 (or RS1) to

control the rate.

When the RS0 (or RS1) pin is held LOW, the low-speed rate-dependent registers of the

channel 0 (or channel 1) path are active. When the RS0 (or RS1) pin is held HIGH, the

high-speed rate-dependent profile of the channel 0 (or channel 1) path is active. RS0 is

logically OR'ed with CH0PLLRATESEL, while RS1 is logically OR'ed with

CH1PLLRATESEL. Due to the OR'ing operation, when RS0 and RS1 are used for rate

control, CH0PLLRATESEL and CH1PLLRATESEL must be set LOW.

Rate

Selection

Method

Rate

Select

Valid

RS0/RS1

Pins

Rate

Select

Registers

Fibre

Channel/

Ethernet

Operation

Data Rate

Dependent

Hard Rate

SelectHIGH

LOW LOW Not

Applicable

The CDRs are placed in bypass

mode. Intended for 2G/4G/8G Fibre

Channel or 1GbE

Low Data Rate

Profile

HIGHNot

Applicable

Fibre

Channel

The CDR will lock to 14.025Gb/s

data

High Data Rate

Profile

Ethernet The CDR will lock to 9.95G to

11.3Gb/s data

High Data Rate

Profile

Soft Rate

SelectHIGH

Low or

High Z LOW Not

Applicable

The CDRs are place in bypass mode.

Intended for 2G/4G/8G Fibre

Channel or 1GbE

Low Data Rate

Profile

Not

Applicable High

Fibre

Channel

The CDR will lock to 14.025Gb/s

data

High Data Rate

Profile

Ethernet The CDR will lock to 9.95G to

11.3Gb/s data

High Data Rate

Profile

Automatic

Rate

Detect

LOW Not

Applicable

Not

Applicable

Fibre

Channel

If the input data is 14.025Gb/s, the

CDR will lock to it. Otherwise, the

CDRs are automatically bypassed

If 14.025Gb/s is

detected: High Data

Rate Profile

If 14.025Gb/s is not

detected: Low Data

Rate Profile

Ethernet

If the input data is 9.95G to 11.3G,

the CDR will lock to it. Otherwise,

the CDRs are automatically

bypassed

If 9.95G to 11.3Gb/s

is detected: High

Data Rate Profile

If 9.95G to 11.3Gb/s

is not detected: Low

Data Rate Profile

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3.1.1.2 Soft Rate Select

The CH1PLLRATESEL and CH0PLLRATESEL bits can be programmed to select a rate

profile using the host interface. Setting these parameters and their associated valid

parameters (CH1PLLRATESELVAL and CH0PLLRATESELVAL) override the on-chip

automatic rate detection circuitry. CH0PLLRATESEL is logically OR'd with the RS0 pin,

while CH1PLLRATESEL is logically OR'd with RS1, so RS0 and RS1 must be LOW or

hi-impedance for the PLLRATESEL bits to function properly.

The default setting is the high (10Gb/s or 14.025Gb/s) data-rate profile, with the on-chip

automatic rate detection circuitry overridden.

3.1.1.3 Automatic Rate Detection

In addition to the controls outlined in the preceding tables, the auto rate detection

circuitry has the following controls. To enable operation of the auto rate detection

function, CH0RATEDETEN (or CH1RATEDETEN) can be set HIGH.

If CH1RATEDETEN (or CH0RATEDETEN) is LOW, the CH1PLLRATESELVAL (or

CH0PLLRATESELVAL) bit must be HIGH, otherwise the device will be in an undefined

state.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0PLL_REG5

14 CH0PLLRATESEL 3:3 RW 1 0-1 Selects data rates:

0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.

14 CH0PLLRATESELVAL 4:4 RW 1 0-1 When HIGH, CH0PLLRATESEL or RS0 are

valid, otherwise they are ignored.

CH1PLL_REG5

24 CH1PLLRATESEL 3:3 RW 1 0-1 Selects data rates:

0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.

24 CH1PLLRATESELVAL 4:4 RW 1 0-1 When HIGH, CH1PLLRATESEL or RS1 are

valid, otherwise they are ignored.

Addressd Parameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0RDET_REG167

CH0RATEDETRESET 0 RW 0 0-1 When HIGH, the Ch0 path rate detector is

reset.

CH0RATEDETEN 1 RW 1 0-1 When HIGH, enables the rate detector.

CH0RDET_REG268CH0RATEDETRATEPER 3:0 RW 1000 0-15 Rate detector rate period (0.3µs to 13ms,

100µs default).

CH1RDET_REG172

CH1RATEDETRESET 0 RW 0 0-1 When HIGH, the Ch1 path rate detector is

reset.

CH1RATEDETEN 1 RW 1 0-1 When HIGH, enables the rate detector

CH1RDET_REG273CH1RATEDETRATEPER 3:0 RW 1000 0-15 Rate detector rate period (0.3µs to 13ms,

100µs default).

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CH0RATEDETPERIOD (address 68) and CH1RATEDETPERIOD (address 73) control the

frequency at which the automatic rate detection block checks the lock state of the PLL.

The recommended setting for shortest lock time is 1001b.

3.1.1.4 Application-Dependent Rate Select Profiles

The RATEDETFCGBEN and RATEDETFCGBENVAL bits indicate whether the

application traffic is running Fibre Channel, Ethernet or unspecified (for example: the

transceiver may be required to handle either Fibre Channel or Ethernet traffic in mission

mode). The default setting is Fibre Channel traffic.

3.1.2 Auto Retimer Bypass

The GX4002 supports an automatic rate detect feature for legacy Fibre Channel data

rates when configured in 16G mode. Upon enabling the automatic rate detect feature,

the device constantly monitors incoming data for a valid 14.025Gb/s data rate. If the

input data rate is a legacy Fibre Channel rate, the CDR is automatically bypassed.

While the automatic rate detect feature is enabled, and the CDR is in bypass mode, the

device continues monitoring the incoming data rate. If the data rate changes to

14.025Gb/s, the CDR goes back into retimed mode.

The auto retimer bypass feature also applies to Ethernet mode.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0RDET_REG167

RATEDETFCGBEN 2:2 RW 1 0-1

When HIGH, the application is Fibre

Channel. When LOW, the application is

Ethernet.

RATEDETFCGBENVAL 3:3 RW 1 0-1 When HIGH, indicates that RATEDETFCGBEN

is valid. When LOW, it is ignored.

Table 3-2: Summary of Rate Selection and Rate Detection Control

CH1PLLRATESELVAL

CH0PLLRATESELVAL RATEDETFCGBENVAL Data Rate Configuration Profile

0 0 Undefined Undefined

0 1 Auto Rate DetectProfile selected based on

detected rate

1 0 Auto Rate DetectProfile selected by hard or soft

rate select

Fixed rate determined by the

combination of

RATEDETFCGBEN and rate

select (hard or soft)

Profile selected by hard or soft

rate select

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The following registers enable and configure the automatic rate detect feature:

The device can be configured to manually bypass each of the Ch1 and Ch0 CDRs

through the CH0PLLBYPASS and CH1PLLBYPASS controls when the automatic bypass

is disabled.

3.2 Channel 0 Path (Ch0)

The channel 0 path is comprised of a trace equalizer, a multi-rate CDR and an output

driver.

Figure 3-1: Channel 0 Path

3.2.1 Ch0 Equalization

The channel 0 path input has an equalizer with 6dB gain at 7GHz. The equalizer can be

bypassed through the following register:

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0PLL_REG514

CH0PLLBYPASS 1:1 RW 0 0-1 When HIGH, forces CDR into bypass mode.

CH0PLLAUTOBYPASSEN 2:2 RW 1 0-1 When HIGH, enables automatic bypass

mode for the Ch0 CDR.

CH0RDET_REG167

CH0RATEDETRESET 0:0 RW 0 0-1 When HIGH, resets the Ch0 path rate

detector.

CH0RATEDETEN 1:1 RW 1 0-1 When HIGH, enables the Ch0 path

automatic rate detector.

CH1RDET_REG172

CH1RATEDETRESET 0:0 RW 0 0-1 When HIGH, resets the Ch1 path rate

detector.

CH1RATEDETEN 1:1 RW 1 0-1 When HIGH, enables the Ch1 path

automatic rate detector.

EQ CDR DR

Input

Ch0 Disable

Output

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0_REG333 CH0EQBOOST0:0RW10-1

When HIGH, applies a fixed CH0 EQ boost of

6dB. 0dB if LOW.

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3.2.2 Ch0 PLL Variable Loop Bandwidth

The loop bandwidth of the channel 0 Phase Locked Loop (PLL) can be varied through the

digital control interface. The loop bandwidths are individually controlled, and can cover

the range of 1MHz to 23MHz through following five-bit registers (recommended settings

are shown):

The temperature coefficient of the loop bandwidth can be adjusted by weighted

summation of CH0PLLLBWCURVT, which has a positive temperature coefficient and

CH0PLLLBWCURVBE, which has a negative temperature coefficient. The default reset

values of the registers above produce an approximate loop bandwidth of 7MHz.

3.2.3 Channel 0 Output Polarity Invert

The channel 0 output polarity can be inverted through the following register:

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0PLL_REG110 CH0PLLLBWCURVT 4:0 RW 10011 0-31 Adjusts LBW positive temperature

coefficient control.

CH0PLL_REG211CH0PLLLBWCURVBE 4:0 RW 01110 0-31 Adjusts LBW negative temperature

coefficient control.

CH0PLL_REG918 CH0PLLLBWMULT 1:0 RW 10 0-3 LBW multiplier;

00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67

Table 3-3: Typical Loop Bandwidths for Various Register Settings

CH0PLLLBWMULT CH0PLLLBWCURVT CH0PLLLBWCURVBE Loop

Bandwidth

00 10011 01110 4.6MHz

10 (default) 10011 01110 7.3MHz

01 10011 01110 9.9MHz

10 11111 10110 13MHz

11 11000 11000 22.7MHz

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0PLL_REG514 CH0PLLPOLINV 0:0 RW 0 0-1 When HIGH, inverts the Ch0 data path

polarity.

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3.3 Channel 1 Path (Ch1)

The GX4002 channel 1 path contains a high-sensitivity limiting amplifier with optional

equalization, a multi-rate CDR, and a pre-emphasis driver.

Figure 3-2: Channel 1 Path

3.3.1 Integrated Limiting Amplifier

The GX4002 has an integrated Limiting Amplifier (LA), with better than 10mV

sensitivity. Optional equalization is available on the limiting amplifier input.

3.3.2 Ch1 Equalization

The channel 1 input implements an equalizer that provides peaking at 7GHz. This

feature allows for optimal performance with extended reach connections.

The equalizer implements 0dB to 14dB of high-frequency boost in fifteen steps, while

achieving optimal receive sensitivity at any given equalization setting. The equalization

setting is set through the CH1LABOOST control.

Output

Input DRCDRLA

Ch1 LOS

Chip Control & Status

I C

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1_REG148 CH1LABOOST 3:0 RW 0000 0-15 0: 0dB to 15: 14dB.

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When the equalization setting is 0dB, the equalization function is bypassed and the

receive sensitivity performance is the same as that of a limiting amplifier.

Figure 3-3: Channel 1 Equalization

3.3.3 Ch1 PLL Variable Loop Bandwidth

The loop bandwidth of the channel 1 Phase Locked Loops (PLLs) can be varied through

the digital control interface. The loop bandwidths are individually controlled, and can

cover a range of 1MHz to 23MHz through the following 5-bit registers:

The temperature coefficient of the loop bandwidth can be adjusted by a weighted

summation of CH1PLLLBWCURVT, which has a positive temperature coefficient, and

CH1PLLLBWCURVBE, which has a negative temperature coefficient. The default reset

values of the above registers produce an approximate loop bandwidth of 7MHz.

7GHz

14dB

Boost

8dB

-6dB

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1PLL_REG120 CH1PLLLBWCURVT 4:0 RW 10011 0-31 Adjusts LBW positive temperature

coefficient control.

CH1PLL_REG221CH1PLLLBWCURVBE 4:0 RW 01110 0-31 Adjusts LBW negative temperature

coefficient control.

CH1PLL_REG928 CH1PLLLBWMULT 7:6 RW 10 0-3 LBW multiplier;

00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67

Table 3-4: Typical Loop Bandwidths for Various Register Settings

CH1PLLLBWMULT CH1PLLLBWCURVT CH1PLLLBWCURVBE Loop

Bandwidth

00 10011 01110 4.6MHz

10 (default) 10011 01110 7.3MHz

01 10011 01110 9.9MHz

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3.3.4 Pre-Emphasis Driver with Auto-Mute

The channel 1 driver is a pre-emphasis driver that can be used to compensate for losses

in the connector and trace between the module and ASIC. The pre-emphasis can

compensate for up to 6dB of loss. The output swing can be set from 100mV to 800mV in

steps of 50mV through the CH1SDOSWING[3:0] register. The pre-emphasis amplitude

can be varied from 0dB to 6dB in eight non-linear steps through CH1SDOPECTRL[4:2].

Figure 3-4: Pre-Emphasis Waveform Description

Figure 3-4 above shows the pre-emphasis waveform. Amplitudes V1, V2 and

pre-emphasis in dB are defined as follows:

10 11111 10110 13MHz

11 11000 11000 22.7MHz

Table 3-4: Typical Loop Bandwidths for Various Register Settings (Continued)

CH1PLLLBWMULT CH1PLLLBWCURVT CH1PLLLBWCURVBE Loop

Bandwidth

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1SDO_REG177 CH1SDOSWING3:0 RW 1010 0-15 Driver swing.

0-15: 100-850mVppd, Default = 10: 600mV

CH1SDO_REG278 CH1SDOPECTRL 4:2 RW 000 0-7 Pre-emphasis amplitude.

0: 0dB, 7: 6dB for 200mVppd swing.

Ch1 signal after Pre-emphasis

Volts

0.6

0.4

0.2

0.0

-0.6

-0.4

-0.2

268269 270 271 272 273 274 275

-V1

-V2

11110000 pattern

Pre-emphasis

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V1, V2 and Pre-emphasis are defined as follows:

V1 which represents the “peak”

V2 which represents DC or Steady State

Pre-emphasis [dB] = 20 x log(V1/V2)

The amount of pre-emphasis varies with CH1SDOSWING as shown in Table 3-5:

The output can be configured to automatically mute if Ch1 LOS is detected through the

following registers. When muted, the output driver remains powered-up, and the output

common mode is maintained. The output driver can be configured to power-down

when muted by setting the CH1SDOPWRDNONMUTE bit:

3.3.5 Channel 1 Output Polarity Invert

The channel 1 output polarity can be inverted through the following register:

Table 3-5: Pre-Emphasis vs. Ch1 SDO Swing

CH1SDOSWING CH1SDOPECTRL Pre-emphasis

0010 (200mV) 001 2.3dB

0101 (350mV) 001 1.8dB

1010 (600mV) 001 1.0dB

0010 (200mV) 011 4.7dB

0101 (350mV) 011 3.8dB

1010 (600mV) 011 3.1dB

0010 (200mV) 111 6.2dB

0101 (350mV) 111 5.5dB

1010 (600mV) 111 3.4dB

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1SDO_REG379

CH1SDOMUTE 5:5 RW 0 0-1

When HIGH, mutes driver and maintains

output common mode when not in auto

mute mode.

CH1SDOAUTOMUTEEN 6:6 RW 1 0-1 When HIGH, enables muting the driver

upon LOS. LOW disables muting.

CH1SDOPWRDNONMUTE 7:7 RW 1 0-1

When HIGH, enables power-down on mute

for output stage. LOW disables

power-down.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1PLL_REG524 CH1PLLPOLINV 0:0 RW 0 0-1 When HIGH, inverts the Ch1 data path

polarity.

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3.4 Crosspoint

The GX4002 provides eight different crosspoint paths, as shown in Table 3-6. The blocks

referenced in the different crosspoint paths are shown in Figure 3-5.

Figure 3-5: Crosspoint Block Diagram

When the crosspoint is enabled, the standard data path is not interrupted. For example:

in Mode 1, the input to SDI1 will also be accessible at SDO1. When using crosspoint

modes, the automute feature for SDO1 or SDO0 may have to be disabled if the

corresponding SDI1 or SDI0 inputs are unused.

The relevant parameters in these registers and their values required to enable each of

the crosspoint options indicated above, are shown in Table 3-7.

The selection of a crosspoint path impacts the following feature:

• Polarity inversion

Table 3-7 also captures the impact on these features in each crosspoint mode.

LA Ch1 CDR

Ch0 CDR DR

SDI0 SDO0

SDO1

SDI1

Table 3-6: Crosspoint Paths

Mode Crosspoint Path Reference

1SDI1 =>LA=>DR=>SDO0 Figure 3-6

2SDI1 =>LA=>CH1CDR=>DR=>SDO0 Figure 3-6

3SDI1 =>LA=>CH0CDR=>DR=>SDO0 Figure 3-7

4SDI1 =>LA=>CH1CDR=>CH0CDR=>DR=>SDO0 Figure 3-7

5SDI0=>EQ=>DR=>SDO1 Figure 3-8

6SDI0=>EQ=>CH0CDR=>DR=>SDO1 Figure 3-8

7SDI0=>EQ=>CH1CDR=>DR=>SDO1 Figure 3-9

8SDI0=>EQ=>CH0CDR=>CH1CDR=>DR=>SDO1 Figure 3-9

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Table 3-7: Crosspoint Options

Crosspoint Mode

(see Table 3-6)

LBCH1INEN

LBCH1INPRBSGEN

LBCH1INCH0DATA

LBCH1OUTEN

LBCH1OUTCH0DATA

LBCh1OutPRBSGen

LBCH1OUTCH1CLK

CH1PLLBYPASS

LBCH0INEN

LBCH0INPRBSGEN

LBCH0INCH1DATA

LBCH0OUTEN

LBCH0OUTCH1DATA

LBCH0OUTPRBSGEN

LBCH0OUTCH0CLK

CH0PLLBYPASS

CH0PLLPOLINV Effective

1 0000000100011000YN

2 0000000000011000YN

3 0000000110100000YN

4 0000000010100000YN

5 0001100000000001NY

6 0001100000000000NY

7 1010000000000001NY

8 1010000000000000NY

Control

Address

777777724 8 8 8 8 8 8 8 14 — —

Associated

Bit

Slice

0 1 2 4 5 6 7 1 0 1 2 4 5 6 7 1 — —

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Figure 3-6: Crosspoint Modes 1 & 2

Figure 3-7: Crosspoint Modes 3 & 4

Ch1 LA

Ch0 EQ

SDI1

SDO0

SDI0

Ch0Clk

Ch1Clk

Mode 1: SDI1 => LA => LD => SDO0

Mode 2: SDI1 => LA => Ch1 CDR => LD => SDO0

CH1PLLBYPASS = 1 (Mode 1)

CH1PLLBYPASS = 0 (Mode 2)

LBCH1INEN = 0

LBCH0OUTCH1DATA = 1

LBCH0OUTEN = 1

CH0PLLPOLINV

SDO1

PRBS 7

Generator

PRBS 7

Checker

VEye

Monitor

Peak

Detector

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

HEye Monitor

Ch0 Driver

Ch1 Driver

Recovered

Clock

Ch1 CDR (10G/14G)

Input

Data

Retimed

Data

Peak

Detector

VEye

Monitor

Standard data path:

can be enabled in crosspoint mode

Ch1 LA

Ch0 EQ

SDI1

SDI0

Ch0Clk

Ch1Clk

Mode 3: SDI1 => LA => Ch0 CDR => LD => SDO0

Mode 4: SDI1 => LA => Ch1 CDR => Ch0 CDR => LD => SDO0

CH1PLLBYPASS = 1 (Mode 3)

CH1PLLBYPASS = 0 (Mode 4)

LBCH1INEN = 0

LBCH0INEN = 1

CH0PLLBYPASS = 0

LBCH0INCH1DATA = 1

Ch0 Driver

SDO0

LBCH0OUTEN = 0

CHPLLPOLINV

SDO1

PRBS 7

Generator

PRBS 7

Checker

VEye

Monitor

Peak

Detector

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

HEye Monitor

Recovered

Clock

Ch1 CDR (10G/14G)

Input

Data

Retimed

Data

Peak

Detector

VEye

Monitor

Ch1 Driver

Standard data path:

can be enabled in crosspoint mode

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Figure 3-8: Crosspoint Modes 5 & 6

Figure 3-9: Crosspoint Modes 7 & 8

Ch1 LA

Ch0 EQ

SDI1

SDI0

Ch0Clk

Ch1Clk

Mode 5: SDI0 => EQ => DR => SDO1

Mode 6: SDI0 => EQ => Ch0 CDR => DR => SDO1

LBCH0INEN = 0

CH0PLLBYPASS = 1 (MODE 5)

CH0PLLBYPASS = 0 (MODE 6)

LBCH1OUTCH0DATA = 1

Ch0 Driver

SDO0

Ch1 Driver SDO1

CH1PLLPOLINV

LBCH1OUTEN = 1

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

HEye Monitor

Recovered

Clock

Ch1 CDR (10G/14G)

Input

Data

Retimed

Data

VEye

Monitor

Peak

Detector

VEye

Monitor

Peak

Detector

PRBS 7

Generator

PRBS 7

Checker

Standard data path:

can be enabled in crosspoint mode

Ch1 LA

Ch0 EQ

PRBS 7

Generator

PRBS 7

Checker

SDI1

SDI0

VEye

Monitor

Peak

Detector

Ch0 Clk

Ch1 Clk

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

HEye Monitor

Mode 7: SDI0 => EQ => Ch1 CDR => DR => SDO1

Mode 8: SDI0 => EQ => Ch0 CDR = > Ch1 CDR => DR => SDO1

CH1PLLBYPASS = 0

LBCH1INEN = 1

LBCH0INEN = 0

CH0PLLBYPASS = 1 (MODE 7)

CH0PLLBYPASS = 0 (MODE 8)

LBCH1INCH0DATA = 1

Ch0 Driver

SDO0 1

Ch1 Driver SDO1

CH1PLLPOLINV

LBCH1OUTEN = 0

Recovered

Clock

Ch1 CDR (10G/14G)

Input

Data

Retimed

Data

Peak

Detector

VEye

Monitor

Standard data path:

can be enabled in crosspoint mode

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3.5 Status Indicators

The GX4002 supports three status indicators: Loss of Signal (LOS), Loss of Lock (LOL) and

Channel 0 Fault (Ch0FAULT). LOS and LOL indicators are available on both the Ch1 and

the Ch0 paths.

3.5.1 Ch0 Loss Of Signal (LOS)

The Ch0 LOS indicator status is available through a register. If desired, its status can be

included in the generation of the Ch0FAULT output pin. The LOS assert threshold can be

set from 20mV to 100mV in <1mV steps. In addition, the temperature coefficient of the

LOS threshold can be adjusted to ensure consistent LOS operation over temperature.

The LOS also has hysteresis that is programmable from 0dB to 6dB in steps of 0.5dB.

The following registers are used to control the Ch0 LOS feature:

3.5.1.1 Ch0 LOS Threshold

Figure 3-10 and Figure 3-11 show the typical recommended range of Ch0 LOS assert

thresholds and corresponding CH0LOSTHNEG[7:0] setting to achieve these thresholds.

It is recommended to keep CH0LOSPOS[7:0] = 0 to achieve a flat temperature

coefficient for LOS threshold. The Ch0 LOS de-assert thresholds are the same as the Ch0

LOS assert thresholds for a hysteresis setting of 0.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0_REG939 CH0LOSTHNEG7:0 RW 01010011 0-255 Negative temperature coefficient LOS

threshold setting.

CH0_REG10 40 CH0LOSTHPOS7:0 RW 00000000 0-255 Positive temperature coefficient LOS

threshold setting.

CH0_REG11 41 CH0LOSHYS3:0 RW 1001 0-15 Sets LOS hysteresis from 0dB to 6dB in steps

of 0.5dB.

CH0_REG12 42

CH0LOSSOFTASSERT 3:3 RW 0 0-1

When HIGH, asserts LOS for internal

functions, asserts LOS register (CH0PLLLOS)

and asserts external indication through

Ch0FAULT.

CH0LOSSOFTASSERTEN 4:4 RW 0 0-1 When HIGH, LOS is controlled by

CH0LOSSOFTASSERT.

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Figure 3-10: Ch0 LOS Assert Threshold – Typical

Figure 3-11: Ch0 LOS De-Assert Threshold – Typical

The LOS threshold will have a slight dependence on data rate.

3.5.1.2 Manual LOS Assert

The on-chip LOS circuit can be bypassed, and LOS asserted, through the host interface.

This operation is initiated when CH0LOSSOFTASSERTEN is HIGH. The state of

CH0LOSSOFTASSERT then controls the LOS register CH0PLLLOS and external

indication through Ch0FAULT.

100

120

140

160

0 50 100 150 200 250 300

CH0LOSTHNEG

Assert Threshold (mVppd)

Hys = 0 Hys = 9 Hys = 15

0dB

3dB

6dB

100

120

140

160

0 50 100 150 200

CH0LOSTHNEG

De-Assert Threshold (mVppd)

Hys = 0 Hys = 9

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0_REG12 61

CH0LOSSOFTASSERT 3:3 RW 0 0-1

When HIGH, asserts LOS.

CH0LOSSOFTASSERTEN must be HIGH to use

this bit.

CH0LOSSOFTASSERTEN 4:4 RW 0 0-1 When HIGH, LOS is controlled by

CH0LOSSOFTASSERT.

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3.5.2 Ch1 Loss Of Signal

The Ch1 Loss Of Signal (LOS) indicator status is available through a register and the

Ch1LOS pin. The Ch1LOS pin is by default open-drain, active-high. However, the pin

can be configured in a LVCMOS/LVTTL compatible mode by setting

OPENDRAINCH1LOS to 0. In addition, Ch1LOS can be configured to be active-low by

setting POLINVCH1LOS HIGH. The status of Ch1LOS can be read out through

CH1PLLLOS.

The LOS assert threshold can be set from 5mV to 400mV in three distinct ranges. The LOS

assert threshold is a function of the CH1LABOOST setting. Figure 3-8 describes the

selection of CH1LOSRANGE based on the required LOS assert threshold and

CH1LABOOST settings.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

TOP_REG22

POLINVCH1LOS1:1 RW 0 0-1 When HIGH, inverts polarity of Ch1LOS

output.

OPENDRAINCH1LOS2:2 RW 1 0-1 When HIGH, makes Ch1LOS output driver

open-drain.

CH1PLL_REG10 29 CH1PLLLOS0:0 RO 0 0-1 Ch1 CDR loss of signal when HIGH.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1_REG14 61 CH1LOSRANGE2:0RW0010-7

1:0 - LOS range 0: highest - 3: lowest, 2

(MSB) unused.

Table 3-8: LOS Assert Ranges

CH1LABOOST

[3:0]

LOS Assert Threshold Range CH1LOSRANGE

[1:0]

Resolution

(controlled by

CH1LOSTHNEG/POS)

Unit

Min Max

5 400 LOS Threshold -

Total Range—mVppd

0-7 — — 11 - Unused — —

0-7 5 30 10 - Low Range <0.1mV mVppd

0-7 30 100 01 - Mid Range <1.0mV mVppd

0-7 100 400 00 - High Range <2.0mV mVppd

8-15 5 30 11 - Low Range <0.1mV mVppd

8-15 30 100 10 - Mid Range <1.0mV mVppd

8-15 — — 01 - Unused — —

8-15 100 400 00 - High Range <2.0mV mVppd

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3.5.2.1 Ch1 LOS Threshold

The LOS assert threshold is set using the following registers. Apart from setting the assert

thresholds, these registers also set the temperature coefficient. Through weighted

summing of the CH1LOSTHNEG[7:0] and CH1LOSTHPOS[7:0] values, a range of

temperature coefficients can be achieved to ensure consistent LOS operation over

temperature:

Figure 3-12 to Figure 3-15 show the typical recommended range of CH1LOSASSERT

thresholds and corresponding CH1LOSTHNEG[7:0] setting to achieve these thresholds.

It is recommended to keep CH1LOSPOS[7:0] = 0. The CH1LOSDEASSERT thresholds

are the same as the CH1LOSASSERT thresholds for a hysteresis setting of 0.

Figure 3-12: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 0)

Figure 3-13: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 1)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1_REG956 CH1LOSTHNEG7:0 RW 10000011 0-255 Negative temperature coefficient LOS

threshold setting.

CH1_REG10 57 CH1LOSTHPOS7:0 RW 00010001 0-255 Positive temperature coefficient LOS

threshold setting.

100

200

300

400

500

600

700

0 50 100 150 200 250 300

CH1LOSTHNEG

LOS Assert Voltage (mVppd)

CH1LOSHYS = 0 CH1LOSHYS = 9 CH1LOSHYS = 15

3.5dB

6dB

0dB

100

120

140

160

0 50 100 150 200 250 300

CH1LOSTHNEG

LOS Assert Voltage (mVppd)

CH1LOSHYS = 0 CH1LOSHYS = 9 CH1LOSHYS = 15

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Figure 3-14: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 2)

Figure 3-15: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 3)

3.5.2.2 Ch1 LOS Hysteresis

The LOS detector supports programmable hysteresis ranging from 0dB to 6dB,

adjustable in steps of less than 0.5dB. The following register can be used to program the

hysteresis. Note that the effective hysteresis is somewhat dependent on the threshold

value:

0 50 100 150 200 250 300

CH1LOSTHNEG

LOS Assert Voltage (mVppd)

CH1LOSHYS = 0 CH1LOSHYS = 9 CH1LOSHYS = 15

0 50 100 150 200 250 300

CH1LOSTHNEG

LOS Assert Voltage (mVppd)

CH1LOSHYS = 0 CH1LOSHYS = 9 CH1LOSHYS = 15

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1_REG13 60 CH1LOSHYS3:0 RW 1001 0-15 Sets LOS hysteresis from 0dB to 6dB in steps

of 0.5dB.

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Hysteresis control only affects the assert threshold. The LOS de-assert threshold is set by

CH1LOSTHNEG and CH1LOSTHPOS controls only. Figure 3-16 shows the hysteresis

characteristics and the impact of CH1LOSHYS[3:0]:

Figure 3-16: Ch1 LOS Hysteresis

3.5.2.3 Manual LOS Assert

The on-chip LOS circuit can be bypassed, and LOS asserted, through the host interface.

This operation is initiated when CH1LOSSOFTASSERTEN is HIGH. The state of

CH1LOSSOFTASSERT then controls the LOS register CH1PLLLOS and external

indication through Ch1LOS.

3.5.3 Loss Of Lock (LOL)

The channel 0 and channel 1 LOL status indicators are both available in registers as

shown below:

Vin (mVppd)

LOS O/P

LOS Asserted

LOS Assert

Threshold

LOS De-assert

Threshold

6.715

5.413

4.812

4.411

3.910

3.49

3.08

2.57

2.16

1.85

1.44

1.13

0.72

0.31

0.10

Hys (dB)CH1LOSHYS

CH1LOSTHNEG

(for fixed Vin)

LOS Assert

Threshold

LOS De-asserted

LOS O/P

LOS Asserted

LOS De-assertedLOS De-assert

Threshold

Hys (dB) = 20*log10(Vth_assert/Vth_deassert)

CH1LOSHYS 15 to 0

The LOS de-assert

threshold stays constant,

and only the LOS assert

threshold level varies with

the hysteresis setting,

CH1LOSHYS.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH1_REG14 61

CH1LOSSOFTASSERT 6:6 RW 0 0-1

When HIGH, asserts LOS.

CH1LOSSOFTASSERTEN must be HIGH to use

this bit.

CH1LOSSOFTASSERTEN 7:7 RW 0 0-1 When HIGH, LOS is controlled by

CH1LOSSOFTASSERT.

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3.5.4 Ch0FAULT - Channel 0 Fault

Various status indicator pins are combined to generate a single Ch0FAULT indicator

output. The Ch0FAULT output is, by default, an open-drain output. It can be configured

in a LVCMOS/LVTTL compliant mode through register 2, bit 3

(OPENDRAINCH0FAULT). When set LOW, the Ch0FAULT output is configured as

LVCMOS/LVTTL compatible output.

The Ch0FAULT output is active-high by default. Its polarity can be changed to make it

active-low through register 2, bit 0 (POLINVCH0FAULT). When set HIGH, Ch0FAULT is

configured as an active-low output.

The following status indicator controls can be combined to generate the Ch0FAULT

output. Each of the indicators can be independently masked through the register

controls. By default, the Ch0FAULT output combines (ORs) the status of all indicators.

The following registers control the masking of the various indicators for Ch0FAULT and

the configuration of Ch0FAULT pin.

3.6 Test Features

The GX4002 contains built-in test features that can be used during module test, mission

mode, or system testing.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0PLL_REG10 19 CH0PLLLOL 1:1 RO 0 0-1 Ch0 CDR loss of lock when HIGH.

CH1PLL_REG10 29 CH1PLLLOL 1:1 RO 0 0-1 Ch1 CDR loss of lock when HIGH.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

TOP_REG11

FAULTMASKCH1LOS0:0 RW 1 0-1 When HIGH, masks out Ch1LOS from

asserting CH0FAULT.

FAULTMASKCH1LOL 1:1 RW 1 0-1 When HIGH, masks Ch1LOL from asserting

Ch0FAULT.

FAULTMASKCH0LOS2:2 RW 1 0-1 When HIGH, masks outCh0LOS from

asserting CH0FAULT.

FAULTMASKCH0LOL 3:3 RW 1 0-1 When HIGH, masks Ch0LOL from asserting

Ch0FAULT.

FAULTMASKCH0FAULT 4:4 RW 0 0-1 When HIGH, masks out Ch0Fault from

asserting CH0FAULT.

TOP_REG22

POLINVCH0FAULT 0:0 RW 0 0-1 When HIGH, inverts polarity of CH0FAULT

output.

OPENDRAINCH0FAULT 3:3 RW 1 0-1 When HIGH, makes CH0FAULT output driver

open drain.

NOTE: To support system diagnostics, a manual Ch0FAULT assert feature is available through the following register:

TOP_REG4 4 FORCECH0FAULT 4:4 RW 0 0-1 When HIGH, asserts CH0FAULT.

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3.6.1 PRBS Generator and Checker

The GX4002 has a built in PRBS7 generator and checker. The generator and checker are

disabled by default to save power, and can be enabled through the digital control

interface. There are multiple ways to use the PRBS generator/checker, as shown in

Table 3-9 below:

Figure 3-17: PRBS Generator on Ch1 Output and PRBS Check Monitoring Ch0 Input

Table 3-9: PRBS Generator/Checker Modes of Operation

Mode Description

Lock to data pattern on Ch1 input

A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch1 path

input. A PRBS7 pattern can be viewed at the Ch1 path output, or can be looped back to the

Ch0 side to use the PRBS checker.

Lock to data pattern on Ch0 input

A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch0 path

input. A PRBS7 pattern can be viewed at the Ch0 path output, or can be looped back to the

Ch1 side to use the PRBS checker.

Lock to low-speed reference on

Ch1 input

A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch1 input. A PRBS7

pattern can be viewed at the Ch1 path output, or can be looped back to the Ch0 side to use

the PRBS checker. This mode can be used when testing a module so that high-speed test

equipment is not required. See Figure 3-17.

Lock to low-speed reference on

Ch0 input

A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch0 input. A PRBS7

pattern can be viewed at the Ch0 path output, or can be looped back to the Ch1 side to use

the PRBS checker. This mode can be used when testing a module so that high-speed test

equipment is not required. See Figure 3-18.

Ch1 LA

Ch1 Driver

Ch0 EQ

Ch0 Driver

PRBS 7

Generator

PRBS 7

Checker

SDI1

SDO1

SDO0

SDI0

VEye

Monitor

Peak

Detector

Ch0Clk

Ch1Clk

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

VEye

Monitor

Peak

Detector

HEye Monitor

PRBSGENCLKSEL = 0

PRBSCHKCLKSEL = 1

High-speed Data

High-speed Clock

External

Loopback

Low-speed Reference

LBCH1INEN = 0

LBCH0INEN = 0

CH0PLLBYPASS = 0

CH1PLLPOLINV

LBCH1OUTEN = 1

LBCH1OUTPRBSGEN = 1

PRBS Out

CH0PLLPOLINV

LBCH0OUTEN = 0

Input

Data

Retimed

Data

Recovered

Clock

HEye Monitor

Ch1 CDR (10G/14G)

fclk/8 (14G)

fclk/4 (10G)

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Figure 3-18: PRBS Generator on Ch0 Output and PRBS Check Monitoring Ch1 Input

The following registers enable and configure the PRBS generator and checker:

Ch1 LA

Ch1 Drv

Ch0 EQ

Ch0 Driver

PRBS 7

Generator

PRBS 7

Checker

SDI1

SDO1

SDO0

SDI0

VEye

Monitor

Peak

Detector

Ch0Clk

Ch1Clk

Ch0 CDR (10G/14G)

Input

Data

Retimed

Data

Recovered

Clock

VEye

Monitor

Peak

Detector

HEye Monitor

High-speed Data

High-speed Clock

Low-speed Reference

fclk/8 (14G)

fclk/4 (10G)

External

Loopback

PRBSCHKCLKSEL = 0

PRBSGENCLKSEL = 1

LBCH1INEN = 0

LBCH0INEN = 0

CH1PLLBYPASS = 0

CH0PLLPOLINV

LBCH0OUTEN = 1 LBCH0OUTPRBSGEN

= 1

CH1PLLPOLINV

LBCH1OUTEN = 0

PRBS Out

Recovered

Clock

Retimed

Data

Input

Data

HEye Monitor

Ch1 CDR (10G/14G)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

TOP_REG33

PRBSGENSTART 0:0 RW 0 0-1 When pulsed HIGH and LOW, starts off the

PRBS generator.

PRBSCHKCLEARERR 1:1 RW 0 0-1 When HIGH, clears the latched error flag

from checker.

TOP_REG66PRBSCHKSTATUS0:0 RO 0 0-1 When HIGH, checker detected an error.

LOOPBK_REG17

LBCH1INPRBSGEN 1:1 RW 0 0-1 Selects PRBS generator output into Ch1

CDR.

LBCH1OUTPRBSGEN 6:6 RW 0 0-1 Selects PRBS generator output into Ch1

Driver.

LOOPBK_REG28

LBCH0INPRBSGEN 1:1 RW 0 0-1 Selects PRBS generator output into Ch0

CDR.

LBCH0OUTPRBSGEN 6:6 RW 0 0-1 Selects PRBS generator output into Ch0

Driver.

LOOPBK_REG39

PRBSGENCLKSEL 0:0 RW 0 0-1 When HIGH, selects Ch0 recovered clock.

LOW selects Ch1 clock.

PRBSCHKCLKSEL 1:1 RW 0 0-1 When HIGH, selects Ch0 recovered clock.

LOW selects Ch1 clock.

PWRDN_REG2 161

PDPRBSGEN 1:1 RW 1 0-1 When HIGH, power-down the PRBS

generator and associated buffers.

PDPRBSCHK 2:2 RW 1 0-1 When HIGH, power-down the PRBS

generator and associated checkers.

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To ensure proper operation of the PRBS7 generator, PRBSGENSTART needs to be set

HIGH and then LOW once after the generator is powered-up through PDPRBSGEN.

To ensure proper operation of the PRBS7 checker, PRBSCHKCLEARERR needs to be set

HIGH and then LOW after application of valid PRBS7 pattern to clear any spurious

errors. PRBSCHKSTATUS, may be polled to check for errors flagged by the checker.

The PRBS generator can be configured to apply the PRBS7 pattern to SDO1 or SDO0 or

internally. Apply to either the Ch1 or the Ch0 CDR for retiming before transmitting out

through SDO. Controls LBCH1INPRBSGEN, LBCH1OUTPRBSGEN,

LBCH0INPRBSGEN and LBCH0OUTPRBSGEN determine the path of the PRBS pattern.

Both PRBS generator and checker can be clocked off either the Ch0 or Ch1 recovered

clocks independently through controls PRBSGENCLKSEL and PRBSCHKCLKSEL. The

PRBS checker automatically selects retimed data from the CDR which is chosen to

provide its clock through PRBSCHKCLKSEL.

3.6.2 Eye Monitor & Peak Detector

The GX4002 has built-in eye monitors in both the horizontal and vertical direction for

the inner eye. These eye monitors are available for both Ch1 and Ch0 paths. In addition,

both Ch1 and Ch0 inputs have peak detectors available to provide outer eye

information. The information from these monitors can be used to indicate if the input to

the module has degraded. These features can be used during mission mode.

Figure 3-19 shows where the eye monitoring functions are implemented:

Figure 3-19: Eye Monitor Implementation

The vertical eye monitor outputs a value proportional to the inner eye opening. The

output of the eye monitor can be sampled and read out digitally through the ADC (see

Section 3.7.1). The acquisition time for the eye monitor is approximately 10ms.

The peak detector outputs a value proportional to the outer eye amplitude. The output

of the peak detector can be sampled and read out digitally through the ADC. The

acquisition time is approximately 10ms.

The horizontal eye monitor outputs a value that is proportional to the horizontal eye

opening, as shown in Figure 3-20 below. The output of the horizontal eye monitor can

be sampled and read out digitally through the ADC. The acquisition time is

approximately 10ms.

Ch0 CDREQ

Ch1 CDRLA SDO1SDI1

SDI0 SDO0

Vertical Eye

Monitor,

Peak Detect

Horizontal

Eye Monitor

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Figure 3-20: Horizontal Eye Monitor

All eye monitoring functions can be independently enabled to optimize power. The

following register can be used to enable and control the eye monitors. See Section 3.7 for

details on sampling and reading out the monitors:

Data Jitter, UIpp

ADCOUT

0.25 0.5

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

CH0_REG13 43 CH0VEYETHADJ 7:0 RW 00000000 0-255 Vertical eye monitor threshold adjustment,

0-255.

CH0_REG14 44

CH0VEYETHPOL 0:0 RW 0 0-1 Vertical eye monitor threshold polarity.

HIGH is positive.

CH0VEYELORANGE1:1RW 0 0-1

When HIGH, reduces the range to

0-600mVppd.

CH0VEYEOFFCALEN 2:2 RW 0 0-1 Vertical eye monitor offset calibration

enable.

CH1_REG15 62 CH1VEYETHADJ 7:0 RW 00000000 0-255 Vertical eye monitor threshold adjustment,

0-255.

CH1_REG16 63

CH1VEYETHPOL 0:0 RW 0 0-1 Vertical eye monitor threshold polarity.

HIGH is positive.

CH1VEYELORANGE1:1RW 0 0-1

When HIGH, reduces the range to

0-600mVppd.

CH1VEYEOFFCALEN 2:2 RW 0 0-1 Vertical eye monitor offset calibration

enable.

CH0PWRDN_REG3 153

CH0PDVEYEMON 1:1 RW 1 0-1 Power-down for the Ch0 vertical eye

monitor.

CH0PDHEYEMON 2:2 RW 1 0-1 Power-down for the Ch0 horizontal eye

monitor.

CH0PDPKDET 3:3 RW 1 0-1 Power-down for the Ch0 peak detector.

CH1PWRDN_REG3 158

CH1PDVEYEMON 1:1 RW 1 0-1 Power-down for the Ch1 vertical eye

monitor.

CH1PDHEYEMON 2:2 RW 1 0-1 Power-down for the Ch1 horizontal eye

monitor.

CH1PDPKDET 3:3 RW 1 0-1 Power-down for the Ch1 peak detector.

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3.7 Digital Diagnostics

The GX4002 has an on-chip ADC to provide diagnostic information through the digital

interface. Temperature and voltage can be monitored.

3.7.1 Analog to Digital Converter (ADC)

The ADC converts several analog quantities including temperature, supply, vertical and

horizontal eye monitor outputs, and peak detector outputs.

The ADC is a sigma-delta converter with programmable resolution allowing trade-off

between conversion time and accuracy. The full scale dynamic range of the ADC is 0 to

1.8V. The various sources can be selected into the ADC for conversion and read-out.

Offset calibration signals are provided to zero-out the selected sources to facilitate the

calibration. Calibrated offsets can be programmed-in, such that the data read-out has

corrected offsets.

Furthermore, a user-defined offset can be programmed-in to account for external

systemic shifts. For example: if the temperature at the case is desired instead of the

device temperature, the temperature delta between device and case can be

programmed-in. Subsequent temperature read-outs will account for the temperature

delta, and provide the case temperature.

3.7.1.1 Usage Model

Two usage models are possible, manual conversion and auto conversion.

3.7.1.1.1 MANUAL CONVERSION MODE

For manual conversion mode, register controls provide a conversion-on-demand

interface. Polling or timing is required at the master end to read out the converted values

in manual mode.

The user is expected to select the desired source and to write a 1 to the

ADCSTARTCONV bit to initiate the conversion. The user can poll the ADCDONECONV

bit or time the conversion based on the requested resolution before reading out the data.

To read out the data in the timed mode, a block read transfer can be performed on the

ADCDONECONV, ADCOUTLO and ADCOUTHI registers. If the ADCDONECONV bit

is HIGH, then the data is valid.

The ADCSTARTCONV bit does not have to be reset before initiating another conversion.

Similarly, the ADCDONECONV bit does not have to be reset before initiating another

conversion. This minimizes the host interface transaction overhead while using the

ADC.

3.7.1.1.2 AUTO CONVERSION MODE

The user selects the desired source, and enables the auto conversion mode by setting

ADCAUTOCONVEN HIGH. The ADC will continuously convert the selected source and

update the ADCOUTHI/LO registers.

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The ADCDONECONV bit will always remain HIGH, indicating a valid converted value

is available for read-out. This flag may be cleared by writing to the ADCSTARTCONV bit

if positive indication of valid data is required.

3.7.1.2 ADC Control Registers

The following registers are used to select the various sources for conversion and

read-out through the ADC. The offset calibration controls ADCOFFCALEN[3:0]

facilitate calibrating the offsets of the selected sources:

The following registers are used to program a calibrated offset for automatic offset

correction. ADCOFFMODE and ADCRESOLUTION determine how the offset values

are interpreted.

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

ADC_REG1 143

ADCSRCSEL 3:0 RW 0000 0-15 Selects input for ADC (see Table 3-3: ADC

Source Select).

ADCOFFCALEN 7:4 RW 0000 0-15 Selects source for offset calibration (see

Table 3-2).

Table 3-3: ADC Source Select

ADCSRCSEL[3:0] Source

0000 0.9V

0001 Ch0 Vertical Eye

0010 Ch1 Vertical Eye

0011 Ch0 Horizontal Eye

0100 Ch1 Horizontal Eye

0101 Ch0 Peak Detector

0110 Ch1 Peak Detector

0111 RSVD

1000 RSVD

1001 RSVD

1010 Temperature Sensor

1011 Supply Sensor

1100 0.45V

1101 1.35V

1110 RSVD

1111 RSVD

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The following registers are used to configure the ADC:

AddressdParameter Name Bit Position Access Reset ValuebValid RangedFunction

ADC_REG7149 ADCOFFSETLO 7:0 RW 00000000 0-255 ADC offset LSB, unsigned binary.

ADC_REG8150 ADCOFFSETHI 7:0 RW 00000000 0-255 ADC offset MSB, unsigned binary.

AddressdParameter Name Bit Position Access Reset ValuebValid RangedFunction

ADC_REG0 142

ADCRESET 0:0 RW 1 0-1 Reset for the ADC.

ADCAUTOCONVEN 1:1 RW 1 0-1 When HIGH, enables auto conversion.

Set LOW for manual.

ADCJUSTLSB2:2RW1 0-1

When HIGH, justify towards LSB. LOW

justifies towards MSB.

ADCOFFMODE 3:3 RW 0 0-1

When LOW, offset is subtracted from the

ADC output. When HIGH, offset is added

to the ADC output.

NOTE: When HIGH, ADCOFFSETHI[7] is

sign and rest of the bits are magnitude.

A sign value of 1 represents negative

numbers.

ADC_REG2 143

ADCRESOLUTION 2:0 RW 001 0-7 ADC resolution control.

ADCCLKRATE 5:3 RW 0101 0-15 ADC clock divide ratio.

Table 3-4: ADC Resolution

ADCRESOLUTION ADC Resolution (bits) Number of ADC Clocks

for Conversion

000 4 15

001 6 63

010 8 255

011 10 1023

100 12 4095

101 14 16383

110 16 65535

111 Unused Unused

Table 3-5: ADC Clock Rate

ADCCLKRATE[2:0] ADC Sampling Clock Rate

(MHz)

ADC Conversion Time

(μs) Res = 10 bits

000 1 1023

001 1.6 651

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The following registers are used to control the conversion, and read-out the converted

data:

3.7.1.3 ADC Offset Calibration

The ADC supports conversion of several different sources. Each source can have a

different offset associated with it. To allow accurate conversion for each source, it is

recommended that the offset be calibrated for each source, so that the appropriate

correction can be applied when converting a given source.

There are two steps involved in the calibration of offsets:

1. Offset measurement.

2. Offset correction.

3.7.1.3.1 OFFSET MEASUREMENT

Offset measurement of any source requires zeroing-out the source, such that its output

constitutes the offset only. With the source zeroed-out, the output of the ADC is then the

cumulative offset. This offset is subtracted from subsequent measurements of the same

source to get an accurate offset corrected conversion.

010 2.1 477

011 2.7 377

100 3.3 311

101 3.9 265 (default)

110 4.4 231

111 5 205

Table 3-5: ADC Clock Rate (Continued)

ADCCLKRATE[2:0] ADC Sampling Clock Rate

(MHz)

ADC Conversion Time

(μs) Res = 10 bits

AddressdParameter Name Bit Position Access Reset ValuebValid RangedFunction

ADC_REG3 145 ADCSTARTCONV 0:0 RW 0 0-1 ADC starts conversion.

ADC_REG4 146 ADCDONECONV 0:0 RO 0 0-1 ADC conversion done flag.

ADC_REG5 147 ADCOUTLO 7:0 RO 00000000 0-255 ADC output LOW MSB.

ADC_REG6 148 ADCOUTHI 7:0 RO 00000000 0-255 ADC output HIGH MSB.

PWRDN_REG2 161

PDTEMPSENSOR 3:3 RW 1 0-1 When HIGH, power-down the

temperature sensor.

PDSUPPLYSENSOR 4:4 RW 1 0-1 When HIGH, power-down the supply

sensor.

PDADC5:5 RW 1 0-1 When HIGH, power-down the ADC.

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The device supports offset measurement of each source through the ADCSRCSEL and

ADCOFFCALEN register controls. ADCOFFCALEN selects the source to zero-out, as

shown in Table 3-2:

When a selected source is zeroed-out, the input to the ADC is set to its calibration voltage

(Vcal) as per Table 3-2. The ideal code for that calibration voltage for a given resolution,

can be subtracted from the output code to get the offset. Refer to the formula shown

below:

Equation 3-1

For example: if the temperature sensor is selected as the source, then it’s Vcal = 0.9V.

Assuming that the ADC resolution (N) is set to 10 bits; by setting ADCOFFCALEN =

“1010”, and reading-out the ADC, (in this example) ADCOUT = 521.

Therefore, Offset = 521 - 511 = 10.

This measured offset can be subtracted from subsequent measurements automatically,

as described in the next section.

Table 3-2: Offset Measurement Sources

ADCOFFCALEN[3:0] Source ADC Offset Calibration

Input (Vcal)

0000 0.9V 0.9V

0001 Ch0 Vertical Eye 0.9V

0010 Ch1 Vertical Eye 0.9V

0011 Ch0 Horizontal Eye 0.9V

0100 Ch1 Horizontal Eye 0.9V

0101 Ch0 Peak Detector 0.45V

0110 Ch1 Peak Detector 0.45V

0111 RSVD N/A

1000 RSVD N/A

1001 RSVD N/A

1010 Temperature Sensor 0.9V

1011 Supply Sensor 0.9V

1100 0.45V 0.45V

1101 1.35V 1.35V

1110 RSVD N/A

1111 RSVD N/A

8.1

2( −−=

Vca

ADCOutOffset N

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3.7.1.3.2 OFFSET CORRECTION

The ADC supports offset correction for both internal offsets as well as external

systematic offsets through the ADCOFFSETLO and ADCOFFSETHI registers.

The offset correction behaviour depends on the ADCOFFMODE control bit. Table 3-3

describes the offset correction operation:

Supporting both subtraction and addition of offsets allows the user the flexibility to

adjust for systematic shifts. However, the default mode 0 (subtraction) should suffice for

most applications.

In the previous example, the offset was measured to be 10 for ADCOUT = 521 for the

temperature sensor. This offset can be automatically subtracted for all subsequent

measurements of the temperature sensor by setting ADCOFFSETLO = 10 and

ADCOFFSETHI = 0. With these values, ADCOUT will read 511 (instead of 521).

3.7.1.4 ADC Conversion Sequence

The following sequence is recommended for ADC conversions:

1. Power-up the ADC.

2. Bring the ADC out of reset.

3. Setup the ADC mode of operation (Auto or Manual).

4. Setup the ADC resolution.

5. Setup the ADC conversion rate (clock rate).

6. Select the ADC source to convert.

7. Setup the ADC offset and offset modes.

8. Start the ADC conversion.

9. Read the ADC-done conversion flag to confirm a successful conversion.

10. Read the ADC output, first the low byte, immediately followed by high byte.

The following section gives a detailed example of performing an ADC conversion in

manual mode.

Table 3-3: Offset Correction Operation

ADCOFFMODE Operation Description

ADCOUTLO,HI = uncorrected

ADC Out[15:0] -

ADCOFFSETLO,HI

ADCOFFSETLO,HI is un-signed.

Result is unsigned. Output is all 0s

for negative results.

ADCOUTLO,HI = uncorrected

ADC Out[15:0] +

ADCOFFSETLO,HI

ADCOFFSETLO,HI is sign + mag.

Bit 15 is sign, and 1 represents

positive. Result is unsigned. Output

is all 0s for negative results.

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Example ADC Conversion in Manual Mode

The following example illustrates how to use the ADC to read-out the supply sensor in

manual conversion mode:

1. Power-up the ADC and the supply sensor.

2. Bring the ADC out of reset.

3. Set the ADC mode of operation to manual mode.

Note that this must be a separate write operation than the reset exit, even though

it's the same register.

4. Set the ADC resolution to 12 bits.

5. Set the ADC conversion rate.

6. Select the ADC source as the supply sensor.

7. Set the ADC offset and offset mode (in this example, an offset of 0 is assumed).

8. Start the ADC conversion.

Note that it is not required to reset the ADCSTARTCONV to 0 before starting

another conversion. Writing a value of 1 to the ADCSTARTCONV bit again will

initiate a new conversion.

Read the ADC-done flag and output.

ADCOUTHI.

These three registers can be read-out as burst read. Note that it is important that the

LOW byte be read-out first, immediately followed by a HIGH byte. This is required to

ensure data consistency. The ADCDONECONV flag can be checked to confirm

successful conversion.

3.7.1.5 ADC Transfer Functions for Each Source

The following subsections show the typical transfer functions for each source that can

be read-out from ADC.

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Peak Detectors

Table 3-4 and Figure 3-21 show typical peak detector outputs:

Figure 3-21: Peak Detector Output

Table 3-4: Peak Detector Outputs

Peak Detector Input

Amplitude (mVppd) ADC (12-bit resolution) ADC (10-bit resolution)

10 806 201

30 810 202

50 817 204

75 830 207

100 849 212

140 887 222

180 931 233

220 975 244

240 998 250

280 1044 261

320 1092 273

360 1139 285

400 1184 296

1000 1828 457

1200 1993 498

ADC Output (decimal)

Peak Detector Output (Res=12b)

2000

1750

1500

1250

1000

750

200 400 600 800 1000 1200 14000

Ch1 Input (mVppd)

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Temperature Sensor

Table 3-5 and Figure 3-22 show typical temperature sensor outputs:

Figure 3-22: ADC Temperature Monitor Transfer Function

Table 3-5: Typical Temperature Sensor Output

Temperature (°C) ADC (12-bit resolution) ADC (10-bit resolution)

-20.00 653 163

0.00 896 223

20.00 1138 284

40.00 1381 345

60.00 1623 405

80.00 1866 466

90.00 1987 496

120.00 2351 587

ADC Temp Monitor Transfer Function

100

200

300

400

500

600

700

-40.00 -20.00 0.00 20.00 40.00 60.00 80.00 100.00 120.00 140.00

Temp(°C)

ADC Read-Out (10-bits) dec

10-bit

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Supply Sensor

Table 3-6 and Figure 3-23 show typical Ch0SDOVCC supply sensor outputs:

Figure 3-23: ADC Supply Monitor Transfer Function

Table 3-6: Typical Ch0SDOVCC Supply Sensor Output

Ch0SDOVCC (V) ADC (12-bit resolution) ADC (10-bit resolution)

2.3 644 161

2.4 771 192

2.5 898 224

2.6 1025 256

2.7 1152 288

2.8 1279 319

2.9 1406 351

3.0 1532 383

3.1 1659 414

3.2 1786 446

3.3 1913 478

3.4 2040 510

3.5 2167 605

3.6 2294 573

3.7 2421 605

ADC Supply Monitor Transfer Function

100

200

300

400

500

600

700

2.0 2.2 2.4 2.62.8 3 3.2 3.4 3.63.8

Supply Voltage (V)

ADC Read-Out (10-bits) dec

10-bit

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3.8 Power Control Options

The GX4002 provides a high-degree of flexibility in configuring the device for optimal

power through power-down and power adjustment registers. Typical usage scenarios

are shown. For further description on each of the individual control bits, see Table 7-1,

registers 134 to 137. This section describes the power-down controls for the following

sub-systems:

1. Ch1 CDR & SDO Power-Down

2. Ch0 CDR Power-Down

3. Ch0 SDO Power-Down

Table 3-7: Ch1 CDR & SDO Power-Down

CH1PLLBYPASS

CH1PDPATH

CH1PDCH1CDR

CH1PDHEYEMON

CH1PDCKDIVOUT

CH1PDSDO

Description

01xxx1Completely powers-down the Ch1 CDR and Ch1 SDO.

0x1xx1Completely powers-down the Ch1 CDR and Ch1 SDO

1 0 x x x 0 Main data path through Ch1 CDR and Ch1 SDO is powered-up for bypass

mode. (Ch1LA has to be powered-up).

000110Mission mode, Ch1 CDR & SDO enabled in low-power mode.

000110Mission mode for fibre channel. Ch1 CDR & SDO are enabled with

automatic bypass through rate detection.

000010Diagnostic mode with horizontal eye monitor enabled.

000100Diagnostic mode with divided recovered clock available through Ch1 SDO.

Requires appropriate configuration of loopback registers.

Table 3-8: Ch0 CDR Power-Down

CH0PLLBYPASS

CH0PDPATH

CH0PDCH0CDR

CH0PDHEYEMON

CH0PDCKDIVOUT

CH0PDCH0SDO

Description

011xx1Completely powers-down the Ch0 CDR

1 0 1 x x 0 Main data path through Ch0 CDR is powered-up for bypass mode. (Ch0Eq

has to be powered-up).

000110Mission mode, Ch0 CDR is enabled in low power mode.

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3.9 Device Reset

RESET is an active-low signal with LVTTL/LVCMOS compatible signalling levels. RESET

has a weak pull-down to keep the device in reset upon power-up. RESET does not have

schmitt trigger since reset negation is internally synchronized. See Figure 6-7.

3.9.1 Reset State During Power-up

The device requires RESET to be continuously asserted LOW during power ramp up.

RESET must continue to be held in an asserted LOW state for the minimum specified

time after the power supply has reached 90% of its final settling value. Following a

RESET assertion at power-up, the device may be reset again at any time with the

minimum specified pulse width on RESET. Refer to Figure 3-24.

000010Diagnostic mode with horizontal eye monitor enabled.

000100Diagnostic mode with divided recovered clock available through Ch0 SDO.

Requires appropriate configuration of loopback registers.

Table 3-8: Ch0 CDR Power-Down (Continued)

CH0PLLBYPASS

CH0PDPATH

CH0PDCH0CDR

CH0PDHEYEMON

CH0PDCKDIVOUT

CH0PDCH0SDO

Description

Table 3-9: Ch0 SDO Power-Down

CH0PDPATH

CH0PDCH0SDO

CH0PDCH0CDR

PDCH0SDOCPA

Description

1xxxCompletely powers-down the Ch0 SDO.

x1xxCompletely powers-down the Ch0 SDO.

0 0 x 1 Independently powers-down the Ch0 SDO cross point adjust feature.

0000Ch0 SDO with all features enabled.

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Figure 3-24: Reset State During Power-up

3.9.2 RESET Timing

The following RESET timing specifications apply:

t_chip_reset: 10μs

Defined as the minimum duration that RESET must be asserted after the supply has

reached 90% of final settling value. The device can be accessed 1μs after RESET goes

HIGH.

Figure 3-25: GX4002 Device Reset Timing Diagram

0.9*Vcc

t_chip_reset*Minimum pulse width

on RESET = t_chip_reset*

for subsequent resets

following reset

assertion at power-up

RESET

Vcc

*NOTE: Refer to Section 3.8.2

t_chip_reset

0.9*VCC

RESET

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3.9.3 I/O and Register States During and After Reset

All configuration registers are set to their post-reset defaults state immediately

following RESET assertion.

The following I/O states are applicable upon RESET assertion:

3.10 Digital Control Interface

The GX4002 has a serial control interface to communicate with the part. An I2C protocol

can be used.

3.10.1 I2C Host Interface Mode

The I2C mode supports standard-mode (100kb/s) and fast-mode (400kb/s) signalling.

The device only supports slave mode. The pins SDA and SCL are used for bi-directional

serial data and clock respectively.

The GX4002 device slave address is 24h (= 0100100x).

The I2C protocol is implemented as per the following description:

Each access begins with a 7-bit I2C slave address word, an 8-bit register address word,

followed by two 8-bit data words written to, or read from, the GX4002.

Table 3-10: I/O and Register States During and After Reset

Pin Name I/O State upon RESET Assertion

SDA

This pin is configured as an input while RESET is asserted and

immediately following RESET negation. When configured as an

input, this pin is high-impedance.

SCL

This pin is configured as an input while RESET is asserted, and

immediately following RESET negation. When configured as an

input, this pin is high-impedance.

Ch0FAULT

This pin is configured as an open-drain output while RESET is

asserted and immediately following RESET negation.

This output will be high-impedance, and its state will depend on

the external pull-up.

Ch1LOS

This pin is configured as an open-drain output while RESET is

asserted and immediately following RESET negation. If a signal

is present, the output will be pulled LOW. Otherwise, this output

will be high-impedance and it’s state will depend on the

external pull-up.

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Figure 3-26: Single Register Write Cycle over I2C Bus

Figure 3-27: Single Register Read Cycle over I2C Bus

Figure 3-28: Bulk Register Write Cycle over I2C Bus

Figure 3-29: Bulk Register Read Cycle over I2C Bus

SAAAPregister addressWregister’s data

Single 8-bit-Register Write Cycle - Over I C Bus

I C Slave Address

From Master to Slave

From Slave to Master

A = Acknowledge (SDA LOW)

N = No Acknowledge (SDA HIGH)

S = Start Condition

Sr = Restart Condition

P = Stop Condition

R = Read mode (=1)

W = Write mode (=0)

Legend:

From Master to Slave

From Slave to Master

A = Acknowledge (SDA LOW)

N = No Acknowledge (SDA HIGH)

S = Start Condition

Sr = Restart Condition

P = Stop Condition

R = Read mode (=1)

W = Write mode (=0)

SAA NPregister addressWSr R A

Single 8-bit-Register Read Cycle - Over I C Bus

I C Slave Address

Legend:

SAA A

A AA A

Adata (RA)

Multiple 8-bit-Registers (consecutive address) Write Cycle - Over I C Bus

I C Slave Address

data (RA + 1) data (RA + 2)

data (RA + n - 4) data (RA + n - 3) data (RA + n - 2) data (RA + n - 1)

From Master to Slave

From Slave to Master

A = Acknowledge (SDA LOW)

N = No Acknowledge (SDA HIGH)

S = Start Condition

Sr = Restart Condition

P = Stop Condition

R = Read mode (=1)

W = Write mode (=0)

Legend:

From Master to Slave

From Slave to Master

A = Acknowledge (SDA LOW)

N = No Acknowledge (SDA HIGH)

S = Start Condition

Sr = Restart Condition

P = Stop Condition

R = Read mode (=1)

W = Write mode (=0)

SAA A

WSr R A

A A AA

Multiple Registers (consecutive address) Read Cycle - Over I C Bus

I C Slave Address

data (RA + n - 4) data (RA + n - 3) data (RA + n - 2) data (RA + n - 1)

Legend:

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4. Typical Application Circuit

Figure 4-1: GX4002 Typical Application Circuit

• Place lowest value decoupling capacitor closest to the device

• Status indicator connections are shown for a LVCMOS/LVTTL compatible mode.

These I/Os can be configured as open-drain with pull-up

4.1 Power Supply Filter Recommendations

RC filters for isolating supplies are not recommended due to the large currents drawn

from each supply.

• The Ch0 and Ch1 VCOs do not have independent supplies. Both of the Ch0 and Ch1

VCOs have internal regulators sourced from Ch0VCC and Ch1VCC respectively. As

a result, additional filtering for the VCOs is not required

SDO0VCC

SDO0VEE

SDI1

Ch1LOS

Ch1VCOVEE

Ch1VEE Ch1VCC

SDO1

Ch0VCC

Ch0VEE

SDI0

Ch0VCOVEE

GND

VREG

DIGVSS

SDO0

TAB

RS0

RS1

Ch0FAULT

SDA

SCL

18 22

TAB

1210

220nF

4.7kΩ

100nF

Ch1_3V3

100nF

Ch0_3V3

10nF

GX4002

4.7kΩ

DIG_3V3

SDO0_3V3

10nF

RESET

100Ω dierential pair

100Ω dierential pair 100Ω dierential pair

100nF

SDI1

GND

SDI0

Ch0FAULT

SDO0

RESET

SDO1

Ch1LOS

SDA

SCL

RS0

RS1

Populate for

open-collector

mode

From SFP+

connector

or to/from

controller

Ch0 Input

100nF

100Ω dierential pair

To/from

controller

100nF

Ch1 Output

6Ω

10Ω

1kΩ1kΩ

AC Common Mode

Enhancement

SDO0

SDI1

SDO1

SDI0

Ch0 Output

Ch1 Input

SDI0

SDO1

Ch1LF

Ch1VCOFILT

1µF

100nF

Ch1VCOFILT

Ch1LF

Ch0VCOFILT

Ch0LF

1µF

100nF

Place close to chip

Ch0VCOFILT

Ch0LF

4.7kΩ

DIG_3V3

From SFP+

connector

or to/from

controller

4.7kΩ

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For improved isolation between the Ch0 and Ch1 paths, and to achieve the best Ch1

Sensitivity and Ch0 Jitter Generation, a supply filter such as the one shown in Figure 4-2

is recommended.

Figure 4-2: Power Supply Filter Recommendations

4.2 Power Supply Domains

Figure 4-3 shows the power supply domains for the GX4002:

Figure 4-3: Power Supply Domains

C21 C22

1µF 100nF

C23 C24

C25 C26

Ch0SDOVCC

Ch0VCC

Ch1VCC

L9: Ferrite Bead (0603)

1k, Rdc = 0.35Ω

Example: Murata

P/N BLM18HE102SN1

V3.3

1µF 100nF

L10: Ferrite Bead (0603)

1k, Rdc = 0.35Ω

Example: Murata

P/N BLM18HE102SN1

L11: Ferrite Bead (0603)

1k, RDC = 0.35Ω

Example: Murata

P/N BLM18HE102SN1

L10

L11

Trace Driver

O/P Stage

Ch0 CDR

Ch0EQ

Host I/F

1.8V

Regulator

Pre-Driver

Diagnostics

(ADC, Ch0Fault)

Supply

Sensor

VCO

Digital I/Os

Ch1 CDR

Ch1 LA Trace Driver

VCO

PRBS Generator

+ Checker

Ch0SDOVCC

Ch0VCC

Ch1VCC

Power Domains Legend

Ch1VCOFILT

Reg

Ch0VCOFILT

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5. Layout Considerations

The following high-frequency design rules should be considered to achieve optimum

performance of the GX4002:

• Use carefully designed controlled-impedance transmission lines with minimal local

discontinuities for all high-speed data signals

• Place decoupling capacitors as close as possible to the supply pins

• For optimal electrical and thermal performance, the QFN’S exposed pad should be

soldered to the module ground plane

• It is recommended to have LF cap ground and VCO caps ground to be common with

multiple stitching of vias to ground. Capacitors should be placed from smallest

value to largest value away from chip

• All supply decoupling capacitors should have multiple vias to ground/power

planes, and placed as close to chip as possible

• All supplies/grounds should be routed to corresponding decoupling capacitors

pads, and never to the centre pad

• The recommended PCB layout for the GX4002 device is shown in Section 7.2

• Some sample layouts are shown in Figure 5-1

Figure 5-1: Sample Layouts

Ground Pad

(bottom of package)

32 25

9 16

Ch1LOS 8

SDO0VCC

SDI1

RS1

SDO0VEE

Ch0VCC

GND

Ch0VEE

SDI0

Ch0VCOFILT

Ch0VCOVEE

Ch0LF

XPOINT

Ch0FAULT

SDO0

RS0

DIGVSS

VREG

SCL

SDA

Ch1LF

Ch1VCOVEE

Ch1VCOFILT

Ch1VEE

Ch1VCC

SDO1

RESET

31 30 29 28 27 26

10 11 12 13 14 15

SDI1

SDO1

SDI0

SDO0

OUT

GX4002

OUT

GX4002

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6. Input/Output Equivalent Circuits

Figure 6-1: SDI1

Figure 6-2: SDI0

Figure 6-3: SDO1

Ch1VCC Ch1VCC

Ch1VEECh1VEE

50Ω

Ch1VCC

Ch1VEE

SDI1

Ch0VCC

50Ω

Ch0VCC

50Ω

Ch0VCC

Ch0VEE

Ch0VEE Ch0VEE

SDI0

Swing Control

Ch1VCC

Ch1VEE

50Ω

Ch1VCC

Ch1VEE

50Ω

Ch1VEE

2mA

Pre-emphasis

Control

SDO

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Figure 6-4: SDO0

Figure 6-5: Ch0FAULT

Figure 6-6: Ch1LOS

Ch0SDOVCC

Ch0SDOVEE

50Ω50Ω

Ch0SDOVCC

Ch0SDOVEE

SDO

Ch0SDOVEE

Ch0FAULT

Ch0SDOVEE

Ch0SDOVCC

Ch0SDOVEE

ch0FAULT

Ch0SDOVEE

Ch0SDOVCC

Configured as open-drain Configured as LVCMOS

Ch1VEE

Ch1LOS

Ch1VEE

Ch1VCC

Ch1LOS

Ch1VCC

Ch1VEE Ch1VEE

Configured as open-drain Configured as LVCMOS

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Figure 6-7: RESET

Figure 6-8: I2C, SCL, SDA

Figure 6-9: RS0, RS1

Ch1VCC

Ch1VEE

50Ω

RESET

Ch1VCC

Ch1VEE Ch1VEE

5µA

Ch1VEE

Ch1VCC

Ch1VEE

Ch1VCC

Ch0SDOVCC

Ch0SDOVEE

SCL

50Ω

Ch0SDOVCC

Ch0SDOVEE

1kΩ

Ch0SDOVCC

Ch0SDOVEE

I2C Clock Output

VREGCh0SDOVCC

Ch0SDOVEE Ch0SDOVEE

Ch0SDOVEE

I2C Clock Input

Schmitt

VREGCh0SDOVCC

Ch0SDOVEE Ch0SDOVEE

Ch1VCC

Ch1VEE

RS0

RS1

50Ω

Ch1VCC

Ch1VEE

Schmitt

Ch1VCC

Ch1VEE

Ch1

VEE

25µA

Ch1

VEE

Ch1

VCC

To Rate Select Logic

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7. Package and Ordering Information

7.1 Package Dimensions

The GX4002 is a 5mm x 5mm, 32-pin QFN.

7.2 Recommended PCB Footprint

Bottom View

Side View

Top View

MAX.

MIN.

NOM.

0.800

0.900

0.850

5.000±0.050

Pin 1 dot

by marking

32L QFN

(5 x 5mm)

3.300±0.050

Exp.DAP

3.500

Ref.

3.300±0.050

Exp.DAP

0.400±0.050

Pin #1 identification

chamfer 0.400 x 45°

0.203 Ref

0.000-0.050

0.230±0.050

0.500 Bsc

0.6

0.30.50

4.20

3.30

0.40 x 45°

Notes:

1. All dimensions in mm.

2. Drawing not to scale.

3. 16 thermal relief pins, evenly spaced on centre paddle,

connected to ground plane.

4. Drill size: 0.254mm.

Pin #1

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7.3 Packaging Data

7.4 Solder Reflow Profile

The device is manufactured with Matte-Sn terminations and is compatible with both

standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed

using the maximum Pb-free reflow profile shown in Figure 7-1.

Figure 7-1: Maximum Pb-free Solder Reflow Profile

Parameter Value

Package Type 32-pin QFN / 5mm x 5mm

/ 0.5mm pad pitch

Moisture Sensitivity Level 3

Junction to Case Thermal Resistance, θj-c17.8°C/W

Junction to Air Thermal Resistance (at zero airflow), θj-a 26.4°C/W

Psi = Junction-to-Top (of Package) Characterization Parameter, Ψ0.4°C/W

Pb-free and RoHS compliant Yes

25°C

150°C

200°C

217°C

260°C

250°C

Time

Temperature

8m maximum

60s to180s maximum

60s to 150s

20s to 40s

3°C/s maximum

6°C/s maximum

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7.5 Marking Diagram

7.6 Ordering Information

GX4002

XXXXE3

YYWW

Pin 1 ID

XXXX - Last 4 digits (excluding decimal)

of SAP Batch Assembly (FIN) as listed

on Packing Slip.

E3 - Pb-free & Green indicator

YYWW - Date Code

Part Number Package Temperature Range

GX4002-INE3 32-pin QFN -40°C to 100°C

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Appendix: Configuration and Status Register Map

NOTE: *Indicates bits for lower data rates (below 10G operation).

Table 7-1: Configuration and Status Register Map

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

RSVD 0 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

TOP_REG11

FAULTMASKCH1LOS0:0 RW 1 0-1 When HIGH, masks out Ch1LOS from asserting

Ch0FAULT.

FAULTMASKCH1LOL 1:1 RW 1 0-1 When HIGH, masks Ch1LOL from asserting

Ch0FAULT.

FAULTMASKCH0LOS2:2 RW 1 0-1 When HIGH, masks out Ch0LOS from asserting

Ch0FAULT.

FAULTMASKCH0LOL 3:3 RW 1 0-1 When HIGH, masks Ch0LOL from asserting

Ch0FAULT.

FAULTMASKCH0FAULT 4:4 RW 0 0-1 When HIGH masks out Ch0FAULT from

asserting Ch0FAULT.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

TOP_REG22

POLINVCH0FAULT 0:0 RW 0 0-1 When HIGH, inverts polarity of Ch0FAULT

output.

POLINVCH1LOS1:1 RW 0 0-1 When HIGH, inverts polarity of Ch1LOS output.

OPENDRAINCH1LOS2:2 RW 1 0-1 When HIGH, makes Ch1LOS output driver

open-drain.

OPENDRAINCH0FAULT 3:3 RW 1 0-1 When HIGH, makes Ch0FAULT output driver

open-drain.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

TOP_REG33

PRBSGENSTART 0:0 RW 0 0-1 When pulsed HIGH and LOW, starts off the

PRBS generator.

PRBSCHKCLEARERR 1:1 RW 0 0-1 When HIGH, clears the latched error flag from

checker.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

TOP_REG44

RSVD 3:0 RW 1111 0-15 Reserved. Do not change.

FORCECH0FAULT 4:4 RW 0 0-1 When HIGH, asserts CH0FAULT.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

RSVD 5 RSVD 7:0 RW 00001111 0-255 Reserved. Do not change.

TOP_REG66

PRBSCHKSTATUS0:0 RO 0 0-1 When HIGH, checker detected an error.

RSVD 7:1 RW 0000000 0-127 Reserved. Do not change.

NOTE: * Indicates bits for lower data rates (below 10G operation)

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LOOPBK_REG17

LBCH1INEN 0:0 RW 0 0-1 Selects LB input into Ch1 CDR.

LBCH1INPRBSGEN 1:1 RW 0 0-1 Selects PRBS generator output into Ch1 CDR.

LBCH1INCH0DATA 2:2 RW 0 0-1 Selects Ch0 data into Ch1 CDR.

RSVD 3:3 RW 00-1 Reserved. Do not change.

LBCH1OUTEN 4:4 RW 0 0-1 Selects LB input into Ch1 Driver.

LBCH1OUTCH0DATA 5:5 RW 0 0-1 Selects Ch0 data into Ch1 Driver.

LBCH1OUTPRBSGEN 6:6 RW 0 0-1 Selects PRBS generator output into Ch1 Driver.

LBCH1OUTCH1CLK 7:7 RW 0 0-1 Selects Ch1 Clock into Ch1 Driver.

LOOPBK_REG28

LBCH0INEN 0:0 RW 0 0-1 Selects LB input into Ch0 CDR.

LBCH0INPRBSGEN 1:1 RW 0 0-1 Selects PRBS generator output into Ch0 CDR.

LBCH0INCH0DATA 2:2 RW 0 0-1 Selects Ch0 data into Ch0 CDR.

RSVD 3:3 RW 00-1 Reserved. Do not change.

LBCH0OUTEN 4:4 RW 0 0-1 Selects LB input into Ch0 Driver.

LBCH0OUTCH0DATA 5:5 RW 0 0-1 Selects Ch1 data into Ch0 Driver.

LBCH0OUTPRBSGEN 6:6 RW 0 0-1 Selects PRBS generator output into Ch0 Driver.

LBCH0OUTCH1CLK 7:7 RW 0 0-1 Selects Ch1 clock into Ch0 Driver.

LOOPBK_REG39

PRBSGENCLKSEL 0:0 RW 0 0-1 When HIGH, selects Ch0 recovered clock. LOW

selects Ch1 clock.

PRBSCHKCLKSEL 1:1 RW 0 0-1 When HIGH selects Ch0 recovered clock. LOW

selects Ch1 clock.

RSVD 7:2 RW 000111 0-63 Reserved. Do not change.

CH0PLL_REG110

CH0PLLLBWCURVT 4:0 RW 10011 0-31 Adjusts LBW positive temperature coefficient

control.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH0PLL_REG211

CH0PLLLBWCURVBE 4:0 RW 01110 0-31 Adjusts LBW negative temperature coefficient

control.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

RSVD 12

RSVD 1:0 RW 01 0-3 Reserved. Do not change.

CH0PLLCUR 3:2 RW 01 0-3 CH0PLL control current.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

RSVD 13 RSVD 7:0 RW 00100000 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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CH0PLL_REG514

CH0PLLPOLINV 0:0 RW 0 0-1 When HIGH, inverts data path polarity.

CH0PLLBYPASS 1:1 RW 0 0-1 When HIGH, forces CDR into bypass mode.

CH0PLLAUTOBYPASSEN 2:2 RW 1 0-1 When HIGH, enables automatic bypass mode.

CH0PLLRATESEL 3:3 RW 1 0-1 Selects data rates:

0 = 1.25 - 8.5G, 1= 10.3G or 14.025G

CH0PLLRATESELVAL 4:4 RW 1 0-1 When HIGH, CH0PLLRATESEL is valid, otherwise

it is ignored.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

RSVD 15 RSVD 7:0 RW 00001010 0-255 Reserved. Do not change.

RSVD 16 RSVD 7:0 RW 00100000 0-255 Reserved. Do not change.

RSVD 17 RSVD 7:0 RW 00000101 0-255 Reserved. Do not change.

CH0PLL_REG918

RSVD 5:0 RW 000000 0-63 Reserved. Do not change.

CH0PLLBWMULT 7:6 RW 10 0-3 LBW multiplier:

00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67

CH0PLL_REG10 19

CH0PLLLOS0:0 RO 0 0-1 Loss of signal when HIGH.

CH0PLLLOL 1:1 RO 0 0-1 Loss of lock when HIGH.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

CH1PLL_REG120

CH1PLLLBWCURVT 4:0 RW 10011 0-31 Adjusts LBW positive temperature coefficient

control.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH1PLL_REG221

CH1PLLLBWCURVBE 4:0 RW 01110 0-31 Adjusts LBW negative temperature coefficient

control.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH1PLL_REG322

RSVD 1:0 RW 01 0-3 Reserved. Do not change.

CH1PLLCUR 3:2 RW 01 0-3 Ch1 PLL control current.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

RSVD 23 RSVD 7:0 RW 00100000 0-255 Reserved. Do not change.

CH1PLL_REG524

CH1PLLPOLINV 0:0 RW 0 0-1 When HIGH, inverts data path polarity.

CH1PLLBYPASS 1:1 RW 0 0-1 When HIGH, forces CDR into bypass mode.

CH1PLLAUTOBYPASSEN 2:2 RW 1 0-1 When HIGH, enables automatic bypass mode.

CH1PLLRATESEL 3:3 RW 1 0-1 Selects data rates:

0 = 1.25 - 8.5G, 1 = 10.3G or 14.025G

CH1PLLRATESELVAL 4:4 RW 1 0-1 When HIGH, CH1PLLRATESEL is valid.

Otherwise, it is ignored.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

RSVD 25 RSVD 7:0 RW 00001010 0-255 Reserved. Do not change.

RSVD 26 RSVD 7:0 RW 00100000 0-255 Reserved. Do not change.

RSVD 27 RSVD 7:0 RW 00000101 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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CH1PLL_REG928

RSVD 5:0 RW 001000 0-63 Reserved. Do not change.

CH1PLLBWMULT 7:6 RW 10 0-3 LBW multiplier:

00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67

CH1PLL_REG10 29

CH1PLLLOS0:0 RO 0 0-1 Loss of signal when HIGH.

CH1PLLLOL 1:1 RO 0 0-1 Loss of lock when HIGH.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

RSVD 30 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 31 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 32 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH0_REG333

CH0EQBOOST* 0:0 RW 10-1

When HIGH, applies fixed Ch0 equalizer boost

of 6dB. 0dB if LOW.

Valid for below 10G operation.

CH0EQBOOST1:1RW10-1

When HIGH, applies a fixed Ch0 Equalizer

boost of 6dB, 0dB if LOW.

Valid for 10G to 14G operation.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

CH0_REG434

CH0EQOFFOVRVAL 6:0 RW 0111111 0-127 Offset correction. 63 for 0 correction

with +64/-63 steps.

RSVD 7:7 RW 00-1 Reserved. Do not change.

RSVD 35 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 36 RSVD 7:0 RW 00000101 0-255 Reserved. Do not change.

RSVD 37 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 38 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH0_REG939CH0LOSTHNEG7:0 RW 01010011 0-255 Negative temperature coefficient LOS

threshold setting.

CH0_REG10 40 CH0LOSTHPOS7:0 RW 00000000 0-255 Positive temperature coefficient LOS threshold

setting.

CH0_REG11 41

CH0LOSHYS3:0 RW 1001 0-15 0: minimum hysteresis, 15: maximum hysteresis.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

CH0_REG12 42

RSVD 2:0 RW 000 0-7 Reserved. Do not change.

CH0LOSSOFTASSERT 3:3 RW 0 0-1 When HIGH, does a software LOS assert.

CH0LOSSOFTASSERTEN 4:4 RW 0 0-1 When HIGH, selects software LOS. LOW selects

hardware LOS.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH0_REG13 43 CH0VEYETHADJ 7:0 RW 00000000 0-255 Vertical eye monitor threshold adjustment,

0-255.

CH0_REG14 44

CH0VEYETHPOL 0:0 RW 0 0-1 Vertical eye monitor threshold polarity. HIGH is

positive.

CH0VEYELORANGE1:1RW00-1

When HIGH, reduces the range to

0-600mVppd.

CH0VEYEOFFCALEN 2:2 RW 0 0-1 Vertical eye monitor offset calibration enable.

RSVD 7:3 RW 00000 0-31 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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CH0_REG15 45

CH0PWR1 4:0 RW 01010 0-31

Main power configuration register for the Ch0

path. Default is the high-power setting. Refer

to Section 2.4.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH0_REG16 46

RSVD 2:0 RW 111 0-31 Reserved. Do not change.

CH0PWR2 4:3 RW 01 0-3

Secondary power configuration register for the

Ch0 path. Default is the high-power setting.

Refer to Section 2.4.

RSVD 7:5 RW 000 0-1 Reserved. Do not change.

RSVD 47 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH1_REG148

CH1LABOOST* 3:0 RW 0000 0-15 0: 0dB to 15: 14dB.

Valid for below 10G operation.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

CH1_REG249

CH1LABOOST 3:0 RW 0000 0-15 0: 0dB to 15: 14dB.

Valid for 10G to 14G operation.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

RSVD 50 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH1_REG451

CH1LAOFFOVRVAL 6:0 RW 0111111 0-127 Offset correction. 63 for 0 correction with

+64/-63 steps.

RSVD 7:7 RW 00-1 Reserved. Do not change.

RSVD 52 RSVD 7:0 RW 00010000 0-255 Reserved. Do not change.

RSVD 53 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 54 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 55 RSVD 7:0 RW 00001010 0-255 Reserved. Do not change.

CH1_REG956 CH1LOSTHNEG*7:0 RW 10000011 0-255

Negative temperature coefficient LOS

threshold setting.

Valid for below 10G operation.

CH1_REG10 57 CH1LOSTHPOS*7:0 RW 00010001 0-255 Positive temperature coefficient LOS threshold

setting. Valid for below 10G operation.

CH1_REG11 58 CH1LOSTHNEG7:0 RW 10000011 0-255

Negative temperature coefficient LOS

threshold setting.

Valid for 10G to 14G operation.

CH1_REG12 59 CH1LOSTHPOS7:0 RW 00010001 0-255

Positive temperature coefficient LOS threshold

setting.

Valid for 10G to 14G operation.

CH1_REG13 60

CH1LOSHYS*3:0 RW 1001 0-15 0: minimum hysteresis, 15: maximum hysteresis.

Valid for below 10G operation.

CH1LOSHYS7:4 RW 1001 0-15 0: minimum hysteresis, 15: maximum hysteresis.

Valid for 10G to 14G operation.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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CH1_REG14 61

CH1LOSRANGE* 2:0 RW 001 0-7 1:0 - LOS range 0: highest - 3: lowest, 2 (MSB)

unused. Valid for below 10G operation.

CH1LOSRANGE5:3RW0010-7

1:0 - LOS range 0: highest - 3: lowest, 2 (MSB)

unused.

Valid for 10G to 14G operation.

CH1LOSSOFTASSERT 6:6 RW 0 0-1 When HIGH, selects a software LOS. LOW

selects hardware LOS.

CH1LOSSOFTASSERTEN 7:7 RW 0 0-1 When HIGH, selects software LOS. LOW selects

hardware LOS.

CH1_REG15 62 CH1VEYETHADJ 7:0 RW 00000000 0-255 Vertical eye monitor threshold adjustment,

0-255.

CH1_REG16 63

CH1VEYETHPOL 0:0 RW 0 0-1 Vertical eye monitor threshold polarity. HIGH is

positive.

CH1VEYELORANGE1:1RW00-1When HIGH, reduces the range to 0-600mVppd

CH1VEYEOFFCALEN 2:2 RW 0 0-1 Vertical eye monitor offset calibration enable.

RSVD 7:3 RW 00000 0-31 Reserved. Do not change.

CH1_REG17 64

CH1PWR1 4:0 RW 01010 0-31

Main power configuration register for the Ch1

path. Default is the high-power setting. Refer

to Section 2.4.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH1_REG18 65

RSVD 4:0 RW 11100 0-31 Reserved. Do not change.

CH1PWR2 6:5 RW 00 0-3

Secondary power configuration register for the

Ch1 path. Default is the high-power setting.

Refer to Section 2.4.

RSVD 7:7 RW 00-1 Reserved. Do not change.

CH1_REG19 66 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH0RDET_REG167

CH0RATEDETRESET 0:0 RW 0 0-1 When HIGH, the rate detector is reset.

CH0RATEDETEN 1:1 RW 1 0-1 When HIGH, the rate detector is enabled.

RATEDETFCGBEN 2:2 RW 1 0-1 When HIGH, the application is Fibre Channel,

when LOW the application is Ethernet.

RATEDETFCGBENVAL 3:3 RW 1 0-1 When HIGH, FCGBEn is valid.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

CH0RDET_REG268

CH0RATEDETRATEPER 3:0 RW 1000 0-15 Rate detector rate period (0.3µs to 13ms, 100µs

default).

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

RSVD 69 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 70 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 71 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH1RDET_REG172

CH1RATEDETRESET 0:0 RW 0 0-1 When HIGH, the rate detector is reset.

CH1RATEDETEN 1:1 RW 1 0-1 When HIGH, the rate detector is enabled.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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CH1RDET_REG273

CH1RATEDETRATEPER 3:0 RW 1000 0-15 Rate detector rate period (0.3µs to 13ms, 100µs

default).

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

RSVD 74 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 75 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 76 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH1SDO_REG177

CH1SDOSWING*3:0 RW 1010 0-15

Driver swing.

0-15: 100-850mVppd, default=10: 600mV.

Valid for below 10G operation.

CH1SDOSWING7:4 RW 1010 0-15

Driver swing.

0-15: 100-850mVppd, default=10: 600mV.

Valid for 10G to 14G operation.

CH1SDO_REG278

CH1SDOPERTCTRL* 1:0 RW 00 0-3

Rise time control.

0:18ps, 1 & 2:22ps, 3: 30ps for 450mVppd

swing. Valid for below 10G operation.

CH1SDOPECTRL* 4:2 RW 000 0-7

Pre-emphasis amplitude.

0: 1.3dB, 7: 6dB for 450mVppd swing.

Valid for below 10G operation.

RSVD 7:5 RW 000 0-7 Reserved. Do not change.

CH1SDO_REG379

CH1SDOPERTCTRL 1:0 RW 00 0-3

Rise time control.

0:18ps, 1 & 2:22ps, 3: 30ps for 450mVppd

swing.

Valid for 10G to 14G operation.

CH1SDOPECTRL 4:2 RW 000 0-31

Pre-emphasis amplitude.

0: 1.3dB, 7: 6dB for 450mVppd swing.

Valid for 10G to 14G operation.

CH1SDOMUTE 5:5 RW 0 0-1 When HIGH, mutes driver and maintains

common mode when not in auto mute mode.

CH1SDOAUTOMUTEEN 6:6 RW 1 0-1 When HIGH, enables muting the driver upon

LOS.

CH1SDOPWRDNONMUTE 7:7 RW 1 0-1 When HIGH, enables power-down on mute for

output stage.

RSVD 80 RSVD 7:0 RW 0000000 0-255 Reserved. Do not change.

RSVD 81 RSVD 7:0 RW 0000000 0-255 Reserved. Do not change.

RSVD 82 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 83 RSVD 7:0 RW 00000100 0-255 Reserved. Do not change.

RSVD 84 RSVD 70 RW 00000010 0-255 Reserved. Do not change.

RSVD 85 RSVD 7:5 RW 00000100 0-255 Reserved. Do not change.

RSVD 86 RSVD 7:0 RW 10000010 0-255 Reserved. Do not change.

RSVD 87 RSVD 7:0 RW 00101111 0-255 Reserved. Do not change.

RSVD 88 RSVD 7:0 RW 01010000 0-255 Reserved. Do not change.

SDO0_REG10 89 CH0SWINGSETLO 7:0 RW 00000000 0-255

Ch0 swing setting LSB. 0x0 = 0mVppd, 0xC8 =

400mVppd, 0x190 = 800mVppd swing.

Valid for below 10G operation.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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SDO0_REG11 90

CH0SWINGSETHI 1:0 RW 00 0-3

Ch0 swing setting MSB. 0x0 = 0mVppd, 0xC8 =

400mVppd, 0x190 = 800mVppd swing.

Valid for below 10G operation.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

RSVD 91 RSVD 7:0 RW 00011111 0-255 Reserved. Do not change.

RSVD 92 RSVD 7:0 RW 00011111 0-255 Reserved. Do not change.

RSVD 93 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 94 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 95 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 96 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 97 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 98 RSVD 7:0 RW 11110000 0-255 Reserved. Do not change.

RSVD 99 RSVD 7:0 RW 01010101 0-255 Reserved. Do not change.

RSVD 100 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH0SDO_REG25 101

RSVD 2:0 RW 000 0-7 Reserved. Do not change.

CH0SDOMUTE 3:3 RW 0 0-1 When HIGH, mutes driver and maintains

common mode when not in auto mute mode.

CH0SDOAUTOMUTEEN 4:4 RW 1 0-1 When HIGH, enables muting the driver upon

LOS.

CH0SDOPWRDNONMUTE 5:5 RW 1 0-1 When HIGH, enables power-down on mute for

output stage.

RSVD 7:6 RW 00 0-3 Reserved. Do not change.

RSVD 102 RSVD 7:0 RW 00010011 0-255 Reserved. Do not change.

RSVD 103 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 104 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 105 RSVD 7:0 RW 00000010 0-255 Reserved. Do not change.

RSVD 106 RSVD 7:0 RW 00000100 0-255 Reserved. Do not change.

RSVD 107 RSVD 7:0 RW 10000010 0-255 Reserved. Do not change.

RSVD 108 RSVD 7:0 RW 00101111 0-255 Reserved. Do not change.

RSVD 109 RSVD 7:0 RW 01010000 0-255 Reserved. Do not change.

SDO0_REG34 110 CH0SWINGSETLO 7:0 RW 00000000 0-255

Ch0 swing setting LSB. 0x0 = 0mVppd, 0xC8 =

400mVppd, 0x190 = 800mVppd swing.

Valid for 10G to 14G operation.

SDO0_REG35 111

CH0SWINGSETHI 1:0 RW 00 0-3

Ch0 swing setting MSB. 0x0 = 0mVppd, 0xC8 =

400mVppd, 0x190 = 800mVppd swing.

Valid for 10G to 14G operation.

RSVD 7:2 RW 000000 0-63 Reserved. Do not change.

RSVD 112 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 113 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 114 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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RSVD 115 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 116 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 117 RSVD 7:0 RW 11110000 0-255 Reserved. Do not change.

RSVD 118 RSVD 7:0 RW 11111010 0-255 Reserved. Do not change.

RSVD 119 RSVD 7:0 RW 11111010 0-255 Reserved. Do not change.

RSVD 120 RSVD 7:0 RW 00000001 0-255 Reserved. Do not change.

RSVD 121 RSVD 7:0 RW 01010000 0-255 Reserved. Do not change.

RSVD 122 RSVD 7:0 RW 01010000 0-255 Reserved. Do not change.

RSVD 123 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 124 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 125 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 126 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 127 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 128 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 129 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 130 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 131 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 132 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 133 RSVD 7:0 RO 00000000 0-255 Reserved. Do not change.

CH0FLT_REG1 134

CH0FAULTEN 0:0 RW 1 0-1 Enable all Ch0 Faults.

RSVD 5:1 RW 01111 0-31 Reserved. Do not change.

CH0FAULTCLEARSTATUS6:6 RW 0 0-1 When HIGH, clears the latched Ch0 fault status.

RSVD 7:7 RW 00-1 Reserved. Do not change.

RSVD 135 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

RSVD 136 RSVD 7:0 RW 11111111 0-255 Reserved. Do not change.

RSVD 137 RSVD 7:0 RW 11111111 0-255 Reserved. Do not change.

RSVD 138 RSVD 7:0 RW 11111111 0-255 Reserved. Do not change.

RSVD 139 RSVD 7:0 RW 00001111 0-255 Reserved. Do not change.

CH0FLT_REG7 140

RSVD 4:0 RO 00000 0-31 Reserved. Do not change.

CH0FAULTMUTE 5:5 RO 0 0-1 Hardware Fault mask.

CH0FAULTCH0FAULT 6:6 RO 0 0-1 Latched signal from CH0FAULT output pin of

Ch0Fault.

RSVD 7:7 RW 00-1 Reserved. Do not change.

RSVD 141 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

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ADC_REG0 142

ADCRESET 0:0 RW 1 0-1 Reset for the ADC.

ADCAUTOCONVEN 1:1 RW 1 0-1 When HIGH, enables auto conversion. Set LOW

for manual.

ADCJUSTLSB2:2RW10-1

When HIGH, justify towards LSB. LOW justifies

towards MSB.

ADCOFFMODE 3:3 RW 0 0-1

When LOW, offset is subtracted from the ADC

output. When HIGH, offset is added to the ADC

output.

NOTE: When HIGH, ADCOFFSETHI[7] is sign and

rest of the bits are magnitude. A sign value of 1

represents negative numbers.

RSVD 7:4 RW 0000 0-15 Reserved. Do not change.

ADC_REG1 143

ADCSRCSEL 3:0 RW 0000 0-15 Select input for ADC (see Section 3.7.1).

ADCOFFCALEN 7:4 RW 0000 0-15 Select source for offset calibration.

ADC_REG2 144

ADCRESOLUTION 2:0 RW 001 0-7 ADC resolution control: 0-7 -> 4b to 16b.

ADCCLKRATE 5:3 RW 101 0-7 ADC clock divide ratio.

RSVD 7:6 RW 00 0-3 Reserved. Do not change.

ADC_REG3 145

ADCSTARTCONV 0:0 RW 0 0-1 ADC start conversion.

RSVD 7:1 RW 0000000 0-127 Reserved. Do not change.

ADC_REG4 146

ADCDONECONV 0:0 RO 0 0-1 ADC conversion done flag.

RSVD 7:1 RW 0000000 0-127 Reserved. Do not change.

ADC_REG5 147 ADCOUTLO 7:0 RO 00000000 0-255 ADC output LOW MSB.

ADC_REG6 148 ADCOUTHI 7:0 RO 00000000 0-255 ADC output HIGH MSB.

ADC_REG7 149 ADCOFFSETLO 7:0 RW 00000000 0-255 ADC offset LSB, unsigned binary.

ADC_REG8 150 ADCOFFSETHI 7:0 RW 00000000 0-255 ADC offset MSB, unsigned binary

CH0PWRDN_REG1 151

CH0PDCH0PATH 0:0 RW 0 0-1 When HIGH, power-down for the entire Ch0

path.

CH0PDCH0CDR* 1:1 RW 00-1 When HIGH, power-down for the entire CDR.

Valid for below 10G operation.

CH0PDCH0CDR 2:2 RW 0 When HIGH, power-down for the entire CDR.

Valid for 10G to 14G operation.

CH0PDCH0SDO 3:3 RW 1 0-1 When HIGH, power-down for the entire driver.

RSVD 7:4 RW 0010 0-15 Reserved. Do not change.

CH0PWRDN_REG2 152

CH0PDEQ 0:0 RW 0 0-1 When HIGH, power-down for the equalizer.

CH0PDLOS1:1 RW 0 0-1 When HIGH, power-down for the LOS.

RSVD 7:2 RW 100000 0-63 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace

Equalization and Output De-Emphasis

Data Sheet

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Proprietary & Confidential

CH0PWRDN_REG3 153

CH0PDRATEDET 0:0 RW 1 0-1 When HIGH, power-down for rate detector.

CH0PDVEYEMON 1:1 RW 1 0-1 When HIGH, power-down for the Ch0 vertical

eye monitor.

CH0PDHEYEMON 2:2 RW 1 0-1 When HIGH, power-down for the Ch0

horizontal eye monitor.

CH0PDPKDET 3:3 RW 1 0-1 When HIGH, power-down for the Ch0 peak

detector.

RSVD 4:4 RW 10-1 Reserved. Do not change.

CH0PDCKDIVOUT 5:5 RW 1 0-1 When HIGH, power-down for the divided Ch0

clock divider.

RSVD 7:6 RW 01 0-3 Reserved. Do not change.

RSVD 154 RSVD 7:0 RW 00001111 0-255 Reserved. Do not change.

CH1PWRDN_REG0 155

CH1PDCH1PATH 0:0 RW 0 0-1 When HIGH, power-down for the entire Ch1

path.

CH1PDCH1CDR* 1:1 RW 00-1 When HIGH, power-down for the entire CDR.

Valid for below 10G operation.

CH1PDCH1CDR 2:2 RW 0 0-1 When HIGH, power-down for the entire CDR.

Valid for 10G to 14G operation.

CH1PDCH1SDO 3:3 RW 0 0-1 When HIGH, power-down the trace driver.

RSVD 7:4 RW 0001 0-15 Reserved. Do not change.

CH1PWRDN_REG1 156 RSVD 7:0 RW 00000000 0-255 Reserved. Do not change.

CH1PWRDN_REG2 157

CH1PDLA 0:0 RW 0 0-1 When HIGH, power-down for the LA.

RSVD 1:1 RW 10-1 Reserved. Do not change.

CH1PDLOS2:2 RW 0 0-1 When HIGH, power-down for the LOS.

RSVD 7:3 RW 00000 0-31 Reserved. Do not change.

CH1PWRDN_REG3 158

CH1PDRATEDET 0:0 RW 1 0-1 When HIGH, power-down for rate detector.

CH1PDVEYEMON 1:1 RW 1 0-1 When HIGH, power-down for the Ch1 vertical

eye monitor.

CH1PDHEYEMON 2:2 RW 1 0-1 When HIGH, power-down for the Ch1

horizontal eye monitor.

CH1PDPKDET 3:3 RW 1 0-1 When HIGH, power-down for the Ch0 peak

detector.

CH1PDDELMON 4:4 RW 1 0-1 When HIGH, power-down for the delay

monitor.

CH1PDCKDIVOUT 5:5 RW 1 0-1 When HIGH, power-down for the divided Ch1

clock divider.

RSVD 7:6 RW 01 0-3 Reserved. Do not change.

RSVD 159 RSVD 7:0 RW 00001111 0-255 Reserved. Do not change.

RSVD 160 RSVD 7:0 RW 00011111 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace

Equalization and Output De-Emphasis

Data Sheet

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Proprietary & Confidential

PWRDN_REG2 161

RSVD 0:0 RW 10-1 Reserved. Do not change.

PDPRBSGEN 1:1 RW 1 0-1 When HIGH, power-down the PRBS generator

and associated buffers.

PDPRBSCHK 2:2 RW 1 0-1 When HIGH, power-down the PRBS checker

and associated buffers.

PDTEMPSENSOR 3:3 RW 1 0-1 When HIGH, power-down the temperature

sensor(s).

PDSUPPLYSENSOR 4:4 RW 1 0-1 When HIGH, power-down the supply sensor.

PDADC5:5 RW 1 0-1 When HIGH, power-down the ADC.

RSVD 7:6 RW 00 0-3 Reserved. Do not change.

RSVD 162 to 195 RSVD 7:0 RW N/A 0-255 Reserved. Do not change.

Table 7-1: Configuration and Status Register Map (Continued)

AddressdParameter Name Bit

Position Access Reset ValuebValid

RangedFunction

NOTE: * Indicates bits for lower data rates (below 10G operation)

CANADA

Suite 320, 3553 31st St. N.W.

Calgary, Alberta T2L 2K7

Canada

Phone: +1 (403) 284-2672

Fax: +1 (905) 632-2055

415 Legget Drive, Suite 200

Kanata, Ontario K2K 2B2

Canada

Phone: +1 (613) 270-0458

Fax: +1 (613) 270-0429

GERMANY

Gennum Canada Limited

Niederlassung Deutschland

München, Germany

Phone: +49 89 309040 290

Fax: +49 89 309040 293

E-mail: gennum-germany@gennum.com

INDIA

#208(A), Nirmala Plaza,

Airport Road, Forest Park Square

Bhubaneswar 751009

India

Phone: +91 (674) 65304815

Fax: +91 (674) 259-5733

JAPAN KK

Shinjuku Green Tower Building 27F

6-14-1, Nishi Shinjuku

Shinjuku-ku, Tokyo, 160-0023

Japan

Phone: +81 (03) 3349-5501

Fax: +81 (03) 3349-5505

E-mail: gennum-japan@gennum.com

Web Site: http://www.gennum.co.jp

MEXICO

Venustiano Carranza 122 Int. 1

Centro, Aguascalientes

Mexico CP 20000

Phone: +1 (416) 848-0328

NORTH AMERICA WESTERN REGION

691 South Milpitas Blvd., Suite #200

Milpitas, CA 95035

United States

Phone: +1 (408) 934-1301

Fax: +1 (408) 934-1029

E-mail: naw_sales@gennum.com

NORTH AMERICA EASTERN REGION

4281 Harvester Road

Burlington, Ontario L7L 5M4

Canada

Phone: +1 (905) 632-2996

Fax: +1 (905) 632-2055

E-mail: nae_sales@gennum.com

TAI W AN

6F-4, No.51, Sec.2, Keelung Rd.

Sinyi District, Taipei City 11502

Taiwan R.O.C.

Phone: (886) 2-8732-8879

Fax: (886) 2-8732-8870

E-mail: gennum-taiwan@gennum.com

UNITED KINGDOM

South Building, Walden Court

Parsonage Lane,

Bishop’s Stortford Hertfordshire, CM23 5DB

United Kingdom

Phone: +44 1279 714170

Fax: +44 1279 714171

2, West Point Court, Great Park Road

Bradley Stoke, Bristol BS32 4PY

Great Britain

Phone: +44 1454 462200

Fax: +44 1454 462201

SNOWBUSH IP - A DIVISION OF GENNUM

439 University Ave. Suite 1700

Toronto, Ontario M5G 1Y8

Canada

Phone: +1 (416) 925-5643

Fax: +1 (416) 925-0581

E-mail: sales@snowbush.com

Web Site: http://www.snowbush.com

DATA SHEET

The product is in production. Gennum reserves the right to make changes to

the product at any time without notice to improve reliability, function or

design, in order to provide the best product possible.

GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace

Equalization and Output De-Emphasis

Data Sheet

55972 - 0 March 2012

74 of 74

Proprietary & Confidential

Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of

the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent

infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

www.gennum.com

GENNUM CORPORATE HEADQUARTERS

4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055

E-mail: sales@gennum.com www.gennum.com

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A

STATIC-FREE WORKSTATION