Data Sheet
April 1998
T7290A DS1/T1/CEPT/E1 Line Interface
Features
■
Fully integrated DS1/T1/CEPT/E1 line interface
■
F or use in systems that are compliant with CB119,
AT&T PUB 43801, AT&T PUB 43802, AT&T PUB
62411, TR-TSY-000170, TR-TSY-000009, ITU-T
G.703, G.735, G.823, and I.431 specifications
■
Dual-rail system interface
■
On-chip transmit equalization
■
On-chip jitter attenuator
■
Monolithic clock recovery with frequency-
acquisition aide
■
High jitter accommodation (>0.4 U.I.)
■
No external crystal required
■
Three clocking modes to accommodate multiple
system clocking requirements
■
Multiple link-status and alarm features
■
Microprocessor interface option
■
AIS (blue alarm) transmission
■
Loopback modes for fault isolation
■
Minimal external circuitry required
Description
The Lucent Technologies Microelectronics Group
T7290A DS1/T1/CEPT/E1 Line Interface is a fully
integrated line tr ansceiver capab le of operation at the
domestic DS1/T1 carrier rate (1.544 Mbits/s) or the
international CEPT/E1 rate (2.048 Mbits/s). The
T7290A device combines features found in existing
line-interface devices with additional desirable fea-
tures.
The on-chip, low-impedance output drivers provide
shaped waveforms to the transformer, guaranteeing
template conformance. The T7290A device inter-
f aces to the digital cross connect (DSX) at lengths up
to 655 feet during DS1 operation and interfaces to
line impedances of 75
Ω
or 120
Ω
during CEPT oper-
ation. The device line interface also can transmit
waveforms compatible with T1 lines.
The T7290A line interface provides phase-locked
loop clock recovery and data retiming on received
data. Also, on-chip, selectable jitter attenuation is
available. The jitter attenuator can be placed in the
receive or transmit data path. No external crystals
are required with the T7290A device.
Digital control circuitry allows for multiple loopbacks,
testing, and alarm status monitoring. A microproces-
sor interface option allows for either control via a
microprocessor or direct pin-selectable control
(hardware mode).
The T7290A device is manufactured by using a low-
power CMOS technology and is a v ailable in a 28-pin,
plastic SOJ package or a 28-pin, plastic DIP pack-
age.
Note
: Modification of an existing T7290 application
ma y be required when migrating to a T7290A-
based architecture. The functions of the TBS,
TSC, LP1, DLOS, and LOS pins have been
changed or modified. Please refer to the
T7290A Migration from T7290 section of this
data sheet.
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
2Lucent Technologies Inc.
Table of Contents
Contents Page
Features ................................................................................................................................................................... 1
Description................................................................................................................................................................ 1
Pin Information ......................................................................................................................................................... 4
Receiver ................................................................................................................................................................... 6
Data Interface....................................................................................................................................................... 6
Clock Recovery and Data Retiming...................................................................................................................... 6
Frequency-Acquisition Aide.................................................................................................................................. 6
Jitter...................................................................................................................................................................... 7
Data Patterns........................................................................................................................................................ 8
Loss of Signal....................................................................................................................................................... 8
Transmitter ............................................................................................................................................................... 8
Output Pulse Shape ............................................................................................................................................. 8
Output Pulse Generation.................................................................................................................................... 10
Jitter Attenuator...................................................................................................................................................... 11
Alarms and Maintenance........................................................................................................................................ 13
Digital Loss of Signal (DLOS)............................................................................................................................. 13
Output Loss of Signal (OUT-LOS)...................................................................................................................... 13
Jitter Attenuator Alarm (ESA) ............................................................................................................................. 14
Transmitter Short Circuit..................................................................................................................................... 14
AIS (Blue Signal) Generator............................................................................................................................... 14
Loopbacks .......................................................................................................................................................... 14
Microprocessor Interface.................................................................................................................................... 14
In-Circuit Testing ................................................................................................................................................ 14
Absolute Maximum Ratings.................................................................................................................................... 15
Handling Precautions ............................................................................................................................................. 15
Electrical Characteristics........................................................................................................................................ 16
Operating Conditions.......................................................................................................................................... 16
Timing Characteristics............................................................................................................................................ 17
Applications............................................................................................................................................................ 19
Line Termination................................................................................................................................................. 19
Outline Diagrams.................................................................................................................................................... 21
28-Pin, Plastic SOJ............................................................................................................................................. 21
28-Pin, Plastic DIP.............................................................................................................................................. 22
Ordering Information............................................................................................................................................... 22
T7290A Migration from T7290................................................................................................................................ 23
DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates....................................................... 23
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
3
Lucent Technologies Inc.
Description
(continued)
Figure 1. Block Diagram
5-2484(C)r.6
MODE1
MODE2
T1
R1
ALOS
ALOS
PLL
FREQ
ACQUISITION
EXCLK
DLOS
DLOS
DLOS
+
EXCLK
JITTER
ATTEN SCLK
MODE2 LP2
TPDATA,
TNDATA
TCLK
RPDATA,
RNDATA
RCLK
ESA
LP3
PULSE
EQUALIZER
EC1 EC2 EC3
LOSS OF
CLOCK BLUE
SIGNAL
TBS
UGRCLK
OUT-LOS
EXCLK
+
TRANSMIT
MONITOR TSC
T2
R2
TRI
DRIVERS
DECODE
µP
INTER-
FACE
TBS
EC1
EC2
EC3
MODE1
MODE2
EXCLK EXCLK
TBS
EC1
EC2
EC3
MODE1
MODE2
LOOPA
LOOPB
VDDA, GNDA
VDDD, GNDD
CS
LP1
LP2
LP3
IN-LOS
MODE1
+
LP1
UGRCLK
2
2
2
2
2
22
2
2
2
2
4
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
4Lucent Technologies Inc.
Pin Information
Figure 2. Pin Diagram
Table 1. Pin Descriptions
* I = input, O = output, I
u
= input with pull-up, I
d
= input with pull-down.
Pin Symbol Type
*
Name/Function
1, 27, 28 EC1, EC3, EC2 I
d
Equalizer/Rate Control 1—3.
Three control leads for selecting transmit
equalization.
2 TRI I
u
3-State (Active-Low).
This pin is set low to configure all output buffers into
a high-impedance state during in-circuit testing.
3V
DDA
—
5 V
±
5% Analog Supply.
The powerup rise time (0 V to 4.75 V) must be
less than 15 ms.
4 GND
A
—
Analog Ground.
5R1I
Receive Bipolar Ring.
Negative bipolar receive data.
6T1I
Receive Bipolar Tip.
Positive bipolar receive data.
7, 8 MODE2, MODE1 I
d
Mode Select 2 and 1.
Two control leads for selecting clock and data paths
through the jitter attenuator.
9, 10 LOOPB, LOOPA I
d
Loopback Control B and A.
Two control leads for selecting clock and data
loopback paths.
11 TBS I
d
Transmit Blue Signal (AIS).
This pin is set high to transmit the blue signal
(all 1s). A remote loopback (LP2) has priority over the transmit blue signal.
12 IN-LOS O
Input Loss of Signal.
This pin is set high if analog loss of signal at the
receiver inputs is detected or if digital loss of signal of the recovered data is
detected. IN-LOS can be tied directly to TBS to initiate a transmit b lue signal
upon loss of signal.
T7290A
1
2
3
5
6
7
8
10
11
12
13
14
4
9
24
23
22
21
20
19
18
17
16
15
EC1
VDDA
GNDA
R1
T1
MODE2
MODE1
LOOPB
LOOPA
TBS
OUT-LOS
IN-LOS
ESA
EC2
EC3
GNDD
VDDD
T2
RNDATA
RPDATA
TNDATA
TCLK
EXCLK
25
26
27
28
R2
RCLK
CS
TPDATA
TRI
5-1810 (F).a
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
5
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* I = input, O = output, I
u
= input with pull-up, I
d
= input with pull-down.
Pin Symbol Type
*
Name/Function
13 ESA O
Jitter Attenuator Alarm.
This pin is set high if the phase jitter of the incom-
ing signal exceeds the tolerance of the jitter attenuator's buffer. This may
result in a loss of receive data.
14 OUT-LOS O
Output Loss of Signal.
This pin is set high when either the transmit clock
(TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is
absent.
15 CS I
d
Chip Select for Microprocessor Interface (Active-Low).
CS loads data
into the de vice on its f alling edge and latches the data on its rising edge. CS
is set low for hardware mode.
16 EXCLK I
External Clock.
DS1/T1 clock signal (1.544 MHz
±
130 ppm) or CEPT/E1
clock signal (2.048 MHz
±
80 ppm) for transmit blue signal, jitter attenuator
calibration, and PLL acquisition aid. EXCLK must be an independent clock
to guarantee device performance for all specifications. This clock should be
continuously activ e (i.e ., ungapped and uns witched) and void of jitter f or the
above features to operate.
17 TCLK I
Transmit Clock.
DS1/T1 clock signal (1.544 MHz
±
130 ppm) or CEPT/E1
clock signal (2.048 MHz
±
80 ppm).
18 TPDATA I
Transmit Positive Data.
DS1/T1 (1.544 Mbits/s) or CEPT/E1
(2.048 Mbits/s) positive bipolar data.
19 TNDATA I
Transmit Negative Data.
DS1/T1 (1.544 Mbits/s) or CEPT/E1
(2.048 Mbits/s) negative bipolar data.
20 RCLK O
Receive Clock.
Recovered receive clock signal for the terminal equipment.
21 RPDATA O
Receive Positive Data.
DS1/T1 (1.544 Mbits/s) or CEPT/E1
(2.048 Mbits/s) recovered positive data (NRZ).
22 RNDATA O
Receive Negative Data.
DS1/T1 (1.544 Mbits/s) or CEPT/E1
(2.048 Mbits/s) recovered negative data (NRZ).
23 T2 O
Transmit Bipolar Tip.
Positive bipolar transmit data.
24 V
DDD
—
5 V
±
5% Digital Supply.
The powerup rise time (0 V to 4.75 V) must be
less than 15 ms.
25 R2 O
Transmit Bipolar Ring.
Negative bipolar transmit data.
26 GND
D
—
Digital Ground.
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
6Lucent Technologies Inc.
Receiver
Data Interface
The receive line-interface transmission format of the
T7290A device is alternate mark inversion (AMI). The
receive digital output format is dual-rail, nonreturn to
zero (NRZ). Receiver specifications are shown in
Table 2.
Clock Recovery and Data Retiming
The bipolar input signals from T1 and R1 are peak-
detected and sliced by the receiver front end. Timing
recovery is performed by a phase-locked loop (PLL)
that locks an internal free-running, current-controlled
oscillator (ICO) to the data-rate component. EC1, EC2,
and EC3 rate control inputs must be set appropriately
for DS1 or CEPT/E1 operation.
Frequency-Acquisition Aide
For robust operation, PLL is enhanced with a fre-
quency-acquisition capability. The frequency-acquisi-
tion circuitry is intended to guarantee proper phase
locking during start-up situations, such as powerup or
data activation. Once the T7290A device is phase-
locked to data, the frequency-acquisition mode is
not
activated unless a digital loss of signal occurs , in which
case RCLK is frequency-locked/phase-locked to
EXCLK. RCLK is always active and does not have any
instantaneous phase hits or discontinuities.
A continuously active (i.e., ungapped and unswitched)
reference clock must be present at EXCLK to enable
the frequency-acquisition circuitry. EXCLK must be an
independent reference such as an oscillator or system
clock for proper operation. The EXCLK cloc k frequency
must be 1.544 MHz
±
130 ppm for T1/DS1 operation or
2.048 MHz
±
80 ppm for CEPT/E1 operation.
Table 2. Receiver Specifications
* Values shown are for flat loss only. Receiver also meets ITU-T G.703 interface immunity test (6 dB cable loss with
–18 dB interference) for CEPT/E1 operation.
† Transfer characteristics (1/8 input).
‡ The maximum number of consecutive zeros = 15.
§ Return loss specifications according to ITU-T G.703/RC6367A (CEPT only).
Parameter Min Typ Max Unit
Receiver Sensitivity:*
DS1
CEPT 0.85
0.7 —
——
—
Vp
Vp
Analog LOS Level:
DS1
CEPT —
—0.48
0.28 —
—
Vp
Vp
PLL:
†
3 dB Bandwidth
Peaking
ICO Free-run Frequency Error
—
—
—
33
1.2
—
—
2
±
6
kHz
dB
%
Input Density (1s)
‡
12.5 — — %
Return Loss:
§
51 kHz—102 kHz
102 kHz—2.048 MHz
2.048 MHz—3.072 MHz
12
18
14
—
—
—
—
—
—
dB
dB
dB
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
7
Lucent Technologies Inc.
Receiver
(continued)
Jitter
PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in
noisy environments. PLL has a minimum input jitter tolerance exceeding all requirements shown in Figure 3. The
measured receiver jitter toler ance for DS1 and CEPT oper ation is also shown in Figure 3, with pseudorandom input
data (2
15
– 1) and with EXCLK synchronous with the data source. The receiver transfers incoming jitter to RCLK
with no more than 2 dB of gain at any frequency, which can be further reduced with the jitter attenuator.
Data Points (Hz, U.I.)
Figure 3. PLL Jitter Tolerance Requirements
ITU-T
G.823 TR-TSY-000170,
AT&T PUB
43801
TR-TSY-000009,
AT&T PUB
43802
AT&T
PUB
62411
AT&T
PUB
62411
Looped
Timed
Measured
Receiver DS1
Performance
(BER = 10
–6
)
Measured
Receiver CEPT
Performance
(BER = 10
–6
)
1, 2.9
20, 1.5
2.4k, 1.5
18k, 0.2
100k, 0.2
—
—
—
—
—
10, 300
10k, 0.3
50k, 0.3
—
—
—
—
—
—
—
10, 5
500, 5
8k, 0.1
40k, 0.1
—
—
—
—
—
—
1, 138
48, 138
10k, 0.2
100k, 0.2
—
—
—
—
—
—
1, 138
85, 138
10k, 0.4
100k, 0.4
—
—
—
—
—
—
2.0k, 6.51
5.0k, 2.03
8.0k, 1.12
10k, 0.97
15k, 0.84
20k, 0.66
30k, 0.52
40k, 0.49
70k, 0.48
100k, 0.48
2.0k, 9.43
5.0k, 2.84
8.0k, 1.70
10k, 1.38
15k, 1.00
20k, 0.84
30k, 0.57
40k, 0.48
70k, 0.47
100k, 0.47
5-1157(C)r.4
500.0
100.0
1.0
0.1
1 10 100 1000 10,000 100,000
JITTER FREQUENCY (Hz)
50.0
28.0
10.0
5.0
0.5
MEASURED
RECEIVER DS1
PERFORMANCE
(JITTER ATTENUATOR
NOT ACTIVE)
MEASURED RECEIVER
CEPT PERFORMANCE
(JITTER ATTENUATOR
NOT ACTIVE)
PEAK-TO-PEAK JITTER MAGNITUDE (U.I.)
MINIMUM JITTER
ATTENUATOR PERFORMANCE
ITU-T G.823
TR-TSY-000009,
PUB 43802
TRI-TSY-000170, PUB 43801
PUB 62411
PUB 62411 (LOOP TIMED)
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
8Lucent Technologies Inc.
Receiver
(continued)
Data Patterns
Any data pattern with a minimum long-term 1s density
of 12.5% with 15 or fewer consecutive 0s is allowed.
Loss of Signal
Both digital (DLOS) and analog (ALOS) loss-of-signal
detection is used in the T7290A device. The digital sig-
nal detector is described later under the Alarms and
Maintenance section. The analog signal detector uses
the output of the receiver peak detector to determine if
a signal is present at T1 and R1. If the input amplitude
drops below approximately 0.48 Vp for DS1/T1 opera-
tion or 0.28 Vp for CEPT/E1 operation, the analog
detector output becomes active . Hysteresis (250 mV) is
provided in the analog detector to eliminate ALOS
chattering. Either the analog or the digital detector sets
IN-LOS high.
The time required to detect analog loss of signal
(ALOS) depends on the incoming signal amplitude
before it disappears. Typical ALOS detection times are
given in Table 3.
Table 3. Typical ALOS Detection Times
Signal Amplitude
(Vp) Typical ALOS
Detection Time (ms)
3.6
2.5
1.7
1.0
5.0
3.7
2.8
1.4
T ransmitter
Output Pulse Shape
Transmitter specifications are shown in Table 4. The T1 pulse shape template is specified at the network interface
as shown in Figure 4. The DS1 pulse shape template is specified at the DSX and is illustrated in Figure 5. CEPT
transmit waveforms at the device output conform to the template shown in Figure 6.
Table 4. Transmitter Specifications
* In accordance with the interfaces described in the Line Termination section under Applications.
† Below the power at 772 kHz.
‡ Total power difference.
§
Percentage of the pulse amplitude and pulse width.
**
Percentage of the pulse amplitude.
†† Meets CH-PTT return loss specifications (CEPT only).
Parameter Min Typ Max Unit
Output Pulse Amplitude:*
T1
DS1 (at DSX)
CEPT (into 75
Ω
)
CEPT (into 120
Ω
)
2.7
2.4
2.13
2.7
3.0
3.0
2.37
3.0
3.3
3.6
2.61
3.3
V
V
V
V
Output Pulse Width:
T1
DS1
CEPT
279
330
219
324
350
244
369
370
269
ns
ns
ns
Output Power Levels:
T1 (3 kHz band at 772 kHz)
T1 (3 kHz band at 1544 kHz)
†
DS1 (2 kHz band at 772 kHz)
DS1 (2 kHz band at 1544 kHz)
†
12.0
–25
12.6
–29
16.5
–39
16.5
–39
19.0
—
17.9
—
dBm
dB
dBm
dB
Positive/Negative Pulse Imbalance:
DS1
‡
CEPT
§
—
—0.1
20.5
±5dB
%
CEPT Zero Level** — 1 10 %
Return Loss:††
51 kHz—102 kHz
102 kHz—2.048 MHz
2.048 MHz—3.072 MHz
8
14
10
—
—
—
—
—
—
dB
dB
dB
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
9Lucent Technologies Inc.
Transmitter (continued)
Output Pulse Shape (continued)
T1 Isolated-Pulse Corner Points According to
FCC Part 68
Note: Successive corner points are joined by straight lines.
Figure 4. T1 Isolated-Pulse Template
DSX-1 Pulse Template Corner Points According
to CB119
Note: Successive corner points are joined by straight lines.
Figure 5. DSX-1 Isolated-Pulse Template
Maximum Curve Minimum Curve
ns Normalized
Voltage ns Normalized
Voltage
0
242
325
325
425
500
675
728
1000
1250
—
—
0.05
0.05
0.80
1.20
1.20
1.05
1.05
0.05
0.05
0.05
—
—
0
350
350
400
500
600
650
650
800
896
1100
1250
–0.05
–0.05
0.50
0.90
0.95
0.90
0.50
–0.45
–0.45
–0.26
–0.05
–0.05
NORMALIZED AMPLITUDE (A)
1.0
0.5
0
–0.5
0 250 500 750 1000 1250
TIME (ns)
5-1604(F)r.3
Maximum Curve Minimum Curve
ns Normalized
Voltage ns Normalized
Voltage
0
250
325
325
425
500
675
725
1100
1250
—
—
0.05
0.05
0.80
1.15
1.15
1.05
1.05
–0.07
0.05
0.05
—
—
0
350
350
400
500
600
650
650
800
925
1100
1250
–0.05
–0.05
0.50
0.95
0.95
0.90
0.50
–0.45
–0.45
–0.20
–0.05
–0.05
NORMALIZED AMPLITUDE (A)
1.0
0.5
0
–0.5 0 250 500 750 1000 1250
TIME (ns)
5-1160(C)r.6
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
10 Lucent Technologies Inc.
Transmitter (continued)
Output Pulse Shape (continued)
Note: V corresponds to the nominal peak value.
Figure 6. ITU-T G.703 Pulse Template
Output Pulse Generation
The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal to a
balanced bipolar data signal (AMI format). Positive 1s are produced by a positive pulse on device pin T2, and neg-
ative 1s are produced b y a positiv e pulse on device pin R2. Binary 0s are conv erted to null pulses. All pulse shapes
are controlled on-chip according to equalizer control inputs, as defined in Table 5. Transmitter specifications are
shown in Table 4.
Table 5. Equalizer/Rate Control
*Distance to DSX in feet for 22-Ga. PIC (ABAM) cable (DS1 only). Use maximum loss figures for other cable types.
† dB at 772 kHz.
‡ According to FCC Part 68, Subpart D, Option A for 0 dB line build-out.
Service Clock
Rate Transmitter
Equalization*Maximum
Cable Loss†EC1 EC2 EC3
T1 1.544 MHz — 22‡000
DS1 1.544 MHz
0 ft.—131 ft. 0.6 0 0 1
131 ft.—262 ft. 1.2 0 1 0
262 ft.—393 ft. 1.8 0 1 1
393 ft.—524 ft. 2.4 1 0 0
524 ft.—655 ft. 3.0 1 0 1
CEPT 2.048 MHz 75 Ω— 110
120 Ω— 111
10%
488 ns
(244 + 244)
219 ns
(244 – 25)
10%
0%
NOMINAL PULSE
269 ns
(244 + 25)
20%
10%
10%
V = 100%
20%
50%
10% 10%
244 ns
194 ns
(244 – 50)
20%
5-3145(C)r.7
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
11Lucent Technologies Inc.
Jitter Attenuator
Jitter transfer functions describe the amount of jitter
that is transferred from the input to the output of the
specified equipment. The jitter transfer functions are
affected by the jitter attenuator circuitry, which can be
placed in the receive data path, placed in the transmit
data path, or bypassed. Placement of this circuit is con-
trolled as described in Table 6. The external clock
(EXCLK) must be present for the attenuation function
to operate. When attenuation is selected, the T7290A
device exhibits a jitter transfer function that has no
peaking and a single 3.6 Hz pole frequency (DS1) or
4.8 Hz pole frequency (CEPT). Figure 7 displays a typ-
ical DS1 jitter transf er function for a constant input jitter
amplitude of 2.0 U.I. peak-to-peak.
The amount of generated output jitter when no input jit-
ter is present is measured by using the scheme shown
in Figure 8. The jitter filters depicted represent the
AT&T PUB 62411 specification for a 1.544 MHz data
rate. The jitter produced at the labeled points does not
exceed the following peak-to-peak levels: 0.05 U.I. at
point 1, 0.025 U.I. at point 2, 0.025 U.I. at point 3, and
0.02 U.I. at point 4. A similar test can be performed for
ITU-T I.431 qualification at the 2.048 MHz data rate, in
which two jitter filters are 20 Hz—100 kHz (0.125 U.I.)
and 700 Hz—100 kHz (0.02 U.I.).
The jitter tolerance of the attenuator meets the require-
ments of the TR-TSY-000009, AT&T PUB 43802, and
ITU-T G.823 (see Figure 3). The attenuator also
ensures that jitter accommodation is a minimum of
28 U.I. peak-to-peak (DS1) or 40 U.I. peak-to-peak
(CEPT) (1 U.I. = 648 ns [T1/DS1] or 488 ns [CEPT])
during attenuation. The jitter attenuation function is
identical when placed in either transmit or receiv e path.
Ideally, the tolerance of the attenuator is ±32 bits
(64 U.I.). However, if ∆f (Hz) = frequency (EXCLK) –
frequency (input clock) and N = 23 (DS1) or 30.5
(CEPT), then the tolerance is degraded and equals:
Figure 9 shows the phase step response (DS1) of the
attenuator given ∆f. The response is based on a phase
offset (U.I.) generated by the read pointer of the buffer.
It is this phase offset that degrades the attenuator's tol-
erance.
64 2 RND–UP ABS ∆f
()
N
------------------------- 1+
×– (U.I.)
Data Points (Hz, dB)
Figure 7. Jitter Transfer Function of the Jitter Attenuator
TR-TSY-000009,
AT&T PUB 43802 ITU-T G.735,
ITU-T I.431
1, 0.1
350, 0.1
2.5k, –33.6
15k, –49.2
10, 0.5
40, 0.5
400, –19.5
15k, –19.5
5-1311(C)r.4
JITTER ATTENUATION (dB)
0
–10
–20
–30
1 10 40 100 2.5k 15k
JITTER FREQUENCY (Hz)
–40
–50
–60
–70 350 1k 10k
400
20 dB/
DECADE
TYPICAL
PERFORMANCE
20 dB/DECADE
20 dB/DECADE
40 dB/DECADE
ITU-T G.735,
ITU-T I.431
TR-TSY-
000009,
PUB 43802
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
12 Lucent Technologies Inc.
Jitter Attenuator (continued)
When the T7290A device is used only as a jitter attenuator, loopback 1 (LP1) should be active and the attenuator
must be placed in the transmit path (MODE1:2 = 01).
Table 6. Connectivity of Jitter Attenuator
* The jitter attenuator must be enabled after VDD exceeds 4.75 V during device powerup.
† Jitter attenuator is powered down during this mode (see Table 8 under the Electrical Characteristics section).
‡ Not used for normal operation.
Figure 8. Measurement of Generated Jitter
Connectivity of Jitter Attenuator*MODE1 MODE2
Bypass†00
Transmit Path 0 1
Receive Path 1 0
Test Mode‡11
MEASURED
SIGNAL
FILTERS
(SLOPES MUST BE
20 dB PER DECADE)
JITTER
DETECTOR
10 Hz 8 kHz
8 Hz 40 kHz
(700 Hz) (100 kHz)
10 Hz 40 kHz
(20 Hz) (100 kHz)
4
3
2
1
PEAK
DETECTOR
TRUE RMS
VOLTMETER
TO EACH POINT
TO EACH POINT
SPECTRUM
ANALYZER
5-1163(F)r.2
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
13Lucent Technologies Inc.
Jitter Attenuator (continued)
Figure 9. Jitter Attenuator Phase Response
0 50 100 150
TIME (ms)
READ COUNTER OFFSET (U.I.)
20
15
10
5
0
PHASE STEP RESPONSE (I∆fI = 0 → 400 Hz)
5-2485(C)r.3
Alarms and Maintenance
Digital Loss of Signal (DLOS)
A digital loss of signal (DLOS = 1) is indicated if 128 or
more consecutive 0s occur in the receive data stream
during DS1/T1 operation. During CEPT operation, a
DLOS is indicated when 32 or more consecutive 0s
occur in the receive data stream. DLOS is then deacti-
vated when the ones density exceeds 12.5% and there
are no more than 15 consecutive 0s (T1, DS1, and
CEPT), signifying the return of good signal. DLOS
deactivation monitors the data in fixed 32-bit windows.
Each window must have at least four 1s with no more
than 15 consecutive 0s. Consecutive 0s are also moni-
tored across the window boundary. This condition m ust
persist for two consecutive 32-bit windows, at which
time DLOS is deactivated at the end of the window.
Upon DLOS detection, RCLK is phase-locked to the
external clock (EXCLK) so that other system devices
slaved to the line clock continue to operate without
instantaneous phase hits or discontinuities. Either an
analog loss of signal (ALOS) or a digital loss of signal
(DLOS) activates the IN-LOS output pin.
Output Loss of Signal (OUT-LOS)
An output loss of signal (OUT-LOS = 1) is indicated if
either the transmit cloc k (TCLK) or the smoothing clock
(SCLK) output of the jitter attenuator is absent. If the jit-
ter attenuator is placed in the transmit path, SCLK is
monitored. If the jitter attenuator is not used in the
transmit path, TCLK is monitored. For every ten clock
periods of the PLL oscillator clock, denoted as
UGRCLK in Figure 1, a strobe is generated. If a single
transmit clock period occurs between strobes, then
OUT-LOS = 0. If no transmit clock period occurs
between strobes, then OUT-LOS = 1, and the output
drivers (T2 and R2) are placed into a high-impedance
state and no data is transmitted. UGRCLK is always
present, even in the absence of both EXCLK and
T1/R1 input data; therefore, UGRCLK is the most suit-
able clock for monitoring OUT-LOS.
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
14 Lucent Technologies Inc.
Alarms and Maintenance (continued)
Jitter Attenuator Alarm (ESA)
A jitter attenuator alarm (ESA = 1) is indicated if the
phase jitter exceeds the tolerance of the jitter attenua-
tor. Bit errors occur when ESA is active. This signal is
asserted until error-free operation resumes. See
Figure 9 to determine the tolerance limits of the attenu-
ator.
Transmitter Short Circuit
A transmitter monitor is provided to detect nonfunction-
ing links and protect the device from damage. If one of
the transmitter's line drivers (T2 or R2) is shorted to the
power supply or ground, or if T2 and R2 are shorted
together, internal circuitry protects the device from
damage. After 35 transmit clock cycles, the transmitter
is powered up in its normal operating mode. The driv ers
attempt to correctly transmit the next data bit (+1, 0, or
–1). If the short is still present, the transmitter is again
internally protected for 35 transmit clock cycles. This
process is continuously repeated until the short has dis-
appeared. The TSC alarm is not available off-chip.
AIS (Blue Signal) Generator
When the transmit b lue signal is set (TBS = 1), a contin-
uous stream of bipolar 1s is transmitted onto the line
synchronous with EXCLK. The TPDATA and TNDATA
inputs are ignored during this mode. If the IN-LOS
output is externally connected to the TBS input, an
IN-LOS error initiates a transmit blue signal as long as
IN-LOS = 1. Also, TBS input is ignored when a remote
loopback is selected. There is no microprocessor inter-
face for the TBS input, i.e., any change on the TBS pin
is fed directly into the device and is not impeded by the
CS function.
Loopbacks
The T7290A device has three independent loopback
paths, which are activated as shown in Table 7.
A local loopback (LP1) connects the jitter attenuator's
output clock and data to the receive clock and data out-
put pins. MODE1:2 = 01 must be selected for this loop-
back to operate (jitter attenuator in the transmit path).
Valid transmit output data continues to be sent to the
network. However, if the transmit blue is initiated
(TBS = 1), an all-1s signal is sent to the network and
does not corrupt the looped data. The IN-LOS alarm still
monitors the entire receive function.
A remote loopback (LP2) loops the recovered clock and
retimed data into the transmitter and back onto the line.
The receive front end, receive PLL, jitter attenuator (if
engaged), and transmit driver circuitry are all exercised.
The transmit clock, transmit data, and TBS inputs are
ignored. Valid receive output data continues to be sent
to RPD ATA and RND ATA. This loop can be used to isolate
failures between systems.
A digital local loopback (LP3) directly loops the transmit
clock and data to the receive clock and data output pins.
The blue signal can be tr ansmitted when in this loopback.
LP3 (rather than LP1) must be selected if MODE2 = 0.
Table 7. Loopback Control
* TBS is ignored.
Microprocessor Interface
A chip-select input (CS) configures the device in either
hardware mode or microprocessor mode . The chip-select
function applies to the f ollowing inputs: MODE1, MODE2,
EC1, EC2, EC3, LOOPA, and LOOPB. In the hardware
mode, any change on these asynchronous input pins is
fed directly into the device. To maintain hardware mode,
set CS = 0. In the microprocessor mode, new digital con-
trol inputs are loaded into the T7290A device on the fall-
ing edge of CS and are latched on the rising edge of CS.
Figure 11 shows a timing diagram of this function.
Note that there are special requirements only when using
microprocessor mode. For example, the state of the input
should not change while CS = 0. Also, the state of the
internal latch is undefined (unknown to the user) until the
first falling edge of CS is encountered.
In-Circuit T esting
The device has the ability to allow for in-circuit testing by
activating the high-impedance mode (TRI = 0). During
this mode, all output buffers (T2, R2, RCLK, RPDATA,
RNDATA, IN-LOS, ESA, and OUT-LOS) are 3-stated.
During the 3-stated condition, the absolute maximum
voltage ratings must not be exceeded on any pin.
Operation Symbol LOOPA LOOPB
Normal — 0 0
Digital Local Loopback LP3 0 1
Remote Loopback LP2* 1 0
Local Loopback LP1 1 1
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
15Lucent Technologies Inc.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These
are absolute stress ratings only. Functional oper ation of the de vice is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
External leads can be soldered safely at temperatures up to 300 °C.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be tak en to a v oid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM)
and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been
adopted f or the CDM. Howe ver, a standard HBM (resistance = 1500 Ω, capacitance = 1000 pF) is widely used and,
therefore, can be used for comparison purposes. The HBM ESD threshold presented here is obtained by using
these circuit parameters:
Parameter Symbol Min Max Unit
dc Supply Voltage Range VDD –0.5 6.5 V
Power Dissipation PD— 500 mW
Storage Temperature Tstg –65 125 °C
Maximum Voltage (any pin) with Respect to VDD — — 0.5 V
Minimum Voltage (any pin) with Respect to GND — –0.5 — V
Maximum Allowable Voltages (T1, R1) with Respect to GND — –5.0 5.0 V
Human-Body Model ESD Threshold
Device Voltage
T7290A-EL >1200 V
T7290A-PL >1200 V
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
16 Lucent Technologies Inc.
Electrical Characteristics
Operating Conditions
–40 °C ≤ T A ≤ +85 °C, VDD = 5 V ± 5%, except as noted. VDD rise time (0 V to 4.75 V) must be less than 15 ms.
Table 8. Power Specifications
* Conditions with 50% 1s on the transmit side, TA = 25 °C, VDD = 5 V.
† Equalizer settings: EC1 = 0, EC2 = 1, EC3 = 1.
Table 9. Logic Interface Characteristics
An internal pull-up device is provided on the TRI lead. Internal pull-down devices are provided on the following
leads: CS , MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, and LOOPB . The internal pull-up or pull-down de vices
require the input to source or sink no more than 20 µA.
Parameter Symbol Min Typ Max Unit
Power Dissipation:*
Without Jitter Attenuator:
T1
DS1†
CEPT (75 Ω)
CEPT (120 Ω)
With Jitter Attenuator:
T1
DS1†
CEPT (75 Ω)
CEPT (120 Ω)
PD
—
—
—
—
—
—
—
—
125
132
126
120
165
172
174
168
131
139
132
126
173
181
183
176
mW
mW
mW
mW
mW
mW
mW
mW
Parameter Symbol Min Max Unit
Input Voltage:
Low
High VIL
VIH GNDD
2.0 0.8
VDDD V
V
Output Voltage:
Low
High VOL
VOH GNDD
2.4 0.4
VDDD V
V
Input Capacitance CI—20pF
Load Capacitance CL—40pF
Source Current Isource — 4.9 mA
Sink Current Isink — 4.9 mA
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
17Lucent Technologies Inc.
Timing Characteristics
All duty-cycle and timing relationships for receive and transmit data signals are referenced to a TTL, 1.4 V
threshold level. Figure 10 shows this timing.
Table 10. Interface Data Timing (See Figure 10.)
* A tolerance of ±130 ppm.
† A tolerance of ±80 ppm.
Figure 10. Interface Data Timing
Symbol Parameter Min Typ Max Unit
— TCLK Duty Cycle 40 50 60 %
tTCLTCL
TCLK Clock Period:
DS1/T1
CEPT
*
†647.7
488
*
†ns
ns
tTDVTCL Transmit Data Setup Time 50 — — ns
tTCLTDX Transmit Data Hold Time 40 — — ns
tTCH1TCH2 Clock Rise Time (10%—90%) — — 40 ns
tTCL2TCL1 Clock Fall Time (10%—90%) — — 40 ns
tRDVRCH Receive Data Setup Time 140 — — ns
tRCHRDX Receive Data Hold Time 180 — — ns
tRCLRDV Receive Propagation Delay — — 40 ns
TCLK
TPDATA
OR
TNDATA
RCLK
RPDATA
OR
RNDATA
tTCLTCL tTCH1TCH2
tTCL2TCL1
tTDVTCL tTCLTDX
tRCLRDV
tRDVRCH tRCHRDX
5-1156(C)r.8
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
18 Lucent Technologies Inc.
Timing Characteristics (continued)
Table 11. Microprocessor Interface Timing (See Figure 11.)
Figure 11. Microprocessor Interface Timing
Symbol Parameter Min Max Unit
tSVCSL Control Signal Setup Time 50 — ns
tCSLCSH Control Signal Pulse Width Time 40 — ns
tCSHSX Control Signal Hold Time 40 — ns
tCSH1CSH2 Control Signal Rise Time (10%—90%) — 40 ns
tCSL2CSL1 Control Signal Rise Time (10%—90%) — 40 ns
tCSL2CSL1 tCSH1CSH2
tCSLCSH
tSVCSL tCSHSX
MODE1
MODE2
EC1
EC2
EC3
LOOPA
LOOPB
CS
5-1165(F)r.4
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
19Lucent Technologies Inc.
Applications
Line Termination
For the following applications (shown in Figures 12—15), the Lucent 2741 and 2745 Series transformers are rec-
ommended. The same transformers used for the T7290 device can be used for the T7290A device. The tolerance
of all transf ormer turns ratios is a maximum of ±2%. The tolerance of all resistors in the tr ansmit path (excluding the
cable termination) is a maximum of ±1%.
Figure 12. DS1 Application for Twisted-Pair Interface
Figure 13. T1 Application Diagram
RECEIVE DATA
+5 V
1 µF
RPDATA
RNDATA
RCLK
VDDD
VDDA
GNDD
GNDA
TPDATA
TNDATA
TCLK
T1
R1
T2
R2
500 Ω
500 Ω
200 Ω
1:2
TRANSMIT DATA
1.08:1
LOAD
100 Ω
RECEIVE
INPUT
TRANSMIT
OUTPUT
T7290A
5-1152(C)r.6
T7290A
RECEIVE DATA
+5 V
1 µF
RPDATA
RNDATA
RCLK
VDDD
VDDA
GNDD
GNDA
TPDATA
TNDATA
TCLK
T1
R1
T2
R2
1:2
TRANSMIT DATA
1.36:1
21.5 Ω
21.5 Ω
LOAD
100 Ω
RECEIVE
INPUT
TRANSMIT
OUTPUT
LBO/
EQUAL-
IZER
WAVEFORM MEETS FIGURE 3
TEMPLATE AT THIS POINT
FOR 0 dB LINE BUILD-OUT.
5-1153(C)
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
20 Lucent Technologies Inc.
Applications (continued)
Line Termination (continued)
Figure 14. CEPT Application for Twisted-Pair Interface
Figure 15. CEPT Application for Coaxial Interface
RECEIVE DATA
+5 V
1 µF
RPDATA
RNDATA
RCLK
VDDD
VDDA
GNDD
GNDA
TPDATA
TNDATA
TCLK
T1
R1
T2
R2
866 Ω
866 Ω
200 Ω
1:2
TRANSMIT DATA
1.36:1
LOAD
120 Ω
RECEIVE
INPUT
TRANSMIT
OUTPUT
26.1 Ω
26.1 Ω
T7290A
5-1154(C)
RECEIVE DATA
+5 V
1 µF
RPDATA
RNDATA
RCLK
VDDD
VDDA
GNDD
GNDA
TPDATA
TNDATA
TCLK
T1
R1
T2
R2
270 Ω
270 Ω
200 Ω
1:2
TRANSMIT DATA
1.36:1
LOAD
75 Ω
RECEIVE
INPUT
TRANSMIT
OUTPUT
15.4 Ω
15.4 Ω
T7290A
5-1155(C)r.6
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
21Lucent Technologies Inc.
Outline Diagrams
28-Pin, Plastic SOJ
Dimensions are in millimeters.
Number of
Pins (N) Package Dimensions (SOJ)
Maximum Length
Including Leads (L) Maximum Width
Without Leads (B) Maximum Width
Including Leads (W) Maximum Height
Above Board (H)
28 18.03 7.62 8.81 3.18
5-4413(C).r4
N
1
B
PIN #1 IDENTIFIER ZONE
L
0.51 MAX
H
0.79 MAX
0.10
SEATING PLANE
1.27 TYP
W
Data Sheet
T7290A DS1/T1/CEPT/E1 Line Interface April 1998
22 Lucent Technologies Inc.
Outline Diagrams (continued)
28-Pin, Plastic DIP
Dimensions are in millimeters.
Ordering Information
Number of
Pins (N) Package Dimensions (DIP)
Maximum Length
Including Leads (L) Maximum Width
Without Leads (B) Maximum Width
Including Leads (W) Maximum Height
Above Board (H)
28 37.34 13.97 15.49 5.59
Device Code Package Temperature Comcode
(Ordering Number)
T - 7290A - - PL 28-Pin DIP –40 °C to +85 °C 106785645
T - 7290A - - EL 28-Pin SOJ –40 °C to +85 °C 106785637
5-4410(C).r2
W
H
0.58 MAX2.54 TYP
0.38 MIN
SEATING PLANE
N
1
PIN #1 IDENTIFIER ZONE
L
B
Data Sheet
April 1998 T7290A DS1/T1/CEPT/E1 Line Interface
23Lucent Technologies Inc.
T7290A Migration from T7290
The T7290A is a replacement for the T7290 family of devices that includes the T7290-EL, T7290-PL, T7290-EL2,
and T7290-PL2. The following list describes the functional changes made to the T7290 to produce the
T7290A. Modification of an existing T7290 application may be required.
■The TBS input of the T7290A directly controls the TBS function. The TBS function of the T7290 is gated by chip
select (CS).
■The transmitter short circuit (TSC) output alarm has been eliminated; however, the transmit drivers are still pow-
ered down under short-circuit conditions. The pin is renamed as output loss of signal (OUT-LOS) and indicates
when either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent.
■Loopback 1 (LP1) has been modified to route signals through the jitter attenuator only. The MODE2 pin must be
set high for this loopback to operate (jitter attenuator on).
■The digital loss-of-signal (DLOS) functionality is now compatible for use in systems that must be compliant with
Bellcore TR-TSY-000009.
■The loss-of-signal (LOS) output indication is renamed as input loss of signal (IN-LOS) and is now the ORed func-
tion of analog loss of signal (ALOS) and digital loss of signal (DLOS) regardless of the loopback setting.
■The frequency acquisition mode is enabled when a digital loss-of-signal (DLOS) condition occurs , in which case
the receive clock (RCLK) is frequency-locked/phase-locked to the external clock (EXCLK).
■Improved ITU-T G.703 interference immunity for CEPT mode operation.
DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates
1. Page 3, Figure 1, Block Diagram, updated.
2. Page 21, 28-Pin, Plastic SOJ, changed dimensions to millimeters.
3. Page 22, 28-Pin, Plastic DIP, changed dimensions to millimeters.
4. Page 22, corrected Device Code.
T7290A DS1/T1/CEPT/E1 Line Interface Data Sheet
April 1998
Copyright © 1998 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
April 1998
DS98-190TIC (Replaces DS97-197TIC) Printed On
Recycled Paper
Lucent Technologies Inc. reserves the right to make changes to the product(s) or infor mation contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road,
Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell),
FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY : (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
