Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Features Fully integrated DS1/T1/CEPT/E1 line interface For use in systems that are compliant with CB119, AT&T PUB 43801, AT&T PUB 43802, AT&T PUB 62411, TR-TSY-000170, TR-TSY-000009, ITU-T G.703, G.735, G.823, and I.431 specifications Dual-rail system interface On-chip transmit equalization On-chip jitter attenuator Monolithic clock recovery with frequencyacquisition aide High jitter accommodation (>0.4 U.I.) No external crystal required Three clocking modes to accommodate multiple system clocking requirements Multiple link-status and alarm features Microprocessor interface option AIS (blue alarm) transmission Loopback modes for fault isolation Minimal external circuitry required Description The Lucent Technologies Microelectronics Group T7290A DS1/T1/CEPT/E1 Line Interface is a fully integrated line transceiver capable of operation at the domestic DS1/T1 carrier rate (1.544 Mbits/s) or the international CEPT/E1 rate (2.048 Mbits/s). The T7290A device combines features found in existing line-interface devices with additional desirable features. The on-chip, low-impedance output drivers provide shaped waveforms to the transformer, guaranteeing template conformance. The T7290A device interfaces to the digital cross connect (DSX) at lengths up to 655 feet during DS1 operation and interfaces to line impedances of 75 or 120 during CEPT operation. The device line interface also can transmit waveforms compatible with T1 lines. The T7290A line interface provides phase-locked loop clock recovery and data retiming on received data. Also, on-chip, selectable jitter attenuation is available. The jitter attenuator can be placed in the receive or transmit data path. No external crystals are required with the T7290A device. Digital control circuitry allows for multiple loopbacks, testing, and alarm status monitoring. A microprocessor interface option allows for either control via a microprocessor or direct pin-selectable control (hardware mode). The T7290A device is manufactured by using a lowpower CMOS technology and is available in a 28-pin, plastic SOJ package or a 28-pin, plastic DIP package. Note: Modification of an existing T7290 application may be required when migrating to a T7290Abased architecture. The functions of the TBS, TSC, LP1, DLOS, and LOS pins have been changed or modified. Please refer to the T7290A Migration from T7290 section of this data sheet. T7290A DS1/T1/CEPT/E1 Line Interface Data Sheet April 1998 Table of Contents Contents Page Features ................................................................................................................................................................... 1 Description................................................................................................................................................................ 1 Pin Information ......................................................................................................................................................... 4 Receiver ................................................................................................................................................................... 6 Data Interface ....................................................................................................................................................... 6 Clock Recovery and Data Retiming...................................................................................................................... 6 Frequency-Acquisition Aide.................................................................................................................................. 6 Jitter...................................................................................................................................................................... 7 Data Patterns........................................................................................................................................................ 8 Loss of Signal ....................................................................................................................................................... 8 Transmitter ............................................................................................................................................................... 8 Output Pulse Shape ............................................................................................................................................. 8 Output Pulse Generation .................................................................................................................................... 10 Jitter Attenuator ...................................................................................................................................................... 11 Alarms and Maintenance........................................................................................................................................ 13 Digital Loss of Signal (DLOS)............................................................................................................................. 13 Output Loss of Signal (OUT-LOS)...................................................................................................................... 13 Jitter Attenuator Alarm (ESA) ............................................................................................................................. 14 Transmitter Short Circuit..................................................................................................................................... 14 AIS (Blue Signal) Generator ............................................................................................................................... 14 Loopbacks .......................................................................................................................................................... 14 Microprocessor Interface .................................................................................................................................... 14 In-Circuit Testing ................................................................................................................................................ 14 Absolute Maximum Ratings.................................................................................................................................... 15 Handling Precautions ............................................................................................................................................. 15 Electrical Characteristics ........................................................................................................................................ 16 Operating Conditions.......................................................................................................................................... 16 Timing Characteristics ............................................................................................................................................ 17 Applications ............................................................................................................................................................ 19 Line Termination................................................................................................................................................. 19 Outline Diagrams.................................................................................................................................................... 21 28-Pin, Plastic SOJ............................................................................................................................................. 21 28-Pin, Plastic DIP.............................................................................................................................................. 22 Ordering Information............................................................................................................................................... 22 T7290A Migration from T7290................................................................................................................................ 23 DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates....................................................... 23 2 Lucent Technologies Inc. Lucent Technologies Inc. R1 T1 ALOS R2 T2 TRANSMIT MONITOR ALOS TSC TRI + DRIVERS OUT-LOS 2 TBS EXCLK UGRCLK LOSS OF CLOCK PULSE EQUALIZER EC1 EC2 EC3 DLOS FREQ ACQUISITION PLL 2 DLOS DLOS 2 LP1 LP2 LP3 EXCLK BLUE SIGNAL 2 2 2 2 2 DECODE TBS EC1 EC2 EC3 MODE1 MODE2 MODE2 JITTER ATTEN EXCLK UGRCLK MODE1 MODE2 + LP2 SCLK MODE1 + LP1 P INTERFACE EXCLK 2 4 2 LP3 2 VDDA, GNDA VDDD, GNDD CS EXCLK TBS EC1 EC2 EC3 MODE1 MODE2 LOOPA LOOPB TCLK TPDATA, TNDATA ESA RCLK RPDATA, RNDATA IN-LOS Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Description (continued) 5-2484(C)r.6 Figure 1. Block Diagram 3 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Pin Information EC1 1 28 EC2 TRI 2 27 EC3 VDDA 3 26 GNDD GNDA 4 25 R2 R1 5 24 VDDD T1 23 MODE2 6 7 22 T2 RNDATA MODE1 8 21 RPDATA LOOPB 9 20 RCLK LOOPA 10 19 TNDATA TBS 11 18 TPDATA IN-LOS 12 17 TCLK ESA 13 16 EXCLK OUT-LOS 14 15 CS T7290A 5-1810 (F).a Figure 2. Pin Diagram Table 1. Pin Descriptions Pin 1, 27, 28 Symbol EC1, EC3, EC2 Type* Name/Function Id Equalizer/Rate Control 1--3. Three control leads for selecting transmit equalization. 2 TRI Iu 3 VDDA -- 4 5 6 7, 8 GNDA R1 T1 MODE2, MODE1 -- I I Id 9, 10 LOOPB, LOOPA Id 11 TBS Id 12 IN-LOS O 3-State (Active-Low). This pin is set low to configure all output buffers into a high-impedance state during in-circuit testing. 5 V 5% Analog Supply. The powerup rise time (0 V to 4.75 V) must be less than 15 ms. Analog Ground. Receive Bipolar Ring. Negative bipolar receive data. Receive Bipolar Tip. Positive bipolar receive data. Mode Select 2 and 1. Two control leads for selecting clock and data paths through the jitter attenuator. Loopback Control B and A. Two control leads for selecting clock and data loopback paths. Transmit Blue Signal (AIS). This pin is set high to transmit the blue signal (all 1s). A remote loopback (LP2) has priority over the transmit blue signal. Input Loss of Signal. This pin is set high if analog loss of signal at the receiver inputs is detected or if digital loss of signal of the recovered data is detected. IN-LOS can be tied directly to TBS to initiate a transmit blue signal upon loss of signal. * I = input, O = output, Iu = input with pull-up, Id = input with pull-down. 4 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin 13 Symbol ESA Type* Name/Function O Jitter Attenuator Alarm. This pin is set high if the phase jitter of the incoming signal exceeds the tolerance of the jitter attenuator's buffer. This may result in a loss of receive data. O Output Loss of Signal. This pin is set high when either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent. 14 OUT-LOS 15 CS Id 16 EXCLK I 17 TCLK I 18 TPDATA I 19 TNDATA I 20 21 RCLK RPDATA O O 22 RNDATA O 23 24 T2 VDDD O -- 25 26 R2 GNDD O -- Chip Select for Microprocessor Interface (Active-Low). CS loads data into the device on its falling edge and latches the data on its rising edge. CS is set low for hardware mode. External Clock. DS1/T1 clock signal (1.544 MHz 130 ppm) or CEPT/E1 clock signal (2.048 MHz 80 ppm) for transmit blue signal, jitter attenuator calibration, and PLL acquisition aid. EXCLK must be an independent clock to guarantee device performance for all specifications. This clock should be continuously active (i.e., ungapped and unswitched) and void of jitter for the above features to operate. Transmit Clock. DS1/T1 clock signal (1.544 MHz 130 ppm) or CEPT/E1 clock signal (2.048 MHz 80 ppm). Transmit Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) positive bipolar data. Transmit Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) negative bipolar data. Receive Clock. Recovered receive clock signal for the terminal equipment. Receive Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) recovered positive data (NRZ). Receive Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT/E1 (2.048 Mbits/s) recovered negative data (NRZ). Transmit Bipolar Tip. Positive bipolar transmit data. 5 V 5% Digital Supply. The powerup rise time (0 V to 4.75 V) must be less than 15 ms. Transmit Bipolar Ring. Negative bipolar transmit data. Digital Ground. * I = input, O = output, Iu = input with pull-up, Id = input with pull-down. Lucent Technologies Inc. 5 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Receiver Frequency-Acquisition Aide Data Interface For robust operation, PLL is enhanced with a frequency-acquisition capability. The frequency-acquisition circuitry is intended to guarantee proper phase locking during start-up situations, such as powerup or data activation. Once the T7290A device is phaselocked to data, the frequency-acquisition mode is not activated unless a digital loss of signal occurs, in which case RCLK is frequency-locked/phase-locked to EXCLK. RCLK is always active and does not have any instantaneous phase hits or discontinuities. The receive line-interface transmission format of the T7290A device is alternate mark inversion (AMI). The receive digital output format is dual-rail, nonreturn to zero (NRZ). Receiver specifications are shown in Table 2. Clock Recovery and Data Retiming The bipolar input signals from T1 and R1 are peakdetected and sliced by the receiver front end. Timing recovery is performed by a phase-locked loop (PLL) that locks an internal free-running, current-controlled oscillator (ICO) to the data-rate component. EC1, EC2, and EC3 rate control inputs must be set appropriately for DS1 or CEPT/E1 operation. A continuously active (i.e., ungapped and unswitched) reference clock must be present at EXCLK to enable the frequency-acquisition circuitry. EXCLK must be an independent reference such as an oscillator or system clock for proper operation. The EXCLK clock frequency must be 1.544 MHz 130 ppm for T1/DS1 operation or 2.048 MHz 80 ppm for CEPT/E1 operation. Table 2. Receiver Specifications Parameter Receiver Sensitivity:* DS1 CEPT Analog LOS Level: DS1 CEPT PLL: 3 dB Bandwidth Peaking ICO Free-run Frequency Error Input Density (1s) Min Typ Max Unit 0.85 0.7 -- -- -- -- Vp Vp -- -- 0.48 0.28 -- -- Vp Vp -- -- -- 33 1.2 -- -- 2 6 kHz dB % 12.5 -- -- % 12 18 14 -- -- -- -- -- -- dB dB dB Loss: Return 51 kHz--102 kHz 102 kHz--2.048 MHz 2.048 MHz--3.072 MHz * Values shown are for flat loss only. Receiver also meets ITU-T G.703 interface immunity test (6 dB cable loss with -18 dB interference) for CEPT/E1 operation. Transfer characteristics (1/8 input). The maximum number of consecutive zeros = 15. Return loss specifications according to ITU-T G.703/RC6367A (CEPT only). 6 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Receiver (continued) Jitter PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. PLL has a minimum input jitter tolerance exceeding all requirements shown in Figure 3. The measured receiver jitter tolerance for DS1 and CEPT operation is also shown in Figure 3, with pseudorandom input data (215 - 1) and with EXCLK synchronous with the data source. The receiver transfers incoming jitter to RCLK with no more than 2 dB of gain at any frequency, which can be further reduced with the jitter attenuator. 500.0 TRI-TSY-000170, PUB 43801 PUB 62411 PEAK-TO-PEAK JITTER MAGNITUDE (U.I.) PUB 62411 (LOOP TIMED) 100.0 MINIMUM JITTER ATTENUATOR PERFORMANCE 50.0 28.0 MEASURED RECEIVER CEPT PERFORMANCE (JITTER ATTENUATOR NOT ACTIVE) TR-TSY-000009, PUB 43802 10.0 MEASURED RECEIVER DS1 PERFORMANCE (JITTER ATTENUATOR NOT ACTIVE) 5.0 1.0 ITU-T G.823 0.5 0.1 1 10 100 1000 10,000 JITTER FREQUENCY (Hz) 100,000 5-1157(C)r.4 Data Points (Hz, U.I.) ITU-T G.823 TR-TSY-000170, AT&T PUB 43801 TR-TSY-000009, AT&T PUB 43802 AT&T PUB 62411 1, 2.9 20, 1.5 2.4k, 1.5 18k, 0.2 100k, 0.2 -- -- -- -- -- 10, 300 10k, 0.3 50k, 0.3 -- -- -- -- -- -- -- 10, 5 500, 5 8k, 0.1 40k, 0.1 -- -- -- -- -- -- 1, 138 48, 138 10k, 0.2 100k, 0.2 -- -- -- -- -- -- AT&T PUB 62411 Looped Timed 1, 138 85, 138 10k, 0.4 100k, 0.4 -- -- -- -- -- -- Measured Receiver DS1 Performance (BER = 10-6) Measured Receiver CEPT Performance (BER = 10-6) 2.0k, 6.51 5.0k, 2.03 8.0k, 1.12 10k, 0.97 15k, 0.84 20k, 0.66 30k, 0.52 40k, 0.49 70k, 0.48 100k, 0.48 2.0k, 9.43 5.0k, 2.84 8.0k, 1.70 10k, 1.38 15k, 1.00 20k, 0.84 30k, 0.57 40k, 0.48 70k, 0.47 100k, 0.47 Figure 3. PLL Jitter Tolerance Requirements Lucent Technologies Inc. 7 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Receiver (continued) detector output becomes active. Hysteresis (250 mV) is provided in the analog detector to eliminate ALOS chattering. Either the analog or the digital detector sets IN-LOS high. Data Patterns Any data pattern with a minimum long-term 1s density of 12.5% with 15 or fewer consecutive 0s is allowed. The time required to detect analog loss of signal (ALOS) depends on the incoming signal amplitude before it disappears. Typical ALOS detection times are given in Table 3. Loss of Signal Table 3. Typical ALOS Detection Times Both digital (DLOS) and analog (ALOS) loss-of-signal detection is used in the T7290A device. The digital signal detector is described later under the Alarms and Maintenance section. The analog signal detector uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below approximately 0.48 Vp for DS1/T1 operation or 0.28 Vp for CEPT/E1 operation, the analog Signal Amplitude (Vp) 3.6 2.5 1.7 1.0 Typical ALOS Detection Time (ms) 5.0 3.7 2.8 1.4 Transmitter Output Pulse Shape Transmitter specifications are shown in Table 4. The T1 pulse shape template is specified at the network interface as shown in Figure 4. The DS1 pulse shape template is specified at the DSX and is illustrated in Figure 5. CEPT transmit waveforms at the device output conform to the template shown in Figure 6. Table 4. Transmitter Specifications Parameter Output Pulse Amplitude:* T1 DS1 (at DSX) CEPT (into 75 ) CEPT (into 120 ) Output Pulse Width: T1 DS1 CEPT Output Power Levels: T1 (3 kHz band at 772 kHz) T1 (3 kHz band at 1544 kHz) DS1 (2 kHz band at 772 kHz) DS1 (2 kHz band at 1544 kHz) Positive/Negative Pulse Imbalance: DS1 CEPT CEPT Zero Level** Return Loss: 51 kHz--102 kHz 102 kHz--2.048 MHz 2.048 MHz--3.072 MHz Min Typ Max Unit 2.7 2.4 2.13 2.7 3.0 3.0 2.37 3.0 3.3 3.6 2.61 3.3 V V V V 279 330 219 324 350 244 369 370 269 ns ns ns 12.0 -25 12.6 -29 16.5 -39 16.5 -39 19.0 -- 17.9 -- dBm dB dBm dB -- -- -- 0.1 2 1 0.5 5 10 dB % % 8 14 10 -- -- -- -- -- -- dB dB dB * In accordance with the interfaces described in the Line Termination section under Applications. Below the power at 772 kHz. Total power difference. Percentage of the pulse amplitude and pulse width. ** Percentage of the pulse amplitude. Meets CH-PTT return loss specifications (CEPT only). 8 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Transmitter (continued) 1.0 NORMALIZED AMPLITUDE (A) NORMALIZED AMPLITUDE (A) Output Pulse Shape (continued) 0.5 0 -0.5 1.0 0.5 0 -0.5 0 250 500 750 1000 1250 0 250 500 750 1000 TIME (ns) TIME (ns) 5-1604(F)r.3 T1 Isolated-Pulse Corner Points According to FCC Part 68 Maximum Curve Normalized ns Voltage 0 0.05 242 0.05 325 0.80 1.20 325 425 1.20 1.05 500 1.05 675 728 0.05 1000 0.05 1250 0.05 -- -- -- -- Minimum Curve Normalized ns Voltage -0.05 0 -0.05 350 0.50 350 400 0.90 500 0.95 600 0.90 0.50 650 -0.45 650 -0.45 800 896 -0.26 1100 -0.05 1250 -0.05 Note: Successive corner points are joined by straight lines. Figure 4. T1 Isolated-Pulse Template Lucent Technologies Inc. 1250 5-1160(C)r.6 DSX-1 Pulse Template Corner Points According to CB119 Maximum Curve Normalized ns Voltage 0.05 0 250 0.05 0.80 325 325 1.15 1.15 425 500 1.05 675 1.05 725 -0.07 0.05 1100 0.05 1250 -- -- -- -- Minimum Curve Normalized ns Voltage -0.05 0 350 -0.05 0.50 350 400 0.95 500 0.95 0.90 600 0.50 650 -0.45 650 -0.45 800 925 -0.20 1100 -0.05 1250 -0.05 Note: Successive corner points are joined by straight lines. Figure 5. DSX-1 Isolated-Pulse Template 9 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Transmitter (continued) Output Pulse Shape (continued) 269 ns (244 + 25) 20% 10% V = 100% 194 ns (244 - 50) 10% NOMINAL PULSE 20% 50% 244 ns 219 ns (244 - 25) 10% 10% 0% 10% 10% 20% 488 ns (244 + 244) 5-3145(C)r.7 Note: V corresponds to the nominal peak value. Figure 6. ITU-T G.703 Pulse Template Output Pulse Generation The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal to a balanced bipolar data signal (AMI format). Positive 1s are produced by a positive pulse on device pin T2, and negative 1s are produced by a positive pulse on device pin R2. Binary 0s are converted to null pulses. All pulse shapes are controlled on-chip according to equalizer control inputs, as defined in Table 5. Transmitter specifications are shown in Table 4. Table 5. Equalizer/Rate Control Service T1 Clock Rate 1.544 MHz DS1 1.544 MHz CEPT 2.048 MHz Transmitter Equalization* -- 0 ft.--131 ft. 131 ft.--262 ft. 262 ft.--393 ft. 393 ft.--524 ft. 524 ft.--655 ft. 75 120 Maximum Cable Loss 22 0.6 1.2 1.8 2.4 3.0 -- -- EC1 0 0 0 0 1 1 1 1 EC2 0 0 1 1 0 0 1 1 EC3 0 1 0 1 0 1 0 1 * Distance to DSX in feet for 22-Ga. PIC (ABAM) cable (DS1 only). Use maximum loss figures for other cable types. dB at 772 kHz. According to FCC Part 68, Subpart D, Option A for 0 dB line build-out. 10 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Jitter Attenuator Jitter transfer functions describe the amount of jitter that is transferred from the input to the output of the specified equipment. The jitter transfer functions are affected by the jitter attenuator circuitry, which can be placed in the receive data path, placed in the transmit data path, or bypassed. Placement of this circuit is controlled as described in Table 6. The external clock (EXCLK) must be present for the attenuation function to operate. When attenuation is selected, the T7290A device exhibits a jitter transfer function that has no peaking and a single 3.6 Hz pole frequency (DS1) or 4.8 Hz pole frequency (CEPT). Figure 7 displays a typical DS1 jitter transfer function for a constant input jitter amplitude of 2.0 U.I. peak-to-peak. The amount of generated output jitter when no input jitter is present is measured by using the scheme shown in Figure 8. The jitter filters depicted represent the AT&T PUB 62411 specification for a 1.544 MHz data rate. The jitter produced at the labeled points does not exceed the following peak-to-peak levels: 0.05 U.I. at point 1, 0.025 U.I. at point 2, 0.025 U.I. at point 3, and 0.02 U.I. at point 4. A similar test can be performed for ITU-T I.431 qualification at the 2.048 MHz data rate, in which two jitter filters are 20 Hz--100 kHz (0.125 U.I.) and 700 Hz--100 kHz (0.02 U.I.). The jitter tolerance of the attenuator meets the requirements of the TR-TSY-000009, AT&T PUB 43802, and ITU-T G.823 (see Figure 3). The attenuator also ensures that jitter accommodation is a minimum of 28 U.I. peak-to-peak (DS1) or 40 U.I. peak-to-peak (CEPT) (1 U.I. = 648 ns [T1/DS1] or 488 ns [CEPT]) during attenuation. The jitter attenuation function is identical when placed in either transmit or receive path. Ideally, the tolerance of the attenuator is 32 bits (64 U.I.). However, if f (Hz) = frequency (EXCLK) - frequency (input clock) and N = 23 (DS1) or 30.5 (CEPT), then the tolerance is degraded and equals: ABS ( f ) 64 - 2 x RND - UP ------------------------- + 1 (U.I.) N Figure 9 shows the phase step response (DS1) of the attenuator given f. The response is based on a phase offset (U.I.) generated by the read pointer of the buffer. It is this phase offset that degrades the attenuator's tolerance. 40 dB/DECADE JITTER ATTENUATION (dB) 0 -10 ITU-T G.735, ITU-T I.431 20 dB/ DECADE -20 TR-TSY000009, PUB 43802 TYPICAL PERFORMANCE 20 dB/DECADE -30 -40 -50 20 dB/DECADE -60 -70 1 10 40 100 350 1k 2.5k 400 15k 10k JITTER FREQUENCY (Hz) 5-1311(C)r.4 Data Points (Hz, dB) TR-TSY-000009, AT&T PUB 43802 1, 0.1 350, 0.1 2.5k, -33.6 15k, -49.2 ITU-T G.735, ITU-T I.431 10, 0.5 40, 0.5 400, -19.5 15k, -19.5 Figure 7. Jitter Transfer Function of the Jitter Attenuator Lucent Technologies Inc. 11 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Jitter Attenuator (continued) When the T7290A device is used only as a jitter attenuator, loopback 1 (LP1) should be active and the attenuator must be placed in the transmit path (MODE1:2 = 01). Table 6. Connectivity of Jitter Attenuator Connectivity of Jitter Attenuator* MODE1 MODE2 Transmit Path Receive Path 0 0 1 0 1 0 Test Mode 1 1 Bypass * The jitter attenuator must be enabled after VDD exceeds 4.75 V during device powerup. Jitter attenuator is powered down during this mode (see Table 8 under the Electrical Characteristics section). Not used for normal operation. FILTERS (SLOPES MUST BE 20 dB PER DECADE) 4 10 Hz TO EACH POINT 8 kHz PEAK DETECTOR 3 MEASURED SIGNAL JITTER DETECTOR 8 Hz (700 Hz) 40 kHz (100 kHz) 10 Hz (20 Hz) 40 kHz (100 kHz) TRUE RMS VOLTMETER 2 TO EACH POINT 1 SPECTRUM ANALYZER 5-1163(F)r.2 Figure 8. Measurement of Generated Jitter 12 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Jitter Attenuator (continued) READ COUNTER OFFSET (U.I.) PHASE STEP RESPONSE (IfI = 0 400 Hz) 20 15 10 5 0 0 50 100 150 TIME (ms) 5-2485(C)r.3 Figure 9. Jitter Attenuator Phase Response Alarms and Maintenance Output Loss of Signal (OUT-LOS) Digital Loss of Signal (DLOS) An output loss of signal (OUT-LOS = 1) is indicated if either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent. If the jitter attenuator is placed in the transmit path, SCLK is monitored. If the jitter attenuator is not used in the transmit path, TCLK is monitored. For every ten clock periods of the PLL oscillator clock, denoted as UGRCLK in Figure 1, a strobe is generated. If a single transmit clock period occurs between strobes, then OUT-LOS = 0. If no transmit clock period occurs between strobes, then OUT-LOS = 1, and the output drivers (T2 and R2) are placed into a high-impedance state and no data is transmitted. UGRCLK is always present, even in the absence of both EXCLK and T1/R1 input data; therefore, UGRCLK is the most suitable clock for monitoring OUT-LOS. A digital loss of signal (DLOS = 1) is indicated if 128 or more consecutive 0s occur in the receive data stream during DS1/T1 operation. During CEPT operation, a DLOS is indicated when 32 or more consecutive 0s occur in the receive data stream. DLOS is then deactivated when the ones density exceeds 12.5% and there are no more than 15 consecutive 0s (T1, DS1, and CEPT), signifying the return of good signal. DLOS deactivation monitors the data in fixed 32-bit windows. Each window must have at least four 1s with no more than 15 consecutive 0s. Consecutive 0s are also monitored across the window boundary. This condition must persist for two consecutive 32-bit windows, at which time DLOS is deactivated at the end of the window. Upon DLOS detection, RCLK is phase-locked to the external clock (EXCLK) so that other system devices slaved to the line clock continue to operate without instantaneous phase hits or discontinuities. Either an analog loss of signal (ALOS) or a digital loss of signal (DLOS) activates the IN-LOS output pin. Lucent Technologies Inc. 13 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Alarms and Maintenance (continued) does not corrupt the looped data. The IN-LOS alarm still monitors the entire receive function. Jitter Attenuator Alarm (ESA) A remote loopback (LP2) loops the recovered clock and retimed data into the transmitter and back onto the line. The receive front end, receive PLL, jitter attenuator (if engaged), and transmit driver circuitry are all exercised. The transmit clock, transmit data, and TBS inputs are ignored. Valid receive output data continues to be sent to RPDATA and RNDATA. This loop can be used to isolate failures between systems. A jitter attenuator alarm (ESA = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenuator. Bit errors occur when ESA is active. This signal is asserted until error-free operation resumes. See Figure 9 to determine the tolerance limits of the attenuator. Transmitter Short Circuit A transmitter monitor is provided to detect nonfunctioning links and protect the device from damage. If one of the transmitter's line drivers (T2 or R2) is shorted to the power supply or ground, or if T2 and R2 are shorted together, internal circuitry protects the device from damage. After 35 transmit clock cycles, the transmitter is powered up in its normal operating mode. The drivers attempt to correctly transmit the next data bit (+1, 0, or -1). If the short is still present, the transmitter is again internally protected for 35 transmit clock cycles. This process is continuously repeated until the short has disappeared. The TSC alarm is not available off-chip. A digital local loopback (LP3) directly loops the transmit clock and data to the receive clock and data output pins. The blue signal can be transmitted when in this loopback. LP3 (rather than LP1) must be selected if MODE2 = 0. Table 7. Loopback Control Operation Normal Digital Local Loopback Remote Loopback Local Loopback Symbol LOOPA LOOPB -- 0 0 LP3 0 1 LP2* 1 0 LP1 1 1 * TBS is ignored. Microprocessor Interface AIS (Blue Signal) Generator When the transmit blue signal is set (TBS = 1), a continuous stream of bipolar 1s is transmitted onto the line synchronous with EXCLK. The TPDATA and TNDATA inputs are ignored during this mode. If the IN-LOS output is externally connected to the TBS input, an IN-LOS error initiates a transmit blue signal as long as IN-LOS = 1. Also, TBS input is ignored when a remote loopback is selected. There is no microprocessor interface for the TBS input, i.e., any change on the TBS pin is fed directly into the device and is not impeded by the CS function. A chip-select input (CS) configures the device in either hardware mode or microprocessor mode. The chip-select function applies to the following inputs: MODE1, MODE2, EC1, EC2, EC3, LOOPA, and LOOPB. In the hardware mode, any change on these asynchronous input pins is fed directly into the device. To maintain hardware mode, set CS = 0. In the microprocessor mode, new digital control inputs are loaded into the T7290A device on the falling edge of CS and are latched on the rising edge of CS. Figure 11 shows a timing diagram of this function. Loopbacks Note that there are special requirements only when using microprocessor mode. For example, the state of the input should not change while CS = 0. Also, the state of the internal latch is undefined (unknown to the user) until the first falling edge of CS is encountered. The T7290A device has three independent loopback paths, which are activated as shown in Table 7. In-Circuit Testing A local loopback (LP1) connects the jitter attenuator's output clock and data to the receive clock and data output pins. MODE1:2 = 01 must be selected for this loopback to operate (jitter attenuator in the transmit path). Valid transmit output data continues to be sent to the network. However, if the transmit blue is initiated (TBS = 1), an all-1s signal is sent to the network and 14 The device has the ability to allow for in-circuit testing by activating the high-impedance mode (TRI = 0). During this mode, all output buffers (T2, R2, RCLK, RPDATA, RNDATA, IN-LOS, ESA, and OUT-LOS) are 3-stated. During the 3-stated condition, the absolute maximum voltage ratings must not be exceeded on any pin. Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be soldered safely at temperatures up to 300 C. Parameter dc Supply Voltage Range Power Dissipation Storage Temperature Maximum Voltage (any pin) with Respect to VDD Minimum Voltage (any pin) with Respect to GND Maximum Allowable Voltages (T1, R1) with Respect to GND Symbol VDD PD Tstg -- -- -- Min -0.5 -- -65 -- -0.5 -5.0 Max 6.5 500 125 0.5 -- 5.0 Unit V mW C V V V Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 1000 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here is obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage T7290A-EL >1200 V T7290A-PL >1200 V Lucent Technologies Inc. 15 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Electrical Characteristics Operating Conditions -40 C TA +85 C, VDD = 5 V 5%, except as noted. VDD rise time (0 V to 4.75 V) must be less than 15 ms. Table 8. Power Specifications Parameter Power Dissipation:* Without Jitter Attenuator: T1 DS1 CEPT (75 ) CEPT (120 ) With Jitter Attenuator: T1 DS1 CEPT (75 ) CEPT (120 ) Symbol PD Min Typ Max Unit -- -- -- -- 125 132 126 120 131 139 132 126 mW mW mW mW -- -- -- -- 165 172 174 168 173 181 183 176 mW mW mW mW * Conditions with 50% 1s on the transmit side, TA = 25 C, VDD = 5 V. Equalizer settings: EC1 = 0, EC2 = 1, EC3 = 1. Table 9. Logic Interface Characteristics An internal pull-up device is provided on the TRI lead. Internal pull-down devices are provided on the following leads: CS, MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, and LOOPB. The internal pull-up or pull-down devices require the input to source or sink no more than 20 A. Parameter Input Voltage: Low High Output Voltage: Low High Input Capacitance Load Capacitance Source Current Sink Current 16 Symbol Min Max Unit VIL VIH GNDD 2.0 0.8 VDDD V V VOL VOH CI CL GNDD 2.4 -- -- -- -- 0.4 VDDD 20 40 4.9 4.9 V V pF pF mA mA Isource Isink Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Timing Characteristics All duty-cycle and timing relationships for receive and transmit data signals are referenced to a TTL, 1.4 V threshold level. Figure 10 shows this timing. Table 10. Interface Data Timing (See Figure 10.) Symbol -- tTCLTCL tTDVTCL tTCLTDX tTCH1TCH2 tTCL2TCL1 tRDVRCH tRCHRDX tRCLRDV Parameter TCLK Duty Cycle TCLK Clock Period: DS1/T1 CEPT Transmit Data Setup Time Transmit Data Hold Time Clock Rise Time (10%--90%) Clock Fall Time (10%--90%) Receive Data Setup Time Receive Data Hold Time Receive Propagation Delay Min 40 Typ 50 * 647.7 488 -- -- -- -- -- -- -- 50 40 -- -- 140 180 -- Max 60 Unit % * ns ns ns ns ns ns ns ns ns -- -- 40 40 -- -- 40 * A tolerance of 130 ppm. A tolerance of 80 ppm. tTCLTCL tTCH1TCH2 TCLK tTDVTCL tTCLTDX tTCL2TCL1 TPDATA OR TNDATA tRCLRDV RCLK tRDVRCH tRCHRDX RPDATA OR RNDATA 5-1156(C)r.8 Figure 10. Interface Data Timing Lucent Technologies Inc. 17 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Timing Characteristics (continued) Table 11. Microprocessor Interface Timing (See Figure 11.) Symbol tSVCSL tCSLCSH tCSHSX tCSH1CSH2 tCSL2CSL1 Parameter Control Signal Setup Time Control Signal Pulse Width Time Control Signal Hold Time Control Signal Rise Time (10%--90%) Control Signal Rise Time (10%--90%) tCSL2CSL1 Min 50 40 40 -- -- Max -- -- -- 40 40 Unit ns ns ns ns ns tCSH1CSH2 CS MODE1 MODE2 EC1 EC2 EC3 LOOPA LOOPB tCSLCSH tSVCSL tCSHSX 5-1165(F)r.4 Figure 11. Microprocessor Interface Timing 18 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Applications Line Termination For the following applications (shown in Figures 12--15), the Lucent 2741 and 2745 Series transformers are recommended. The same transformers used for the T7290 device can be used for the T7290A device. The tolerance of all transformer turns ratios is a maximum of 2%. The tolerance of all resistors in the transmit path (excluding the cable termination) is a maximum of 1%. RECEIVE DATA T1 500 RPDATA RNDATA RECEIVE INPUT 200 500 RCLK R1 1:2 VDDD +5 V VDDA T7290A 1 F GNDD TRANSMIT DATA GNDA T2 100 TPDATA TRANSMIT OUTPUT LOAD TNDATA R2 TCLK 1.08:1 5-1152(C)r.6 Figure 12. DS1 Application for Twisted-Pair Interface RECEIVE DATA T1 LBO/ EQUALIZER RPDATA RECEIVE INPUT RNDATA RCLK R1 1:2 VDDD WAVEFORM MEETS FIGURE 3 TEMPLATE AT THIS POINT FOR 0 dB LINE BUILD-OUT. T7290A VDDA +5 V 1 F GNDD TRANSMIT DATA 21.5 GNDA T2 100 TRANSMIT OUTPUT LOAD 21.5 1.36:1 R2 TPDATA TNDATA TCLK 5-1153(C) Figure 13. T1 Application Diagram Lucent Technologies Inc. 19 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Applications (continued) Line Termination (continued) RECEIVE DATA T1 866 RPDATA RECEIVE INPUT 200 866 RNDATA RCLK R1 1:2 VDDD T7290A +5 V VDDA 1 F GNDD TRANSMIT DATA GNDA 26.1 T2 120 TRANSMIT OUTPUT LOAD 26.1 R2 TPDATA TNDATA TCLK 1.36:1 5-1154(C) Figure 14. CEPT Application for Twisted-Pair Interface RECEIVE DATA T1 270 RPDATA RECEIVE INPUT 200 270 RNDATA RCLK R1 1:2 VDDD T7290A +5 V VDDA 1 F GNDD TRANSMIT DATA GNDA 15.4 T2 75 TRANSMIT OUTPUT LOAD 15.4 R2 1.36:1 TPDATA TNDATA TCLK 5-1155(C)r.6 Figure 15. CEPT Application for Coaxial Interface 20 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Outline Diagrams 28-Pin, Plastic SOJ Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.79 MAX 5-4413(C).r4 Number of Pins (N) 28 Package Dimensions (SOJ) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 18.03 7.62 8.81 3.18 Lucent Technologies Inc. 21 Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface Outline Diagrams (continued) 28-Pin, Plastic DIP Dimensions are in millimeters. L N B 1 W PIN #1 IDENTIFIER ZONE H SEATING PLANE 0.38 MIN 2.54 TYP 0.58 MAX 5-4410(C).r2 Number of Pins (N) Package Dimensions (DIP) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 37.34 13.97 15.49 5.59 28 Ordering Information 22 Device Code Package Temperature T - 7290A - - PL T - 7290A - - EL 28-Pin DIP 28-Pin SOJ -40 C to +85 C -40 C to +85 C Comcode (Ordering Number) 106785645 106785637 Lucent Technologies Inc. Data Sheet April 1998 T7290A DS1/T1/CEPT/E1 Line Interface T7290A Migration from T7290 The T7290A is a replacement for the T7290 family of devices that includes the T7290-EL, T7290-PL, T7290-EL2, and T7290-PL2. The following list describes the functional changes made to the T7290 to produce the T7290A. Modification of an existing T7290 application may be required. The TBS input of the T7290A directly controls the TBS function. The TBS function of the T7290 is gated by chip select (CS). The transmitter short circuit (TSC) output alarm has been eliminated; however, the transmit drivers are still powered down under short-circuit conditions. The pin is renamed as output loss of signal (OUT-LOS) and indicates when either the transmit clock (TCLK) or the smoothing clock (SCLK) output of the jitter attenuator is absent. Loopback 1 (LP1) has been modified to route signals through the jitter attenuator only. The MODE2 pin must be set high for this loopback to operate (jitter attenuator on). The digital loss-of-signal (DLOS) functionality is now compatible for use in systems that must be compliant with Bellcore TR-TSY-000009. The loss-of-signal (LOS) output indication is renamed as input loss of signal (IN-LOS) and is now the ORed function of analog loss of signal (ALOS) and digital loss of signal (DLOS) regardless of the loopback setting. The frequency acquisition mode is enabled when a digital loss-of-signal (DLOS) condition occurs, in which case the receive clock (RCLK) is frequency-locked/phase-locked to the external clock (EXCLK). Improved ITU-T G.703 interference immunity for CEPT mode operation. DS98-190TIC Replaces DS97-197TIC to Incorporate the Following Updates 1. Page 3, Figure 1, Block Diagram, updated. 2. Page 21, 28-Pin, Plastic SOJ, changed dimensions to millimeters. 3. Page 22, 28-Pin, Plastic DIP, changed dimensions to millimeters. 4. Page 22, corrected Device Code. Lucent Technologies Inc. 23 T7290A DS1/T1/CEPT/E1 Line Interface Data Sheet April 1998 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. April 1998 DS98-190TIC (Replaces DS97-197TIC) Printed On Recycled Paper