CA064C153K5RACAUTO - KEMET ELECTRONICS

One world. One KEMET

Overview

KEMET’s Ceramic Chip Capacitor Array in X7R dielectric is an

advanced passive technology where multiple capacitor elements

are integrated into one common monolithic structure. Array

technology promotes reduced placement costs and increased

throughput. This is achieved by alternatively placing one device

rather than two or four discrete devices. Use of capacitor arrays

also saves board space which translates into increased board

density and more functions per board. Arrays consume only a

portion of the space required for standard chips resulting in savings

in inventory and pick/place machine positions.

KEMET’s X7R dielectric features a 125°C maximum operating

temperature and is considered “temperature stable.” The

Electronics Industries Alliance (EIA) characterizes X7R dielectric

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ceramic dielectric capacitors suited for bypass and decoupling

applications or for frequency discriminating circuits where Q and

stability of capacitance characteristics are not critical. X7R exhibits

a predictable change in capacitance with respect to time and

voltage and boasts a minimal change in capacitance with reference

to ambient temperature. Capacitance change is limited to ±15%

from -55°C to +125°C.

KEMET automotive grade array capacitors meet the demanding

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requirements.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC

(Commercial & Automotive Grade)

Ordering Information

CA 06 4 C 104 K 4 R A C TU

Ceramic

Array

Case Size

(L" x W")1

Number of

Capacitors

6SHFL¿FDWLRQ

Series

Capacitance

Code (pF)

Capacitance

Tolerance Voltage Dielectric Failure Rate/

Design

Termination

Finish2

Packaging/Grade

(C-Spec)3

05 = 0508

06 = 0612

2 = 2

4 = 4

C = Standard

X = Flexible

Termination

6LJQL¿FDQW

Digits + Number

of Zeros

J = ±5%

K = ±10%

M = ±20%

8 = 10 V

4 = 16 V

3 = 25 V

5 = 50 V

1 = 100 V

2 = 200 V

R = X7R A = N/A C = 100%

Matte Sn

L = SnPb

(5%

minimum)

Blank = Bulk

TU = 7" Reel

Unmarked

TM = 7" Reel Marked

AUTO = Automotive

Grade

1 All previous reference to metric case dimension "1632" has been replaced with an inch standard reference of "0612". Please reference all new designs using the

"0612" nomenclature. "CA064" replaces "C1632" in the ordering code.

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3 Additional reeling or packaging options may be available. Contact KEMET for details.

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• -55°C to +125°C operating temperature range

• Saves both circuit board and inventory space

• Reduces placement costs and increases throughput

• RoHS Compliant

• EIA 0508 (2-element) and 0612 (4-element) case sizes

• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V, and 200 V

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

Dimensions – Millimeters (Inches)

EIA

Size

Code

Metric

Size

Code

Length W

Width BW

Bandwidth BL

Bandlength T

Thickness P

Pitch P

Reference

0508 1220 1.30 (0.051)

±0.15 (0.006)

2.10 (0.083)

±0.15 (0.006)

0.53 (0.021)

±0.08 (0.003)

0.30 (0.012)

±0.20 (0.008) See Table 2 for

Thickness

1.00 (0.039)

±0.10 (0.004)

0.50 (0.020)

±0.10 (0.004)

0612 1632 1.60 (0.063)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

0.40 (0.016)

±0.20 (0.008)

0.30 (0.012)

±0.20 (0.008)

0.80 (0.031)

±0.10 (0.004)

0.40 (0.016)

±0.05 (0.002)

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• Capacitance offerings ranging from 330 pF – 0.22 μF

• Available capacitance tolerances of ±5%, ±10%, and ±20%

• Non-polar device, minimizing installation concerns

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excellent solderability

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minimum)

• Flexible termination option available upon request

• Commercial and Automotive (AEC–Q200) grades available

Applications

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telecommunications, computers, handheld devices and automotive.

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Table 4, Performance & Reliability.

Automotive Grade products meet or exceed the requirements outlined by the Automotive Electronics Council. Details regarding test

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information regarding the Automotive Electronics Council and AEC–Q200, please visit their website at www.aecouncil.com.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

Environmental Compliance

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Operating Temperature Range -55°C to +125°C

Capacitance Change with Reference to +25°C and 0 VDC Applied (TCC ±15%

Aging Rate (Maximum % Capacitance Loss/Decade Hour) 3.0%

Dielectric Withstanding Voltage (DWV) 250% of rated voltage

(

5 ±1 seconds and char

e/dischar

e not exceedin

50 mA

)

Dissipation Factor (DF) Maximum Limit @ 25ºC 5%(10 V), 3.5%(16 V and 25 V) and 2.5%(50 V to 200 V)

Insulation Resistance (IR) Limit @ 25°C PHJRKPPLFURIDUDGVRU*ȍ

(Rated voltage applied for 120 ±5 seconds @ 25°C)

Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 1,000 hours.

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Capacitance and dissipation factor (DF) measured under the following conditions:

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Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Dielectric Rated DC

Voltage

Capacitance

Value

Dissipation Factor

(Maximum %)

Capacitance

Shift

Insulation

Resistance

X7R

> 25

All

3.0

±20% 10% of Initial Limit16/25 5.0

< 16 7.5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

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Capacitance Capacitance

Code

&DVH6L]H6HULHV C0508 (CA 052C 2-Cap Case Size) C0612 ( C A 064C 4-Cap Case Size )

Voltage Code 84351843512

Rated Voltage (VDC) 10 16 25 50 100 10 16 25 50 100 200

Capacitance

Tolerance Product Availability and Chip Thickness Codes

See Table 2 for Chi

Thickness Dimensions

330 pF 331 J K M PA PA PA PA PA MA MA MA MA MA MA

390 pF 391 J K M PA PA PA PA PA MA MA MA MA MA MA

470 pF 471 J K M PA PA PA PA PA MA MA MA MA MA MA

560 pF 561 J K M PA PA PA PA PA MA MA MA MA MA MA

680 pF 681 J K M PA PA PA PA PA MA MA MA MA MA

820 pF 821 J K M PA PA PA PA PA MA MA MA MA MA

1,000 pF 102 J K M PA PA PA PA PA MA MA MA MA MA

1,200 pF 122 J K M PA PA PA PA PA MA MA MA MA MA

1,500 pF 152 J K M PA PA PA PA PA MA MA MA MA MA

1,800 pF 182 J K M PA PA PA PA PA MA MA MA MA MA

2,200 pF 222 J K MPAPAPAPAPAMAMAMAMAMA

2,700 pF 272 J K M PA PA PA PA PA MA MA MA MA MA

3,300 pF 332 J K M PA PA PA PA PA MA MA MA MA MA

3,900 pF 392 J K M PA PA PA PA PA MA MA MA MA MA

4,700 pF 472 J K M PA PA PA PA PA MA MA MA MA MA

5,600 pF 562 J K M PA PA PA PA MA MA MA MA

6,800 pF 682 J K M PA PA PA PA MA MA MA MA

8,200 pF 822 J K M PA PA PA PA MA MA MA MA

10,000 pF 103 J K M PA PA PA PA MA MA MA MA

12,000 pF 123 J K M PA PA PA PA MA MA MA MA

15,000 pF 153 J K M PA PA PA PA MA MA MA MA

18,000 pF 183 J K M PA PA PA PA MA MA MA MA

22,000 pF 223 J K M PA PA PA PA MA MA MA MA

27,000 pF 273 J K M PA PA PA PA MA MA MA

33,000 pF 333 J K MPAPAPAPA MAMAMA

39,000 pF 393 J K M PA PA PA PA MA MA MA

47,000 pF 473 J K M PA PA PA PA MA MA MA

56,000 pF 563 J K M PA PA PA PA MA MA MA

68,000 pF 683 J K M PA PA PA PA MA MA

82,000 pF 823 J K M PA PA PA PA MA MA

0.10 uF 104 J K M PA PA PA PA MA MA

0.15 uF 154 J K M PA

0.22 uF 224 J K M PA

Capacitance Capacitance Code

Rated Voltage (VDC) 10 16 25 50 100 10 16 25 50 100 200

Voltage Code 84351843512

&DVH6L]H6HULHV C0508 C0612

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Thickness

Code Case

Size Thickness ±

Range (mm) Paper Quantity Plastic Quantity

7" Reel 13" Reel 7" Reel 13" Reel

PA 0508 0.80 ± 0.10 0 0 4,000 10,000

MA 0612 0.80 ± 0.10 0 0 4,000 10,000

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

Table 3 – Chip Capacitor Array Land Pattern Design Recommendations per IPC–7351

EIA SIZE

CODE

METRIC

SIZE

CODE

Density Level A:

Maximum (Most) Land

Protrusion (mm)

Density Level B:

Median (Nominal) Land

Protrusion (mm)

Density Level C:

Minimum (Least) Land

Protrusion (mm)

C Y X P V1 V2 C Y X P V1 V2 C Y X P V1 V2

0508/CA052 1220 1.60 1.00 0.55 1.00 3.50 3.30 1.50 0.90 0.50 1.00 2.90 2.80 1.40 0.75 0.45 1.00 2.40 2.50

0612/CA064 1632 1.80 1.10 0.50 0.80 3.90 4.40 1.80 0.95 0.50 0.80 3.30 3.90 1.70 0.85 0.40 0.80 2.80 3.60

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Density Level B: )RUSURGXFWVZLWKDPRGHUDWHOHYHORIFRPSRQHQWGHQVLW\3URYLGHVDUREXVWVROGHUDWWDFKPHQWFRQGLWLRQIRUUHÀRZVROGHUSURFHVVHV

Density Level C: )RUKLJKFRPSRQHQWGHQVLW\SURGXFWDSSOLFDWLRQV%HIRUHDGDSWLQJWKHPLQLPXPODQGSDWWHUQYDULDWLRQVWKHXVHUVKRXOGSHUIRUPTXDOL¿FDWLRQ

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Grid P lacem ent Courtyard

V1 Y

Soldering Process

Recommended Soldering Technique:

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• KEMET recommends following the guidelines outlined in IPC/JEDEC J–STD–020

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress Reference Test or Inspection Method

Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Board Flex JIS–C–6429 Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G.

Flexible termination system – 3.0 mm (minimum).

Solderability J–STD–002

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a) Method B, 4 hours @ 155°C, dry heat @ 235°C

b) Method B @ 215°C category 3

c) Method D, category 3 @ 260°C

Temperature Cycling JESD22 Method JA–104 1,000 Cycles (-55°C to +125°C). Measurement at 24 hours +/- 2 hours after test conclusion.

Biased Humidity MIL–STD–202 Method 103

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. Measurement

at 24 hours +/- 2 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.

Measurement at 24 hours +/- 2 hours after test conclusion.

Moisture Resistance MIL–STD–202 Method 106 t = 24 hours/cycle. Steps 7a and 7b not required. Unpowered.

Measurement at 24 hours +/- 2 hours after test conclusion.

Thermal Shock MIL–STD–202 Method 107 -55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell

time – 15 minutes. Air – Air.

High Temperature Life MIL–STD–202 Method 108

/EIA–198 1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied.

Storage Life MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours.

Vibration MIL–STD–202 Method 204

5 g's for 20 min., 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick 7 secure

points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2"

from an

secure

oint. Test from 10 – 2,000 Hz

Mechanical Shock MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F.

Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent.

Storage & Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other

environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term

storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may

increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70%

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chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of

receipt.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Capacitor Array, X7R Dielectric, 10 – 200 VDC (Commercial & Automotive Grade)

Construction – Standard Termination

Reference Item Material

Termination

System

Finish 100% Matte Sn

B Barrier Layer Ni

CBase MetalCu

D Inner Electrode Ni

E Dielectric Material BaTiO3

Note: Image is exaggerated in order to clearly identify all components of construction.

Construction – Flexible Termination

Reference Item Material

Termination

System

Finish 100% Matte Sn

B Barrier Layer Ni

CEpoxy LayerAg

DBase MetalCu

E Inner Electrode Ni

F Dielectric Material BaTiO3

Note: Image is exaggerated in order to clearly identify all components of construction.

One world. One KEMET

Overview

KEMET’s COTS program is an extension of KEMET knowledge

of high reliability test regimes and requirements. KEMET regularly

supplies “up-screened” products by working with customer

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The COTS program offers the same high quality and high reliability

components as up-screened products, but at a lower cost to

the customer. This is accomplished by eliminating the need for

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for customer applications. A series of tests and inspections have

been selected to provide the accelerated conditioning and 100%

screening necessary to eliminate infant mortal failures from the

population.

KEMET’s C0G dielectric features a 125°C maximum operating

temperature and is considered “stable.” The Electronics

Components, Assemblies & Materials Association (EIA)

characterizes C0G dielectric as a Class I material. Components

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for resonant circuit applications or those where Q and stability

of capacitance characteristics are required. C0G exhibits no

change in capacitance with respect to time and voltage and boasts

a negligible change in capacitance with reference to ambient

temperature. Capacitance change is limited to ±30 ppm/ºC from

-55°C to +125°C.

All COTS testing includes voltage conditioning and post-electrical

testing as per MIL–PRF–55681. For enhanced reliability, KEMET

also provides the following test level options and conformance

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial Off-the-Shelf (COTS) for Higher Reliability

Applications, C0G Dielectric, 10 – 200 VDC

1 Additional capacitance tolerance offerings may be available. Contact KEMET for details.

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3 Additional reeling or packaging options may be available. Contact KEMET for details.

Ordering Information

C1206 T 104 K 5 G A C TU

Ceramic Case Size

(L" x W")

6SHFL¿FDWLRQ

Series

Capacitance

Code (pF)

Capacitance

Tolerance1Voltage Dielectric Failure Rate/Design Termination

Finish2

Packaging/Grade

(C-Spec)3

0402

0603

0805

1206

1210

1812

2220

T = COTS 6LJQL¿FDQW

Digits + Number

of Zeros

Use 9 for

1.0 – 9.9 pF

Use 8 for

0.5 – .99 pF

ex. 2.2 pF = 229

ex. 0.5 pF = 508

B = ±0.10 pF

C = ±0.25 pF

D = ±0.5 pF

F = ± 1%

G = ±2%

J = ±5%

K = ±10%

M = ±20%

8 = 10 V

4 = 16 V

3 = 25 V

6 = 35 V

5 = 50 V

1 = 100 V

2 = 200 V

G = C0G A = Testing per MIL–PRF–

55681 PDA 8%

B= Testing per MIL–PRF–

55681 PDA 8%, DPA per

EIA–469

C = Testing per MIL–

PRF–55681 PDA 8%, DPA

per EIA–469, Humidity per

MIL–STD–202, Method 103,

Condition A

C = 100%

Matte Sn

L = SnPb (5%

minimum)

Blank = Bulk

TU = 7" Reel

Unmarked

TM = 7" Reel

Marked

Test Level A Test Level B Test Level C

Voltage Conditioning

DWV

IR@25°C

CAP

Voltage Conditioning

DWV

IR@25°C

CAP

Voltage Conditioning

DWV

IR@25°C

CAP

PDA 8% PDA 8% PDA 8%

C of C DPA DPA

C of C 85/85

C of C