The Smart Timing Choice
The Smart Timing Choice
SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com
Rev. 1.06 Revised October 6, 2014
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Features Applications
0.3 ps RMS phase jitter (random) for 10GbE applications 10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Frequency stability as low as ±10 ppm
100% drop-in replacement for quartz and SAW oscillators Telecom, networking, instrumentation, storage, servers
Configurable positive frequency shift, +25, +50, or +75 ppm
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mmxmm
Industrial and extended commercial temperature ranges
Best in class 1-year and 10-year aging
Best resilience, up to 40x better than quartz
For other frequencies, refer to SiT9121 or 9122 datasheet
Electrical Characteristics
Parameter and Conditions Symbol Min. Typ. Max. Unit Condition
LVPECL and LVDS, Common Electrical Characteristics
Supply Voltage Vdd 2.97 3.3 3.63 V
2.25 2.5 2.75 V
2.25 – 3.63 V Termination schemes in Figures 1 and 2 - XX ordering code
Output Frequency Range f 156.25000, 156.253906,
156.257812, 156.261718,
161.132800
MHz 156.253906 MHz, +25 PPM from 156.250000
156.257812 MHz, +50 PPM from 156.250000
156.261718 MHz, +75 PPM from 156.250000
Frequency Stability F_stab -10 – +10 ppm
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
-20 – +20 ppm
-25 – +25 ppm
-50 – +50 ppm
First Year Aging F_aging1 -2 – +2 ppm 25°C
10-year Aging F_aging10 -5 – +5 ppm 25°C
Operating Temperature Range T_use -40 – +85 °C Industrial
-20 – +70 °C Extended Commercial
Input Voltage High VIH 70% – – Vdd Pin 1, OE or ST
Input Voltage Low VIL – – 30% Vdd Pin 1, OE or ST
Input Pull-up Impedance Z_in – 100 250 kΩ Pin 1, OE logic high or logic low, or ST logic high
2––MΩ
Pin 1, ST logic low
Start-up Time T_start – 6 10 ms Measured from the time Vdd reaches its rated minimum value.
Resume Time T_resume – 6 10 ms In Standby mode, measured from the time ST pin crosses
50% threshold.
Duty Cycle DC 45 – 55 % Contact SiTime for tighter duty cycle
LVPECL, DC and AC Characteristics
Current Consumption Idd – 61 69 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current I_OE – – 35 mA OE = Low
Output Disable Leakage Current I_leak – – 1 A OE = Low
Standby Current I_std – – 100 AST = Low, for all Vdds
Maximum Output Current I_driver – – 30 mA Maximum average current drawn from OUT+ or OUT-
Output High Voltage VOH Vdd-1.1 – Vdd-0.7 V See Figure 1(a)
Output Low Voltage VOL Vdd-1.9 – Vdd-1.5 V See Figure 1(a)
Output Differential Voltage Swing V_Swing 1.2 1.6 2.0 V See Figure 1(b)
Rise/Fall Time Tr, Tf – 300 500 ps 20% to 80%, see Figure 1(a)
OE Enable/Disable Time T_oe – – 120 ns f = 156.25 MHz - For other frequencies, T_oe = 100ns + 3 period
RMS Phase Jitter (random) T_phj – 0.25 0.3 ps IEEE802.3-2005 10GbE jitter measurement specifications
LVDS, DC and AC Characteristics
Current Consumption Idd – 47 55 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current I_OE – – 35 mA OE = Low
Differential Output Voltage VOD 250 350 450 mV See Figure 2
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 2 of 8 www.sitime.com
Electrical Characteristics (continued)
Parameter and Conditions Symbol Min. Typ. Max. Unit Condition
LVDS, DC and AC Characteristics (continued)
Output Disable Leakage Current I_leak––1AOE = Low
Standby Current I_std – – 100 AST = Low, for all Vdds
VOD Magnitude Change VOD – – 50 mV See Figure 2
Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2
VOS Magnitude Change VOS – – 50 mV See Figure 2
Rise/Fall Time Tr, Tf – 495 600 ps 20% to 80%, see Figure 2
OE Enable/Disable Time T_oe – – 115 ns f = 156.25 MHz - For other frequencies, T_oe = 100ns + 3 period
RMS Phase Jitter (random) T_phj – 0.25 0.3 ps IEEE802.3-2005 10GbE jitter measurement specifications
Pin Description
Pin Map Functionality
1
OE Input H or Open: specified frequency output
L: output is high impedance
ST Input
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to
I_std.
2NC NA
No Connect; Leave it floating or connect to GND for better
heat dissipation
3 GND Power VDD Power Supply Ground
4 OUT+ Output Oscillator output
5 OUT- Output Complementary oscillator output
6 VDD Power Power supply voltage
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter Min. Max. Unit
Storage Temperature -65 150 °C
VDD -0.5 4 V
Electrostatic Discharge (HBM) – 2000 V
Soldering Temperature (follow standard Pb free soldering guidelines) – 260 °C
Thermal Consideration
Package
JA, 4 Layer Board
(°C/W)
JC, Bottom
(°C/W)
7050, 6-pin 142 27
5032, 6-pin 97 20
3225, 6-pin 109 20
Environmental Compliance
Parameter Condition/Test Method
Mechanical Shock MIL-STD-883F, Method 2002
Mechanical Vibration MIL-STD-883F, Method 2007
Temperature Cycle JESD22, Method A104
Solderability MIL-STD-883F, Method 2003
Moisture Sensitivity Level MSL1 @ 260°C
43
1 6
GND
VDD
OUT+
52
NC OUT-
OE/ST
Top View
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 3 of 8 www.sitime.com
Waveform Diagrams
Figure 1(a). LVPECL Voltage Levels per Differential Pin (OUT+/OUT-)
Figure 1(b). LVPECL Voltage Levels Across Differential Pair
Figure 2. LVDS Voltage Levels per Differential Pin (OUT+/OUT-)
OUT+
OUT-
GND
Tr Tf
20%
80%
20%
VOL
80%
VOH
0 V
t
V_ Swing
OUT+
OUT-
GND
Tr Tf
20%
80%
20%
VOS
80%
VOD
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 4 of 8 www.sitime.com
Termination Diagrams
LVPECL:
Z0 = 50
Z0 = 50
D+
D-
OUT+
OUT-
50
VTT = VDD – 2.0 V
LVPECL Driver Receiver Device
50
VDD
Figure 3. LVPECL Typical Termination
D+
D-
OUT+
OUT-
LVPECL Driver Receiver Device
Z0 = 50
Z0 = 50
R1
50 50
R1
VTT
100 nF
100 nF
VDD VDD= 3.3V => R1 = 100 to 150
VDD= 2.5V => R1 = 75
Figure 4. LVPECL AC Coupled Termination
Z0 = 50
Z0 = 50
D+
D-
OUT+
OUT-
LVPECL Driver Receiver Device
R1
R2
R3
R4
VDD
VDD = 3.3V => R1 = R3 = 133 and
R2 = R4 = 82
VDD = 2.5V => R1 = R3 = 250 and
R2 = R4 = 62.5
VDD
Figure 5. LVPECL with Thevenin Typical Termination
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 5 of 8 www.sitime.com
LVDS:
Figure 6. LVDS Single Termination (Load Terminated)
Z0 = 50
Z0 = 50
D+
D-
OUT+
OUT-
100
LVDS Driver Receiver Device
VDD
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 6 of 8 www.sitime.com
Notes:
1. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
2. A capacitor of value 0.1 F between Vdd and GND is recommended.
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)[1] Recommended Land Pattern (Unit: mm)[2]
3.2 x 2.5x 0.75 mm
5.0 x 3.2 x 0.75 mm
7.0 x 5.0x 0.90 mm
0.75±0.05
YXXXX
0.9
#2
#5
#2
#5
#1#3
#4 #6
#1 #3
#4#6
3.2±0.05
2.5±0.05
0.7
0.6
2.20
1.050.65
1.00
2.25
1.6
0.75±0.05
YXXXX
1.20
#2
#5
#2
#5
#1#3
#4 #6
#1 #3
#4#6
5.0±0.10
1.40
1.10
5.08
7.0±0.10
2.60
#1 #3
#6 #4
#1#3
#6
#4
0.90 ±0.10
#2
#5
#2
#5
YXXXX
5.08
1.60
1.60
3.80
The Smart Timing Choice
The Smart Timing Choice
SiT9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
Rev. 1.06 Page 7 of 8 www.sitime.com
Ordering Information
Ordering Codes for Supported Tape & Reel Packing Method
Device Size
8 mm T&R
(3ku)
8 mm T&R
(1ku)
8 mm T&R
(250u)
12 mm T&R
(3ku)
12 mm T&R
(1ku)
12 mm T&R
(250u)
16 mm T&R
(3ku)
16 mm T&R
(1ku)
16 mm T&R
(250u)
7.0 x 5.0 mm––––––TYX
5.0 x 3.2 mm – – – T Y X – – –
3.2 x 2.5 mm D E G T Y X – – –
SiT9156AC -
Frequency
Part Family
“SiT9156”
Revision Letter
“A” is the revision of Silicon
Temperature Range
“I” Industrial, -40 to 85°C
Packaging:
“T”, “Y”, “X”, “D”, “E” or “G”
Refer to table below for
packing method
Leave Blank for Bulk
Package Size
Frequency Stability
“C” Extended Commercial, -20 to 70°C
Signalling Type
Feature Pin
“E” for Output Enable
“S” for Standby
“25” for 2.5V ±10%
“33” for 3.3V ±10%
“XX” for 2.25V to 3.63V
“B” 3.2 x 2.5 mm x mm
“C” 5.0 x 3.2 mm x mm
“D” 7.0 x 5.0 mm x mm
“1” = LVPECL
“2” = LVDS
“F” for ±10 ppm
“1” for ±20 ppm
“2” for ±25 ppm
“3” for ±50 ppm
Voltage Supply
1C2-33E156.250000T
156.250000 MHz
156.253906 MHz
156.257812 MHz
156.261718 MHz
161.132800 MHz
Rev. 1.06 Page 8 of 8 www.sitime.com
© SiTime Corporation 2014. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a
Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii)
unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper
installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by
operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or
usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by
SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved
or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below.
CRITICAL USE EXCLUSION POLICY
BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES
OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE.
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prohibited.
The Smart Timing Choice
The Smart Timing Choice
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet
SiT9156
Revision History
Version Release Date Change Summary
1.01 2/20/13 Original
1.02 12/3/13 Added input specifications, LVPECL/LVDS waveforms, packaging T&R options
1.03 2/6/14 Added 8mm T&R option
1.04 3/3/14 Added ±10 ppm
1.05 7/23/14 Include Thermal Consideration Table
1.06 10/6/14 Modified Thermal Consideration values
