Features * Operating voltage: 5V * Access time: 30, 45ns * Very low power consumption * * * * * * * * - active: 250mW (Typ) - standby: 1 W (Typ) - data retention: 0.5 W (Typ) Wide temperature Range: -55C to +125C 400Mils width package TTL compatible inputs and outputs Asynchronous Single 5 volt supply Equal Cycle and access time Gated inputs: - no pull-up/down - resistors are required QML Q and V with SMD 5962-89598 Rad Tolerant 5V 128 K x 8 Very Low Power CMOS SRAM Description The M65608E is a very low power CMOS static RAM organized as 131072 x 8bits. Atmel Wireless & Microcontrollers brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. M65608E Utilizing an array of six transistors (6T) memory cells, the M65608E combines an extremely low standby supply current (Typical value= 20A) with a fast access time at 30ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The M65608E is processed according to the methods of the latest revision of the MIL STD 883 (class B or S), ESA SCC 9000 or QML. Rev. F-20-Aug-01 1 M65608E Interface Block Diagram 2 Rev. F-20-Aug-01 Pin Configuration 32 pins DIL side-brazed 400 MILS 32 pins Flatpack 400 MILS Table 1. Pin Names A0-A16 Address inputs I/O0- I/O7 Data Input/Output CS1 Chip select 1 CS2 Chip select 2 W Write Enable OE Output Enable VCC Power GND Ground Table 2. Truth Table CS1 CS2 W OE INPUTS/ OUTPUTS H X X X Z X L X X Z L H H L Data Out Read L H L X Data In Write L H H H Z MODE Deselect/ Power-down Deselect/ Power Down Output Disable L = low, H = high, X = H or L, Z = high impedance. 3 M65608E Rev. F-20-Aug-01 M65608E Electrical Characteristics Absolute Maximum Ratings Supply voltage to GND potential:..................................... -0.5V + 7.0V DC input voltage: ............................................................. GND - 0.3V to VCC + 0.3 DC output voltage high Z state: .......................................GND - 0.3V to VCC + 0.3 Storage temperature: ....................................................... -65C to +150C Output current into outputs (low):..................................... 20mA Electro statics discharge voltage: .................................... > 2001V (MIL STD 883D method 3015.3) Operating Range OPERATING VOLTAGE OPERATING TEMPERATURE 5V + 10% -55C to + 125C Military Recommended DC Operating Conditions PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT Vcc Supply voltage 4.5 5.0 5.5 V Gnd Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.3 0.0 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V MINIMUM TYPICAL MAXIMUM UNIT Input low voltage - - 8 pF Output high voltage - - 8 pF Capacitance PARAMETER Cin (1) Cout (1) 1. DESCRIPTION Guaranteed but not tested. 4 Rev. F-20-Aug-01 DC Parameters PARAMETER IIX (1) IOZ (1) DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT Input leakage current -1 - 1 A Output leakage current -1 - 1 A VOL (2) Output low voltage - - 0.4 V VOH (3) Output high voltage 2.4 - - V 1. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled. 2. 3. Vcc min. IOL = 1 mA. Vcc min. IOH = -0.5 mA. Consumption 65608E 65608E DESCRIPTION - 30 - 45 UNIT VALUE Standby supply current 2 2 mA max Standby supply current 300 300 A max Dynamic operating current 130 100 mA max SYMBOL ICCSB (1) ICCSB1 ICCOP 1. 2. 3. (2) (3) CS1 > VIH or CS2 < VIL and CS1 < VIL. CS1 > Vcc - 0.3V or, CS2 < Gnd + 0.3 V and CS1 < 0.2V F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd or Vcc, Vcc max. AC Parameters Input pulse levels:............................................. Gnd to 3.0 V Input rise: ......................................................... 5 ns Input timing reference levels: ........................... 1.5 V Output loading IOL/IOH (see figure 1a and 1b):.....+30 pF AC Test Loads Waveforms Figure 1a 5 Figure 1b Figure 2 M65608E Rev. F-20-Aug-01 M65608E Data Retention Mode Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention chip select CS1 must be held high within VCC to VCC 0.2V or, chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V). Timing Data Retention Characteristics Parameter Description Minimum Typical TA=25 C Maximum Unit VCCDR Vcc for data retention 2.0 V TCDR Chip deselect to data retention time 0.0 ns TR Operation recovery time TAVAV (*) ns ICCDR1 (**) Data retention current @ 2.0V - Data retention current @ 3.0V - ICCDR2 (**) 0.1 A 150 200 Note: 0.2 A *TAVAV = Read Cycle Time **CS1 = Vcc or CS2 = CS1 = GND, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2V. 6 Rev. F-20-Aug-01 Write Cycle SYMBOL PARAMETER 65608-30 65608-45 UNIT VALUE TAVAW Write cycle time 30 45 ns min TAVWL Address set-up time 0 0 ns min TAVWH Address valid to end of write 22 35 ns min TDVWH Data set-up time 18 25 ns min TE1LWH CS1 low to write end 22 35 ns min TE2HWH CS2 high to write end 22 35 ns min TWLQZ Write low to high Z 8 15 ns max TWLWH Write pulse width 22 35 ns min TWHAX Address hold from to end of write 0 0 ns min TWHDX Data hold time 0 0 ns min TWHQX Write high to low Z (1) 0 0 ns min 1. (1) Parameters guaranteed, not tested, with output loading 5 pF. (see 1b) Read Cycle SYMBOL PARAMETER 65608-30 65608-45 UNIT VALUE TAVAV Read cycle time 30 45 ns min TAVQV Address access time 30 45 ns max TAVQX Address valid to low Z 5 5 ns min TE1LQV Chip-select1 access time 30 45 ns max TE1LQX CS1 low to low Z 3 3 ns min TE1HQZ CS1 high to high Z (1) 18 20 ns max TE2HQV Chip-select2 access time 30 45 ns max TE2HQX CS2 high to low Z (1) 3 3 ns min TE2LQZ CS2 low to high Z (1) 18 20 ns max TGLQV Output Enable access time 12 15 ns max TGLQX OE low to low Z (1) 0 0 ns min TGHQZ OE high to high Z (1) 8 15 ns max (1) 1.*Parameters Guaranteed, not tested, with output loading 5 pF (see , 1b) 7 M65608E Rev. F-20-Aug-01 M65608E Write Cycle 1. W Controlled. OE High During Write Write Cycle 2. W Controlled. OE Low. 8 Rev. F-20-Aug-01 Write Cycle 3. CS1 or CS2 Controlled. Note: 9 The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH. M65608E Rev. F-20-Aug-01 M65608E Read Cycle nb 1 Read Cycle nb 2 Read Cycle nb 3 10 Rev. F-20-Aug-01 Ordering Information Table 3. Possible order entries Part-number Temperature range Speed Package Flow MMDJ-65608EV-30 -55 to +125 30 ns FP32.4 Standard Mil MMDJ-65608EV-45 -55 to +125 45 ns FP32.4 Standard Mil MMC9-65608EV-30 -55 to +125 30 ns SB32.4 Standard Mil MMC9-65608EV-45 -55 to +125 45 ns SB32.4 Standard Mil SMDJ-65608EV-30SC -55 to +125 30 ns FP32.4 SCC C SMDJ-65608EV-45SC -55 to +125 45 ns FP32.4 SCC C SMC9-65608EV-30SC -55 to +125 30 ns SB32.4 SCC C SMC9-65608EV-45SC -55 to +125 45 ns SB32.4 SCC C SMDJ-65608EV-30SB -55 to +125 30 ns FP32.4 SCC B SMDJ-65608EV-45SB -55 to +125 45 ns FP32.4 SCC B SMC9-65608EV-30SB -55 to +125 30 ns SB32.4 SCC B SMC9-65608EV-45SB -55 to +125 45 ns SB32.4 SCC B MMDJ-65608EV-30/883(*) -55 to +125 30 ns FP32.4 MIL 883 B MMDJ-65608EV-45/883(*) -55 to +125 45 ns FP32.4 MIL 883 B MMC9-65608EV-30/883(*) -55 to +125 30 ns SB32.4 MIL 883 B MMC9-65608EV-45/883(*) -55 to +125 45 ns SB32.4 MIL 883 B SMDJ-65608EV-30/883(*) -55 to +125 30 ns FP32.4 MIL 883 S SMDJ-65608EV-45/883(*) -55 to +125 45 ns FP32.4 MIL 883 S SMC9-65608EV-30/883(*) -55 to +125 30 ns SB32.4 MIL 883 S SMC9-65608EV-45/883(*) -55 to +125 45 ns SB32.4 MIL 883 S 5962-895647QTC -55 to +125 30 ns FP32.4 QML Q 5962-895618MTC -55 to +125 45 ns FP32.4 QML Q 5962-895647VTC -55 to +125 30 ns FP32.4 QML V 5962-895618VTC -55 to +125 45 ns FP32.4 QML V 5962-895647QZC -55 to +125 30 ns SB32.4 QML Q 5962-895618MZC -55 to +125 45 ns SB32.4 QML Q 5962-895647VZC -55 to +125 30 ns SB32.4 QML V 5962-895618VZC -55 to +125 45 ns SB32.4 QML V MMDJ-65608EV-30-E 25 30 ns FP32.4 Engineering Samples MMC9-65608EV-30-E(*) 25 30 ns SB32.4 Engineering Samples MM0-65608EV-30-E 25 30 ns Die Engineering Samples 5962-895647Q6A -55 to +125 30 ns Die QML Q 5962-895647V6A -55 to +125 30 ns Die QML V Note: 11 (*)contact factory M65608E Rev. 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