Rev. F–20-Aug-01
1
Features
•Operating voltage: 5V
•Access time: 30, 45ns
•Very low power consumption
– active: 250mW (Typ)
– standby: 1 µW (Typ)
– data retention: 0.5 µW (Typ)
•Wide temperature Range: -55°C to +125°C
•400Mils width package
•TTL compatible inputs and outputs
•Asynchronous
•Single 5 volt supply
•Equal Cycle and access time
•Gated inputs:
–no pull-up/down
–resistors are required
•QML Q and V with SMD 5962-89598
Description
The M65608E is a very low power CMOS static RAM organized as 131072 x 8bits.
Atme l Wireles s & Microc ontrol lers bring s the sol ution to app licat ions wher e fast co m-
puting is as mandatory as low consumption, such as aerospace electronics, portable
instruments, or embarked systems.
Utilizing an array of s ix transistors (6T ) memory cel ls, the M65608E c ombines an
extremely low standby supply current (Typical va lue= 20µA) with a fast access time at
30ns ove r th e fu ll m il itar y te mpe rat ure r an ge. The high s tab il ity of the 6T c ell pr ovi des
excellent protection against soft errors due to noise.
The M6560 8E is proc esse d acco rding to t he method s of the late st revis ion of the MI L
STD 883 (class B or S), ESA SCC 9000 or QML.
Rad Tolerant
5V 128 K x 8
V ery Low Power
CMOS SRAM
M65608E
2
M65608E
Rev. F–20-Aug-01
Interface
Block Diagram
3M65608E Rev. F–20-Aug-01
Pin Configuration
Table 1. Pin Names
Table 2. Truth Table
L = low, H = high, X = H or L, Z = high impedance.
32 pins DIL side-brazed 400 MILS
32 pins Flatpack 400 MILS
A0-A16 Address inputs
I/O0- I/O7 Data Input/Output
CS1 Chip select 1
CS2 Chip select 2
W Write Enable
OE Output Enable
VCC Power
GND Ground
CS1 CS2 W OE INPUTS/
OUTPUTS MODE
HXXXZ
Deselect/
Power-down
XLXXZ
Deselect/
Power Down
L H H L Data Out Read
L H L X Data In Write
L H H H Z Output Disable
4
M65608E
Rev. F–20-Aug-01
Electrical Characteristics
Absolute Maximum
Ratings Supply voltage to GND potential:.....................................-0.5V + 7.0V
DC input voltage:.............................................................GND - 0.3V to VCC + 0.3
DC output voltage high Z state: .......................................GND - 0.3V to VCC + 0.3
Stora ge temperature:.......... ................. ..... ...... ..... ...... ......-6 5°C to +150°C
Output current into outputs (low):.....................................20mA
Electro statics discharge voltage: ....................................> 2001V
(MIL STD 883D method 3015.3)
Operating Range
Recommended DC Operating Conditions
Capacitance
OPERATING VOLTAGE OPERATING TEMPERATURE
Military 5V + 10% -55°C to + 125°C
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Vcc Supply voltage 4.5 5.0 5.5 V
Gnd Ground 0.0 0.0 0.0 V
VIL Input low voltage GND - 0.3 0.0 0.8 V
VIH Input high voltage 2.2 - VCC + 0.3 V
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Cin (1)
1. Guaranteed but not tested.
Input low voltage - - 8 pF
Cout (1) Output high voltage - - 8 pF
5M65608E Rev. F–20-Aug-01
DC Parameters
Consumption
AC Parameters Input pulse levels:.............................................Gnd to 3.0 V
Input rise: .........................................................5 ns
Input timing refer ence lev els: ........................... 1. 5 V
Output loading IOL/IOH (see figure 1a and 1b):.....+30 pF
AC Test Loads Waveforms
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
IIX (1)
1. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled.
Input leakage current -1 - 1 µA
IOZ (1) Output leakage current -1 - 1 µA
VOL (2)
2. Vcc mi n. IOL = 1 mA.
Output low voltage - - 0.4 V
VOH (3)
3. Vcc min. IOH = -0.5 mA.
Output high voltage 2.4 - - V
SYMBOL DESCRIPTION 65608E
- 30 65608E
- 45 UNIT VALUE
ICCSB (1) St andby supply cur rent 2 2 mA max
ICCSB1 (2) Standby supply current 300 300 µA max
ICCOP (3) Dynamic operating
current 130 100 mA max
1. CS1 > VIH or CS2 < VIL and CS1 < VIL.
2. CS1 > Vcc - 0.3V or, CS2 < Gnd + 0.3 V and CS1 < 0.2V
3. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd or Vcc, Vcc max.
Figure 1a Figure 1b Figure 2
6
M65608E
Rev. F–20-Aug-01
Data Retention Mode A tmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage
and supply current ar e guaranteed over tem perature. The following r ules ensure data
retention:
1. During da ta retention chip select CS1 must be held high within VCC to VCC -
0.2V or, chip select CS2 must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high imped-
ance, minimizing power dissipation.
3. During power up and power down transitions CS1 and OE must be kept between
VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum opera-
tion voltages (4.5V).
Timing
Data Retention Characteristics
Note: *TAVAV = Read Cycle Time
**CS1 = Vcc or CS2 = CS1 = GND, Vin = Gn d/Vc c, thi s p ara me ter i s o nl y t est ed at Vc c =
2V.
Parameter Description Minimum Typical
TA=25 °C Maximum Unit
VCCDR Vcc for data
retention 2.0 V
TCDR Chip deselect to
data retention
time 0.0 ns
TR Operation
recovery time TAVAV (*) ns
ICCDR1 (**) Data retention
current @ 2.0V -0.1 150
200
µA
ICCDR2 (**) Data retention
current @ 3.0V -0.2 µA
7M65608E Rev. F–20-Aug-01
Write Cycle
Read Cycle
SYMBOL PARAMETER 65608-30 65608-45 UNIT VALUE
TAVAW Write cycle time 30 45 ns min
TAVWL Address set-up time 0 0 ns min
TAVWH Address valid to end of write 22 35 ns min
TDVWH Data set-up time 18 25 ns m in
TE1LWH CS1 low to write end 22 35 ns min
TE2HWH CS2 high to write end 22 35 ns m in
TWLQZ Writ e low to high Z (1)
1. Parameters guaranteed, not tested, with output loading 5 pF. (see 1b)
815ns max
TWLWH Write pulse width 22 35 ns min
TWHAX Address hold from to end of
write 00 nsmin
TWHDX Data hold time 0 0 ns m in
TWHQX Write high to low Z (1) 00 nsmin
SYMBOL PARAMETER 65608-30 65608-45 UNIT VALUE
TAVAV Read cyc le time 30 45 ns min
TAVQV Address access time 30 45 ns max
TAVQX Address valid to low Z 5 5 ns min
TE1LQV Chip-select1 access
time 30 45 ns max
TE1LQX CS1 low to low Z (1)
1.*Parameters Guaranteed, not tested, with output loading 5 pF (see , 1b)
33nsmin
TE1HQZ CS1 high to high Z (1) 18 20 ns max
TE2HQV Chip-select2 access
time 30 45 ns max
TE2HQX CS2 high to low Z (1) 33nsmin
TE2LQZ CS2 low to high Z (1) 18 20 ns max
TGLQV Output Enable access
time 12 15 ns max
TGLQX OE low to low Z (1) 00nsmin
TGHQZ OE high to high Z (1) 815nsmax
8
M65608E
Rev. F–20-Aug-01
Write Cycle 1. W Controlled. OE High During Write
Write Cycle 2. W Controlled. OE Low.
9M65608E Rev. F–20-Aug-01
Write Cycle 3. CS1 or CS2 Controlled.
Note: The internal write time of the memory is defined by the overlap of CS1 Low and CS2
HIGH and W LOW. Both signals must be actived to initiate a write and either signal can
terminate a write by going in actived. The data input setup and hold timing should be ref-
erenced to the actived edge of the signal that terminates the write. Data out is high
impedance if OE = VIH.
10
M65608E
Rev. F–20-Aug-01
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
11 M65608E Rev. F–20-Aug-01
Ordering Information
Note: (*)contact factory
Table 3. Possible order entries
Part-number Temperature range Speed Package Flow
MMDJ-65608EV-30 -55° to +125°30 ns FP32.4 Standard Mil
MMDJ-65608EV-45 -55° to +125°45 ns FP32.4 Standard Mil
MMC9-65608EV-30 -55° to +125°30 ns SB32.4 St andard Mil
MMC9-65608EV-45 -55° to +125°45 ns SB32.4 St andard Mil
SMDJ-65608EV-30SC -55° to +125°30 ns FP32.4 SCC C
SMDJ-65608EV-45SC -55° to +125°45 ns FP32.4 SCC C
SMC9-65608EV-30SC -55° to +125°30 ns SB32.4 SCC C
SMC9-65608EV-45SC -55° to +125°45 ns SB32.4 SCC C
SMDJ-65608EV-30SB -55° to +125°30 ns FP32.4 SCC B
SMDJ-65608EV-45SB -55° to +125°45 ns FP32.4 SCC B
SMC9-65608EV-30SB -55° to +125°30 ns SB32.4 SCC B
SMC9-65608EV-45SB -55° to +125°45 ns SB32.4 SCC B
MMDJ-65608EV-30/883(*) -55° to +125°30 ns FP32.4 MIL 883 B
MMDJ-65608EV-45/883(*) -55° to +125°45 ns FP32.4 MIL 883 B
MMC9-65608EV-30/883(*) -55° to +125°30 ns SB32.4 MIL 883 B
MMC9-65608EV-45/883(*) -55° to +125°45 ns SB32.4 MIL 883 B
SMDJ-65608EV-30/883(*) -55° to +125°30 ns FP32.4 MIL 883 S
SMDJ-65608EV-45/883(*) -55° to +125°45 ns FP32.4 MIL 883 S
SMC9-65608EV-30/883(*) -55° to +125°30 ns SB32.4 MIL 883 S
SMC9-65608EV-45/883(*) -55° to +125°45 ns SB32.4 MIL 883 S
5962-895647QTC -55° to +125°30 ns FP32.4 QML Q
5962-895618MTC -55° to +125°45 ns FP32.4 QML Q
5962-895647VTC -55° to +125°30 ns FP32.4 QML V
5962-895618VTC -55° to +125°45 ns FP32.4 QML V
5962-895647QZC -55° to +125°30 ns SB32.4 QML Q
5962-895618MZC -55° to +125°45 ns SB32.4 QML Q
5962-895647VZC -55° to +125°30 ns SB32.4 QML V
5962-895618VZC -55° to +125°45 ns SB32.4 QML V
MMDJ-65608EV-30-E 25°30 ns FP32.4 Engineering Samples
MMC9-65608EV-30-E(*) 25°30 ns SB32.4 Engineering Samples
MM0-65608EV-30-E 25°30 ns Die Engineering Samples
5962-895647Q6A -55° to +125°30 ns Die QML Q
5962-895647V6A -55° to +125°30 ns Die QML V
© Atmel Nantes SA, 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
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by the Company in connection with the sale of Atmel pr oducts, expres sly or by implication. Atmel’s produc ts are not aut horized for use as crit ical
components in life support dev ices o r systems .
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