100304QCX - Fairchild Semiconductor

August 1989

Revised August 2000

100304 Low Power Quint AND/NAND Gate

100304

Low Power Quint AND/NAND Gate

General Description

The 100304 is monolithic quint AND/NAND gate. The

Function output is the wire-NOR of all five AND gate out-

puts. All inputs have 50 kΩ pull-down resistors.

Features

■Low Power Opera tion

■2000V ESD protection

■Pin/function compatible with 100104

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

(PLCC pack age only )

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

Logic Symbol

Pin Descriptions

Logic Equation

Connection Diagrams

24- Pin DIP

28-Pin PL CC

Order Number Package Number Package Description

100304PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100304QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100304QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Pin Names Description

Dna–Dne Data Inputs

F Functi on Out put

Oa–OeData Outputs

Oa–OeComplementary Data Outputs

F = (D1a • D2a) + (D1b • D2b) + (D1c • D2c) +

(D1d • D2d) + (D1e • D2e).

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100304

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 2: ESD te s ti ng c onforms t o M I L-STD-8 83, Meth od 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 3: The specified limits represe nt the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

DIP AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Storage Temperature (TSTG)−65°C to +150°C

Maximum Ju nction Temperature (T J)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) VEE to +0.5V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltage (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage −1830 −1475 m V Guaran teed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 µAV

IN = VIL (Min)

IIH Input High Current

D2a–D2e 250 µAV

IN = VIH(Max)

D1a–D1e 350

IEE Power Supply Current −69 −43 −30 mA Inputs open

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.40 1.75 0.40 1.65 0.40 1.75 ns

tPHL Dna–Dne to O, O

Figures 1, 2

tPLH Propagation Delay 1.00 2.60 1.00 2.60 1.15 3.20 ns

tPHL Data to F

tTLH Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns

tTHL 20% to 80%, 80% to 20%

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.40 1.55 0.40 1.45 0.40 1.55 ns

tPHL Dna–Dne to O, O

Figures 1, 2

tPLH Propagation Delay 1.00 2.40 1.00 2.40 1.15 3.00 ns

tPHL Data to F

tTLH Transition Time 0.35 1.10 0.35 1.15 0.35 1.10 ns

tTHL 20% to 80%, 80% to 20%

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100304

Industri a l Version

PLCC DC Electrical Characteristics (Note 4)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Symbol Parameter TC = −40°CT

C = 0°C t o +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1565 −1610 or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 0.50 µAV

IN = VIL (Min)

IIH Input HIGH Current

D2a–D2e 250 250 µAV

IN = VIH (Max)

D1a–D1e 350 350

IEE Power Supply Current −69 −30 −69 −30 mA Inputs OPEN

Symbol Parameter TC = 40°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay 0.35 1.55 0.40 1.45 0.40 1.55 ns

Figures 1, 2

tPHL Dna–Dne to O, O

tPLH Propagation Delay 1.00 2.40 1.00 2.40 1.15 3.00 ns

tPHL Data to F

tTLH Transition Time 0.35 1.10 0.35 1.15 0.35 1.10 ns

tTHL 20% to 80%, 80% to 20%

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100304

Test Circuitry

Notes:

VCC, VCCA = +2V, VEE = −2.5V

L1 and L2 = equal lengt h 50Ω impedance li nes

RT = 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to VCC and VEE

All unus ed out put s are loade d w it h 50Ω to G ND

CL = Fixture and stray capacita nc e ≤ 3 pF

FIGURE 1. AC Test Circuit

Switching Wavefo rms

FIGURE 2. Propagation Delay and Transition Times

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100304

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100304 Low Power Quint AND/NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

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user.

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device or system whose failure to perform can be rea-

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device or system, or to affect its safety or effectiveness.