Low Capacitance, Triple/Quad SPDT
±15 V/+12 V iCMOS Switches
Data Sheet ADG1233/ADG1234
Rev. D Document Feedback
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FEATURES
1.5 pF off capacitance
0.5 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP
Typical power consumption (<0.03 μW)
APPLICATIONS
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
ADG1233
S1B
D1
S1A
S2A
IN2IN1 IN3
D2
S2B
S3A
D3
S3B
SWI T CHES SHOWN FO R A L OGI C 1 INPUT
05743-001
LOGIC
EN
Figure 1.
SWITCHES SHOWN FOR A LOGIC 1 INPUT
05743-038
ADG1234
S1B
D1
S1A
S2A
IN2IN1 IN3
D2
S2B
S4B
D4
S4A
S3A
D3
S3B
LOGIC
EN
IN4
Figure 2.
GENERAL DESCRIPTION
The ADG1233 and ADG1234 are monolithic iCMOS® analog
switches comprising three independently selectable single-pole,
double throw SPDT switches and four independently selectable
SPDT switches, respectively.
All channels exhibit break-before-make switching action
preventing momentary shorting when switching channels. An
EN input on the ADG1233 and ADG1234 enables or disables
the device. When disabled, all channels are switched off.
The iCMOS (industrial-CMOS) modular manufacturing process
combines a high voltage complementary metal-oxide semi-
conductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation of
high voltage devices has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lowered power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these multiplexers
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make the
devices suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the devices ideally
suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 1.5 pF off capacitance (±15 V supply).
2. 0.5 pC charge injection.
3. 3 V logic-compatible digital input, VIH = 2.0 V, VIL = 0.8 V.
4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.
ADG1233/ADG1234 Data Sheet
Rev. D | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
8/2016—Rev. C to Rev. D
Changes to Analog Inputs Parameter and Digital Inputs
Parameter, Table 3 ............................................................................. 7
Updated Outline Dimensions ....................................................... 17
3/2016—Rev. B to Rev. C
Changes to Figure 5 and Figure 6 ................................................... 9
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/2009—Rev. A to Rev. B
Change to IDD Parameter, Table 1 ................................................... 4
Change to IDD Parameter, Table 2 ................................................... 6
Updated Outline Dimensions ....................................................... 16
8/2006—Rev. 0 to Rev. A
Updated Format ................................................................ \Universal
Changes to Table 1 .......................................................................... 13
Changes to Table 2 .......................................................................... 14
Changes to Figure 11 .................................................................... 110
Changes to Figure 12 .................................................................... 111
1/2006—Revision 0: Initial Version
Data Sheet ADG1233/ADG1234
Rev. D | Page 3 of 17
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
Y Version1
Unit Test Conditions/Comments
+25°C
−40°C to +85°C
−40°C to +125°C
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
On Resistance (R
ON
)
120
Ω typ VS = ±10 V, IS = −1 mA; see Figure 24
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between
Channels (∆RON)
3.5 Ω typ VS = ±10 V, IS = −1 mA
6 10 12 Ω max
On Resistance Flatness (RFL AT (O N)) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA
60 72 79 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage IS (Off ) ±0.02 nA typ VD = ±10 V, VS = −10 V; see Figure 25
±0.1 ±0.6 ±1 nA max
Drain Off Leakage I
D
(Off )
±0.02
nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = ±10 V; see Figure 26
±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±0.005 µA typ VIN = VINL or VINH
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS2
tTRANSITION 110 ns typ RL = 300 Ω, CL = 35 pF
130 150 170 ns max VS = 10 V; see Figure 27
tBBM 25 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = +10 V; see Figure 28
tON (EN) 120 ns typ RL = 300 Ω, CL = 35 pF
140 170 195 ns max VS = 10 V; see Figure 29
t
OFF
(
EN
)
40
ns typ RL = 300 Ω, CL = 35 pF
45 55 60 ns max VS = 10 V; see Figure 29
Charge Injection
0.5
pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 30
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
Channel-to-Channel Crosstalk
−85
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 33
Total Harmonic Distortion, THD + N 0.14 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz; see Figure 34
−3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 32
CS (Off ) 1.5 pF typ f = 1 MHz; VS = 0 V
1.7
pF max f = 1 MHz; VS = 0 V
C
D
(Off )
1.6
pF typ f = 1 MHz; VS = 0 V
1.8 pF max f = 1 MHz; VS = 0 V
ADG1233/ADG1234 Data Sheet
Rev. D | Page 4 of 17
Parameter
Y Version1
Unit Test Conditions/Comments
+25°C −40°C to +85°C −40°C to +125°C
CD, CS (On) 3.5 pF typ f = 1 MHz; VS = 0 V
4 pF max f = 1 MHz; VS = 0 V
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
IDD 260 µA typ Digital inputs = 5 V
475 µA max
ISS 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
ISS 0.002 µA typ Digital inputs = 5 V
1.0 µA max
V
DD
/V
SS
±5/±16.5
V min/max
GND = 0 V
1 Temperature range for the Y version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Data Sheet ADG1233/ADG1234
Rev. D | Page 5 of 17
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Y Version1
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA;
see Figure 24
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between
Channels (∆RON)
5 Ω typ VS = 0 V to 10 V, IS = −1 mA
16 26 27 Ω max
On Resistance Flatness (RFL AT (O N)) 60 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA
LEAKAGE CURRENTS
VDD = 13.2 V
Source Off Leakage IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
±0.1 ±0.6 ±1 nA max
Drain Off Leakage ID (Off ) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, see Figure 26
±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH
±0.001
µA typ
±0.1
µA max
IN
INL
INH
Digital Input Capacitance, C
IN
2
pF typ
DYNAMIC CHARACTERISTICS2
t
TRANSITION
135
ns typ RL = 300 Ω, CL = 35 pF
170 200 230
VS = 8 V; see Figure 27
tBBM 45 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 8 V; see Figure 28
tON (EN) 150 ns typ RL = 300 Ω, CL = 35 pF
195 230 265 VS = 8 V; see Figure 29
tOFF (EN) 45 ns typ RL = 300 Ω, CL = 35 pF
60 70 75 VS = 8 V; see Figure 29
Charge Injection −0.3 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 30
Off Isolation
−80
dB typ
L
L
see Figure 31
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 33
−3 dB Bandwidth 600 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 32
CS (Off ) 1.5 pF typ f = 1 MHz; VS = 6 V
1.7
pF max f = 1 MHz; VS = 6 V
C
D
(Off )
2
pF typ f = 1 MHz; VS = 6 V
2.2 pF max f = 1 MHz; VS = 6 V
CD, CS (On) 4 pF typ f = 1 MHz; VS = 6 V
4.5
pF max
S
ADG1233/ADG1234 Data Sheet
Rev. D | Page 6 of 17
Y Version1
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
I
DD
260
µA typ Digital inputs = 5 V
475 µA max
VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V
1 Temperature range for the Y version: −40°C to +125°C
2 Guaranteed by design, not subject to production test.
Data Sheet ADG1233/ADG1234
Rev. D | Page 7 of 17
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V
or30 mA (whichever
occurs first)
Digital Inputs GND − 0.3 V to VDD + 0.3 V
or30 mA (whichever
occurs first)
Continuous Current, S or D 24 mA
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Maximum)
100 mA
Operating Temperature Range
Automotive Temperature Range
(Y Version)
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP, θJA, Thermal Impedance 112°C/W
LFCSP, θJA, Thermal Impedance 30.4°C/W
Reflow Soldering Peak Temperature,
Pb-Fee
260°C
1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current must
be limited to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating is applied at any one time.
ESD CAUTION
ADG1233/ADG1234 Data Sheet
Rev. D | Page 8 of 17
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S1A
D1
S1B
S2A
D2
S2B
V
DD
IN1
EN
V
SS
S3A
IN2 IN3
D3
S3B
GND
ADG1233
TOP VIEW
(No t t o Scal e)
05743-002
Figure 3. 16-Lead TSSOP Pin Configuration
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S1A
D1
S1B
S2B
GND
VSS
IN1
S4A
D4
S4B
S3B
EN
VDD
IN2
S2A
D2
IN3
S3A
D3
IN4
ADG1234
TOP VIEW
(No t t o Scal e)
05743-003
Figure 4. 20-Lead TSSOP Pin Configuration
Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations
Pin No. ADG1233 16-Lead TSSOP Pin No. ADG1234 20-Lead TSSOP Mnemonic
1 16 VDD
2 2 S1A
3 3 D1
4 4 S1B
5
7
S2B
6 8 D2
7 9 S2A
8 10 IN2
9 11 IN3
10 12 S3A
11 13 D3
12 14 S3B
13 5 VSS
14 15 EN
15 1 IN1
16 6 GND
Not applicable 17 S4B
Not applicable 18 D4
Not applicable 19 S4A
Not applicable 20 IN4
Data Sheet ADG1233/ADG1234
Rev. D | Page 9 of 17
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
VDD
S1A
GND
IN1
VSS
EN
S3B
D3
05743-004
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
NOTES
1. NC = NO CO NNE CT. DO NO T CONNE CT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, V
SS
.
ADG1233
TOP VIEW
(Not to Scal e)
Figure 5. 16-Lead, 4 mm × 4 mm LFCSP Pin Configuration,
Exposed Pad Tied to Substrate, VSS
D1
S1B
V
SS
GND
S2B
V
DD
S4B
D4
S3B
D3
D2
S2A
IN2
S3A
IN3 EN
IN1
S1A
IN4
S4A
05743-005
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
ADG1234
TOP VIEW
(Not to Scal e)
NOTES
1. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, V
SS
.
Figure 6. 20-Lead, 4 mm × 4 mm LFCSP Pin Configuration,
Exposed Pad Tied to Substrate, VSS
Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations
Pin No. ADG1233 16-Lead LFCSP Pin No. ADG1234 20-Lead LFCSP Mnemonic
1 1 D1
2 2 S1B
3 5 S2B
4 6 D2
5 7 S2A
6 8 IN2
7 9 IN3
8 10 S3A
9 11 D3
10 12 S3B
11
3
V
SS
12 18 EN
13 19 IN1
14 4 GND
15 13 VDD
16 20 S1A
Not applicable 14 S4B
Not applicable 15 D4
Not applicable 16 S4A
Not applicable 17 IN4
Table 6. ADG1233/ADG1234 Truth Table
EN INx Switch xA Switch xB
1 X Off Off
0 0 Off On
0 1 On Off
ADG1233/ADG1234 Data Sheet
Rev. D | Page 10 of 17
TERMINOLOGY
VDD
Most positive supply potential.
VSS
Most negative power supply potential in dual supplies. In
single-supply applications, it can be connected to ground.
GND
Ground (0 V) reference.
RON
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
IS (Off)
Source leakage current when switch is off.
ID (Off)
Drain leakage current when switch is off.
ID, IS (On)
Channel leakage current when switch is on.
VD, VS
Analog voltage on Terminal D, Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (On)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL, IINH
Input current of the digital input.
IDD
Positive supply current.
ISS
Negative supply current.
Off Isolation
A measure of an unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
Frequency at which the output is attenuated by 3 dB.
On Response
Frequency response of the on switch.
THD + N
Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.
Data Sheet ADG1233/ADG1234
Rev. D | Page 11 of 17
TYPICAL PERFORMANCE CHARACTERISTICS
SOURCE OR DRAI N V OLTAG E ( V )
ON RESISTANCE (Ω)
200
100
0
–18 –15 –12 –9 –6 –3 12 15
90 63 18
05743-031
180
160
140
120
80
60
40
20
T
A
= 25° C V
DD
= +15V
V
SS
= –15V
V
DD
= +16. 5V
V
SS
= –16.5V
V
DD
= +13. 5V
V
SS
= –13.5V
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAI N V OLTAGE (V)
ON RES ISTANCE (W)
600
300
0–6 –4 –2 40 2 6
05743-032
500
400
200
100
T
A
= 25°C
V
DD
= 5V
V
SS
= –5V
V
DD
= 5.5V
V
SS
= –5.5V
V
DD
= 4.5V
V
SS
= –4.5V
Figure 8. On Resistance as a Function of VD (VS ) for Dual Supply
SOURCE OR DRAI N V OLTAG E ( V )
ON RESISTANCE (Ω)
450
250
300
00 2 4 6 12810 14
05743-033
400
350
150
200
100
50
TA = 25° C
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
VDD = 10.8V
VSS = 0V
Figure 9. On Resistance as a Function of VD (VS ) for Single Supply
TEMPERATURE (°C)
ON RESISTANCE (Ω)
250
0
–15 –10 –5 100515
05743-034
150
200
100
50
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40° C
VDD = + 15V
VSS = –15V
Figure 10. On Resistance as a Function of VD (VS ) for Different Temperatures,
Dual Supply
TEMPERATURE (°C)
ON RESISTANCE (Ω)
600
002 4 10
6 8 12
05743-035
300
400
200
500
100
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40° C
VDD = 12V
VSS = 0V
Figure 11. On Resistance as a Function of VD (VS ) for Different Temperatures,
Single Supply
TEMPERATURE (°C)
LEAKAGE CURRE NT (pA)
250
–250
–200
–150
–100
–50
0
100
50
150
200
020 40 60 80 100 120
05743-017
VDD = + 15V
VSS = –15V
VBIAS = + 10V /–10V
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
IS (OFF) + –
Figure 12. Leakage Currents as a Function of Temperature, Dual Supply
ADG1233/ADG1234 Data Sheet
Rev. D | Page 12 of 17
TEMPERATURE (°C)
LEAKAGE CURRE NT (pA)
130
–120
–70
–20
30
80
020 40 60 80 100 120
05743-018
VDD = 12V
VSS = 0V
VBIAS = 1V /10V
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
IS (OFF) + –
Figure 13. Leakage Currents as a Function of Temperature, Single Supply
LOGIC, IN
X
(V)
I
DD
(µA)
200
60
80
100
120
140
160
180
40
20
00 2 4 6 8 10 12 14 16
05743-006
V
DD
= 12V
V
SS
= 0V
V
DD
= +15V
V
SS
= –15V
I
DD
PER CHANNEL
T
A
= 25° C
Figure 14. IDD vs. Logic Level
V
S
(V)
CHARGE INJECTION (pC)
6
4
2
0
–2
–4
–6
–15 –10 –5 01510
5
05743-008
V
DD
= +15V
V
SS
= –15V
V
DD
= 12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
T
A
= 25° C
Figure 15. Charge Injection vs. Source Voltage
TEMPERATURE (°C)
TIME (ns)
220
180
200
160
140
120
100
80
20
40
60
0
–40 –20 20040 60 80 100 120
05743-011
BOFF AON 15V DS
BOFF AON 12V DS
AOFF BON 12V DS
AOFF BON 15V DS
Figure 16. tTRANSITION vs. Temperature
FREQUENCY ( Hz )
OFF ISOLATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
10k 100k 1M 10M 100M 1G
05743-036
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
Figure 17. Off Isolation vs. Frequency
FREQUENCY ( Hz )
CROSS TAL K ( dB)
–10
–20
–30
–40
–50
–60
–90
–80
–70
–100
10k 100k 1M 10M 100M 1G
05743-012
SxA – SxB
S1x – S2x
VDD = + 15V
VSS = –15V
TA = 25° C
Figure 18. Crosstalk vs. Frequency
Data Sheet ADG1233/ADG1234
Rev. D | Page 13 of 17
FREQUENCY ( Hz )
ON RESPONSE (dB)
0
–5
–10
–15
–20
–25
10k 100k 1M 10M 100M 10G
1G
05743-013
VDD = + 15V
VSS = –15V
TA = 25° C
Figure 19. On Response vs. Frequency
FREQUENCY ( Hz )
THD + N ( %)
10
1
0.10
0.0110 100 1k 10k 100k
05743-037
LOAD = 10kΩ
TA = 25° C
VDD = +5V, VSS = –5V, VS = +3.5V rms
VDD = + 15V , VSS = –15V , VS = +5V rms
Figure 20. THD + N vs. Frequency
V
BIAS
(V)
CAPACITANCE ( pF )
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0
–15 –10 –5 015105
05743-010
SOURCE /DRAI N ON
DRAIN O FF
SOURCE OF F
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
Figure 21. Capacitance vs. Source Voltage for Dual Supply
V
BIAS
(V)
CAPACITANCE ( pF )
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0024 6 810 12
05743-009
SOURCE /DRAI N ON
DRAIN O FF
SOURCE OF F
V
DD
= 12V
V
SS
= 0V
T
A
= 25° C
Figure 22. Capacitance vs. Source Voltage for Single Supply
V
BIAS
(V)
CAPACITANCE ( pF )
5.0
4.0
4.5
3.5
3.0
2.5
2.0
0.5
1.0
1.5
0–5 –4 –2
–3 –1 0 1 2345
05743-007
SOURCE /DRAI N ON
DRAIN O FF
SOURCE OF F
V
DD
= +5V
V
SS
= –5V
T
A
= 25° C
Figure 23. Capacitance vs. Source Voltage for Dual Supply
ADG1233/ADG1234 Data Sheet
Rev. D | Page 14 of 17
TEST CIRCUITS
I
DS
SD
V
S
05743-020
V
Figure 24. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
05743-021
Figure 25. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
05743-022
Figure 26. On Leakage
05743-023
INx
V
OUT
D
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300Ω
50%
50%
90%
50%
50%
90%
tON tOFF
V
IN
V
OUT
V
IN
Figure 27. Switching Timing
05743-024
INx
VOUT
D
SxA
VDD VSS
V
DD VSS
GND
CL
35pF
SxB
VIN
VS
0.1µF0.1µF
RL
300Ω
80%
t
BBM
t
BBM
VOUT
VIN
Figure 28. Break-Before-Make Delay
Data Sheet ADG1233/ADG1234
Rev. D | Page 15 of 17
OUTPUT
3V
0V
0V
V
O
ENABLE
DRIVE (V
IN
)
05743-025
EN
IN3
IN2
IN1 S1B
D1
V
DD
V
SS
V
DD
V
SS
GND
ADG1233
R
L
300Ω
C
L
35pF
V
S
50%
0.9V
O
0.9V
O
t
ON
(EN)
50%
V
O
S1A
V
IN
0.1µF0.1µF
50Ω
t
OFF
(EN)
Figure 29. Enable Delay, tON (EN), tOFF (EN)
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
∆V
OUT
ON
Q
INJ
= C
L
× ∆V
OUT
05743-026
INx
V
OUT
D
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
NC
SxB
V
IN
V
S
0.1µF0.1µF
Figure 30. Charge Injection
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
SxA
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05743-027
NC
SxB
OFF ISOLATION = 20 logV
OUT
V
S
50Ω
Figure 31. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
SxA
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05743-028
NC
SxB
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
Figure 32. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
SxA
D
SxB
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
05743-029
INx
Figure 33. Channel-to-Channel Crosstalk
VOUT
RS
AUDIO PRECISION
RL
10Ω
INx
VIN
S
D
VS
V p-p
VDD VSS
0.1µF
V
DD
0.1µF
VSS
GND
05743-030
Figure 34. THD + Noise
ADG1233/ADG1234 Data Sheet
Rev. D | Page 16 of 17
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM P LIANT T O JEDEC S TANDARDS M O-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC 1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARITY
0.10
Figure 36. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Data Sheet ADG1233/ADG1234
Rev. D | Page 17 of 17
4.10
4.00 SQ
3.90
0.35
0.30
0.25
2.25
2.10 SQ
1.95
1
0.65
BSC
BOTTOM VIEW
TOP VIEW
16
5
8
9
12
13
4
0.70
0.60
0.50
SEATING
PLANE
0.05 M AX
0.02 NO M
0.203 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGC.
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
04-15-2016-A
PKG-004025/5112
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOMVIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
08-16-2010-B
Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG1233YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1233YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1233YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
ADG1234YRUZ −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG1234YRUZ-REEL7 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG1234YCPZ-REEL −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-6
ADG1234YCPZ-REEL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-6
1 Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05743-0-8/16(D)