P4C164/P4C164L ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS (SCRAMS) Aq FEATURES m Full CMOS, 6T Cell @ High Speed (Equal Access and Cycle Times) 12/15/20/25 ns (Commercial) 20/25/35/45 ns (Military) m Low Power Operation (Commercial/Military) ~770mW Active - 12,15 - 660/743 mW Active - 20 ~ 495/575 mW Active 25, 35, 45 193/220 mW Standby (TTL Input) 5.5mW Standby (CMOS Input) P4C164L (Military) @ Output Enabie and Dual Chip Enable Control Functions Single 5V+10% Power Supply Data Retention with 2.0V Supply, 10 nA Typical Current (P4C164L Military) Common Data VO Fully TTL Compatible Inputs and Outputs Produced with PACE ll Technology Standard Pinout (JEDEC Approved) 28-Pin 300 mil DIP, SOJ ~ 28-Pin 600 mil Ceramic DIP 28-Pin 350 x 550 mil LCC x DESCRIPTION The P4C164 and P4C164L are 65,536-bit ultra high- speed static RAMs organized as 8K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate froma single 5V+10% tolerance power supply. With battery backup, data integrity is maintained with supply voltages down to 2.0V. Current drain is typi- cally 10 pA from a 2.0V supply. Access times as fast as 12 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 770 MW active, 193 mW standby. in full standby mode with CMOS inputs, power consumption is only 5.5 mW for the P4C164L. The P4C164 and P4C164L are members of a family of PACE RAM products offering super fast access times never before available at these complexity levels in TTL-compatible bipolar or CMOS technologies. The P4C164 and P4C164L are manufactured with PACE I! Technology. The P4C164 and P4C164L are available in 28-pin 300 mil DIP and SOU, 28-pin 600 mil ceramic DIP, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. x FUNCTIONAL BLOCK DIAGRAM Ae 65 536-BiT MEMORY ARRAY ROW SELECT A, INPUT~ [: Data |: COLUMN 410 CONTROL COLUMN SELECT 15990 Ay PIN CONFIGURATIONS we c2ek Suparyy ue? No fr: 4 "5 t) bg 26 sc] Ce, Ay fr: 6 1 BIT] Aye Ag [rs 6 24 cI] A,, As]i27 23 SIP Ag Agi: 8 22 52) OF Ayfiig 21 trl Ag Ag fz: 10 20 77] GE, vo, finn 19 2] Os vO, fz: 12. 14.15 16 te cc] vO, Wiss a AP S 288s 609 ssiec DIP (P5, D5-2, DS-1), SOU (J5) LOC (L5) TOP VIEW TOP VIEW SEMICONDUCTOR CORPORATION EON. Means Quality, Service and Speed 1992 Perlormance Semiconductor Corporation 416/924 PAC164/1641 MAXIMUM RATINGS Symbol Parameter Value Unt Symbol Parameter Value Unit Voc Power Supply Pin with | -0.5to+7 | V Tas Temperature Under ~55 to +125 | C Respect to GND Bias Terminal Voltage with 0.5 to Ts1 Storage Temperature | -6510 +150 | C Vyeru (povovy Veg 40.5 | V P, Power Dissipation 1.0 w up to 7. | DC Output Current 50 mA T, Operating Temperature | -55 to +125 | C an Ip ane 1519 01 RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Ambient 2 Ambient Grade Temperature GND Vec Grade' Temperature GND Voc Military ~55 to +125C OV 5.0V + 10% Commercial | 0C to +70C OV 5.0V + 10% 1819 03 1515.06 DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage Symbol P sf Test Conditi pacied pacteat Unit mbo aram st Conditions n ener . Min Max Min Max Vu Input High Voltage 2.2 | Vo,+0.5 2.2 |V_,+0.5] V Vi Input Low Voltage 0.5 0.8 0.58 0.8 Vv Vue CMOS input High Voltage Vog70.2 | Veg40.5 | V0.2 |V,,40.5] V Ve CMOS Input Low Voltage 0.5% 0.2 0.5%) 0.2 Vv Veo Input Clamp Diode Voltage| V,, = Min., |,, =-18 mA -1.2 -1.2 V Vo Output Low Voltage Ip, = +8 mA, Vo, = Min. 0.4 0.4 V (TTL Load) Vou Output High Voltage low= 4 MA, V.. = Min. 2.4 2.4 Vv (TTL Load) I Input Leakage Current Voce = Max. Mil. -10 +10 -5 +5 pA V,,= GND to Vy, Com, -5 +5 na Na leo Output Leakage Current | V,,.=Max.,CE=V,,, Mil. ~10 +10 -5 +5 | pA Vour= GND to V,, Com. -5 +5 Wa na 1559 0S CAPACITANCES (Vog = 5.0V, T, = 25C, f = 1.0MHz) Symbol Parameter Conditions | Typ. | Unit Symbol Parameter Conditions| Typ.| Unit Cy, input Capacitance! V,, = 0V 5 | pF Cour Output Capacitance | V,,,=0V | 7 | pF 151906 1519 07 Notes: 1, Stresses greater than those listed under MAXIMUM RATINGS May cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure ta MAXIMUM rating conditions for extended periods may affect reliability. 4/6/92 4-54 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with V, and |, not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20ns. 4. This parameter is sampled and not 100% tested.P4C164/164L POWER DISSIPATION CHARACTERISTICS Over recommended operating temperature and supply voltage 5 Test Conditi P4C164 P4C164L Unt bol P est Conditions nit ym arameter Min | Max | Min | Max lee Dynamic Operating Voo = Max., f = Max., Mil. _ Wa _ na mA Current 12,15 Outputs Open Com. _ 140 _ na lec Dynamic Operating Vog = Max., f = Max., Mil. _ 135 _ 135 mA Current 20 Outputs Open Com. _ 120 _ Wa lee Dynamic Operating Veg = Max., f = Max., Mi.| 105 105 mA Current - 25, 35, 45 Outputs Open Com. _ 90 _ Wa |, | Standby Power Supply CE, 2 V,, or MiL| = 40 = 40 mA Current (TTL Input Levels) CE, s V., Vog = Max., Comi| 35 _ Wa 20, 25, 35, 45 f = Max.. Outputs Open lgg. | Standby Power Supply CE, 2 V,, oF Current (TTL Input Levels) CE,< Vi, Veg = Max., Com. _ 45 _ na mA 12,15 fs Max. Outputs Open isa, | Standby Power Supply CE, 2 V,,, or Te 25 1 mA Current CE, < Ve Veg = Max., Com. _ 23 na (CMOS Input Levels) f= 0, Outputs. Open, Vin S Vig OF Vig 2 Vue n/a = Not Applicable 481908 DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only) Typ.* Max Symbol Parameter | Test Condition Min Voce Vec Unit i 2.0V 3.0V | 2.0V 3.0V Vor Veg for Data Retention 2.0 | | | ov leepr Data Retention Current | TE,2 V,,-0.2V or 15 200 | 300 LA po CE <0 2V, V2 Veg 0.2V }} a toon Chip Deselect to | or Vn <0.2V 0 ns Data Retention Time : aa > - ! [p_____| ._} ...__--__] t,' Operation Recovery Time | tac! | ns T= 425C T5199 Stic = Read Cycle Time This parameter is guaranteed but not tested DATA RETENTION WAVEFORM DATA RETENTION MODE Voc 45V Vor 2 2V 4.5V # 'cpr tg _4 ve WA LLL, 4-55 1519 01 alG/92PACIB4/164L A AC ELECTRICAL CHARACTERISTICSREAD CYCLE (Vo, = 5V + 10%, All Temperature Ranges)? -12* -15 -20 -25 35 -45 Sym. Parameter Unk Min | Max| Min| Max) Min) Max) Min | Max | Min | Max| Min | Max tae | Read Cycle Time 20 25 35 45 ns t,, | Address Access 15 20 25 35 45 | ns Time tye | Chip Enable 15 20 25 35 45 | ns Access Time ty, | Output Hold from 2 3 3 3 ns Address Change t.2 | Chip Enable to 2 3 3 3 ns Output in Low Z tyz | Chip Disable to 8 8 10 16 20 | ns Output in High Z toe | Output Enable 9 10 13 18 20 | ns Low to Data Valid toz | Output Enable 2 3 3 3 ns Low to Low Z toug | Output Enable 9 9 12 15 20 | ns High to High Z tp, | Chip Enable to 0 0 0 0 ns Power Up Time tpp | Chip Disable to 15 20 20 20 25 | ns Power Down Time : Advance Information terete Vec = 5V+5% READ CYCLE NO. 1 (OE CONTROLLED) ) ADDRESS al CE, CE2 DATA OUT Notes: see 5. WE is HIGH for READ cycle. 8. Transition is measured + 200 mV from steady state voltage prior to 6. cE, is LOW, CE, is HIGH and OE is LOW for READ cycle. change, with loading as specified in Figure 1. This parameter is 7. ADDRESS must be valid prior to, or coincident with TE, transition sampled and not 100% tested. LOW and CE, transition HIGH. 4sero2 4-56P4C164/164L READ CYCLE NO. 2 (ADDRESS CONTROLLED) & @) tre > ADDRESS x y } tay, o-- to, o DATA OUT PREVIOUS DATA VALID J x x DATA VALID 1519 03 READ CYCLE NO. 3 (CE,, CE, CONTROLLED) (7.1 tae cE, t y \ CE. ; K tac let th (010__ gs W tiz - DATAOUT HIGH IMPEDANCE 40) leg tpy al Voc SUPPLY 7 TT CURRENT _!sp 1519 04 Notes: 9. READ Cycle Time is measured from the last valid address to the first 10. Transitions caused by a chip enable control have similar delays transitioning address. irrespective of whether CE, or CE, causes them. 4-57 4/6924 P4C164/164L AC CHARACTERISTICSWRITE CYCLE (Vo, = 5V t 10%, All Temperature Ranges)\?) Sym. Parameter -12* 45 t we Write Cycle Time tow Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hoid Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write Min | Max| Min) Max! Min Max Min | Max Min Max Unit Min | Max 20 25 35 45 ns 15 18 25 33 ns 15 18 25 33 ns 0 ns 15 18 20 25 ns 0 ns 11 13 15 20 ns 0 ns 10 14 18 ns 5 ns Advance Information *Vec = 5V 45% WRITE CYCLE NO. 1 (WE CONTROLLED) (') Notes: 11. CE, and WE must be LOW, and CE, HIGH for WRITE cycle. 12. OE i is LOW for this WRITE cycle to show t,, ADDRESS CE2 DATA IN (ia) ic tow DATA VALID (8) ay DATA OUT / HIGH IMPEDANCE 2 ANG tow tow transitioning address. 13. If CE, goes HIGH, or CE, goes LOW, simultaneously with WE HIGH, the output remains In a high impedance state. 4/6/92 (8.13) ASIO TE 1819 0S 14, Write Cycle Time is measured from the last valid address to the firstP40164/164L TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED) ) 4) two ADDRESS x x j+las tow ce | N 1 A, jy tay > } taw * CE, | a twe We AAA WLLLLLLLLLLLLL1 tow tow DATA IN y DATA VALID / DATA ouT(12) HIGH IMPEDANCE 1519 05 AC TEST CONDITIONS TRUTH TABLE input Pulse Levels GND to 3.0V Mode | CE,| CE,| OE} WE| WO | Power Input Rise and Fall Times 3ns Standby | H x x X | HighZ| Standby input Timing Reference Level 1.5V Standby | X | L | X | X | HighZ) Standby Output Timing Reference Level 1.5V Dour 4 ; Output Load See Figures 1 and 2 Disabled H High 2 | Active 151912 Read L HJ oL H | Do, | Active Write H L | HighZ| Active 151013 +5V Roy = 166.50 4802 D Dour =1.73V OUT . . 30pF* (5pF* for tio rtigtons, 2552 30pF* (5pF' forty. ty, tow: touztwe and tow) toiz: twz and tow) 4519 07 4519 08 Figure 1. Output Lead * including scope and test fixture. Note: Because of the ultra-high speed of the P4C164/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-induc- tance leads that cause supply bounce must be avoided by bringing the Vand ground planes directly up to the contactor fingers. A 0.01 pF high frequency capacitor is also required between Veg and 4-59 Figure 2. Thevenin Equivalent ground. To avoid signal reflections, proper termination must be used; for example, a 502 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 1162 resistor must be used in series with D,,,, to match 1662 (Thevenin Resistance).P4C164/164L > a ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4c 164 I _ ss 1 L Temperature Range Package Code Speed (Access/Cycle Time) Low Power Designation: Blank = None, L = Low Device Number Static RAM Prefix | = Ultra-low standby power designator L, if available. ss = Speed (access/cycle time in ns), e.g., 25, 35 p = Package code, i.e., P, J, C, OW, L. { = Temperature range, i.e., C, M, MB. 1519 00 PACKAGE SUFFIX TEMPERATURE RANGE SUFFIX Package Temperature Suttix Description Range Suffix Description P Plastic DIP, 300 mil wide standard Cc Commercial Temperature Range, J Plastic SOJ, 300 mil wide standard 0C to +70C. CG Sidebrazed DIP, 300 mil wide M Military Temperature Range, DW CERDIP, 600 mil wide 55C to +125C. L Leadiess Chip Carrier (ceramic) MB Mil. Temp. with MIL-STD-883D D CERDIP, 300 mil wide standard Class B compliance 1819 14 181915 SELECTION GUIDE The P4C 164 is available in the following temperature, speed and package options. The P4C164L is available for military temperatures with access times of 25ns and slower. The P4C164/164L is available to Standardized Military Drawings 5962-85525 and 5962-38294. Check Mil-Bul-103 for current listing of part types. Temp. Speed Range | Package 15 20 25 35 45 Com'l Plastic DIP -15PC -20PC -25PC N/A N/A Plastic SOJ -15JC -205C -25J5C N/A N/A CERDIP (300 mil) -15DC -20DC -25DC N/A N/A Loc -15LC -20LC -25LC NYA N/A Mil. CERDIP (300 mil) N/A -20DM -25DM -35DM -45DM Temp CERDIP (600 mil) N/A -20DWM | -25DWM | -35DWM | -45DWM LCC N/A -20LM -25LM -35LM -45LM Military | CERDIP (300 mil) N/A -20DMB | -25DMB | -35DMB | -45DMB Procd* | CERDIP (600 mil} N/A -20DWMB |-25DWMB_, -35DWMB -45DWMB LCC L N/A | -20LMB | -25LMB | -35LMB | -45LMB 2; Advance Information sere * Military temperature range with MIL-STD-883 Revision D, Class B processing. N/A = Not available 4/6/92 4-60