PRELIMINARY
128K x 36 Synchronous-Pipelined Cache RAM
f
ax
id
:
1113
CY7C1347
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
g
ust 24
,
1998
Features
• Lo w (1.65 mW) standby power (f=0, L version)
• Supp orts 100- M H z bus for Pentium® and Power PC™
operations with zero w ait states
• Fully registered inputs and outputs f or pipel ined
operation
• 128K x 36 common I/O architect ure
• Single 3.3V po wer supply
• Fast cloc k-to-output times
—3.5 ns (f or 166-MHz device)
—4.0 ns (f or 133-MHz device)
—4.5 ns (f or 117-MHz device)
—5.5 ns (f or 100-MHz device)
• User-selectable burst counter supporting Intel®
P entium interleaved or linear burst sequen ces
• Sep arate proces sor and controller address strobes
• Synchronous sel f-time d writ es
• Asynchronous out put enable
• JEDEC-standard 100-pin TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Descripti on
The CY7C1347 is a 3.3V 128K by 36 synchronous-pipelined
cache SRAM designed to suppor t zero wait state secondary
cache with mini mal gl ue logic.
All sync hronous i nputs pass through i nput regi ster s control led
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
devi ce). A 2 -bit on- chip wrap around bur st counter captures t he
first addr ess in a burst se quence an d automati cally increments
the address for the rest of the burst access.
The CY7C1347 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the P owerPC. The burst
sequence is select ed through the MODE pi n. Accesses can be
initiated by asserting either the processor address strobe
(ADSP) or the controller address strobe (ADSC) a t cl ock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A G lobal Writ e Enable (GW ) ov errides
the b yte write i npu ts and write s data t o all f our b y tes. All writ es
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three sy nchronou s chip sel ects (CE1, CE2, CE3) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output th ree-state control. In order to provi de proper data
during dep th e xpans ion, OE is mas k ed during t he fi rst cloc k o f
a read cycle when em erging from a deselected state.
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Logic Block Diagram
CLK
ADV
ADSC
A[15:0]
GW
BWE
BW3
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
OUTPUT
REGISTERS INPUT
REGISTERS
MEMORY
ARRAY
CLK CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ
DQ[31:24]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
DQ
ENABLE
REGISTER
DQ
CE
CLK
ENABLE DELAY
REGISTER
D Q
CLK
36 36
16
14
14
16
(A0,A1)2
ADSP
DQ[31:0]
DP[3:0]
BW2DQ
DQ[23:16]
BYTEWRITE
REGISTERS
BW1DQ
DQ[15:8]
BYTEWRITE
REGISTERS
128K x 36
CY7C1347
PRELIMINARY
2
Pin Configuration 100-Lead TQFP
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
DP1
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE0
BYTE1
BYTE3
BYTE2
Selec tion Guid e
7C1347-166 7C1347-133 7C1347-117 7C1347-100
Maximum Access Time (ns) 3.5 4.0 4.5 5.5
Maxim um Operating Current (mA) 420 375 350 325
Maximum Standby Current ( mA) 2.0 2.0 2.0 2.0
CY7C1347
PRELIMINARY
3
Pin Definitions
Pin Number Name I/O Description
50–44, 81,82,
99, 100,
32–37
A[16:0] Input-
Synchronous Address Inputs used to select on e of the 128K address locatio ns. Sampl ed at th e
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A0 and A1 feed the 2-bit counter.
96–93 BW[3:0] Input-
Synchronous Byte Write Select In puts, active LOW. Quali fi ed with BWE to conduct byte writes
to the SRAM. Sampl ed on the rising edge of CLK.
88 GW Input-
Synchronous Global Write Enabl e Input, acti ve LO W . When asserted LOW on the risi ng edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the v alues
on BW[3:0] and BWE).
87 BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampl ed on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
89 CLK Input-Cl ock Clock input. Used to capture all sy nchronous inputs to the de vice. Also used to
increment the bur st count er when ADV is asserted LOW, during a burst operat ion.
98 CE1Input-
Synchronous Chip Enab le 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the devic e. ADSP is i gnored if
CE1 is HIGH.
97 CE2Input-
Synchronous Chip Enable 2 Input, act ive HIGH. Sam pled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/de select t he devic e.
92 CE3Input-
Synchronous Chip Enab le 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to sel e ct/deselect the de vice.
86 OE Input-
Asynchronous Output Enable, asynchronous input, active LO W. Controls th e direction of t he I/O
pins. When LOW , the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are t hree-st ated, and a ct as i nput dat a pins . OE i s mas ked duri ng the f irst cloc k of
a read cycle when emerging fro m a dese lected state.
83 ADV Input-
Synchronous Adva nce Input signal , samp led on the risi ng edge o f CLK. When asserted, it auto-
mat ically increments the add ress in a burst cycle.
84 ADSP Input-
Synchronous Address Strobe from Processor, sampled on the rising edge of CLK. When assert-
ed LOW , A[16:0] is capt ured in t he address registe rs. A 0 and A1 are also load ed into
the b ur st count er. When ADSP and ADSC are bo th a ssert ed, onl y ADSP is recog-
nized. ASDP is ignored when CE1 is deasserted HIGH.
85 ADSC Input-
Synchronous Address Strobe from Cont roll er , samp led on t he risi ng edge of CLK. When as sert-
ed LOW , A[16:0] is capt ured in t he address registe rs. A 0 and A1 are also load ed into
the b ur st count er. When ADSP and ADSC are bo th a ssert ed, onl y ADSP is recog-
nized.
64 ZZ Input-
Asynchronous ZZ “s leep” I nput. This active HIGH input pl aces the device in a non-t ime critical
“sleep” co ndition with data int egrity preserv ed.
30–28,
25–22, 19,
18, 13, 12,
9–6, 3–1,
80–78,
75–72, 69,
68, 63, 62,
59–56, 53–51
DQ[31:0],
DP[3:0] I/O-
Synchronous Bidirectional Data I/O lines. As inputs, they f eed into an on-chip data register that
is trigger ed b y the rising edge of CLK. As outp uts, the y deli ver the data con tained
in the memory location specified by A[16:0] during t he previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When O E is asserted
LO W, the pins behave as outputs . When HIGH, DQ [31:0] and DP[3:0] are placed in
a three- state conditi on.
15, 41, 65, 91 VDD Power Supply Power suppl y inpu ts to t he core of the de vice . Shou ld be conn ect ed to 3.3V power
supply.
17, 40, 67, 90 VSS Ground G round fo r the core of the device. Should be connected to gr ound of the system.
4, 11, 20, 27,
54, 61, 70, 77 VDDQ I/O P ower
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
5, 10, 21, 26,
55, 60, 71, 76 VSSQ I/O Ground Ground for the I/O ci rcuitry. Should be connected to ground of the system.
31 MODE Input-
Static Selects b urst order. When tied to GND sele cts li near burst s equence. When ti ed
to VDDQ or left floa ting selects interl eaved burst sequenc e. This is a strap pin and
should remain static during device operation.
14, 16, 38, 39,
42, 43, 66 NC -No Connects
CY7C1347
PRELIMINARY
4
Introduction
Functional Overview
All synchrono us inp uts pass th rou gh input r egiste rs con trol led
by the rising edge of the clock. All data outputs pass through
outpu t regist ers control le d by the ri sing edge of the cloc k. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device). A two-bit on-chip wraparound burst counter captures
the first addr ess in a burst sequence and automatically incre-
ments the address for the rest of the burst access.
The CY7C134 7 supports secondary cache in systems utiliz ing
either a linear or interl eaved burst sequence. The int erleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst seque nce. The burst order is user selectab le, and is de-
termined by sampling the MODE inpu t. Accesses can be initi-
ated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input.
Byte write operations are qual ified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Gl obal Write
Enable (GW) overrides al l byte writ e inputs an d writ es data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circ uitry.
Three synchronous chip selects (CE1, CE2, CE3) and an asyn-
chronous output enable (OE) provide for easy bank selecti on
and output three-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE 2, CE3 ar e all ass erted activ e, and ( 3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs
(A0–A16) is store d into the addr ess advancemen t logi c and th e
address register while being presented to the memory core.
The cor res ponding data is allo we d to pro pagate t o t he input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.5 ns (166-MHz device) if OE is active
LO W. The only e xcept ion occur s when the SRAM is emerg ing
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the fi rst cycle of the access, the output s are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at cl ock r ise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Ini tiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asser t ed LOW, and (2)
CE1, CE 2, CE3 a re all a sserted act iv e. The add res s prese nte d
to A0–A16 is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals ( G W, B W E, and BW[0:3]) and ADV inputs are ig-
no red during this first cycle.
ADSP triggered write accesses require two clock cycles to
comp lete . If GW is asserted LO W on the second clock rise , th e
data presented to the DQ0–DQ31 and DP inputs are written
into the corresponding address location in the RAM core. If
GW is HIGH, then the write operation is controlled by BWE and
BW[3:0] signals. The CY7C1347 provides byte write capability
that is described in the write cycle description table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[3:0]) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed writ e mechanism
has been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enabl e (OE) must be deasse rted HIGH b efore pre senting dat a
to the DQ0–DQ31 and DP inputs. Doing so will thre e -s tat e the
output drivers. As a safety precaution, DQ0–DQ31 and DP s are
automatically three-stated whene ver a write cycle is detected,
regardless of the state of OE.
Single Write Acce sses Ini ti ated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, C E2, CE 3 are all asser ted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a write to
t h e de sired byte (s). A D S C t riggered write accesses require a
single clock cycle to complete. The address presented to
A0–A16 is loaded into the address register and the address
advan cement l ogic while be ing deli vered to t he RAM core . The
ADV input is i gnored during this cycle. If a global write is con-
ducted, the data presented to the DQ0–DQ31 and DPs are
written into the corresponding address location in the RAM
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write me chanism
has been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enabl e (OE) must be deasse rted HIGH b efore pre senting dat a
to the DQ0–DQ31 and DP inputs. Doing so will thre e -s tat e the
output drivers. As a safety precaution, DQ0–DQ31 and DP s are
automatically three-stated whene ver a write cycle is detected,
regardless of the state of OE.
Burst Se quences
The CY7C1347 pr ov ides a tw o-bit wrapar ound c ounter, f ed b y
A0 and A1, t hat imple ments either an interleave d or linear burst
sequence . The inte rleaved b urst sequen ce i s des ign ed speci f-
ically to support Intel Pentium applications. The linear burst
sequence is designed to suppor t processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input .
Asser ting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
CY7C1347
PRELIMINARY
5
Sleep Mode
The ZZ input pin is an asyn chronous input. Assert ing ZZ plac -
es the SRAM in a pow er conservat ion “slee p” mode . Two cloc k
cycles are req uired t o enter i nto or e xi t from t his “ sleep” mode .
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be desele cted prior to entering t he “sleep” mo de.
CE1, CE2, CE3, ADSP, and ADSC must remain inactiv e f or the
duratio n of tZZREC after the ZZ input returns LOW.
Linear Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Cycle Description Table[1, 2, 3]
Cycle Description ADD
Used CE1CE3CE2ZZ ADSP ADSP ADV WE OE CLK DQ
Deselected Cyc le, P ower- down None H X X L X L X X X L-H High-Z
Deselected Cyc le, P ower- down None L X L L L X X X X L-H High-Z
Deselected Cyc le, P ower- down None L H X L L X X X X L-H High-Z
Deselected Cyc le, P ower- down None L X L L H L X X X L-H High-Z
Deselected Cyc le, P ower- down None X X X L H L X X X L-H High-Z
Snooze M ode, P ower-down None X X X H X X X X X X Hi gh-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycl e, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycl e, Continue Burst Ne xt X X X L H H L L X L-H D
Write Cycl e, Continue Burst Ne xt H X X L X H L L X L-H D
Read Cycle, Sus pend Burst Current X X X L H H H H L L-H Q
Read Cycle, Sus pend Burst Current X X X L H H H H H L -H High-Z
Read Cycle, Sus pend Burst Current H X X L X H H H L L-H Q
Read Cycle, Sus pend Burst Current H X X L X H H H H L-H High-Z
Write Cycl e, Suspend Burst Cur rent X X X L H H H L X L -H D
Write Cycl e, Suspend Burst Cur rent H X X L X H H L X L -H D
Note:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active
CY7C1347
PRELIMINARY
6
Maximum Ratings
(Above whi ch the usefu l l ife ma y be impaired. For user guide-
li nes, not tested.)
Storage Temperat ure .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage on V DD Relative to GND.........−0.5V to +4.6V
DC Voltage Appli ed to Output s
in High Z State[5] .....................................−0.5V to VDDQ + 0.5V
DC Input Volt age[5]..................................−0.5V to V DDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage . ............ ............ .. ........ ....... >2001V
(per MIL- STD-883, Met hod 3015)
Latch-Up Curr ent............... .. .......... .. ...... .. .. ............. >200 mA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the “instant on” case temperature
Write Cycle Descriptions[1, 2, 3, 4]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byt e 0, DP0101110
Write Byt e 1, DP1101101
Write Byt es 1, 0, DP0, DP 1101100
Write Byt e 2, DP2101011
Write Byt es 2, 0, DP2, DP 0101010
Write Byt es 2, 1, DP2, DP 1101001
Write Byt es 2, 1, 0, DP2, DP1, DP0101000
Write Byt e 3, DP3100111
Write Byt es 3, 0, DP3, DP 0100110
Write Byt es 3, 1, DP3, DP 0100101
Write Byt es 3, 1, 0, DP3, DP1, DP0100100
Write Byt es 3, 2, DP3, DP 2100011
Write Byt es 3, 2, 0, DP3, DP2, DP0100010
Write Byt es 3, 2, 1, DP3, DP2, DP1100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
Operating Range
Range Ambient
Temperature[6] VDD
Com’l 0°C to +70°C 3.3V −5%/+10%
CY7C1347
PRELIMINARY
7
Electrica l Characteristics Over the Opera ti ng Range
Parameter Description Test Conditions Min. Max. Unit
VCC Power Supply Voltage 3.135 3.6 V
VDDQ I/O Suppl y Voltage 3.135 3.6 V
VOH Output HIGH Voltage VDD = Min., IOH = −4.0 mA 2.4 V
VOL Output LO W Voltage VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VDDQ + 0.3V V
VIL Input LOW Vol tage[7] –0.3 0.8 V
IXInput Load C urrent
except ZZ and MODE GND ≤ VI ≤ VDDQ −55µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDDQ 30 µA
IOZ Out put Leakage
Current GND ≤ VI ≤ VDDQ, Output Disab led −55µA
ICC VDD Operating Supply
Current VDD = Max., IOUT = 0 mA ,
f = fMAX = 1/ t CYC 6-ns cycl e, 166 MHz 420 mA
7.5-ns cycle, 133 MHz 375 mA
8.5-ns cycle, 117 MHz 350 mA
10-ns cycle, 100 MHz 325 mA
ISB1 Auto ma tic C S
Power-Down
Current—TTL Inputs
Max. VDD, D evi ce D es e le cte d ,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/ t CYC
6-ns cycle, 166 MHz 35 mA
7.5-ns cycle, 133 MHz 30 mA
8.5-ns cycle, 117 MHz 25 mA
10-ns cycle, 100 MHz 25 mA
ISB2 Auto ma tic C S
Power-Down
Current—CMOS Inputs
Max. VDD, D evi ce D es e le cte d ,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
2.5 mA
L Version 500 µA
ISB3 Auto ma tic C S
Power-Down
Current—CMOS Inputs
Max. VDD, Devi ce Desel ected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/ t CYC
6-ns cycle, 166 MHz 10 mA
7.5-ns cycle, 133 MHz 10 mA
8.5-ns cycle, 117 MHz 10 mA
10-ns cycle, 100 MHz 10 mA
ISB4 Auto ma tic C S
Power-Down
Current—TTL Inputs
Max. VDD, D evi ce D es e le cte d ,
VIN ≥ VIH or VIN ≤ VIL, f = 0 18 mA
ZZ Mode Elec trical Characteristics
Parameter Description Test Conditions Min Max Unit
ICCZZ Snooze mo de
standby curr ent ZZ > VDD − 0.2V 3 mA
ICCZZ (L Version) Snooze mode
standby curr ent ZZ > VDD − 0.2V 800 µA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2t CYC ns
CY7C1347
PRELIMINARY
8
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
6pF
CCLK Clock Input Capacitanc e 8pF
CI/O Input/Output Capacitance 8pF
AC Test Loads and Waveforms
Notes:
7. Tested initially and after any design or process changes that may affect these parameters.
8. Input waveform should have a slew rate of 1V/ns.
3.0V
GND
OUTPUT
R=317Ω
R=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INPUT PULSES
OUTPUT
RL=50Ω
Z0=50Ω
VL= 1. 5V
3.3V [8]
CY7C1347
PRELIMINARY
9
Switching Charac teris t ics Ov er the Operating Range[9,10,11]
-166 -133 -117 -100
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cycle Time 67.5 8.5 10 ns
tCH Clock HIGH 1.7 1.9 2.5 3.5 ns
tCL Clock LOW 1.7 1.9 2.5 3.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.5 2. 5 2.5 ns
tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCO Data Output Valid After CLK Rise 3.5 44.5 5.5 ns
tDOH Data Output Hol d After CLK Rise 1.5 2.0 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns
tADH ADSP, ADSC Hold After CLK Ris e 0.5 0.5 0.5 0.5 ns
tWES BWE, GW, BW[1:0] Set-Up Before CLK
Rise 2.0 2.5 2.5 2.5 ns
tWEH BWE, GW, BW[1:0] Hold After CLK
Rise 0.5 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tDS Data Input Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns
tDH Data Input Hold Aft er CLK Rise 0.5 0.5 0.5 0.5 ns
tCES Chip Select Set -Up 2.0 2.5 2. 5 2.5 ns
tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCHZ Clock to Hi gh-Z[10, 11] 3.5 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[10, 11] 0 0 0 0 ns
tEOHZ OE HIGH to Output High-Z[10, 11] 3.5 3.5 3.5 3.5 ns
tEOLZ OE LOW to Output Low-Z[10,11] 0 0 0 0 6 ns
tEOV OE LOW to Output Valid[10] 3.5 3.5 3.5 3.5 ns
Notes:
9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference lev els of 1.5V, input pulse level s of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
10. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
11. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
CY7C1347
PRELIMINARY
10
Switching Wa vef orms
Write Cycle Timing
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Data-
In
tCYC
tCH
tCL
tADS
tADH
tADS
tADH
tADVS
tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single Write Burst Write Unselected
ADSP ignored wit h CE1 inact ive
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipelined Write
WE is the combination of BWE & BWx to define
a write cycle (see Wr it e C ycle Descriptions table).
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unselected wit h CE2
CY7C1347
PRELIMINARY
11
Read Cycle Timing
Switching Wa vef orms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data-
Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCO
tDOE
2b 2c 2d 3a
1a
tEOHZ tDOH
tCLZ tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 inactive
Suspend Burst
CE1 masks AD SP
= DON’T CARE = UNDEFINED
Pipel ined Read
WE is the co mb ination of BWE & BWx to define
a writ e cycle (see Write Cycle Descriptions t able).
ADSC initiated r ead
Uns el ected with CE 2
CY7C1347
PRELIMINARY
12
Read/Writ e Cycle Timing
Switching Wa vef orms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Data-
In/Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 WD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tEOLZ
tCO
tDOE
3a 3c 3d
1a
tEOHZ tDOH
tCHZ
Singl e Read Burst Read Unselected
ADSP ig no re d with C E 1 inactive
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
WE is the combination of BWE & BWx to define
a write cycle (see Wr ite Cycle Descriptions table).
Out 2a
In 3b
Out
Out Out Out
Single Write
tDS tDH
2a
Out
See Note.
Note: Wri te data fo rwarded to outputs on read immediately
following a write.
CY7C1347
PRELIMINARY
13
Switching Wa vef orms (continued)
In/Out
A
tAS
= DON’T CARE = UNDEFINED
WE is t he combination of BWE , B WS [1:0] and GW to defin e a writ e cycle (see Write Cycle Descriptions table).
tCLZ
tCHZ
CE is the co mb ination of CE2 and CE3. All chip selects need t o be acti ve in order to select
the device. RAx stands for Read Addr ess X, WAx stands f or Wri te Address X, Dx stands for Data-i n X,
tDOH
CLK
ADD
WE
CE1
Data
B
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q(D) D(C)
D (E) D (F) D (G)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCDV
Pipeli ne Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
Qx stands for Data-out X.
CD
Q(C)
EFGH
D (H)
CY7C1347
PRELIMINARY
14
Switching Wa vef orms (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
ICC ICC(active)
Three-state
I/Os
Note:
12. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device.
13. I/Os are in three-state when exiting ZZ sleep mode.
ZZ Mode Timing [12,13]
CE2
ICCZZ
HIGH
CY7C1347
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or other rights. C ypress Semi condu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems appli cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00727
Orde ring Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
166 CY7C13 47–166AC A101 100-Lead Thin Quad Flat Pack Commer cial
166 CY7C1347L–166A C A1 01 100-Lead Thin Quad Flat Pack Commercial
133 CY7C13 47–133AC A101 100-Lead Thin Quad Flat Pack Commer cial
133 CY7C1347L–133A C A1 01 100-Lead Thin Quad Flat Pack Commercial
117 CY7C13 47–117AC A101 100-Lead Thin Quad Flat Pack Commer cial
117 CY7C1347L–117A C A1 01 100-Lead Thin Quad Flat Pack Commercial
100 CY7C13 47–100AC A101 100-Lead Thin Quad Flat Pack Commer cial
100 CY7C1347L–100A C A1 01 100-Lead Thin Quad Flat Pack Commercial
Package D iagr am
100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
