SONY. CXKS864BP/BSP/BM OH ea 8,192-word x 8-bit High Speed CMOS Static RAM Maintenance Only Description CXK5864BP/BSP//BM are 65,536 bits high speed CMOS static RAMs organized as 8,192 words by 8 bits and operates from a single 5V supply. These IC are suitable for use in high speed and low power. applications in which battery back up for nonvolatility is required. Features Fast access time (Access time) CXK5864BP/B8SP/BM-70L, 7OLL 7Ons(Max.) CXK5864BP/BSP/BM-10L, 10LL 100ns(Max.) CXKS864BP/BSP/BM-12L, 12LL 120ns(Max.) @ Low power operation: CXK5864BP/BSP/BNM-7OLL, 10LL, 12LL; Standby/Operation : 5 uW (Typ.) /40mW (Typ.) CXK5864BP/BSP/BM-7OL, 10L, 12L; Standby/Operation : 10 uW (Typ.) /40mW (Typ.) e Single power supply 5V:+5V+10% CXK5864BP 28 pin DIP (Plastic) CXK5864BSP CXK5864BM 28 pin DIP (Plastic) 28 pin SOP (Plastic) Fully static memory --- No clock or timing strobe required Function Equa! access and cycle time 8,192-word X 8-bit static @Common data input and output: three state output RAM Directly TTL compatible: All inputs and outputs Low voltage data retention : 2.0V (Min.) Structure @ Available in 28 pin 600mil DIP, 300mi! DIP and 450mil SOP Silicon gate CMOS IC Block Diagram Pin Configuration Pin Description {Top View) Symbol Description AO to . A12 Address input |uemery terns 1/01 to 256 x 256 f- GND aro F ao S putter . (70 Gorn az FF 3 Column Decoder ay 4 as Te 170 Butter cez W709 +708 1/08 Data input output CE1, CE2 |Chip enable 1, 2 input WE Write enable input OE Output enable input Vec +5V Power supply GND Ground NC No connection E89720B0Y ~ ST - 62 -SONY CXK5864BP/BSP,//BM Absolute Maximum Ratings (Ta = 25C, GND = OV) Item Symbol Rating Unit Supply voltage Veco ~0.5 to +7.0 Vv Input voltage Vin -0.5* to Veco+0.5 Vv Input and output voltage Vifo -0.5* to Veco+0.5 Vv oo, CXK5864BP//BSP 1.0 Allowable power dissipation | Pp Ww CXK5864BM 0.7 : Operating temperature Topr ve 0 to +70 ae Storage temperature Tstg -55 to +150 a) Soldering temperature time Tsolder 260+ 10 C * sec * Vin, Vio= 3.0V Min. for pulse width less than 50ns. Truth Table CET | CE2 OE WE Mode 1/01 to 1/08 | Vec Current H x x x Not selected High Z Isai, IsB2 xX L x x Not selected High Z \sa1, Isp2 L H H H Output disable High Z lec1, Iece L H L H Read Data out Iec1, Iec2 L H x L Write Data in lec1, bec2 x: H" or L DC Recommended Operating Conditions (Ta=0 to + 70C, GND=OV) Item Symbol! Min. Typ. Max. Unit Supply voltage Vec 45 5.0 5.5 Vv Input high voltage Vi 2.2 _ Veo + 0.3 Vv Input low voltage Vit -0.3* 0.8 Vv * Vi =3.0V Min. for pulse width less than 50ns. 63 -SONY CXKS864BP/BSP/BM Electrical Characteristics @DC and operating characteristics (Vec = 5V + 10%, GND=OV, Ta=0 to + 70C) 7OL/10L/12L Item Symbol Test conditions 7OLL/1OLL/12LL Unit Min. | Typ.* | Max. Input leak current lu Vin =GND to Veco - 500; 500 nA Vivo=GND to Vcc Output leak current ILo CE1=Vin or CE2=Vit or - 500} 500 nA OE =Vin or WE=Vit Operating suppl CE1 = Vit, CE2 = Vin, current g pply lect Vin = Vin or Vi, _ 8 15 mA lout = OmMA Average operating Min. cycle _ current lec2 Duty = 100 %, lout = OmA 30 50 mA CE2 $0.2V -L 2 60 Isai CE1 2 Voc 0.2V HA Standby current OF \GE2 2 Veo - 0.2V -tl | 1 30 Isp2 CE1=Vin or CE2=ViL 0.1 2 mA Output high voltage Vou lon = 1.0mMA 2.4 _ v Output low voltage Vou lo. = 2.1mMA 0.4 Vv * Voc = 5V, Ta = 25C Pin capacitance (Ta = 25C, f = 1MHz) Item Symbol | Test conditions | Min. Max. Unit Input capacitance Cin Vin = OV 7 pF Input/Output capacitance | Cio Vizo = OV _ 7 pF Note) This parameter is sampled and is not 100% tested. AC characteristics @AC test conditions (Vcc =5V+ 10%, Ta=0 to + 70) Item Conditions Input pulse high level Vin = 2.2V Input pulse low level Vit = 0.8V Input rise time tr=5ns input fall time tf =5ns TT Input and output reference level 1.5V Te Output load | 10L/10LL/12L/12LL | CL*= 100pF, 1TTL com conditions | 70L/70LL CL*= 30pF, 1TTL * CL includes scope and jig capacitances. 64 -SONY CXK5864BP /BSP//BM @Read cycle 7OL/7OLL!| 10L/10LLj) 12L/12LL ; Item Symbol - - - Unit Min..| Max. | Min. | Max. | Min. | Max. Read cycle time tre 70 | ~~] 100 ; | 120 | ! ns Address access time taa | 70 | |} 100 | | 120 | ns Chip enable access time (CE1, CE2) ne | 70 !|~ | 100 | - |] 120 | ns Output enable to output valid toe }|} 35 | ] 50 | ) 60 ns Output hold from address change tou 10 | 10 | 10 | ! ns Chip enable to output in low Z tLz1 __ _ (CET, CE2) tiz2 10 10 10 ns Output enable to output in low Z __ __ (GE) toLz 5 5 5 ns Chip disable to output in high Z tHz1 * (CET, CE2) tez2* 0 30 0 35 0 45 ns oD disable to output in high Z touz * 0 30 0 35 0 45 ns * tHz1, tHz2 and toHz are defined as the time at which the outputs become the high impedance state and are not referred to output voltage levels. @Write cycle 7OL/7OLL) 10L/10LL] 12L/12LL ; Item Symbol - - - Unit Min. | Max. | Min. | Max. | Min. | Max. Write cycle time twe 70 | | 100 | | 120 | | ns Address valid to end of write taw 60 | | 80 | | 85 | j|ns Chip enable to end of write tcw 60 ; - | 80 || 85 | ~]|ns Data to write time overlap tow 30 | | 35 | |! 50 | - | ns Data hold from write time tDH 0 _ 0 _ 0 | ns Write pulse width twp 40 | |} 60 | /| 70 | ~|] ns Address setup time tas 0 0 0 | ns Write recovery time (WE) twr Oo |} 0 |j 0 |] ns Write recovery time (CET, CE2) twrl Oo |y| 0 | 0 | ns Output active from end of write tow 5 _ 5 _ 5 | ns Write to output in high Z twuz * 0 30 0 35 0 45 ns * twuz is defined as the time at which the outputs become the high impedance state and are not referred to output voltage levels. ~ 65 -SONY CXK58648P/8SP,/BM Timing Waveform Read cycle (1) : CE1 = OE = Vu, CE2 = Vin, WE = Vin tac | Address * aa tt tou Data out Previous data valid Kx xXx) Data valid @ Read cycle (2) : WE = Vin tac 7 ceT v tHZ) o4 f LZ) CE2 yo tco2z be 1.22 } m 4 10E w L__. tonz my torz jeter Data out Data valid } High impedance @ Write cycle (1) : WE control 1422 te] Address Ce2 Data in Data valid i: tow Data out High impedance (#3) (*3)SONY CXK5864BP//BSP/BM e Write cycle (2) : CET control Address twa (* 2) Data in Data valid Data out High impedance Write cycle (3) : CE2 control Address twat (*2) CcE2 Data in .. nt Data valid Data out High impedance Note) *1. Write is executed when both CET and WE are at low and CE2 is at high simultaneously. *2. twrt is tested from either the rising edge of CET or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. *3. Do not apply the data input voltage of the opposite phase to the output while the |/O pin is in output condition. - 67 -SONY CXKS864BP/BSP,/BM Data Retention Characteristics (Ta=0 to+ 70%) . - 7OL/10L/12L | ~ 70LL/10LL/12LL Item Symbol Test conditions - ; Unit Min. | Typ. | Max. | Min. | Typ. | Max. Data retention | [ey 20|/}55/20/I55]v voltage *4 Ta=0T to 70T|] 1 35 |! 05; 15 A i CcoR1 Data retention Vee = 3.0V [Ta=0 to 40 ~|~| ;_] 3 e current Iccor2 | Vcc = 2.0 to 5.5V, *1 !| 2 60 || 1 30 | WA Data retention Chip disable to data : tcpRs . QO |i-! 0 ;)|i ns setup time retention mode Recovery time | tr trac*2| | |trc*2} | J ns * 1. CET 2 Voc - 0.2V, CE2 2 Vee ~ 0.2V [CET Control] or CE2 S$ 0.2V [CE2 Control] * 2. trac: Read cycle time Data Retention Waveform 1. CE1 control 2. CE2 contro! tcors | Data retention mode CEt S Vcc-0.2V GND->- ~~ 777202 von e neon ne- oo eo nee - 2-2 ee Data retention mode _ CE2S0.207777 - 68 -SONY CXKS864BP/BSP/BM Example of Representative Characteristics Supply current vs. Supply voltage 14 Toes lees Ta=25C lcci, lcc2 Supply current (Relative value) 45 4.75 5.0 5.25 5.5 Voc Supply voltage (V) Supply current vs. Frequency 150 120 100 85 70 ns 0.25 lccz ~ Supply current (Relative value) 0 4 8 12 16 Frequency (1/tac, 1//twco) (MHz) Access time vs. Supply voltage TAA, tco1, C02 oO; 45 4.75 5.0 5.25. Vcc Supply voltage (V) 5.5 taa, tco1, tcoz, toe Access time (Relative value) taa, tco1, tcoz, toe - Access time (Relative value) Icci, Icc2 Supply current (Relative value) taa, tco1, tco2z, toe Access time (Relative value) Supply current vs. Ambient temperature Vee =5.0V 8 10 Tec2 Tec fo} 20 40 60 80 Ta Ambient temperature (C) Access time vs. Load capacitance 16 1 tAA, tc01, tcOo2 12 Ta = 28C, Vcc = 5.0V 08 Oo 100 200 300 400 Ci. Load capacitance (pF) Access time vs. Ambient temperature 14 nv TaA, tcO1, tcO2 OE & 20 40 60 Ta - Ambient temperature (C) 80 69 SONY _.. CXK5864BP//BSP//BM Standby current vs. Supply voltage Standby current vs. Ambient temperature > 20 T 3 Ta= 25C 3 Voc 5.0V A > 2 0 y, s g! : 7 2 3 $ S| % 5 & = 7 - ec Y| 5 Lh a 2 2 7 2 ~ So 3 LZ yD > 1 2 YY 3 1 Yn & 05 a a \ 2 - : 3 / 2 2 = 20 3,0 4.0 5.0 60 20 40 60 80 Vcc Supply voltage (V) Ta Ambient temperature (C) Input voitage level vs. Supply voltage Standby current vs. Ambient temperature 12 14 Ta=25C Viw. Vi 0g Vit, Vi Input voltage (Relative value) lse2 Standby current (Relative value) O85 475. +50 525 55 0 20 40 60 80 Vcc ~ Supply voltage (V) Ta- Ambient temperature (C) Output high current vs. Output high voltage Output low current vs. Output low voitage 14 : Voc = 5.0V 1.8 loH Output high current (Relative value) lo. - Output low current (Relative value) 1 2 3 4 5 3 Q2 04 06 08 Von Output. high voltage (V) Vo. Output low voltage (V)SONY CXK58648P,//BSP_//BM Package Outline Unit : mm CXK5864BP 28 pin DIP (Plastic) 600mil 4.2g 36.9708 4 28 15 2 8 ooonon agonal 7 ait o*-15 oO O a9 | o. om F 14 254 SONY NAME| DIP-~28P-04 ELA NAME |#01P028-P-0600-0 CXK5864BSP VEDEC CODE 28 pin DIP (Plastic) 35.1288 28 300mil <2. \ wo of i. o*-15 SONY NAME OIP-28P-06 ElAJ NANE #Q1P026-P-0300-A JEDEC CODE MO-058-AB = - CXK5864BM 10.08% DORDORDORR DANE 28 pin SOP (Plastic) * (Sim 450mil 2athts 0.7g +7015 aa? hi 1 4.9204 9.8 O 0.1" bas COUURR OEE dha patel pret 3.27 a1528bs Tho CF DIO - 71 - 2.09