VIPer35 Quasi-resonant high performance off line high voltage converter Datasheet - production data * Less than 30 mW @ 230 VAC in no-load condition * Brown-out set through resistor divider * Short-circuit protection (auto-restart) * Hysteretic thermal shutdown 621 6',3 Applications Figure 1. Basic application schematic * Auxiliary power supply * Adapter/charger for PDA, camcorders, shavers, tablet, video games, STB '&LQSXWYROWDJH '&RXWSXWYROWDJH %5 '5$,1 9,3(5 )% =&' 9'' *1' * Supplies for industrial systems, metering, appliances Description *,3*59 Features * 800 V avalanche-rugged power MOSFET allowing ultra wide range input VAC to be achieved * Embedded HV start-up and senseFET * Built-in soft-start * Quasi-resonant current mode PWM controller with drain current limit (IDlim) * Multifunction ZCD pin: - Zero-current detection - OCP threshold (IDlim) setup - Output OVP (auto-restart) - Feed-forward compensation The device is a high voltage converter, which smartly integrates an 800 V rugged power MOSFET with a quasi-resonant current mode PWM control. This IC meets severe energy saving standards as it has very low consumption and operates in burst mode under light load conditions. The device features the brown-out enabling the IC to set the switch-off and switch-on threshold independently one of each other. The quasiresonant operation reduces the level of EMI and the quantity of components in the application. The quasi-resonant operation reduces the switching losses and improves power conversion efficiency. The device features high level protections such as: output overvoltage, shortcircuit and thermal shutdown with hysteresis. After the removal of a fault condition, the IC is automatically restarted. * Support isolated flyback topology with optocoupler * Frequency limit: - 136 kHz (L type), 225 kHz (H type) February 2016 DocID026980 Rev 4 1/44 www.st.com Contents VIPer35 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Typical output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Efficiency performance for a typical flyback converter . . . . . . . . . . . . 18 8 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/44 8.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2 High voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3 Power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4 Power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.5 Auto-restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 Quasi-resonant operation (QR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 Frequency foldback function and valley-skipping mode . . . . . . . . . . . . . . 25 8.8 Blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.9 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.10 Current limit set-point and feed-forward option . . . . . . . . . . . . . . . . . . . . 27 8.11 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.12 ZCD pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.13 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 32 8.14 Burst mode operation at no-load or very light load . . . . . . . . . . . . . . . . . . 35 8.15 Brown-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID026980 Rev 4 VIPer35 9 Contents Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 SDIP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DocID026980 Rev 4 3/44 44 List of tables VIPer35 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. 4/44 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power supply efficiency, VOUT = 12 V, VIN = 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power supply efficiency, VOUT = 12 V, VIN = 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ZCD pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SDIP10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DocID026980 Rev 4 VIPer35 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDon vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDD(RESTART) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IDlim vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDRAIN_START vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 HFB vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VBRth vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VBRhyst vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IBRhysvs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD0 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD1 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VZCD vs IZCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDlim vs IZCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RDS(on) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VBVDSS vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IDDch1 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IDDch2 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FOSClim_L vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FOSClim_H vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal shutdown timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Min-feature quasi-resonant flyback (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Full-feature quasi-resonant flyback (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply consumption at light output loads, VOUT = 12 V . . . . . . . . . . . . . . . . . . . . . . 18 Power supply consumption at no output load, VOUT = 12 V . . . . . . . . . . . . . . . . . . . . . . . . 18 IDD current during start-up and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Timing diagram: normal power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . 21 Timing diagram: start-up phase and soft-start (case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing diagram: start-up phase and soft-start (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Switching frequency vs power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Zero-current detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Drain ringing cycle skipping as the load progressively reduces . . . . . . . . . . . . . . . . . . . . . 25 Timing diagram: double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical power capability vs input voltage in quasi-resonant converter . . . . . . . . . . . . . . . . 28 ZCD pin typical external configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing diagram: OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FB pin configuration (minimal BOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FB pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Timing diagram: overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Burst mode timing: light load management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Brown-out: external setting and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SDIP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DocID026980 Rev 4 5/44 44 Block diagram 1 VIPer35 Block diagram Figure 2. Block diagram 9'' ,''FK %5 9LQB2. ,%5K\VW 9%5WK ,QWHUQDO6XSSO\EXV 6 833 /< 5HIHUHQFH9ROWDJHV 89 /2 '5$,1 +9B21 89/2 293'(7(&7,21 /2*,& 26&,//$725 67$57(5)5(4&/$03 293 %8567 =&' '(0$* /2*,& /2*,& 2&3 /2*,& 4 62)7 67$57 273 6 2&3 7+(50$/ 6+87'2:1 /(% 5 6 4 3:0 +9B21 5 5 273293 9LQB2. 5 %856702'( /2*,& 5VHQVH %8567 )% *1' *,3'59VYJ 2 Typical output power Table 1. Typical power 230 VAC Part number VIPER35 85-265 VAC Adapter(1) Open frame(2) Adapter(1) Open frame(2) 20 W 22 W 15 W 16 W 1. Typical continuous power in non-ventilated enclosed adapter measured at 50 C ambient. 2. Maximum practical continuous power in an open frame design at 50 C ambient, with adequate heatsinking. 6/44 DocID026980 Rev 4 VIPer35 3 Pin settings Pin settings Figure 3. Connection diagram =&' =&' Note: The copper area for heat dissipation has to be designed under the DRAIN pins. Table 2. Pin description SO16N SDIP10 Name 1, 2 1 GND Device ground and source of the power MOSFET. 3 - N.C. Not internally connected. It can be connected to GND. 4 - N.A. Not available for user. This pin is mechanically connected to the controller die pad of the frame. In order to improve the noise immunity it should be connected to GND (pin 1, 2). 5 2 VDD Supply voltage of the control section. This pin provides the charging current of the external capacitor during the power-up. ZCD Multifunction pin: 1. Zero-current detection for quasi-resonant operations. 2. Drain current limit (IDlim) setup for overcurrent protection (RLIM). 3. Feed-forward compensation (RFF) setup. 4. Output overvoltage protection (resistor divider ROVP / RLIM) setup. 6 7 3 4 Function FB Control input for duty cycle control. Internal current generator provides bias current for loop regulation. A voltage below the threshold VFBbm activates the burst-mode operation. A level close to the threshold VFBlin means that the cycle-by-cycle overcurrent set-point is close. Brown-out protection input with hysteresis. A voltage below the threshold VBRth shuts down (not latch) the device and lowers the power consumption. The device operation restarts as the voltage exceeds the threshold VBRth + VBRhyst. It must be connected to ground when it is not used. 8 5 BR 9 to 12 - N.C. 13 to 16 6 to 10 DRAIN Not internally connected. These pins must be left floating in order to get a safe clearance distance. High voltage drain pin. The built-in high voltage switched start-up bias current is drawn from this pin. Pins connected to the metal frame facilitate heat dissipation. DocID026980 Rev 4 7/44 44 Electrical ratings 4 VIPer35 Electrical ratings Table 3. Absolute maximum ratings Value Symbol Parameter Unit Min. VDRAIN Max. Drain-to-source (ground) voltage 800 V EAV Repetitive avalanche energy (limited by TJ = 150 C) 5 mJ IAR Repetitive avalanche current (limited by TJ = 150 C) 1.5 A 3 A IDRAIN Single pulse drain current VZCD Input pin voltage (with IZCD = 1 mA) -0.3 Self limited V VFB Input pin voltage -0.3 5.5 V VBR Input pin voltage (with IBR = 0.25 mA) -0.3 Self limited V VDD Supply voltage -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 60 C 1.5 W PTOT TJ TSTG Operating junction temperature range -40 150 C Storage temperature -55 150 C Table 4. Thermal data Max. value Symbol Parameter Unit SDIP10 SO16N RthJP Thermal resistance junction pin (dissipated power = 1 W) 35 35 C/W RthJA Thermal resistance junction ambient (dissipated power = 1 W) 100 110 C/W RthJA Thermal resistance junction ambient (1) (dissipated power = 1 W) 85 80 C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq inch) of Cu (35 m thick). 8/44 DocID026980 Rev 4 VIPer35 Electrical ratings TJ = -40 to 125 C, VDD = 14 V (a) (unless otherwise specified) Table 5. Power section Symbol Parameter VBVDSS IOFF Typ. Max. Unit IDRAIN = 1 mA, VFB = GND TJ = 25 C Off-state drain current VDRAIN = 800 V VFB = GND, TJ = 25 C 60 uA IDRAIN = 0.4 A, VFB = 3 V VBR = GND, TJ = 25 C 4.5 IDRAIN = 0.4 A, VFB = 3 V VBR = GND, TJ = 125 C 9 Effective (energy related) output capacitance COSS Min. Breakdown voltage Drain-source onstate resistance RDS(on) Test conditions 800 VDRAIN = 0 to 640 V V 17 pF TJ = -40 to 125 C (unless otherwise specified) Table 6. Supply section Symbol Parameter Test conditions Min. Typ. Max. Unit 60 80 100 V -2 -3 -4 mA -0.6 -0.8 mA 23.5 V Voltage VDRAIN_START Drain-source start voltage IDDch1 Start-up charging current (power-up) IDDch2 VDRAIN = 120 V VBR = GND Start-up charging current (auto-restart) VFB = GND VDD = 5 V, after fault -0.4 Operating voltage range After turn-on 8.5 Clamp voltage IDD = 20 mA 23.5 VDD VDDclamp VDDon VDD start-up threshold VDDoff VDD undervoltage shutdown threshold VDD(RESTART) VDD restart voltage threshold VDRAIN = 120 V VBR = GND VFB = GND VDD = 4 V VDRAIN = 120 V VBR = GND VFB = GND V 13 14 15 V 7.5 8 8.5 V 4 4.5 5 V a. Adjust VDD above VDDon start-up threshold before setting 14 V. DocID026980 Rev 4 9/44 44 Electrical ratings VIPer35 Table 6. Supply section (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 0.6 0.7 mA 2 3 mA Current VFB = GND Operating supply V = GND current, not switching BR VDD = 10 V(1) IDD0 IDD1 Operating supply current switching VDRAIN = 120 V VDD = 16 V ZCD switching @100 kHz Resistive load:100 VFB = 2.5 V IDD_FAULT Operating supply current with protection tripping VDD = 10 V 400 uA IDDoff Operating supply current VDD < VDDoff 270 uA 1. Adjust VDD above VDDon start-up threshold before setting 10 V. TJ = -40 to 125 C (unless otherwise specified) Table 7. Controller section Symbol Parameter Test conditions Min. Typ. Max. Unit Feedback pin VFBolp Overload shutdown threshold 4.5 4.8 5.2 V VFBlin Linear dynamics upper limit 3.1 3.3 3.5 V VFBbm Burst mode threshold Voltage falling 0.56 0.6 0.64 V VFBbmhys Burst mode hysteresis Voltage rising 100 mV Feedback sourced current VFB = 0.3 V -150 -215 -280 A IFB 3.3 V < VFB < 4 V -2.5 -3 -3.5 A RFB(DYN) Dynamic resistance VFB > 2.5 V 12 25 k 0.5 2 V/A HFB 10/44 VFB / ID DocID026980 Rev 4 VIPer35 Electrical ratings Table 7. Controller section (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 5 5.5 6 V ZCD pin VZCDCLh Upper clamp voltage IZCD = 1 mA VZCDAth Arming voltage threshold Positive-going edge 0.75 0.8 0.85 V VZCDTth Triggering voltage threshold Negative-going edge 0.55 0.6 0.65 V Internal pull-up VFB < VFBlin -7.5 -10 -12.5 A IZCD tDELAY Turn-on delay after ZCD trigger tBLANK Turn-on inhibit time after MOSFET turnoff 300 ns VZCD < 1 V 6.3 s VZCD >1 V 2.5 s Current limitation IDlim Drain current limitation tSS Soft-start time tSU Start-up time VFB = 4 V IZCD = -10 A TJ = 25 C 0.95 1 1.05 A VFB = 4 V IZCD = - 55 A TJ = 25 C 0.68 0.8 0.92 A VFB = 4 V IZCD = - 105 A TJ = 25 C 0.55 0.65 0.75 A VIPER35L 3.5 ms VIPER35H 4.2 ms VIPER35L 7.5 15 ms VIPER35H 9.5 18 ms 480 ns tON_MIN Minimum turn-on time td Propagation delay (1) 100 ns Leading edge blanking (1) 300 ns Peak drain current during burst mode VFB = 0.6 V tLEB ID_BM 220 DocID026980 Rev 4 120 400 170 220 mA 11/44 44 Electrical ratings VIPer35 Table 7. Controller section (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 3.8 4.2 4.6 V Overvoltage protection VOVP Overvoltage threshold tSTROBE Strobe time 2.2 s Oscillator section FOSClim FSTARTER Internal frequency limit Starter frequency VIPER35L 122 136 150 kHz VIPER35H 200 225 250 kHz VFB = 1 V VZCD < VZCDTth t < tSU 1/4 FOSClim kHz VFB =1 V VZCD < VZCDTth t > tSU 1/8 FOSClim kHz Brown-out protection VBRth Brown-out threshold Voltage falling 0.41 0.45 0.49 A 50 60 mV 12 A VBRHyst Voltage hysteresis above VBRth 40 IBRHyst Current hysteresis 7 VBRclamp VDIS Clamp voltage IBR = 250 A Brown-out disable voltage 3 50 V 150 mV Thermal shutdown TSD Thermal shutdown temperature (1) THYST Thermal shutdown hysteresis (1) 150 1. Specification assured by design, characterization and statistical correlation. 12/44 DocID026980 Rev 4 160 C 30 C VIPer35 5 Typical electrical characteristics Typical electrical characteristics Figure 4. VDDon vs TJ Figure 5. VDD(RESTART) vs TJ 9''21 9''21 #& 9'' 5(67$57 9'' 5(67$57 # & 7- & 7- & Figure 6. IDlim vs TJ ,'OLP ,'OLP # & Figure 7. VDRAIN_START vs 9'5$,1B67$57 9'5$,1B67$57 # & TJ Figure 8. HFB vs TJ 7- & 7- & Figure 9. VBRth vs TJ +)% +)% # & 9%5WK 9%5WK # & 7- & 7- & DocID026980 Rev 4 13/44 44 Typical electrical characteristics VIPer35 Figure 10. VBRhyst vs TJ Figure 11. IBRhysvs TJ ,%5K\VW ,%5K\VW # & 9%5K\VW 9%5K\VW # & 7- & Figure 12. IDD0 vs TJ 7- & Figure 13. IDD1 vs TJ ,'' , '' # & ,'' , '' # & 7- & Figure 15. IDlim vs IZCD / 14/44 7- & Figure 14. VZCD vs IZCD DocID026980 Rev 4 VIPer35 Typical electrical characteristics Figure 16. RDS(on) vs TJ Figure 17. VBVDSS vs TJ 9%9'66 9%9'66 # & 5'6 RQ 5 '6 RQ # & 7- & 7- & Figure 18. IDDch1 vs TJ Figure 19. IDDch2 vs TJ ,''FK ,''FK # & ,''FK ,''FK # & 7- & 7- & Figure 20. FOSClim_L vs TJ Figure 21. FOSClim_H vs TJ )26&OLPB+ )26&OLPB+#& )26&OLPB/ )26&OLPB/#& 7- & 7- & DocID026980 Rev 4 15/44 44 Typical electrical characteristics VIPer35 Figure 22. Thermal shutdown timing diagram 9'' 9''RQ 9''RII 9'' 5(67$57 WLPH ,'5$,1 WLPH 776' 76' 7+<67 1RUPDORSHUDWLRQ 16/44 6KXWGRZQDIWHURYHUWHPSHUDWXUH DocID026980 Rev 4 1RUPDORSHUDWLRQ WLPH VIPer35 Typical circuits Figure 23. Min-feature quasi-resonant flyback (isolated) VOUT D3 T3 BR AC IN C2 C1 R1 C4 D1 D OVP AC IN R OVP GND R2 D2 R3 VIPER35 VDD OPTO DRAIN C5 R5 BR CONTROL ZCD C VDD FB GND REF R4 R LIM OPTO C3 GIPG2801151023LM Figure 24. Full-feature quasi-resonant flyback (isolated) T3 + 6 Typical circuits D3 VOUT BR C2 C1 AC IN R1 C4 D1 D OVP AC IN R OVP R7 GND Rf f R2 D2 R3 VIPER35 OPTO VDD DRAIN BR R5 C5 CONTROL ZCD C VDD FB GND REF R8 R LIM C6 R6 C3 R4 OPTO GIPG2801151020LM DocID026980 Rev 4 17/44 44 Efficiency performance for a typical flyback converter 7 VIPer35 Efficiency performance for a typical flyback converter The efficiency of the converter has been measured in different load and line voltage conditions. In accordance with the Energy Star average active mode testing efficiency method, the efficiency measurements have been performed at 25%, 50% and 75% and 100% of the rated output power, both at 115 VAC and 230 VAC. Table 8. Power supply efficiency, VOUT = 12 V, VIN = 115 VAC %load IOUT [A] VOUT [V] POUT [W] PIN[W] Efficiency [%] 25% 0.31 12.1 3.78 4.53 83.47 50% 0.63 12.1 7.56 8.98 84.21 75% 0.94 12.1 11.34 13.4 84.65 100% 1.25 12.1 15.12 17.93 84.36 Average efficiency 84.17 Table 9. Power supply efficiency, VOUT = 12 V, VIN = 230 VAC %load IOUT [A] VOUT [V] POUT [W] PIN[W] Efficiency [%] 25% 0.31 12.1 3.78 4.71 80.28 50% 0.63 12.1 7.56 9.22 82.02 75% 0.94 12.1 11.34 13.53 83.84 100% 1.25 12.1 15.12 17.77 85.12 Average efficiency ,QSXWYROWDJH>9DF@ 18/44 Figure 26. Power supply consumption at no output load, VOUT = 12 V ,QSXWSRZHU>P:@ ,QSXWSRZHU>P:@ Figure 25. Power supply consumption at light output loads, VOUT = 12 V 82.82 *,3'59 DocID026980 Rev 4 ,QSXWYROWDJH>9DF@ *,3*59 VIPer35 8 Operation description Operation description The device is a high performance low voltage PWM controller chip with an 800 V, avalanche-rugged power section. The controller includes the PWM logic, ZCD logic for quasi-resonant operation, oscillator, start-up circuit with soft-start, current limiting circuit with adjustable set-point, burst mode management, brown-out circuit, UVLO circuit, auto-restart circuit and thermal protection circuit. The current limit set-point can be reduced by ZCD pin. Burst mode operation guarantees high performance in standby mode and meets energy-saving standards. All fault protections are built-in auto-restart mode with very low repetition rate to prevent the IC overheating. 8.1 Power section and gate driver The power section is given by an avalanche-rugged N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power MOSFET has a BVDSS of 800 V min. and a typical RDS(on) of 4.5 at 25 C. The integrated senseFET structure allows a virtual loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common-mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 8.2 High voltage start-up generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 V DC typically. When HV current generator is on, IDDch1 current (3 mA typical value) is delivered to the capacitor on VDD pin. During auto-restart mode after a fault event, the current is reduced to IDDch2 (0.6 mA, typ.) in order to have a slow duty cycle during the restart phase. 8.3 Power-up and soft-start When the input voltage reaches the device start threshold, VDRAIN_START, the VDD voltage begins growing due to IDDch1 current (see Table 7) coming from the internal high voltage start-up circuit. If the VDD voltage reaches VDDon threshold, the power MOSFET starts switching and the HV current generator turns off. The IC is powered by the energy stored in the capacitor on VDD pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage so high to sustain the operation. CVDD capacitor must be correctly sized to avoid fast discharge and keep the required voltage higher than VDDoff threshold. In fact, an insufficient capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. DocID026980 Rev 4 19/44 44 Operation description VIPer35 The following formula can be used to calculate CVDD capacitor: Equation 1 IDDch x t SSaux C VDD = ---------------------------------------V DDon - V DDoff tSSaux is the time needed for the steady-state of the auxiliary voltage. It represents an estimate of the user's application according to the output stage configurations (transformer, output capacitances, etc.). During the normal operation, the power MOSFET switches on after the transformer demagnetization, detected through the voltage VZCD sensed on ZCD pin. At power-up, the initial output voltage is zero and the voltage VZCD is not so high to correctly arm the internal ZCD circuit. In this case, the power MOSFET turns on with the fixed frequency FSTARTER, reported in Table 7. After the start-up, as soon as the voltage on ZCD logic is enabled to work, the turn-on of the power MOSFET is driven by this circuit and it is not related to the internal oscillator (except for the frequency foldback function) any longer. The start-up phase is managed by a dedicated internal logic and is activated by every attempt of the start-up converter or after a fault. An internal clock counter defines the start-up time, tSU, since during quasi-resonant operation, the switching frequency and the duration of the start-up time depend on the load, tSU range is indicated in Table 7. At the beginning of the start-up time, the drain current limitation progressively rises to the maximum value. In this way a soft-start occurs and the stress on the secondary diode is considerably reduced. It also prevents transformer saturation. The soft-start time lasts 3.5 ms (VIPER35L) or 4.2 ms (VIPER35H), (see tSS in Table 7). At the start-up, until the output voltage reaches its regulated value, the feedback loop is open and an improper activation of the overload protection could occur. In order to avoid this, OLP logic is disabled and it is active at the end of the start-up phase, t > tSU. Figure 29 and Figure 30 show two possible start-up cases. As soon as the output voltage reaches the regulated value, the regulation loop takes over and the drain current is regulated below its limit, IDlim, by the feedback voltage, which is at a value lower than the VFBlin threshold. 20/44 DocID026980 Rev 4 VIPer35 Operation description Figure 27. IDD current during start-up and burst mode 9'' 9'' RQ 9'' RII W 9) % 9) % ROS 9) % OLQ 9) % EPK\V 9) % EP ,'5 $,1 W W66 ,'B% 0 ,'' W ,'' ,'' W ,'' FK 6 WDUWXS 1RUPDOPRGH %XUVWPRGH 1RUPDOPRGH *,3'59 Figure 28. Timing diagram: normal power-up and power-down sequence 9,19 9'5$,1B67$57 9,1 +9VWDUWXSLVQRPRUHDFWLYH 9'5$,1B67$5 7 9'' 9''RQ 5HJXODWLRQLVORVWKHUH WLPH 9''RII 9'' 5(67$57 , '' F K WLPH , ''FK WLPH 9'5 $,1 3 RZHURQ 1RUPDORSHUDWLRQ 3 RZHURII WLPH *,3'59 DocID026980 Rev 4 21/44 44 Operation description VIPer35 Figure 29. Timing diagram: start-up phase and soft-start (case 1) ,'5 $,1 ,'OLP W 6 8V WDUWXSSKDV H W 6 6 V RIWV WDUW W 9)% 9) % ROS 9) % OLQ W 9 287 5 HJXODWHGYDOXH W *,3'59 Figure 30. Timing diagram: start-up phase and soft-start (case 2) , '5 $,1 , 'OLP W 6 8 V WDUWXSSKDV H W 6 6 V RIWV WDUW W 72/ 3 GHOD\ 9 )% 9 ) % ROS 9 ) % OLQ W 9 287 5 HJXODWHGYDOXH W *,3'59 22/44 DocID026980 Rev 4 VIPer35 8.4 Operation description Power-down description At converter power-down, the system loses its ability to regulate as soon as the decreasing input voltage is so low to reach the peak current limitation. VDD voltage drops and when it falls below VDDoff threshold (see Table 7) the power MOSFET switches off, the energy is interrupted, VDD voltage decreases, the start-up sequence is inhibited and the power-down is completed. This feature prevents any restart attempt and ensures a monotonic output voltage decay during the system power-down. 8.5 Auto-restart description Every time a protection is tripped, the IC automatically restarts after a duration depending on the discharge and recharge of CVDD capacitor. As shown in Figure 31, after a fault, the IC stops and VDD voltage decreases because of IC consumption. As soon as VDD voltage falls below VDD(RESTART) threshold and if the DC input voltage is higher than VDRAIN_START threshold, the internal HV current source turns on and it starts to charge CVDD capacitor with the current IDDch2 (0.6 mA, typ.). As soon as VDD voltage reaches VDD(ON) threshold, the IC restarts. Figure 31. Timing diagram: behavior after short-circuit 9'' 6KRUWFLUFXLWRFFXUVKHUH 9''RQ 9 ''RII 9 '' 5 (6 7 $5 7 9 )% 9 ) % ROS WLPH 9 ) % OLQ W 5(67$57 , '5 $,1 , '' F K WLPH WLPH , ''FK WLPH *,3'59 8.6 Quasi-resonant operation (QR) The control core of the VIPER35 is a current mode PWM controller with a zero-current detect circuit designed for quasi-resonant (QR) operation, a technique whose benefits are: minimum turn-on losses, low EMI emission and safe behavior in case of short-circuit. At heavy load the converter operates in quasi-resonant mode; operation synchronizes MOSFET turn-on to the transformer demagnetization by detecting the resulting negativegoing edge of the voltage across any winding of the transformer. The system works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer and as a result, the switching frequency is different according to different line/load conditions. See the hyperbolic-like portion reported in Figure 32. DocID026980 Rev 4 23/44 44 Operation description VIPer35 At medium/ light load, depending on the converter input voltage as well, the device enters valley-skipping mode. An internal oscillator, synchronized to MOSFET turn-on, defines the maximum operating frequency of the converter, FOSClim. The VIPER35 is available as type 'L' or type 'H', depending on FOSClim value, see Table 7. During the normal operation the converter works with a frequency below FOSClim, so the 'L' type is suitable for applications where the priority is on the EMI filter minimization. The 'H' type is suitable when an extended QR operation range or the transformer size reduction are priorities. As the load is reduced, and the switching frequency tends to exceed the oscillator's one, MOSFET turn-on doesn't occur on the first valley but on the second one, the third one and so on. In this way a "frequency clamp" effect is achieved, piecewise linear portion is showed in Figure 32. When the load is extremely light or disconnected, the converter enters burst mode operation. By decreasing the load, the frequency is reduced even few hundred hertz, so to comply with energy saving regulations or recommendations. As the peak current is low, no audible noise occurs. The above mentioned operation is based on ZCD pin. This pin is the input of the integrated ZCD circuit which allows the power section turn-on at the end of the transformer demagnetization. The input signal for the ZCD is obtained as a partition of the auxiliary voltage used to supply the device, see Figure 33. When the triggering circuit senses a negative-going edge below VZCDTth threshold (seeTable 7), after an internal delay that helps to achieve minimum drain-source voltage switch-on ("valley switching"), the power MOSFET turns on. However, to enable power MOSFET turn-on, the triggering circuit has to be previously armed by a positive-going edge exceeding VZCDAth threshold (see Table 7) on the same ZCD pin. After the MOSFET turn-off, the blanking time, tBLANK, is generated to avoid an erroneous arming and triggering due to the noise, generated by the leakage inductance resonance of the transformer which rings and couples with ZCD pin. Figure 32. Switching frequency vs power EDFN 3RXW 24/44 DocID026980 Rev 4 VIPer35 Operation description Figure 33. Zero-current detection circuit 9'' '5$,1 5HVHWRVFLOODWRU 26&,//$725 )26& )UHTIROGEDFN =&' $X[LOLDU\ ZLQG LQJ $ 9 9 % & '(/$< 0RQRVWDEOH 7%/$1. o)26& 6WDUWHUVLJQDO 6( 4 5( 4 ) ( ' *DWH GULYHU )URP3:0FRPSDUDWRU 6WDUW7%/$1.DW026)(7WXUQRII *1' *,3'59 8.7 Frequency foldback function and valley-skipping mode The switching frequency, in quasi-resonant mode, is not fixed and it depends on both the load and the converter input voltage. The switching frequency increases when the load decreases, or when the mains voltage increases, and vice versa. To avoid that, the VIPER35 taps the maximum switching frequency of the application thanks to its control logic. The frequency limit is given by an internal oscillator switching at 136 kHz for the VIPER35L or at 225 kHz for the VIPER35H, (see parameter FOSClim in Table 7). This oscillator is synchronized with the power MOSFET turn-on. When the power MOSFET is off, if the first negative-going edge voltage of the ZCD pin, resulting from transformer demagnetization, appears after at least one oscillator cycle has been completed, the MOSFET turns on and the oscillator is synchronized again. Otherwise, if the first negative-going edge voltage appears before completing one oscillator cycle, the signal is ignored. Due to the ringing of the drain voltage, the ZCD pin experiences another positive-going edge voltage that arms the circuit and a negative-going edge voltage. Again, if this appears before the oscillator cycle is completed, it is ignored, otherwise the MOSFET turns on and the oscillator is synchronized. In this manner, one or more drain ringing cycles are skipped (Figure 34 shows the so called "valley-skipping mode") and the switching frequency doesn't exceed FOSClim limit. Figure 34. Drain ringing cycle skipping as the load progressively reduces 72 1 7): 79 7RV F W W 7RVF 3LQ 3LQ OLPLWFRQGLWLRQ W 7RV F 3LQ 3LQ 3LQ DocID026980 Rev 4 3LQ 3LQ 3LQ 25/44 44 Operation description VIPer35 When the system operates in valley-skipping mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the power MOSFET changes its discrete steps one ringing cycle, while the off-time needed for cycleby-cycle energy balance could fall in between. Therefore one or even longer switching cycles are compensated by one or more shorter cycles and vice versa. This mechanism is natural and any effect on the converter performance and on its output voltage appears. This operation does not consider the blanking time tBLANK after power MOSFET turn-off. Actually tBLANK is not taken into account as long as the following condition is met: Equation 2 tBLANK D 1 - ------------------ = 1 - tBLANK F osclim t osclim where D is the MOSFET duty cycle. If this condition is not met, the time during which MOSFET turn-on is inhibited is extended beyond tOSClim by a fraction of tBLANK. As a consequence, the maximum switching frequency is a little bit lower than the internal limit set by the oscillator and valley-skipping mode takes place slightly earlier than expected. 8.8 Blanking time The blanking time, tBLANK, can have two different values: the lower one is 2.5 seconds (typical value) and the higher one is 6.3 seconds (typical value). The value is linked to the voltage VZCD, sampled during the time tSTROBE. The time tBLANK has the lower value if VZCD > 1 V or it has the higher value if VZCD < 1 V, refer to Table 7 and Figure 35. The higher value of the blanking time is active during the start-up phase or in case of output short-circuit, when the output voltage of the converter is quite lower than the regulated value. In this condition, during the demagnetization of the transformer, VZCD can be very close to the arming and triggering thresholds (VZCDAth and VZCDTth) and ZCD circuit can be erroneously trigged, leading the system to work with higher frequency and in continuous mode. This false trigger is inhibited by the selection of tBLANK higher value when VZCD is lower than 1 V. During the normal operation, in steady-state condition, the voltage VZCD during the demagnetization is higher than 1 V and the selected tBLANK value is the lower one. Figure 35 shows the typical waveforms during the power-up and the linked tBLANK selection. 26/44 DocID026980 Rev 4 VIPer35 Operation description Figure 35. Timing diagram: double blanking time 026)(7VZLWFKHGRQE\WKHVWDUWHU 4XDVLUHVRQDQWRSHUDWLRQ 9 DX[ W =& ' SLQ 9 9 9 W 76 7 5 2 % $ 7% /$1. W V V & W W ' W 'HOD\ ) )26 &OLP W W 8.9 Starter If the amplitude of the voltage on ZCD pin at the end of one oscillator cycle is smaller than VZCDAth arming threshold, (in this case MOSFET turn-on could not be triggered), the system stops. This is what normally happens during the converter power-up or under overload/short-circuit conditions. During the converter start-up phase, the voltage on ZCD pin is not so high to arm the triggering circuit. Thus, the converter operates at a fixed frequency, FSTARTER, (see Table 7). As the voltage developed across the auxiliary winding arms the ZCD circuit, MOSFET turn-on is locked to transformer demagnetization, hence quasi-resonant operation is set. 8.10 Current limit set-point and feed-forward option The VIPER35 is a current mode converter and the drain current is limited cycle-by-cycle according to FB pin voltage value, which is related to the feedback loop response and the load. When the drain current, sensed by the integrated senseFET, reaches the current limitation, after the internal propagation delay, the MOSFET switches off. The current limitation cannot exceed a certain value, IDlim, which can vary according to the current sunk by ZCD pin during MOSFET on-time. Usually a resistor, RLIM, connected from ZCD pin to ground fixes this sunk current and then the peak drain current set-point: the lower the resistor, the lower IDlim. DocID026980 Rev 4 27/44 44 Operation description VIPer35 For a quasi-resonant flyback converter, the power capability strongly depends on the input voltage. In wide range applications, at maximum line, the power capability can be more than twice the value at minimum line, as shown by the upper curve in the diagram, see Figure 36. To reduce this dependence, the IDlim has to be reduced according to the increment of the input voltage, this is the line feed-forward. It's given by a resistor, RFF, connected between the ZCD pin and the auxiliary winding, see Figure 37. Since the voltage across the auxiliary winding during MOSFET on-time is proportional to the input voltage through the auxiliary-toprimary turn ratio NAUX /NP, a current proportional to the input voltage is sunk by the ZCD pin, thus the overcurrent set-point lowers. Figure 36. Typical power capability vs input voltage in quasi-resonant converter V\VWHPQRW FRPSHQVDWHG 3LQOLP# 9LQBPLQ 3LQOLP# 9LQ V\VWHPRSWLPDOO\ FRPSHQVDWHG 9LQ 9 LQBPLQ In order to select the RFF resistance value (see Figure 37), when the proper overcurrent setpoints are known at minimum and at the maximum converter input voltage, in Figure 15 the needed current to sink during MOSFET on-time is visible. With the following approximated formula, the value of RFF resistor can be calculated: Equation 3 V in_Max - V in_min R FF = -----------------------------------------------------------N AUX ( I ZCD1 - I ZCD2 ) where * Vin_Max and Vin_min are the maximum and minimum converter rectified input voltage * NAUX is the primary-to-auxiliary winding turn ratio * IZCD1, and IZCD2 are the currents needed to sink from the ZCD pin, in order to obtain the selected overcurrent set-points, at maximum and minimum flyback input voltage, see Figure 15. Given RFF value, RLIM value can be calculated by the following formula: 28/44 DocID026980 Rev 4 VIPer35 Operation description Equation 4 R LIM V ZCD2 V ZCD1 = Max ----------------------------------------------------------------, ----------------------------------------------------------------- V V in_min in_Max ------------------ + V ZCD1 -------------------- + V ZCD2 N N AUX AUX I - ------------------------------------------ IZCD2 - -------------------------------------------- ZCD1 R FF R FF where: VZCD1 and VZCD2 are ZCD pin voltages when the sunk current is IZCD1 and IZCD2 respectively, see Figure 14. Figure 37. ZCD pin typical external configuration 6RIWVWDUW 6HWSRLQW $X[LOLDU\ ZLQGLQJ 8.11 7UDQVIRUPHU GHPDJQHWL]DWLRQ VHQVLQJ Overvoltage protection (OVP) The device has integrated the logic to monitor the output voltage using as input signal, the voltage VZCD during the off-time of the power MOSFET. This is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio NAUX / NSEC. ZCD pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as shown in Figure 37. When, during the off-time, the voltage VZCD exceeds, four consecutive times, the reference voltage VOVP (reported in Table 8), the overvoltage protection stops the power MOSFET and the converter enters auto-restart mode. In order to bypass the noise after the turn-off of the power MOSFET, VZCD voltage is sampled inside a short window after the time tSTROBE, see Table 7 and Figure 38. The sampled signal, if higher than VOVP, triggers the internal OVP digital signal and increments the internal counter. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle. Referring to Figure 37, the resistor divider ratio kOVP is given by below equations: DocID026980 Rev 4 29/44 44 Operation description VIPer35 Equation 5 VOVP K OVP = --------------------------------------------------------------------------------------------------N AUX -------------- ( V OUTOVP + V DSEC ) - VDAUX N SEC Equation 6 RLIM K OVP = ---------------------------------R LIM + R OVP where: * VOVP is the OVP threshold (see Table 7) * VOUTOVP is the converter output voltage value to activate the OVP (set by design) * NAUX is the auxiliary winding turn * NSEC is the secondary winding turn * VDSEC is the secondary diode forward voltage * VDAUX is the auxiliary diode forward voltage * ROVP and RLIM make the output voltage divider By fixing RLIM, according to the desired IDlim, ROVP can be calculated as follows: Equation 7 1 - K OVP R OVP = R LIM x -----------------------K OVP The resistor values let the current sourced and sunk by the ZCD pin be within the rated capability of the internal clamp. 30/44 DocID026980 Rev 4 VIPer35 Operation description Figure 38. Timing diagram: OVP 9 DX[ W =& ' SLQ W 29 3 W & 2817 ( 5 5(6(7 W & 2817 ( 5 6 7 $7 86 W ) $8/7 W 125 0$/23 ( 5 $7 ,21 8.12 7 ( 03 2 5 $5 < ',6 7 85 % $1& ( W ) (( '% $& . /2 23 ) $,/85 ( ZCD pin summary With reference to Figure 37, the circuitry connected to the ZCD pin enables the following functions: 1. Current limit set-point (IDLIM) 2. Line feed-forward compensation (FF) 3. Output overvoltage protection (OVP) 4. Zero-current detection for QR operation Chosen RLIM, RFF and ROVP as described in the previous sections, these functions are automatically defined. Table 7 refers to Figure 37 and lists the external resistance combinations needed to activate one or more functions associated to ZCD pin. DocID026980 Rev 4 31/44 44 Operation description VIPer35 Table 10. ZCD pin configurations IDlim OVP FF RLim ROVP RFF Equation 4 Equation 7 with VOUTOVP 2 VOUT Yes 22 k Equation 7 Yes 22 k Equation 7 with VOUTOVP2 VOUT Equation 3 Yes Equation 4 with RFF= Equation 7 Yes 22 k Equation 7 Equation 3 Yes Equation 4 Equation 7 with VOUTOVP 2 VOUT Equation 3 Yes Equation 4 Equation 7 Equation 3 Yes 8.13 DOVP Feedback and overload protection (OLP) The feedback pin (FB) controls the PWM operation, enters the burst mode and manages the delayed overload protection. VFBbm and VFBlin thresholds (Table 7) are respectively low and high limit of PWM operations, where the drain current is sensed by the integrated resistor, RSENSE, and applied to the comparator PWM. The PWM logic turns off the power MOSFET as soon as the sensed voltage is equal to the voltage applied to FB pin and through the integrated resistor network (see Figure 2 and Figure 23). IC block diagram (Figure 2) shows in parallel with the PWM comparator how OCP comparator limits the drain current to IDlim value, as per Table 7. In case of higher load, the voltage VFB increases, when it reaches VFBlin threshold, the drain current is limited to IDlim by OCP comparator and the internal current starts the charge of CFB capacitor. As soon as the voltage VFB reaches the threshold VFBolp, see Figure 41, the protection turns off the IC. The auto-restart mode is active using the low value of the current IDDch, see Table 7. The time, from the high load detection, VFB = VFBlin, to the overload turn-off, VFB = VFBolp, depends on the value of CFB capacitor and on the internal charge current, IFB. OLP delay time can be calculated as follows: Equation 8 V FBolp - V FBlin T OLP_delay = C FB x ---------------------------------------IFB The current, IFB, is 3 A as minimum value. Components, connected to FB pin, belong to the compensation loop, so they have to be selected taking into account the proper delay and loop stability. Figure 39 and Figure 40 show two different feedback networks. 32/44 DocID026980 Rev 4 VIPer35 Operation description In Figure 39 CFB capacitor, connected to FB pin, is used as part of the circuit to compensate the feedback loop but it is also an element to delay OLP shutdown owing to the time needed to charge the capacitor (see Equation 8). After the start-up time, tSU, during which the feedback voltage is fixed at VFBlin, the output capacitor could not be at its nominal value and the controller detects this situation as an overload condition. In this case, OLP delay avoids the wrong device shutdown during the start-up. Owing to the above considerations, OLP delay time must last to bypass the initial output voltage transient and check the overload condition only when the output voltage is in steady-state. The output transient time depends on the value of the output capacitor and on the load. When CFB capacitor value is too low and cannot ensure the OLP delay, an alternative compensation network can be used as showed in Figure 40. Two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by CFB and CFB1 capacitors and RFB1 resistor. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole compensates zero frequency due to ESR (equivalent series resistor) of the output capacitance of the flyback converter. By taking into account the scheme in Figure 40, these poles and zero frequency are reported as follows: Equation 9 1 f ZFB = ----------------------------------------2 C FB R FB Equation 10 R FB ( DYN ) + R FB1 f PFB = ------------------------------------------------------------------------------2 C FB ( R FB ( DYN ) RFB1 ) Equation 11 1 fPFB1 = -----------------------------------------------------------------------------------2 C FB1 ( R FB1 + RFB ( DYN ) ) RFB(DYN) is the dynamic resistance seen by FB pin and reported in Table 7. CFB1 capacitor fixes the OLP delay and usually it is much higher than CFB. Equation 8 calculates the OLP delay time but CFB1 has to be considered. Using the alternative compensation network, the designer can satisfy the loop stability and OLP delay time. DocID026980 Rev 4 33/44 44 Operation description VIPer35 Figure 39. FB pin configuration (minimal BOM) From senseFET PWM To PWM logic + PWM control - Cfb Burst mode references BURST Burst mode logic OLP comparator + 4.8 V To disable logic - GIPG2801150948LM Figure 40. FB pin configuration From senseFET PWM + PWM CONTROL To PWM logic - Rfb1 Cfb BURST Cfb1 Burst mode logic Burst mode references OLP comparator + 4.8 V To disable logic - GIPG2801150952LM 34/44 DocID026980 Rev 4 VIPer35 Operation description Figure 41. Timing diagram: overload protection , 287 W 9 287 , '5$,1 W ,'OLP W 9)% 9)%ROS 9)%OLQ W 62)7 67$57 29(5/2$' :DUQLQJ 29(5/2$' :DUQLQJ 6723 23(5$7,21 *,3'59 8.14 Burst mode operation at no-load or very light load When the load decreases, the feedback loop lowers the feedback pin voltage. If it falls down the burst mode threshold, VFBBm, the power MOSFET doesn't switch on. After the MOSFET stops, the feedback pin voltage increases and by exceeding the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are reported in Table 7 and Figure 42 shows this behavior. System alternates period of time where power MOSFET switches to period of time where power MOSFET doesn't switch; this device working mode is the burst mode. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced by the period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower than the normal operation working frequency, up to some hundred of hertz, minimizing all frequency-related losses. During the burst mode the drain current peak is clamped to the level, ID_BM, (see Table 7). DocID026980 Rev 4 35/44 44 Operation description VIPer35 Figure 42. Burst mode timing: light load management VCOMP VFBbm +VFBbmhys VFBbm time IDD IDD1 IDD0 time IDRAIN ID_BM time Burst mode GIPG2801151121LM 8.15 Brown-out Brown-out protection is a not-latched shutdown function active when a condition of mains undervoltage is detected. The brown-out comparator is internally referenced to VBRth threshold (see Figure 10) and disables the PWM if the voltage applied to BR pin is below this internal reference. Under this condition the power MOSFET turns off. Until the brown-out condition is present, the VDD voltage continuously oscillates between the VDDon and the UVLO thresholds, as shown in the timing diagram of Figure 43. A voltage hysteresis improves the noise immunity. The switching operation restarts as the voltage on the pin is above the reference plus the voltage hysteresis. The brown-out comparator is provided with a current hysteresis, IBRhyst. The designer has to set the rectified input voltage above which the power MOSFET starts switching after brown-out event, VINon, and below which the power MOSFET switches off, VINoff. Thanks to the IBRhyst, see Table 7, these two thresholds can be set separately. When VINon and VINoff levels are fixed, with reference to Figure 43, the following relationships can be established to calculate RH and RL resistors: Equation 12 V BRhyst V INon - V INoff - VBRhyst V BRth R L = - --------------------- + --------------------------------------------------------------- -----------------V INon - V BRth IBRhyst IBRhyst Equation 13 V INon - V INoff - V BRhyst RL R H = --------------------------------------------------------------- ---------------------------------I BRhyst VBRhyst R L + --------------------I BRhyst 36/44 DocID026980 Rev 4 VIPer35 Operation description Figure 43. Brown-out: external setting and timing diagram 9 ,1 9,1RQ 9,1RII 9 '5$,1B67$57 9 %5 9%5WK 9'' 9,1B'& 9',6 9 LQB2. , %5 , %5K\VW 'LVDEOH 5+ %5 5/ 9%5WK & 9 LQB2. 9 '' 9''RQ 9''RII 9'' 5(67$57 , %5K\VW 9'6 9287 *,3'59 VINon must be less than the peak voltage at minimum mains and VINoff voltage has to be less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. BR pin is a high impedance input connected to high value resistors, thus it is ready to pick up noise, which might alter the VINoff threshold when the converter operates or causes the undesired switch-off of the device during ESD tests. The pin ca be bypassed to ground with a small film capacitor (1-10 nF) to prevent any malfunctioning. If the brown-out function is not used, BR pin has to be connected to GND, ensuring that the voltage is lower than the minimum VDIS threshold (50 mV, see Table 7). In order to enable the brown-out function, BR pin voltage has to be higher than the maximum VDIS threshold (150 mV, see Table 7). DocID026980 Rev 4 37/44 44 Package information 9 VIPer35 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 9.1 SO16N package information Figure 44. SO16N package outline 0016020_F 38/44 DocID026980 Rev 4 VIPer35 Package information Table 11. SO16N mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.10 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8 ccc 0.10 DocID026980 Rev 4 39/44 44 Package information 9.2 VIPer35 SDIP10 package information Figure 45. SDIP10 package outline 40/44 DocID026980 Rev 4 VIPer35 Package information Table 12. SDIP10 mechanical data mm Dim. Min. Typ. A Max. 5.33 A1 0.38 A2 2.92 4.95 b 0.36 0.56 b2 0.51 1.15 c 0.2 0.36 D 9.02 10.16 E 7.62 8.26 E1 6.1 7.11 E2 7.62 E3 10.92 e L 1.77 2.92 DocID026980 Rev 4 3.81 41/44 44 Ordering information 10 VIPer35 Ordering information Table 13. Order codes Order code FOsclim RDS(on) Peak drain current SO16N (tube) VIPER35LD VIPE35LDTR SO16N (tape and reel) 136 kHz SDIP10 (tube) VIPER35LE 4.5 225 kHz SO16N (tape and reel) SDIP10 (tube) VIPER35HE 42/44 1A SO16N (tube) VIPER35HD VIPER35HDTR Package DocID026980 Rev 4 VIPer35 11 Revision history Revision history Table 14. Document revision history Date Revision 23-Feb-2015 1 First release. 19-Mar-2015 2 Updated title in cover page. Minor text changes. 08-Jul-2015 3 Document status promoted from preliminary data to production data. Updated Section 4: Electrical ratings. Minor text changes. 4 Added SDIP10 package. Updated Figure 1 title in cover page from "Internal schematic diagram" to "Basic application schematic". Updated Section 3: Pin settings, Table 2: Pin description, Table 4: Thermal data and Section 10: Ordering information. Added Section 9.2: SDIP10 package information. Minor text changes. 10-Feb-2016 Changes DocID026980 Rev 4 43/44 44 VIPer35 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved 44/44 DocID026980 Rev 4