Data Sheet
NetLight
1417G5 and 1417H5-Type
January 2000 ATM/SONET/SDH Transceivers with Clock Recovery
Lucent Technologies Inc. 3
10 RD+
Received DATA Out.
No internal te rminations will be pr ovided. PECL
Transmitter
11 V
CCT
Transmitter Power Supply.
NA
12 V
EET
Transmitter Signal Ground.
NA
13 T
DIS
Transmitter Disable.
LVTTL
14 TD+
Transmitter Data In
. PECL
15 TD–
Transmitter Data In
Bar
. PECL
16 V
EET
Transmitter Signal Ground.
NA
17 B
MON
(–)
Laser Diode Bias Current Monitor—Negative End.
The laser bias current is
accessi ble as a dc- voltage by measuring the voltage d eveloped across pins
17 and 18.
NA
18 B
MON
(+)
Laser Diode Bias Current Monitor—Positive End.
See pin 17 description. NA
19 P
MON
(–)
Laser Diode Optical Power Monitor—Negative End.
The back- facet diode
monitor current is accessi ble as a dc- voltage by measuring the voltage devel-
oped across pins 19 and 20.
NA
20 P
MON
(+)
Laser Diode Optical Power Monitor—Positive End.
See pin 19 description. NA
Pin
Number Symbol Name/Description Logic
Family
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA stan-
dard EIA-625.
Although protection circuit ry is designed into the
devic e, take proper precautions to avoid exposure to
ESD. Lucent employs a human-body model (HBM) for
ESD-susceptibility testing and protection-design evalu-
ation . ESD voltage thresholds are dependent on the
critical parameters used to define the model . A stan-
dard HBM (resistance = 1.5 k
Ω
, capacitance = 100 pF)
is widely used and, there for e, can be used for compari-
son purposes. The HBM ESD threshold esta blished for
the 1417G5 and 1417H5 transceivers is
±
1000 V.
Application Information
The 1417 receiver section is a highly sensiti ve fiber-
optic recei ver. Although the data outputs are digital
logic l evels (PECL), the d evice should be thought of as
an analog component. When laying out system appli-
cation board s, the 1417 transcei ver should recei ve the
same type of consideration one would gi ve to a sensi-
ti ve analog component.
Printed-Wiring Board Layout Consider-
ations
A fiber-optic recei ver employs a very high-gain, wide-
bandwidth transimpedance amplifie r. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the recei ver is operating near its sensi-
tivity limit . Any unwanted signal currents that couple
into the recei ver circuit ry cause a decrease in the
receiver's sensitivity and can also degrade the per for-
mance of the receiver's signal detect (SD) circuit . To
minimize the coupling of un wanted noise into the
receiver, careful attention must be gi ven to the printed-
wiring board.
At a minimum, a double-sided p rinted-wi ring board
(PWB) with a large component-side ground plane
beneath the transcei ver must be used. In applications
that include ma ny other high-speed d evice s, a multi-
layer PWB is highly recommended. This permits the
placement of p ower and ground on separate l ayers,
which all ows them to be isolated from the signal line s.
Multil ayer const ruction also pe rmits the routing of sen-
siti ve signal traces away from high-l evel, high-speed
signal line s. To minimize the possibility of coupling
noise into the recei ver section, high-l evel, high-speed
signals such as transmitter inputs and clo ck lines
should be routed as far away as possi ble from the
receiver pins.
Pin Information
(continued)
Table 1. Transceiver Pin Descriptions
(continued)