1 A/0.6 A DC to DC Switching Regulator with Independent Positive and Negative Outputs ADP5072 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT VIN ADP5072 L1 SS VPOS RC1 SW1 SW1 COMP1 CC1 EN1 D1 RFT1 FB1 RFB1 PVIN PVIN AVIN VIN CIN PGND PGND VREF COUT1 CVREF EN2 RFB2 RC2 FB2 COMP2 CC2 SYNC SLEW SEQ RFT2 SW2 D2 AGND COUT2 L2 VNEG 12069-001 Input supply voltage range: 2.85 V to 5.5 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 35 V Integrated 1.0 A main switch Inverting regulator to generate VNEG output Adjustable negative output to -30 V Integrated 0.6 A main switch 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first Out of phase operation UVLO, OCP, OVP, and TSD protection 1.61 mm x 2.18 mm, 20-ball WLCSP -40C to +125C junction temperature range Figure 1. APPLICATIONS Bipolar amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and multiplexers Charge coupled device (CCD) bias supplies Optical module supplies RF power amplifier bias Time of flight module supplies GENERAL DESCRIPTION The ADP5072 is a dual, high performance dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 5.5 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to 35 V and a negative output voltage down to -30 V. The ADP5072 operates at a pin selected 1.2 MHz or 2.4 MHz switching frequency. The ADP5072 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first. The ADP5072 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. Rev. 0 Other key safety features in the ADP5072 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5072 is available in a 20-ball WLCSP and is rated for a -40C to +125C junction temperature range. Table 1. Family Models Model ADP5070 Boost Switch (A) 1.0 Inverter Switch (A) 0.6 ADP5071 2.0 1.2 ADP5072 ADP5073 ADP5074 ADP5075 1.0 N/A N/A N/A 0.6 1.2 2.4 0.8 Package 20-lead LFCSP (4 mmx 4 mm) and 20-lead TSSOP 20-lead LFCSP (4 mm x 4 mm) and 20-lead TSSOP 20-ball WLCSP (1.61 mm x 2.18 mm) 16-lead LFCSP (3 mm x 3 mm) 16-lead LFCSP (3 mm x 3 mm) 12-ball WLCSP (1.61 mm x 2.18 mm) Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. 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Technical Support www.analog.com ADP5072 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Precision Enabling...................................................................... 14 Applications ....................................................................................... 1 Soft Start ...................................................................................... 14 Typical Application Circuit ............................................................. 1 Slew Rate Control ....................................................................... 14 General Description ......................................................................... 1 Current-Limit Protection ............................................................ 14 Revision History ............................................................................... 2 Overvoltage Protection .............................................................. 14 Specifications..................................................................................... 3 Thermal Shutdown .................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Start-Up Sequence ...................................................................... 14 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 16 ESD Caution .................................................................................. 5 Component Selection ................................................................ 16 Pin Configuration and Function Descriptions ............................. 6 Output Capacitors ...................................................................... 17 Typical Performance Characteristics ............................................. 7 Loop Compensation .................................................................. 19 Theory of Operation ...................................................................... 13 Common Applications .............................................................. 21 PWM Mode ................................................................................. 13 Layout Considerations ............................................................... 23 PSM Mode ................................................................................... 13 Outline Dimensions ....................................................................... 24 Undervoltage Lockout (UVLO) ............................................... 13 Ordering Guide .......................................................................... 24 Oscillator and Synchronization ................................................ 13 Internal Regulator....................................................................... 13 REVISION HISTORY 1/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADP5072 SPECIFICATIONS PVIN = AVIN = 2.85 V to 5.5 V, positive output voltage (VPOS) = 15 V, negative output voltage (VNEG) = -15 V, fSW = 1200 kHz, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 2. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current PVIN, AVIN (Total) Standby Current UVLO System UVLO Threshold Rising Falling Hysteresis OSCILLATOR CIRCUIT Switching Frequency SYNC Input Input Clock Range Input Clock Minimum On Pulse Width Input Clock Minimum Off Pulse Width Input Clock High Logic Input Clock Low Logic PRECISION ENABLING (EN1, EN2) High Level Threshold Low Level Threshold Shutdown Mode Pull-Down Resistance BOOST REGULATOR Adjustable Positive Output Voltage Feedback Voltage Feedback Voltage Accuracy Symbol VIN Min 2.85 Typ Max 5.5 Unit V Test Conditions/Comments PVIN, AVIN IQ 3.5 4.0 mA ISTNDBY 2.05 2.2 mA No switching, EN1 = EN2 = high, PVIN = AVIN = 5 V No switching, EN1 = EN2 = low, PVIN = AVIN = 5 V VUVLO_RISING VUVLO_FALLING VHYS 2.85 2.5 2.8 2.55 0.25 V V V fSW 1.130 2.240 1.2 2.4 1.270 2.560 MHz MHz fSYNC tSYNC_MIN_ON tSYNC_MIN_OFF VH (SYNC) VL (SYNC) 1.0 100 100 2.6 MHz ns ns V V VTH_H VTH_L VTH_S 1.125 1.025 0.4 AVIN 1.3 0.4 1.15 1.05 REN 1.48 VPOS VFB1 0.8 1.175 1.075 +0.5 +1.5 0.1 V V % % A V %/mA %/V Feedback Bias Current Overvoltage Protection Threshold Load Regulation Line Regulation IFB1 VOV1 (VFB1/VFB1)/ILOAD1 (VFB1/VFB1)/VPVIN Error Amplifier (EA) Transconductance Power FET On Resistance Power FET Maximum Drain Source Voltage Current-Limit Threshold, Main Switch Minimum On Time Minimum Off Time gM1 RDS (ON) BOOST VDS (MAX) BOOST 260 300 175 39 340 A/V m V ILIM (BOOST) 1.0 1.1 50 25 1.3 A ns ns 0.86 0.0003 0.002 Rev. 0 | Page 3 of 24 Internal circuitry disabled to achieve ISTNDBY M 35 -0.5 -1.5 V V V SYNC = low SYNC = high (connect to PVIN) TJ = 25C TJ = -40C to +125C At FB1 pin ILOAD11 = 5 mA to 150 mA VPVIN = 2.85 V to 5.5 V, ILOAD1 = 50 mA ADP5072 Parameter INVERTING REGULATOR Adjustable Negative Output Voltage Reference Voltage Reference Voltage Accuracy Symbol Min VNEG VREF -30 Feedback Bias Current Overvoltage Protection Threshold IFB2 VOV2 Load Regulation ((VREF - VFB2)/(VREF - VFB2))/ ILOAD2 ((VREF - VFB2)/(VREF - VFB2))/ VPVIN gM2 RDS (ON) INVERTER VDS (MAX) INVERTER Hiccup Time THERMAL SHUTDOWN Threshold Hysteresis Unit 0.74 0.0004 %/mA 0.003 %/V +0.5 +1.5 0.8 -0.5 -1.5 ILIM (INVERTER) Max V V % % V % % A V -0.5 -1.5 VREF - VFB2 EA Transconductance Power FET On Resistance Power FET Maximum Drain Source Voltage Current-Limit Threshold, Main Switch Minimum On Time Minimum Off Time SOFT START Soft Start Timer for DC to DC Regulators Typ 1.60 Feedback Voltage Feedback Voltage Accuracy Line Regulation 1 Data Sheet +0.5 +1.5 0.1 260 300 350 39 340 A/V m V 600 660 60 50 750 mA ns ns tSS tHICCUP 4 32 8 x tSS ms ms ms TSHDN THYS 150 15 C C Test Conditions/Comments TJ = 25C TJ = -40C to +125C TJ = 25C TJ = -40C to +125C At FB2 pin after soft start has completed ILOAD2 = 5 mA to 75 mA VPVIN = 2.85 V to 5.5 V, ILOAD2 = 25 mA SS = open SS resistor = 50 k to GND ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load). Rev. 0 | Page 4 of 24 Data Sheet ADP5072 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter PVIN, AVIN SW1 SW2 PGND, AGND EN1, EN2, FB1, FB2, SYNC, COMP1, COMP2, SLEW, SS, SEQ, VREF Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating -0.3 V to +6V -0.3 V to +40 V PVIN - 40 V to PVIN + 0.3 V -0.3 V to +0.3 V -0.3 V to +6 V -0.3 V to AVIN + 0.3 V JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. JT is the junction to case thermal characterization parameter. -40C to +125C Table 4. Thermal Resistance Package Type CB-20-141, 2 -65C to +150C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JA 50 JC 0.54 JT 0.13 Unit C/W JA and JT are based on a 4-layer printed circuit board (PCB) (two signal and two power planes) with nine thermal vias connecting the exposed pad to the ground plane as recommended in the Layout Considerations section. JC is measured at the top of the package and is independent of the PCB. The JT value is more appropriate for calculating junction to case temperature in the application. 2 The thermal resistance values specified in Table 4 are simulated based on JEDEC specifications, unless specified otherwise, and must be used in compliance with JESD51-12. 1 ESD CAUTION Rev. 0 | Page 5 of 24 ADP5072 Data Sheet 1 2 3 4 A PVIN SW2 SW1 PGND B AVIN PVIN SW1 PGND C EN2 SYNC SEQ EN1 D AGND SLEW SS FB1 E COMP2 FB2 VREF COMP1 12069-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. A1, B2 A2 A3, B3 A4, B4 B1 C1 Mnemonic PVIN SW2 SW1 PGND AVIN EN2 C2 SYNC C3 SEQ C4 EN1 D1 D2 AGND SLEW D3 SS D4 FB1 E1 COMP2 E2 FB2 E3 E4 VREF COMP1 Description Power Input for the Boost Regulator. Switching Node for the Inverting Regulator. Switching Node for the Boost Regulator. Power Ground for the Boost Regulator. System Power Supply for the ADP5072. Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable the inverting regulator output. Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC pin high. To set the switching frequency to 1.2 MHz, pull the SYNC pin low. To synchronize the switching frequency, connect the SYNC pin to an external clock. Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, ENx, leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to PVIN (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence. Hold the other enable pin low. Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the boost regulator output. Analog Ground. Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew rate (optimal efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to PVIN. For the slowest slew rate (optimal noise performance), connect the SLEW pin to AGND. Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start time, connect a resistor between the SS pin and AGND. Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost regulator output capacitor and AGND to program the output voltage. Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and AGND. Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting regulator output capacitor and VREF to program the output voltage. Inverting Regulator Reference Output. Connect a 1.0 F ceramic filter capacitor between the VREF pin and AGND. Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin and AGND. Rev. 0 | Page 6 of 24 Data Sheet ADP5072 TYPICAL PERFORMANCE CHARACTERISTICS 700 350 VIN = 3.3V, VIN = 3.3V, VIN = 5.0V, VIN = 5.0V, 600 L L L L = 6.8H = 4.7H = 10.0H = 6.8H 300 150 200 100 100 50 0 5 10 15 20 25 30 35 40 VPOS (V) 0 -35 Figure 3. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator, fSW = 1.2 MHz, TA = 25C, Based on Target of 70% ILIM (BOOST) -30 -25 -20 -15 -10 -5 0 VNEG (V) 16646-006 IOUT (MAX) (mA) 300 200 16646-003 Figure 6. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator, fSW = 1.2 MHz, TA = 25C, Based on Target of 70% ILIM (INVERTER) 700 350 VIN = 3.3V, VIN = 3.3V, VIN = 5.0V, VIN = 5.0V, 600 L L L L = 6.8H = 3.3H = 10.0H = 3.3H 300 VIN = 3.3V, VIN = 3.3V, VIN = 5.0V, VIN = 5.0V, L = 10.0H L = 6.8H L = 10.0H L = 15.0H 250 400 300 200 150 200 100 100 50 0 5 10 15 20 25 30 35 40 VPOS (V) 0 -35 16646-004 0 Figure 4. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator, fSW = 2.4 MHz, TA = 25C, Based on Target of 70% ILIM (BOOST) -25 -20 -10 -15 -5 0 VNEG (V) Figure 7. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator, fSW = 2.4 MHz, TA = 25C, Based on Target of 70% ILIM (INVERTER) 100 90 90 80 80 70 EFFICIENCY (%) 70 60 50 40 30 60 50 40 30 20 20 VIN = 3.3V, fSW = 1.2MHz VIN = 3.3V, fSW = 2.4MHz 0.01 0.1 VIN = 3.3V, fSW = 1.2MHz VIN = 3.3V, fSW = 2.4MHz 10 1.0 LOAD CURRENT (A) Figure 5. Efficiency vs. Load Current for Boost Regulator, VIN = 3.3 V, VPOS = 5 V, TA = 25C 0 0.001 16646-005 10 0 0.001 -30 16646-007 IOUT (MAX) (mA) 500 0.01 0.1 LOAD CURRENT (A) 1.0 16646-008 IOUT (MAX) (mA) 400 0 IOUT (MAX) (mA) L = 10.0H L = 6.8H L = 10.0H L = 15.0H 250 500 EFFICIENCY (%) VIN = 3.3V, VIN = 3.3V, VIN = 5.0V, VIN = 5.0V, Figure 8. Efficiency vs. Load Current for Inverting Regulator, VIN = 3.3 V, VNEG = -5 V, TA = 25C Rev. 0 | Page 7 of 24 Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 30 0.1 10 1.0 0 0.001 90 90 80 80 70 70 EFFICIENCY (%) 100 50 40 60 50 40 30 10 0.01 0.1 = 1.2MHz = 2.4MHz = 1.2MHz = 2.4MHz 10 1.0 LOAD CURRENT (A) Figure 10. Efficiency vs. Load Current for Boost Regulator, VPOS = 15 V, TA = 25C 0 0.001 0.01 = 1.2MHz = 2.4MHz = 1.2MHz = 2.4MHz 0.1 1.0 LOAD CURRENT (A) Figure 13. Efficiency vs. Load Current for Inverting Regulator, VNEG = -15 V, TA = 25C 100 VIN = 3.3V, fSW = 1.2MHz VIN = 5V, fSW = 1.2MHz VIN = 5V, fSW = 2.4MHz 90 80 70 70 EFFICIENCY (%) 80 60 50 40 60 50 40 30 30 20 20 10 10 0.01 LOAD CURRENT (A) 0.1 0 0.001 16646-211 0 0.001 VIN = 3.3V, fSW VIN = 3.3V, fSW VIN = 5.0V, fSW VIN = 5.0V, fSW 20 16646-010 VIN = 3.3V, fSW VIN = 3.3V, fSW VIN = 5.0V, fSW VIN = 5.0V, fSW 20 90 1.0 16646-013 30 100 0.1 Figure 12. Efficiency vs. Load Current for Inverting Regulator, VNEG = -9 V, TA = 25C 100 60 0.01 = 1.2MHz = 2.4MHz = 1.2MHz = 2.4MHz LOAD CURRENT (A) Figure 9. Efficiency vs. Load Current for Boost Regulator, VPOS = 9 V, TA = 25C 0 0.001 VIN = 3.3V, fSW VIN = 3.3V, fSW VIN = 5.0V, fSW VIN = 5.0V, fSW 20 LOAD CURRENT (A) EFFICIENCY (%) 40 16646-012 0.01 = 1.2MHz = 2.4MHz = 1.2MHz = 2.4MHz 16646-009 10 EFFICIENCY (%) 50 30 VIN = 3.3V, fSW VIN = 3.3V, fSW VIN = 5.0V, fSW VIN = 5.0V, fSW 20 0 0.001 60 Figure 11. Efficiency vs. Load Current for Boost Regulator, VPOS = 35 V, TA = 25C VIN = 3.3V, fSW = 1.2MHz VIN = 5V, fSW = 1.2MHz VIN = 5V, fSW = 2.4MHz 0.01 LOAD CURRENT (A) 0.1 16646-214 EFFICIENCY (%) ADP5072 Figure 14. Efficiency vs. Load Current for Inverting Regulator, VNEG = -30 V, TA = 25C Rev. 0 | Page 8 of 24 Data Sheet ADP5072 100 90 80 80 70 70 50 40 40 30 20 20 TA = +125C TA = +25C TA = - 40C 0.01 0.1 1.0 LOAD CURRENT (A) 0 0.001 0.5 0.4 VARIATION FROM NOMINAL (%) 0.5 0.2 0.1 0 -0.1 -0.2 -0.3 3.5 4.0 4.5 5.0 5.5 6.0 VIN (V) VARIATION IN NOMINAL OUTPUT VOLTAGE (%) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.5 0.10 0.15 0.20 0.25 0 -0.1 -0.2 -0.3 VNEG ACCURACY VREF ACCURACY VFB2 ACCURACY 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LOAD CURRENT (A) Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V 0.5 0.4 0.3 1.2MHz 2.4MHz 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 16646-016 1.2MHz 2.4MHz 0.05 0.1 Figure 19. Inverting Regulator Line Regulation, VNEG = -15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25C 0.5 0 0.2 VIN (V) Figure 16. Boost Regulator Line Regulation, VPOS = 15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25C -0.4 0.3 -0.5 2.5 16646-015 3.0 1.0 -0.4 VPOS ACCURACY VFB1 ACCURACY -0.5 2.5 0.1 Figure 18. Efficiency vs. Load Current for Inverting Regulator over Temperature, VIN = 5 V, VNEG = -15 V, fSW = 1.2 MHz 0.4 0.3 0.01 LOAD CURRENT (A) Figure 15. Efficiency vs. Load Current for Boost Regulator over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz -0.4 TA = +125C TA = +25C TA = - 40C 10 0 0.02 0.04 0.06 0.08 LOAD CURRENT (A) 0.10 0.12 16646-220 0 0.001 VARIATION FROM NOMINAL (%) 50 30 10 VARIATION IN NOMINAL OUTPUT VOLTAGE (%) 60 16646-018 60 16646-014 EFFICIENCY (%) 90 16646-011 EFFICIENCY (%) 100 Figure 20. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = -15 V Rev. 0 | Page 9 of 24 ADP5072 Data Sheet 0 -0.1 -0.2 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 INVERTING REGULATOR LOAD (A) Figure 21. Cross Regulation, Boost Regulator VFB1 Regulation, VIN = 5 V, VPOS = 15 V, VNEG = -15 V, fSW = 2.4 MHz, TA = 25C, Boost Regulator Run in Continuous Conduction Mode with Fixed Load for Test 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 BOOST REGULATOR LOAD (A) Figure 24. Cross Regulation, Inverting Regulator VFB2 Regulation, VIN = 5 V, VPOS = 15 V, VNEG = -15 V, fSW = 2.4 MHz, TA = 25C, Inverting Regulator Run in Continuous Conduction Mode with Fixed Load for Test 1.10 1.05 TA = +125C TA = +25C TA = - 40C 3.0 3.5 4.0 4.5 5.0 5.5 Figure 22. Boost Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN) over Temperature 0.72 0.69 0.66 0.63 TA = +125C TA = +25C TA = - 40C 0.60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) 16646-024 INVERTING REGULATOR CURRENT LIMIT (A) 1.15 16646-021 BOOST REGULATOR CURRENT LIMIT (A) 1.20 VIN (V) Figure 25. Inverting Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN) over Temperature 1.27 2.54 OSCILLATOR FREQUENCY (MHz) 2.49 2.44 2.39 2.34 2.29 3.0 3.5 4.0 VIN (V) 4.5 5.0 1.25 1.23 1.21 1.19 1.17 1.15 TA = +125C TA = +25C TA = - 40C 5.5 1.13 2.5 16646-022 OSCILLATOR FREQUENCY (MHz) -0.2 0.75 1.25 2.24 2.5 -0.1 0 1.30 1.00 2.5 0 Figure 23. Oscillator Frequency vs. Input Voltage (VIN) over Temperature, SYNC Pin = High TA = +125C TA = +25C TA = - 40C 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 16646-025 0 0.1 16646-020 0.1 VFB2 DEVIATION FROM AVERAGE VALUE (%) 0.2 16646-017 VFB1 DEVIATION FROM AVERAGE VALUE (%) 0.2 Figure 26. Oscillator Frequency vs. Input Voltage (VIN) over Temperature, SYNC Pin = Low Rev. 0 | Page 10 of 24 Data Sheet ADP5072 3.0 OPERATING QUIESCENT CURRENT (mA) 3.8 2.0 1.5 1.0 0.5 2.7 3.2 3.7 4.2 VIN (V) 4.7 5.7 5.2 3.4 3.2 3.0 2.8 2.6 TA = +125C TA = +25C TA = - 40C 2.4 2.7 16646-023 TA = +125C TA = +25C TA = -40C 3.6 3.2 3.7 4.2 VIN (V) 4.7 16646-026 STANDBY CURRENT (mA) 2.5 5.7 5.2 Figure 30. Operating Quiescent Current vs. Input Voltage (VIN) over Temperature, Both ENx Pins On Figure 27. Standby Current vs. Input Voltage (VIN) over Temperature, Both ENx Pins Below Shutdown Threshold VIN VIN VPOS 2 VNEG 2 1 1 CH1 1.00V CH3 10.0mV B W CH2 50.0mV B W B W M1.00ms A CH1 T 1.906000ms 4.96V 16646-128 3 VFB2 CH1 1.00V CH3 20.0mV Figure 28. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VPOS = 15 V, RLOAD1 = 300 , fSW = 2.4 MHz, TA = 25C B W B W B CH2 200mV W M2.00ms A CH1 T 5.772000ms 5.16V 16646-131 VFB1 3 Figure 31. Inverting Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VNEG = -15 V, RLOAD2 = 300 , fSW = 2.4 MHz, TA = 25 ILOAD1 ILOAD2 4 VPOS 1 1 VFB1 3 CH1 50.0mV CH3 10.0mV B B W W CH4 50.0mA B W M100s A CH4 T 20.30% 140mA 16646-129 3 VNEG VFB2 CH1 100mV CH3 10.0mV Figure 29. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V, ILOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25C B B W W CH4 20.0mA B W M1.00ms A CH4 T 20.30% 48.0mA 16646-132 4 Figure 32. Inverting Regulator Load Transient, VIN = 5 V Step, VNEG = -15 V, ILOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25C Rev. 0 | Page 11 of 24 ADP5072 Data Sheet IINDUCTOR 3 IINDUCTOR 3 SW1 SW2 2 1 VNEG VPOS B W B W CH3 100mA B W M2.00s A CH3 T 7.960000s 82.0mA CH1 5.00V CH2 500mV Figure 33. Boost Regulator Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 12 V, VPOS = 15 V, ILOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25C B B W W B CH3 50.0mA W M4.00s A CH3 T 12.00000s 16646-135 CH1 500mV CH2 10.0V 2 16646-133 1 35.0mA Figure 36. Inverting Regulator Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = -5 V, ILOAD2 = 0 mA, fSW = 2.4 MHz, TA = 25C IINDUCTOR IINDUCTOR 3 3 SW1 SW2 2 1 2 B B W W CH3 200mA B W M200ns A CH3 T 7.960000s 100mA 16646-134 CH1 500mV CH2 10.0V VNEG CH1 5.00V CH2 500mV Figure 34. Boost Regulator Discontinuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 6 mA, fSW = 2.4 MHz, TA = 25C B W B W CH3 50mA B W M200ns A CH3 T 24.46000s 42.0mA 16646-136 VPOS 1 Figure 37. Inverting Regulator Discontinuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = -5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25C IINDUCTOR IINDUCTOR 3 3 SW1 SW2 2 VNEG VPOS CH1 500mV CH2 10.0V B W B W CH3 500mA B W M200ns A CH4 T 7.960000s 310mA CH1 5.00V CH2 500mV Figure 35. Boost Regulator Continuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25C B W B W CH3 50mA B W M100ns A CH3 T 24.46000s 84.0mA 16646-138 2 16646-137 1 1 Figure 38. Inverting Regulator Continuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = -5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25C Rev. 0 | Page 12 of 24 Data Sheet ADP5072 THEORY OF OPERATION VIN CIN SYNC PVIN AVIN CURRENT SENSE INVERTER PWM CONTROL D1 REFERENCES SW1 COUT1 PLL BOOST PWM CONTROL PGND RFB1 COMP1 - REF1 FB2 BOOST_ENABLE SEQUENCE CONTROL ERROR AMP RFB2 INVERTER_ENABLE REF_1V6 + FB1 FB2 CC1 EN1 VREF CVREF COMP2 4A UVLO SLEW TRI-STATE BUFFER SLEW THERMAL SHUTDOWN 1.5M RFT2 REF2 - 1.5M RC1 ERROR AMP + OSCILLATOR CURRENT SENSE FB1 COUT2 L2 SLEW RFT1 VNEG SLEW START-UP TIMERS OVP EN2 SEQ REFERENCE GENERATOR REF1 REF2 RC2 REF_1V6 CC2 SS RSS (OPTIONAL) AGND 16646-037 VPOS D2 SW2 L1 Figure 39. Functional Block Diagram PWM MODE OSCILLATOR AND SYNCHRONIZATION The boost and inverting regulators in the ADP5072 operate at a fixed frequency set by an internal oscillator. At the start of each oscillator cycle, the MOSFET switch turns on, applying a positive voltage across the inductor. The inductor current increases until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch; this threshold is set by the error amplifier output. During the MOSFET off time, the inductor current declines through the external diode until the next oscillator clock pulse starts a new cycle. It regulates the output voltage by adjusting the peak inductor current threshold. The ADP5072 initiates the drive of the boost regulator SW1 pin and the inverting regulator SW2 pin 180 out of phase to reduce peak current consumption and noise. PSM MODE During light load operation, the regulators can skip pulses to maintain output voltage regulation. Skipping pulses increases the device efficiency. UNDERVOLTAGE LOCKOUT (UVLO) The undervoltage lockout circuitry monitors the AVIN pin voltage level. If the input voltage drops below the VUVLO_FALLING threshold, both regulators turn off. After the AVIN pin voltage rises above the VUVLO_RISING threshold, the soft start period initiates, and the regulators are enabled. A phase-locked loop (PLL)-based oscillator generates the internal clock and offers a choice of two internally generated frequency options or external clock synchronization. The switching frequency is configured using the SYNC pin options shown in Table 6. For external synchronization, connect the SYNC pin to a suitable clock source. The PLL locks to an input clock within the range specified by fSYNC. Table 6. SYNC Pin Options SYNC Pin High Low External Clock Switching Frequency 2.4 MHz 1.2 MHz 1 x clock frequency INTERNAL REGULATOR The VREF regulator provides a reference voltage for the inverting regulator feedback network to ensure a positive feedback voltage on the FB2 pin. A current-limit circuit is included for the VREF regulator to protect the circuit from accidental loading. Rev. 0 | Page 13 of 24 ADP5072 Data Sheet PRECISION ENABLING CURRENT-LIMIT PROTECTION TheADP5072 has an individual enable pin for the boost and inverting regulators: EN1 and EN2. The enable pins feature a precision enable circuit with an accurate reference voltage. This reference allows the ADP5072 to be sequenced easily from other supplies. It can also be used as a programmable UVLO input by using a resistor divider. The boost and inverting regulators in the ADP5072 include current-limit protection circuitry to limit the amount of forward current through the MOSFET switch. The enable pins have an internal pull-down resistor that defaults each regulator to off when the pin is floating. When the voltage at the enable pins is greater than the VTH_H reference level, the regulator is enabled. When the peak inductor current exceeds the overcurrent limit threshold for a number of clock cycles during an overload or short-circuit condition, the regulator enters hiccup mode. The regulator stops switching and then restarts with a new soft start cycle after tHICCUP and repeats until the overcurrent condition is removed. OVERVOLTAGE PROTECTION SOFT START Each regulator in the ADP5072 includes soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is internally set to the fastest rate when the SS pin is open. Connecting a resistor between SS and AGND allows the adjustment of the soft start delay. The delay length is common to both regulators. SLEW RATE CONTROL The ADP5072 employs programmable output driver slew rate control circuitry. This circuitry reduces the slew rate of the switching node as shown in Figure 40, resulting in reduced ringing and lower EMI. To program the slew rate, connect the SLEW pin to the PVIN pin for normal mode, to the AGND pin for slow mode, or leave it open for fast mode. This configuration allows the use of an open-drain output from a noise sensitive device to switch the slew rate from fast to slow, for example, during ADC sampling. Note that slew rate control causes a trade-off between efficiency and low EMI. An overvoltage protection mechanism is present on the FB1 and FB2 pins for the boost and inverting regulators. On the boost regulator, when the voltage on the FB1 pin exceeds the VOV1 threshold, the switching on SW1 stops until the voltage falls below the threshold again. This functionality is permanently enabled on this regulator. On the inverting regulator, when the voltage on the FB2 pin drops below the VOV2 threshold, the switching stops until the voltage rises above the threshold. This functionality is enabled after the soft start period has elapsed. THERMAL SHUTDOWN In the event that theADP5072 junction temperature rises above TSHDN, the thermal shutdown circuit turns off the IC. Extreme junction temperatures can be the result of prolonged high current operation, poor circuit board design, and/or high ambient temperature. Hysteresis is included so that when thermal shutdown occurs, the ADP5072 does not return to operation until the on-chip temperature drops below TSHDN minus THYS. When resuming from thermal shutdown, a soft start is performed on each enabled channel. START-UP SEQUENCE The ADP5072 implements a flexible start-up sequence to meet different system requirements. Three different enabling modes can be implemented via the SEQ pin, as explained in Table 7. FASTEST Table 7. SEQ Pin Settings 16646-038 SLOWEST Figure 40. Switching Node at Various Slew Rate Settings SEQ Pin Open PVIN Low Description Manual enable mode Simultaneous enable mode Sequential enable mode To configure the manual enable mode, leave the SEQ pin open. The boost and inverting regulators are controlled separately from their respective precision enable pins. Rev. 0 | Page 14 of 24 Data Sheet ADP5072 To configure the simultaneous enable mode, connect the SEQ pin to the PVIN pin. Both regulators power up simultaneously when the EN2 pin is taken high. The EN1 pin enable can be used to enable the internal references ahead of enabling the outputs, if desired. The simultaneous enable mode timing is shown in Figure 41. VPOS VIN TIME VPOS VNEG 1. VPOS FOLLOWED BY VNEG (SEQ = LOW, EN1 = HIGH, EN2 = LOW) VIN VPOS TIME VIN TIME VNEG Figure 41. Simultaneous Enable Mode To configure the sequential enable mode, pull the SEQ pin low. In this mode, either VPOS or VNEG can be enabled first by using the EN1 pin or EN2 pin. Keep the other pin low. The secondary supply is enabled when the primary supply completes soft start and its feedback voltage reaches approximately 85% of the target value. The sequential enable mode timing is shown in Figure 42. Rev. 0 | Page 15 of 24 2. VNEG FOLLOWED BY VPOS (SEQ = LOW, EN2 = HIGH, EN1 = LOW) Figure 42. Sequential Enable Mode 16646-040 SIMULTANEOUS ENABLE MODE (SEQ = HIGH, EN2 = HIGH) 16646-039 VNEG ADP5072 Data Sheet APPLICATIONS INFORMATION COMPONENT SELECTION Set the negative output for the inverting regulator by Feedback Resistors The ADP5072 provides an adjustable output voltage for both boost and inverting regulators. An external resistor divider sets the output voltage where the divider output must equal the appropriate feedback reference voltage, VFB1 or VFB2. To limit the output voltage accuracy degradation due to feedback bias current, ensure that the current through the divider is at least 10 times IFB1 or IFB2. Set the positive output for the boost regulator by VNEG = VFB2 - RFT2 (VREF - VFB2 ) RFB2 where: VNEG is the negative output voltage. VFB2 is the FB2 reference voltage. RFT2 is the feedback resistor from VNEG to FB2. RFB2 is the feedback resistor from FB2 to VREF. VREF is the VREF pin reference voltage. RFT1 VPOS = VFB1 x 1 + R FB1 where: VPOS is the positive output voltage. VFB1 is the FB1 reference voltage. RFT1 is the feedback resistor from VPOS to FB1. RFB1 is the feedback resistor from FB1 to AGND. Table 8. Recommended Feedback Resistor Values Desired Output Voltage (V) 4.2 5 9 12 13 15 18 20 24 30 RFT1 (M) 0.432 0.604 1.24 1.4 2.1 2.43 2.15 2.55 3.09 3.65 Boost Regulator Calculated RFB1 (k) Output Voltage (V) 102 4.188 115 5.002 121 8.998 100 12.000 137 13.063 137 14.990 100 18.000 107 19.865 107 23.903 100 30.000 Rev. 0 | Page 16 of 24 RFT2 (M) 0.715 1.15 1.62 1.15 2.8 2.32 2.67 2.94 3.16 4.12 Inverting Regulator Calculated RFB2 (k) Output Voltage (V) 115 -4.174 158 -5.023 133 -8.944 71.5 -12.067 162 -13.027 118 -14.929 113 -18.103 113 -20.014 102 -23.984 107 -30.004 Data Sheet ADP5072 OUTPUT CAPACITORS VREF Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias. A 1.0 F ceramic capacitor (CVREF) is required between the VREF pin and AGND. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 25 V or 50 V (depending on output) are recommended for optimal performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. Calculate the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage using the following equation: Soft Start Resistor A resistor can be connected between the SS pin and the AGND pin to increase the soft start time. The soft start time can be set by the resistor between 4 ms (268 k) and 32 ms (50 k). Leaving the SS pin open selects the fastest time of 4 ms. Figure 43 shows the behavior of this operation. Calculate the soft start time using the following formula: tSS = 38.4 x 10-3 - 1.28 x 10-7 x RSS () where 50 k RSS 268 k. SOFT START TIMER 32ms CEFFECTIVE = CNOMINAL x (1 - TEMPCO) x (1 - DCBIASCO) x (1 - Tolerance) To guarantee the performance of the device, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Capacitors with lower effective series resistance (ESR) and effective series inductance (ESL) are preferred to minimize output voltage ripple. SS PIN OPEN R2 R1 SOFT START RESISTOR 16646-041 4ms where: CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst-case capacitor temperature coefficient. DCBIASCO is the dc bias coefficient derating at the output voltage. Tolerance is the worst case component tolerance. Figure 43. Soft Start Behavior Diodes A Schottky diode with low junction capacitance is recommended for D1 and D2, diodes for VPOS and VNEG, respectively. At higher output voltages and especially at higher switching frequencies, the junction capacitance is a significant contributor to efficiency. Higher capacitance diodes also generate more switching noise. As a guide, a diode with less than 40 pF junction capacitance is preferred when the output voltage is greater than 5 V. Inductor Selection for the Boost Regulator Note that the use of large output capacitors can require a slower soft start to prevent reaching the current limit during startup. A 10 F capacitor is suggested as a ideal balance between performance and size. Input Capacitor Higher value input capacitors help to reduce the input voltage ripple and improve transient response. To minimize supply noise, place the input capacitor as close as possible to the AVIN pin and PVIN pin. A low ESR capacitor is recommended. The effective capacitance needed for stability is a minimum of 10 F. If the power pins are individually decoupled, it is recommended to use a minimum of a 5.6 F capacitor on the PVIN pin and a 3.3 F capacitor on the AVIN pin to prevent reaching the current limit. The minimum values specified exclude dc bias, temperature, and tolerance effects that are application dependent and must be taken into consideration. The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 H to 22 H are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc input current for the application typically yields an optimal compromise. Rev. 0 | Page 17 of 24 ADP5072 Data Sheet For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VPOS) voltages determine the switch duty cycle (DUTY1) by the following equation: V - VIN + VDIODE1 DUTY1 = POS VPOS + VDIODE1 where VDIODE1 is the forward voltage drop of the Schottky diode (D1). The dc input current in CCM (IIN) can be determined by the following equation: I IN = IOUT1 (1 - DUTY1 ) Using the duty cycle (DUTY1) and switching frequency (fSW), determine the on time (tON1) using the following equation: tON1 = DUTY1 f SW Inductor Selection for the Inverting Regulator The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 H to 22 H are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VNEG) voltages determine the switch duty cycle (DUTY2) by the following equation: | VNEG | + VDIODE2 DUTY2 = VIN + | VNEG | + VDIODE2 The inductor ripple current (IL1) in steady state is calculated by where VDIODE2 is the forward voltage drop of the Schottky diode (D2). V xt I L1 =IN ON1 L1 Solve for the inductance value (L1) using the following equation: L1 = VIN x t ON1 I L2 = I L1 Assuming an inductor ripple current of 30% of the maximum dc input current results in L1 = The dc current in the inductor in CCM (IL2) can be determined by the following equation: VIN x tON1 x (1 - DUTY1 ) IOUT2 (1 - DUTY2 ) Using the duty cycle (DUTY2) and switching frequency (fSW), determine the on time (tON2) by the following equation: tON2 = 0.3 x IOUT1 Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is less than the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5072 boost regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. This slope compensation is built in to the ADP5072. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, LMIN1, for the application parameters in the following equation: 0.13 L1 > LMIN1 = VIN x - 0.16 (H) (1 - DUTY ) 1 Table 10 suggests a series of inductors to use with the ADP5072 boost regulator. DUTY2 f SW The inductor ripple current (IL2) in steady state is calculated by V xt I L2 =IN ON2 L2 Solve for the inductance value (L2) by the following equation: L2 = VIN x tON2 I L2 Assuming an inductor ripple current of 30% of the maximum dc current in the inductor results in L2 = VIN x tON2 x (1 - DUTY2 ) 0.3 x IOUT2 Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is less than the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. Rev. 0 | Page 18 of 24 Data Sheet ADP5072 When the ADP5072 inverting regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, LMIN2, for the application parameters in the following equation: 0.13 L2 > LMIN2 = VIN x - 0.16 (H) (1 - DUTY ) 2 ZOUT1 is the impedance of the load in parallel with the output capacitor. To determine the crossover frequency (fC1), it is important to note that, at that frequency, the compensation impedance (ZCOMP1) is dominated by a resistor (RC1), and the output impedance (ZOUT1) is dominated by the impedance of an output capacitor (COUT1). Therefore, when solving for the crossover frequency, the equation (by definition of the crossover frequency) is simplified to AVL1 = Table 11 suggests a series of inductors to use with the ADP5072 inverting regulator. LOOP COMPENSATION The ADP5072 uses external components to compensate the regulator loop, allowing the optimization of the loop dynamics for a given application. where fC1 is the crossover frequency. To solve for RC1, use the following equation: Boost Regulator The boost converter produces an undesirable right half plane zero in the regulation feedback loop. This feedback loop requires compensating the regulator such that the crossover frequency occurs well below the frequency of the right half plane zero. The right half plane zero is determined by the following equation: RLOAD1 (1 - DUTY1 )2 2 x L1 RC1 = VFB1 x VIN x g M1 x g CS1 where gCS1 = 6.25 A/V. Using typical values for VFB1 and GM1 results in RC1 = 4188 x fC1 x COUT1 x (VPOS )2 VIN For improved accuracy, it is recommended to use the value of the output capacitance, COUT1, expected for the dc bias conditions under which it operates in the calculation for RC1. where: fZ1(RHP) is the right half plane zero frequency. RLOAD1 is the equivalent load resistance or the output voltage divided by the load current. After the compensation resistor is known, set the zero formed by the compensation capacitor and resistor, CC1 and RC1, to onefourth of the crossover frequency, or V - VIN + VDIODE1 DUTY1 = POS VPOS + VDIODE1 CC1 = where VDIODE1 is the forward voltage drop of the Schottky diode (D1). 2 x fC1 x RC1 where CC1 is the compensation capacitor value. To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-tenth of the right half plane zero frequency. The boost regulator loop gain is AVL1 = 2 x fC1 x COUT1 x (VPOS )2 VFB1 VIN x x g M1 x ROUT1 ||Z COMP1 x g CS1 x ZOUT1 VPOS VPOS where: AVL1 is the loop gain. VFB1 is the feedback regulation voltage VPOS is the regulated positive output voltage. VIN is the input voltage. gM1 is the error amplifier transconductance gain. ROUT1 is the output impedance of the error amplifier and is 33 M. ZCOMP1 is the impedance of the series resistor/capacitor (RC) network from COMP1 to AGND. gCS1 is the current sense transconductance gain (the inductor current divided by the voltage at COMP1), which is internally set by the ADP5072 and is 6.25 A/V. Rev. 0 | Page 19 of 24 FB1 ERROR AMPLIFIER COMP1 gM1 REF1 RC1 CC1 16646-042 f Z1 (RHP ) = VFB1 VIN x x g M1 x RC1 x g CS1 x VPOS VPOS 1 =1 2 x fC1 x COUT1 Figure 44. Compensation Components ADP5072 Data Sheet Inverting Regulator The inverting converter, like the boost converter, produces an undesirable right half plane zero in the regulation feedback loop. This feedback loop requires compensating the regulator such that the crossover frequency occurs well below the frequency of the right half plane zero. The right half plane zero frequency is determined by the following equation: RLOAD2 (1 - DUTY2 ) 2 x L2 x DUTY2 where: fZ2(RHP) is the right half plane zero frequency. RLOAD2 is the equivalent load resistance or the output voltage divided by the load current. VFB2 VIN x x g M2 x |VNEG | (VIN + 2 x | VNEG|) 1 RC2 x g CS 2 x = 1 2 x fC2 x COUT2 where fC2 is the crossover frequency. To solve for RC2, use the following equation: RC2 = | VNEG | + VDIODE2 DUTY2 = V + |V | + V NEG DIODE2 IN where VDIODE2 is the forward voltage drop of the Schottky diode (D2). To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-tenth of the right half plane zero frequency. The inverting regulator loop gain is AVL2= AVL2= 2 VFB2 VIN x x g M2 x | VNEG | (VIN + 2 x | VNEG|) 2 x fC2 x COUT2 x | VNEG | x(VIN + (2 x | VNEG|) VFB2 x VIN x g M2 x g CS2 where GCS2 = 6.25 A/V. Using typical values for VFB2 and GM2 results in RC2 = 4188 x fC2 x COUT 2 x | VNEG| x (VIN + (2 x | VNEG|) VIN For improved accuracy, it is recommended to use the value of the output capacitance, COUT2, expected for the dc bias conditions under which it operates in the calculation for RC2. After the compensation resistor is known, set the zero formed by the compensation capacitor and resistor, CC2 and RC2, to onefourth of the crossover frequency, or ROUT2 ||Z COMP2 x g CS2 x ZOUT2 where: AVL2 is the loop gain. VFB2 is the feedback regulation voltage. VNEG is the regulated negative output voltage. VIN is the input voltage. gM2 is the error amplifier transconductance gain. ROUT2 is the output impedance of the error amplifier and is 33 M. ZCOMP2 is the impedance of the series RC network from COMP2 to AGND. gCS2 is the current sense transconductance gain (the inductor current divided by the voltage at COMP2), which is internally set by the ADP5072 and is 6.25 A/V. ZOUT2 is the impedance of the load in parallel with the output capacitor. CC2 = 2 x fC2 x RC2 where CC2 is the compensation capacitor. Rev. 0 | Page 20 of 24 FB2 ERROR AMPLIFIER COMP2 gM2 REF2 RC2 CC2 16646-043 f Z2 (RHP) = To determine the crossover frequency, it is important to note that, at that frequency, the compensation impedance (ZCOMP2) is dominated by a resistor, RC2, and the output impedance (ZOUT2) is dominated by the impedance of the output capacitor, COUT2. Therefore, when solving for the crossover frequency, the equation (by definition of the crossover frequency) is simplified to Figure 45. Compensation Component Data Sheet ADP5072 COMMON APPLICATIONS L1 3.3H D1 PD3S140 SW1 EN1 SW1 RFT1 2.43M FB1 VIN +5V CIN 10F ON OFF RFB1 137k PVIN PVIN AVIN PGND EN2 VREF PGND FB2 COMP2 VIN +5V SYNC SLEW SEQ D2 L2 PD3S140 6.8F 60 50 40 30 10 0 0.001 0.01 0.1 LOAD CURRENT (A) 1 Figure 47. Efficiency vs. Load Current for Boost Regulator and Inverting Regulator, TA = 25C COUT2 10F RFT2 2.32M SW2 AGND 70 20 COUT1 10F CVREF 1F RFB2 118k RC2 61.9k CC2 2.2nF VPOS +15V VNEG -15V 16646-044 ON OFF 80 VPOS = +15V, 1.2MHz VNEG = -15V, 1.2MHz VPOS = +15V, 2.4MHz VNEG = -15V, 2.4MHz 16646-047 SS COMP1 CC1 1nF 90 VIN +5V ADP5072 RC1 102k 100 EFFICIENCY (%) Table 9 through Table 11 list a number of common component selections for typical VIN, VPOS, and VNEG conditions. These components have been bench tested and are recommended for customer applications that are suited for these conditions. Note that when pairing a boost and inverting regulator bill of materials, choose the same VIN and switching frequency. Figure 47 shows the efficiency curves for the boost and inverting regulator using the recommended, small size components described in Table 9, Table 10, and Table 11 for VPOS = 15 V and VNEG = -15 V at VIN = 5 V. Figure 46. Typical +5 V to 15 V Application Figure 46 shows the schematic referenced by Table 9 through Table 11 with example component values for 5 V input voltage to 15 V output voltage generation. Table 9 shows the components common to all of the VIN, VPOS, and VNEG conditions. Table 10 and Table 11 are based on the smallest sized components. The maximum output current is limited by the ISAT rating of the 2 mm x 2 mm inductor. A higher output current is possible by using larger inductors with higher ISAT ratings, as long as the inductor peak current remains below the appropriate current limit specifications. It is important to verify the thermal performance of the small sized inductor at higher ambient temperature in actual application. Table 9. Recommended Common Components Selections Reference Designator CIN CVREF Description Input capacitor on PVIN VREF capacitor Value (F) 10 1 Rev. 0 | Page 21 of 24 Part Number GRM21BZ71C106KE15L GRM188R71C105KA12C Manufacturer Murata Murata ADP5072 Data Sheet Table 10. Recommended Boost Regulator Small Sized Components VIN (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 VPOS (V) 5 5 9 9 15 15 24 24 9 9 15 15 24 24 34 34 ILOAD1 (MAX) (mA) 340 360 180 200 100 110 50 55 140 280 110 170 50 80 40 45 Freq. (MHz) 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 L1 (H) 3.3 2.2 4.7 3.3 4.7 4.7 6.8 6.8 3.3 2.2 4.7 3.3 10 6.8 10 8.2 L1 Manufacturer Part No. (Coilcraft) EPL2014-332ML_ EPL2014-222ML_ EPL2014-472ML_ EPL2014-332ML_ EPL2014-472ML_ EPL2014-472ML_ EPL2014-682ML_ EPL2014-682ML_ EPL2014-332ML_ EPL2014-222ML_ EPL2014-472ML_ EPL2014-332ML_ EPL2014-103ML_ EPL2014-682ML_ EPL2014-103ML_ EPL2014-822ML_ COUT1 (F) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 COUT1, Murata Part No. GRM21BR71A106KA73L GRM21BR71A106KA73L GRM21BZ71C106KE15L GRM21BZ71C106KE15L GRM31CR71E106MA12L GRM31CR71E106MA12L GRM32ER7YA106MA12L GRM32ER7YA106MA12L GRM21BZ71C106KE15L GRM21BZ71C106KE15L GRM31CR71E106MA12L GRM31CR71E106MA12L GRM32ER7YA106MA12L GRM32ER7YA106MA12L GRM32ER71H106KA12L GRM32ER71H106KA12L D1 PMEG2005AELD PMEG2005AELD PMEG2005AELD PMEG2005AELD PD3S140 PD3S140 PD3S140 PD3S140 PMEG2005AELD PMEG2005AELD PD3S140 PD3S140 PD3S140 PD3S140 PD3S140 PD3S140 RFT1 (M) 0.604 0.604 1.24 1.24 2.43 2.43 3.09 3.09 1.24 1.24 2.43 2.43 3.09 3.09 4.22 4.22 RFB1 (k) 115 115 121 121 137 137 107 107 121 121 137 137 107 107 102 102 CC1 (nF) 0.82 0.47 1.2 0.82 1.5 1.2 1.8 1.8 0.56 0.39 1 0.56 1.8 1.2 1.5 1.2 RC1 (k) 15.8 29.4 26.1 17.4 14.3 16.9 28.7 16.2 16.9 18.7 18.2 20.5 15.8 10 25.5 18.2 D2 PMEG2005AELD PMEG2005AELD PMEG2005AELD PMEG2005AELD PD3S140 PD3S140 PD3S140 PD3S140 PMEG2005AELD PMEG2005AELD PD3S140 PD3S140 PD3S140 PD3S140 PD3S140 PD3S140 RFT2 (M) 1.15 1.15 1.62 1.62 2.32 2.32 3.16 3.16 1.62 1.62 2.32 2.32 3.16 3.16 4.99 4.99 RFB2 (k) 158 158 133 133 118 118 102 102 133 133 118 118 102 102 75 75 CC2 (nF) 8.2 3.3 3.9 1.8 3.3 2.2 3.3 1.5 5.6 2.2 4.7 1.8 4.7 2.2 3.9 1.2 RC2 (k) 7.5 10.5 8.06 8.06 10.5 8.25 10.5 14.3 4.87 10 10 13.3 10 7.15 15.8 1.2 Table 11. Recommended Inverting Regulator Small Sized Components VIN (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 VNEG (V) -5 -5 -9 -9 -15 -15 -24 -24 -9 -9 -15 -15 -24 -24 -30 -30 ILOAD2 (MAX) (mA) 120 130 70 90 50 55 30 30 90 120 60 80 40 50 30 35 Freq. (MHz) 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 L2 (H) 6.8 4.7 4.7 4.7 8.2 6.8 10 6.8 8.2 6.8 8.2 8.2 10 10 10 8.2 L2 Manufacturer Part No. (Coilcraft) EPL2014-682ML_ EPL2014-472ML_ EPL2014-472ML_ EPL2014-472ML_ EPL2014-822ML_ EPL2014-682ML_ EPL2014-103ML_ EPL2014-682ML_ EPL2014-822ML_ EPL2014-682ML_ EPL3015-822ML_ EPL2014-822ML_ EPL3015-103ML_ EPL2014-103ML_ EPL3015-103ML_ EPL2014-822ML_ COUT2 (F) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 COUT2, Murata Part No. GRM21BR71A106KA73L GRM21BR71A106KA73L GRM21BZ71C106KE15L GRM21BZ71C106KE15L GRM31CR71E106MA12L GRM31CR71E106MA12L GRM32ER7YA106MA12L GRM32ER7YA106MA12L GRM21BZ71C106KE15L GRM21BZ71C106KE15L GRM31CR71E106MA12L GRM31CR71E106MA12L GRM32ER7YA106MA12L GRM32ER7YA106MA12L GRM32ER71H106KA12L GRM32ER71H106KA12L Rev. 0 | Page 22 of 24 Data Sheet ADP5072 LAYOUT CONSIDERATIONS * * * * * * * Keep the input bypass capacitor, CIN, close to the PVIN pin and the AVIN pin. Keep the high current paths as short as possible. These paths include the connections between the following: * CIN, L1, D1, COUT1, and PGND for the boost regulator, the connections * L2, D2, COUT2, and PGND for the inverting regulator * The connections of these components for both the boost and inverting regulators to the ADP5072. Keep AGND and PGND separate on the top layer of the board. This separation avoids pollution of AGND with switching noise. Connect both AGND and PGND to the board ground plane with vias. Ideally, connect PGND to the plane at a point between the input and output capacitors. Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and EMI. Avoid routing high impedance traces near any node connected to the SW1 and SW2 pins or near Inductors L1and L2 to prevent radiated switching noise injection. Place the feedback resistors as close to the FB1 and FB2 pins as possible to prevent high frequency switching noise injection. Place the top of the upper feedback resistors, RFT1 and RFT2, as close as possible to the top of COUT1 and COUT2 for * * 16646-045 Layout is important for all switching regulators but is particularly important for regulators with high switching frequencies. To achieve high efficiency, proper regulation, stability, and low noise, a well designed PCB layout is required. Follow these guidelines when designing PCBs (see Figure 48): optimum output voltage sensing, or route traces to the RFT1 and RFT2 resistors as close as possible from the top of COUT1 and COUT2. Place the compensation components as close as possible to COMP1 and COMP2. Do not share vias to the ground plane with the feedback resistors to avoid coupling high frequency noise into the sensitive COMP1 and COMP2 pins. Place the CVREF capacitor as close to the VREF pin as possible. Ensure that short traces are used between VREF and RFB2. Figure 48. Suggested Layout for VIN = 3.3 V, VPOS = 12 V, ILOAD1 = 100 mA and VNEG = -3.2 V, ILOAD2 = 60 mA; Not to Scale Rev. 0 | Page 23 of 24 ADP5072 Data Sheet OUTLINE DIMENSIONS 1.650 1.610 1.570 0.310 0.290 0.270 3 4 2 1 A BALL A1 IDENTIFIER B 2.220 2.180 2.140 1.60 REF C 0.40 BSC D E TOP VIEW 0.225 0.205 0.185 (BALL SIDE DOWN) 0.560 0.500 0.440 SIDE VIEW 0.330 0.300 0.270 BOTTOM VIEW (BALL SIDE UP) 1.20 REF PKG-003773 SEATING PLANE 0.300 0.260 0.220 0.230 0.200 0.170 11-07-2017-A COPLANARITY 0.04 Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-14) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5072ACBZ-R7 ADP5072CB-EVALZ 1 Temperature Range -40C to +125C Package Description 20-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16646-0-1/19(0) Rev. 0 | Page 24 of 24 Package Option CB-20-14