1 A/0.6 A DC to DC Switching Regulator with
Independent Positive and Negative Outputs
Data Sheet
ADP5072
Rev. 0 Document Feedback
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FEATURES
Input supply voltage range: 2.85 V to 5.5 V
Generates well regulated, independently resistor
programmable VPOS and VNEG outputs
Boost regulator to generate VPOS output
Adjustable positive output to 35 V
Integrated 1.0 A main switch
Inverting regulator to generate VNEG output
Adjustable negative output to −30 V
Integrated 0.6 A main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Individual precision enable and flexible start-up sequence
control for symmetric start, VPOS first, or VNEG first
Out of phase operation
UVLO, OCP, OVP, and TSD protection
1.61 mm × 2.18 mm, 20-ball WLCSP
−40°C to +125°C junction temperature range
APPLICATIONS
Bipolar amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and multiplexers
Charge coupled device (CCD) bias supplies
Optical module supplies
RF power amplifier bias
Time of flight module supplies
TYPICAL APPLICATION CIRCUIT
ADP5072
SS
SW1
SW1
RC1
CC1 COMP1
RC2
CC2 COMP2
EN1
SYNC
SLEW
SEQ
EN2
AGND
PVIN
PVIN
AVIN
CIN
VIN
FB1
D1
L1
L2
VIN
RFB1
RFT1
VPOS
SW2
PGND
PGND
FB2
VREF
D2
RFB2
RFT2
VNEG
CVREF
COUT1
COUT2
12069-001
Figure 1.
GENERAL DESCRIPTION
The ADP5072 is a dual, high performance dc-to-dc regulator that
generates independently regulated positive and negative rails.
The input voltage range of 2.85 V to 5.5 V supports a wide
variety of applications. The integrated main switch in both
regulators enables generation of an adjustable positive output
voltage up to 35 V and a negative output voltage down to −30 V.
The ADP5072 operates at a pin selected 1.2 MHz or 2.4 MHz
switching frequency. The ADP5072 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering
in sensitive applications. Both regulators implement programma-
ble slew rate control circuitry for the MOSFET driver stage to
reduce electromagnetic interference (EMI). Flexible start-up
sequencing is provided with the options of manual enable,
simultaneous mode, positive supply first, and negative supply first.
The ADP5072 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up.
Other key safety features in the ADP5072 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5072 is available in a 20-ball WLCSP and is rated for a
−40°C to +125°C junction temperature range.
Table 1. Family Models
Model
Boost
Switch (A)
Inverter
Switch (A) Package
ADP5070 1.0 0.6 20-lead LFCSP (4 mm× 4 mm) and
20-lead TSSOP
ADP5071 2.0 1.2 20-lead LFCSP (4 mm × 4 mm) and
20-lead TSSOP
ADP5072 1.0 0.6 20-ball WLCSP (1.61 mm × 2.18 mm)
ADP5073 N/A 1.2 16-lead LFCSP (3 mm × 3 mm)
ADP5074 N/A 2.4 16-lead LFCSP (3 mm × 3 mm)
ADP5075 N/A 0.8 12-ball WLCSP (1.61 mm × 2.18 mm)
ADP5072 Data Sheet
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
PWM Mode ................................................................................. 13
PSM Mode ................................................................................... 13
Undervoltage Lockout (UVLO) ............................................... 13
Oscillator and Synchronization ................................................ 13
Internal Regulator....................................................................... 13
Precision Enabling...................................................................... 14
Soft Start ...................................................................................... 14
Slew Rate Control ....................................................................... 14
Current-Limit Protection ............................................................ 14
Overvoltage Protection .............................................................. 14
Thermal Shutdown .................................................................... 14
Start-Up Sequence ...................................................................... 14
Applications Information .............................................................. 16
Component Selection ................................................................ 16
Output Capacitors ...................................................................... 17
Loop Compensation .................................................................. 19
Common Applications .............................................................. 21
Layout Considerations ............................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
1/2019—Revision 0: Initial Version
Data Sheet ADP5072
Rev. 0 | Page 3 of 24
SPECIFICATIONS
PVIN = AVIN = 2.85 V to 5.5 V, positive output voltage (VPOS) = 15 V, negative output voltage (VNEG) = −15 V, fSW = 1200 kHz, TJ = −40°C
to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
V
IN
2.85
5.5
V
PVIN, AVIN
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total) IQ 3.5 4.0 mA No switching, EN1 = EN2 =
high, PVIN = AVIN = 5 V
Standby Current ISTNDBY 2.05 2.2 mA No switching, EN1 = EN2 =
low, PVIN = AVIN = 5 V
UVLO
System UVLO Threshold AVIN
Rising VUVLO_RISING 2.8 2.85 V
Falling VUVLO_FALLING 2.5 2.55 V
Hysteresis VHYS 0.25 V
OSCILLATOR CIRCUIT
Switching Frequency fSW 1.130 1.2 1.270 MHz SYNC = low
2.240
2.4
2.560
MHz
SYNC = high (connect to
PVIN)
SYNC Input
Input Clock Range fSYNC 1.0 2.6 MHz
Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns
Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns
Input Clock High Logic VH (SYNC) 1.3 V
Input Clock Low Logic VL (SYNC) 0.4 V
PRECISION ENABLING (EN1, EN2)
High Level Threshold VTH_H 1.125 1.15 1.175 V
Low Level Threshold VTH_L 1.025 1.05 1.075 V
Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to
achieve ISTNDBY
Pull-Down Resistance REN 1.48 MΩ
BOOST REGULATOR
Adjustable Positive Output Voltage VPOS 35 V
Feedback Voltage VFB1 0.8 V
Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C
−1.5 +1.5 % TJ = −40°C to +125°C
Feedback Bias Current IFB1 0.1 µA
Overvoltage Protection Threshold VOV1 0.86 V At FB1 pin
Load Regulation
(∆V
FB1
/V
FB1
)/ΔI
LOAD1
0.0003
%/mA
I
LOAD11
= 5 mA to 150 mA
Line Regulation
(∆V
FB1
/V
FB1)
/ΔV
PVIN
0.002
%/V
V
PVIN
= 2.85 V to 5.5 V, I
LOAD1
=
50 mA
Error Amplifier (EA) Transconductance gM1 260 300 340 µA/V
Power FET On Resistance RDS (ON) BOOST 175 mΩ
Power FET Maximum Drain Source
Voltage
VDS (MAX) BOOST 39 V
Current-Limit Threshold, Main Switch ILIM (BOOST) 1.0 1.1 1.3 A
Minimum On Time 50 ns
Minimum Off Time 25 ns
ADP5072 Data Sheet
Rev. 0 | Page 4 of 24
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INVERTING REGULATOR
Adjustable Negative Output Voltage VNEG −30 V
Reference Voltage VREF 1.60 V
Reference Voltage Accuracy −0.5 +0.5 % TJ = 25°C
−1.5
+1.5
%
T
J
= −40°C to +125°C
Feedback Voltage VREF − VFB2 0.8 V
Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C
−1.5 +1.5 % TJ = −40°C to +125°C
Feedback Bias Current IFB2 0.1 µA
Overvoltage Protection Threshold VOV2 0.74 V At FB2 pin after soft start
has completed
Load Regulation (∆(VREF − VFB2)/(VREF − VFB2))/
ILOAD2
0.0004 %/mA ILOAD2 = 5 mA to 75 mA
Line Regulation (∆(VREF − VFB2)/(VREF − VFB2))/
VPVIN
0.003 %/V VPVIN = 2.85 V to 5.5 V, ILOAD2 =
25 mA
EA Transconductance gM2 260 300 340 µA/V
Power FET On Resistance RDS (ON) INVERTER 350 mΩ
Power FET Maximum Drain Source
Voltage
VDS (MAX) INVERTER 39 V
Current-Limit Threshold, Main Switch ILIM (INVERTER) 600 660 750 mA
Minimum On Time 60 ns
Minimum Off Time 50 ns
SOFT START
Soft Start Timer for DC to DC Regulators tSS 4 ms SS = open
32
ms
SS resistor = 50 kΩ to GND
Hiccup Time tHICCUP 8 × tSS ms
THERMAL SHUTDOWN
Threshold TSHDN 150 °C
Hysteresis THYS 15 °C
1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Data Sheet ADP5072
Rev. 0 | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
PVIN, AVIN −0.3 V to +6V
SW1
−0.3 V to +40 V
SW2 PVIN − 40 V to PVIN + 0.3 V
PGND, AGND −0.3 V to +0.3 V
EN1, EN2, FB1, FB2, SYNC, −0.3 V to +6 V
COMP1, COMP2, SLEW, SS,
SEQ, VREF
−0.3 V to AVIN + 0.3 V
Operating Junction
Temperature Range
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance. ψJT is the junction to
case thermal characterization parameter.
Table 4. Thermal Resistance
Package Type θJA θJC ΨJT Unit
CB-20-141, 2 50 0.54 0.13 C/W
1 θJA and ΨJT are based on a 4-layer printed circuit board (PCB) (two signal and
two power planes) with nine thermal vias connecting the exposed pad to the
ground plane as recommended in the Layout Considerations section. θJC is
measured at the top of the package and is independent of the PCB. The ΨJT
value is more appropriate for calculating junction to case temperature in the
application.
2 The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
compliance with JESD51-12.
ESD CAUTION
ADP5072 Data Sheet
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12069-002
A
B
C
D
E
PVIN
AVIN
EN2
AGND
COMP2
SW2
PVIN
SYNC
SLEW
FB2
SW1
SW1
SEQ
SS
VREF
PGND
PGND
EN1
FB1
COMP1
1234
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
A1, B2 PVIN Power Input for the Boost Regulator.
A2 SW2 Switching Node for the Inverting Regulator.
A3, B3 SW1 Switching Node for the Boost Regulator.
A4, B4 PGND Power Ground for the Boost Regulator.
B1 AVIN System Power Supply for the ADP5072.
C1 EN2 Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable
the inverting regulator output.
C2 SYNC Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC pin high.
To set the switching frequency to 1.2 MHz, pull the SYNC pin low. To synchronize the switching frequency,
connect the SYNC pin to an external clock.
C3 SEQ Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, ENx,
leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to
PVIN (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the
SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence. Hold the
other enable pin low.
C4 EN1 Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the
boost regulator output.
D1 AGND Analog Ground.
D2 SLEW Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest
slew rate (optimal efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to PVIN.
For the slowest slew rate (optimal noise performance), connect the SLEW pin to AGND.
D3 SS Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft
start time, connect a resistor between the SS pin and AGND.
D4 FB1 Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost
regulator output capacitor and AGND to program the output voltage.
E1
COMP2
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this
pin and AGND.
E2 FB2 Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the
inverting regulator output capacitor and VREF to program the output voltage.
E3 VREF Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND.
E4 COMP1 Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin
and AGND.
Data Sheet ADP5072
Rev. 0 | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
700
0040
I
OUT
(MAX) (mA)
V
POS
(V)
100
200
300
400
500
600
510 15 20 25 30 35
V
IN
= 3.3V , L = 6.8µH
V
IN
= 3.3V , L = 4.7µH
V
IN
= 5.0V , L = 10.0µH
V
IN
= 5.0V , L = 6.8µH
16646-003
Figure 3. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator,
fSW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
700
0040
I
OUT
(MAX) (mA)
V
POS
(V)
100
200
300
400
500
600
510 15 20 25 30 35
V
IN
= 3.3V , L = 6.8µH
V
IN
= 3.3V , L = 3.3µH
V
IN
= 5.0V , L = 10.0µH
V
IN
= 5.0V , L = 3.3µH
16646-004
Figure 4. Maximum Output Current (IOUT) vs. VPOS for Boost Regulator,
fSW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
V
IN
= 3.3V ,
f
SW
= 1.2M Hz
V
IN
= 3.3V ,
f
SW
= 2.4M Hz
16646-005
Figure 5. Efficiency vs. Load Current for Boost Regulator, VIN = 3.3 V,
VPOS = 5 V, TA = 25°C
350
0
–35 –30 –25 –20 –15 –10 –5 0
VNEG (V)
IOUT (MAX) (mA)
VIN = 3.3V, L = 10.0µ H
VIN = 3.3V, L = 6. 8µ H
VIN = 5.0V, L = 10.0µ H
VIN = 5.0V, L = 15.0µ H
50
100
150
200
250
300
16646-006
Figure 6. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator,
fSW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER)
350
0
–35 –30 –25 –20 –15 –10 –5 0
VNEG (V)
IOUT (MAX) (mA)
VIN = 3.3V, L = 10.0µ H
VIN = 3.3V, L = 6. 8µ H
VIN = 5.0V, L = 10.0µ H
VIN = 5.0V, L = 15.0µ H
50
100
150
200
250
300
16646-007
Figure 7. Maximum Output Current (IOUT) vs. VNEG for Inverting Regulator,
fSW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER)
0.001 1.0
LO AD CURRE NT (A)
EF FICIE NCY ( %)
0.01 0.1
90
0
10
20
30
40
50
60
70
80
V
IN
= 3.3V ,
f
SW
= 1.2M Hz
V
IN
= 3.3V ,
f
SW
= 2.4M Hz
16646-008
Figure 8. Efficiency vs. Load Current for Inverting Regulator, VIN = 3.3 V,
VNEG = −5 V, TA = 25°C
ADP5072 Data Sheet
Rev. 0 | Page 8 of 24
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
V
IN
= 3.3V ,
fSW
= 1.2M Hz
V
IN
= 3.3V ,
fSW
= 2.4M Hz
V
IN
= 5.0V ,
fSW
= 1.2M Hz
V
IN
= 5.0V ,
fSW
= 2.4M Hz
16646-009
Figure 9. Efficiency vs. Load Current for Boost Regulator, VPOS = 9 V, TA = 25°C
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
V
IN
= 3.3V ,
fSW
= 1.2M Hz
V
IN
= 3.3V ,
fSW
= 2.4M Hz
V
IN
= 5.0V ,
fSW
= 1.2M Hz
V
IN
= 5.0V ,
fSW
= 2.4M Hz
16646-010
Figure 10. Efficiency vs. Load Current for Boost Regulator, VPOS = 15 V,
TA = 25°C
16646-211
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1
EFFICIENCY (%)
LO AD CURRE NT (A)
V
IN
= 3.3V,
f
SW
= 1.2M Hz
V
IN
= 5V,
f
SW
= 1.2M Hz
V
IN
= 5V,
f
SW
= 2.4M Hz
Figure 11. Efficiency vs. Load Current for Boost Regulator, VPOS = 35 V,
TA = 25°C
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
V
IN
= 3.3V ,
fSW
= 1.2M Hz
V
IN
= 3.3V ,
fSW
= 2.4M Hz
V
IN
= 5.0V ,
fSW
= 1.2M Hz
V
IN
= 5.0V ,
fSW
= 2.4M Hz
16646-012
Figure 12. Efficiency vs. Load Current for Inverting Regulator, VNEG = −9 V,
TA = 25°C
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
V
IN
= 3.3V ,
fSW
= 1.2M Hz
V
IN
= 3.3V ,
fSW
= 2.4M Hz
V
IN
= 5.0V ,
fSW
= 1.2M Hz
V
IN
= 5.0V ,
fSW
= 2.4M Hz
16646-013
Figure 13. Efficiency vs. Load Current for Inverting Regulator, VNEG = −15 V,
TA = 25°C
16646-214
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1
EFFICIENCY (%)
LO AD CURRE NT (A)
V
IN
= 3.3V,
f
SW
= 1.2M Hz
V
IN
= 5V,
f
SW
= 1.2M Hz
V
IN
= 5V,
f
SW
= 2.4M Hz
Figure 14. Efficiency vs. Load Current for Inverting Regulator, VNEG = −30 V,
TA = 25°C
Data Sheet ADP5072
Rev. 0 | Page 9 of 24
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
T
A
= +125°C
T
A
= +25°C
T
A
= –40°C
16646-011
Figure 15. Efficiency vs. Load Current for Boost Regulator over Temperature,
VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz
0.5
–0.52.5 6.0
VARIATIO N FROM NOMINAL (%)
VIN (V)
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
3.0 3.5 4.0 4.5 5.0 5.5
VPOS ACCURACY
VFB1 ACCURACY
16646-015
Figure 16. Boost Regulator Line Regulation, VPOS = 15 V,
fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5
–0.5 00.25
VARIATION IN NOMINAL OUTPUT VOLTAGE (%)
LO AD CURRE NT (A)
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.05 0.10 0.15 0.20
1.2MHz
2.4MHz
16646-016
Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V
0.001 1.0
LO AD CURRE NT (A)
100
0
EF FICIE NCY ( %)
10
20
30
40
50
60
70
80
90
0.01 0.1
16646-014
T
A
= +125°C
T
A
= +25°C
T
A
= –40°C
Figure 18. Efficiency vs. Load Current for Inverting Regulator over
Temperature, VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5
–0.52.5 6.0
VARIATIO N FROM NOMINAL (%)
VIN (V)
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
3.0 3.5 4.0 4.5 5.0 5.5
VNEG ACCURACY
VREF ACCURACY
VFB2 ACCURACY
16646-018
Figure 19. Inverting Regulator Line Regulation, VNEG = −15 V,
fSW = 1.2 MHz, 15 mA Load, TA = 25°C
–0.5
–0.4
–0.3
–0.2
0
–0.1
0.2
0.3
0.4
0.5
0.1
VARIATION IN NOMINAL OUTPUT VOLTAGE (%)
LO AD CURRE NT (A)
00.02 0.04 0.06 0.08 0.10 0.12
1.2MHz
2.4MHz
16646-220
Figure 20. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V
ADP5072 Data Sheet
Rev. 0 | Page 10 of 24
0.2
0.1
0
–0.1
–0.2 00.12
VFB1 DEVI ATIO N FROM AV E RAGE VAL UE ( %)
INVE RTING RE GULAT OR LO AD ( A)
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
0.11
16646-017
Figure 21. Cross Regulation, Boost Regulator VFB1 Regulation, VIN = 5 V,
VPOS = 15 V, VNEG = −15 V, fSW = 2.4 MHz, TA = 25°C, Boost Regulator Run in
Continuous Conduction Mode with Fixed Load for Test
1.30
1.002.5 5.5
BOOST REGULATOR CURRENT LIMIT (A)
VIN (V)
3.0 3.5 4.0 4.5 5.0
16646-021
TA = +125°C
TA = +25°C
TA = –40°C
1.05
1.10
1.15
1.20
1.25
Figure 22. Boost Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN)
over Temperature
2.54
2.242.5 5.5
OSCILL ATOR F RE QUENCY (M Hz )
VIN (V)
2.29
2.34
2.39
2.44
2.49
3.0 3.5 4.0 4.5 5.0
16646-022
TA = +125°C
TA = +25°C
TA = –40°C
Figure 23. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC Pin = High
0.2
0.1
0
–0.1
–0.2 00.12
VFB2 DEV IATI ON FRO M AV E RAGE VAL UE ( %)
BOOST REGULATOR LOAD (A)
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11
16646-020
Figure 24. Cross Regulation, Inverting Regulator VFB2 Regulation,
VIN = 5 V, VPOS = 15 V, VNEG = −15 V, fSW = 2.4 MHz, TA = 25°C, Inverting
Regulator Run in Continuous Conduction Mode with Fixed Load for Test
0.75
0.602.5 5.5
INVE RTING RE GULAT OR CURRENT LIMIT (A)
VIN (V)
0.63
0.66
0.69
0.72
3.0 3.5 4.0 4.5 5.0
16646-024
TA = +125°C
TA = +25°C
TA = –40°C
Figure 25. Inverting Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN)
over Temperature
1.27
1.132.5 5.5
OSCILL ATOR F RE QUENCY (M Hz )
V
IN
(V)
1.15
1.17
1.19
1.21
1.23
1.25
3.0 3.5 4.0 4.5 5.0
16646-025
T
A
= +125°C
T
A
= +25°C
T
A
= –40°C
Figure 26. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC Pin = Low
Data Sheet ADP5072
Rev. 0 | Page 11 of 24
3.0
0.52.7 5.7
ST ANDBY CURRE NT (mA)
V
IN
(V)
1.0
1.5
2.0
2.5
3.2 3.7 4.2 4.7 5.2
16646-023
T
A
= +125°C
T
A
= +25°C
T
A
= –40°C
Figure 27. Standby Current vs. Input Voltage (VIN) over Temperature, Both
ENx Pins Below Shutdown Threshold
3
CH1 1.00V M1.00ms A CH1 4.96V
T 1.906000ms
BW
CH3 10.0mV CH2 50.0mV
BW
BW
1
2
16646-128
VFB1
VPOS
VIN
Figure 28. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VPOS = 15 V,
RLOAD1 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
CH1 50.0mV M100µs A CH4 140mA
3
4
T 20.30%
BW
CH3 10.0mV CH4 50.0mA
BWBW
V
FB1
V
POS
I
LOAD1
1
16646-129
Figure 29. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V,
ILOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25°C
3.8
2.4
OPE RATING QUIES CE NT CURRENT ( mA)
2.6
2.8
3.0
3.2
3.4
3.6
2.7 5.7
V
IN
(V)
3.2 3.7 4.2 4.7 5.2
16646-026
T
A
= +125°C
T
A
= +25°C
T
A
= –40°C
Figure 30. Operating Quiescent Current vs. Input Voltage (VIN) over
Temperature, Both ENx Pins On
CH1 1.00V M2.00ms A CH1 5.16V
T 5.772000ms
BW
CH3 20.0mV CH2 200mV
BW
BW
16646-131
VNEG
VFB2
1
2
3
VIN
Figure 31. Inverting Regulator Line Transient, VIN = 4.5 V to 5.5 V Step,
VNEG = −15 V, RLOAD2 = 300 Ω, fSW = 2.4 MHz, TA = 25°
CH1 100mV M1.00ms A CH4 48.0mA
1
3
4
T 20.30%
BW
CH3 10.0mV CH4 20.0mA
BWBW
V
FB2
V
NEG
I
LOAD2
16646-132
Figure 32. Inverting Regulator Load Transient, VIN = 5 V Step, VNEG = −15 V,
ILOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25°C
ADP5072 Data Sheet
Rev. 0 | Page 12 of 24
CH1 500mV M2.00µs A CH3 82.0mA
3
2
1
T 7.960000µ s
BW
CH2 10.0V CH3 100mA
BWBW
V
POS
SW1
I
INDUCTOR
16646-133
Figure 33. Boost Regulator Skip Mode Operation Showing Inductor Current
(IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 12 V, VPOS = 15 V,
ILOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25°C
CH1 500mV M200ns A CH3 100mA
3
2
1
T 7.960000µ s
BW
CH2 10.0V CH3 200mA
BWBW
VPOS
SW1
IINDUCTOR
16646-134
Figure 34. Boost Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 6 mA, fSW = 2.4 MHz, TA = 25°C
CH1 500mV M200ns A CH4 310mA
3
2
1
T 7.960000µ s
BW
CH2 10.0V CH3 500mA
BWBW
V
POS
SW1
I
INDUCTOR
16646-137
Figure 35. Boost Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25°C
T 12.00000µ s
CH1 5.00V M4.00µs A CH3 35. 0mA
3
1
2
BW
CH2 500mV CH3 50.0mA
BWBW
VNEG
SW2
IINDUCTOR
16646-135
Figure 36. Inverting Regulator Skip Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
VNEG = −5 V, ILOAD2 = 0 mA, fSW = 2.4 MHz, TA = 25°C
BW
CH1 5.00V M200ns A CH3 42.0mA
3
2
1
T 24.46000µ s
BW
CH2 500mV CH3 50mA
BW
VNEG
SW2
IINDUCTOR
16646-136
Figure 37. Inverting Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25°C
BW
CH1 5.00V M100ns A CH3 84.0mA
3
2
1
T 24.46000µ s
BW
CH2 500mV CH3 50mA
BW
V
NEG
SW2
I
INDUCTOR
16646-138
Figure 38. Inverting Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Data Sheet ADP5072
Rev. 0 | Page 13 of 24
THEORY OF OPERATION
ERROR
AMP
+
–
BOOST PWM
CONTROL
SW1
V
POS
FB1
COMP1
V
IN
C
IN
CURRENT
SENSE
SYNC
PGND
SW2
FB2
INVERTER
PWM CONTRO L
PVIN
+
–
ERROR
AMP
EN1 EN2
AVIN
COMP2
SEQ
SLEW SS
AGND
CURRENT S E NS E
START-UP
TIMERS
PLL
REFERENCES
4µA REF1
REF2
REF1
REF2
SEQUENCE
CONTROL
OSCILLATOR
SLEW
SLEW
1.5MΩ
BOOST_ENABLE
INVERTER_ENABLE
L1
D1
C
OUT1
R
FT1
R
FB1
R
FT2
R
FB2
L2
D2
C
OUT2
V
NEG
R
C1
C
C1
R
C2
C
C2
R
SS
(OPTIONAL)
THERMAL
SHUTDOWN
UVLO
VREF
OVP
FB1
FB2
REFERENCE
GENERATOR REF_1V6
REF_1V6
C
VREF
SLEW
TRI-STATE
BUFFER
1.5MΩ
16646-037
Figure 39. Functional Block Diagram
PWM MODE
The boost and inverting regulators in the ADP5072 operate at a
fixed frequency set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch turns on, applying a positive
voltage across the inductor. The inductor current increases until
the current sense signal crosses the peak inductor current threshold
that turns off the MOSFET switch; this threshold is set by the error
amplifier output. During the MOSFET off time, the inductor
current declines through the external diode until the next
oscillator clock pulse starts a new cycle. It regulates the output
voltage by adjusting the peak inductor current threshold.
PSM MODE
During light load operation, the regulators can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout circuitry monitors the AVIN pin
voltage level. If the input voltage drops below the VUVLO_FALLING
threshold, both regulators turn off. After the AVIN pin voltage
rises above the VUVLO_RISING threshold, the soft start period initiates,
and the regulators are enabled.
OSCILLATOR AND SYNCHRONIZATION
The ADP5072 initiates the drive of the boost regulator SW1 pin
and the inverting regulator SW2 pin 180° out of phase to reduce
peak current consumption and noise.
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC pin options shown in Table 6.
For external synchronization, connect the SYNC pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC.
Table 6. SYNC Pin Options
SYNC Pin Switching Frequency
High 2.4 MHz
Low 1.2 MHz
External Clock 1 × clock frequency
INTERNAL REGULATOR
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage on
the FB2 pin.
A current-limit circuit is included for the VREF regulator to protect
the circuit from accidental loading.
ADP5072 Data Sheet
Rev. 0 | Page 14 of 24
PRECISION ENABLING
TheADP5072 has an individual enable pin for the boost and
inverting regulators: EN1 and EN2. The enable pins feature a
precision enable circuit with an accurate reference voltage. This
reference allows the ADP5072 to be sequenced easily from other
supplies. It can also be used as a programmable UVLO input by
using a resistor divider.
The enable pins have an internal pull-down resistor that defaults
each regulator to off when the pin is floating.
When the voltage at the enable pins is greater than the VTH_H
reference level, the regulator is enabled.
SOFT START
Each regulator in the ADP5072 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
Connecting a resistor between SS and AGND allows the adjust-
ment of the soft start delay. The delay length is common to both
regulators.
SLEW RATE CONTROL
The ADP5072 employs programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 40, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the PVIN pin for normal mode, to the AGND pin
for slow mode, or leave it open for fast mode. This configuration
allows the use of an open-drain output from a noise sensitive
device to switch the slew rate from fast to slow, for example,
during ADC sampling.
Note that slew rate control causes a trade-off between efficiency
and low EMI.
FASTEST
SLOWEST
16646-038
Figure 40. Switching Node at Various Slew Rate Settings
CURRENT-LIMIT PROTECTION
The boost and inverting regulators in the ADP5072 include
current-limit protection circuitry to limit the amount of forward
current through the MOSFET switch.
When the peak inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after tHICCUP and repeats until the overcurrent condition is
removed.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB1
and FB2 pins for the boost and inverting regulators.
On the boost regulator, when the voltage on the FB1 pin exceeds
the VOV1 threshold, the switching on SW1 stops until the voltage
falls below the threshold again. This functionality is permanently
enabled on this regulator.
On the inverting regulator, when the voltage on the FB2 pin
drops below the VOV2 threshold, the switching stops until the
voltage rises above the threshold. This functionality is enabled
after the soft start period has elapsed.
THERMAL SHUTDOWN
In the event that theADP5072 junction temperature rises above
TSHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient temper-
ature. Hysteresis is included so that when thermal shutdown occurs,
the ADP5072 does not return to operation until the on-chip
temperature drops below TSHDN minus THYS. When resuming from
thermal shutdown, a soft start is performed on each enabled
channel.
START-UP SEQUENCE
The ADP5072 implements a flexible start-up sequence to meet
different system requirements. Three different enabling modes
can be implemented via the SEQ pin, as explained in Table 7.
Table 7. SEQ Pin Settings
SEQ Pin Description
Open Manual enable mode
PVIN Simultaneous enable mode
Low Sequential enable mode
To configure the manual enable mode, leave the SEQ pin open.
The boost and inverting regulators are controlled separately from
their respective precision enable pins.
Data Sheet ADP5072
Rev. 0 | Page 15 of 24
To configure the simultaneous enable mode, connect the SEQ pin
to the PVIN pin. Both regulators power up simultaneously
when the EN2 pin is taken high. The EN1 pin enable can be
used to enable the internal references ahead of enabling the
outputs, if desired. The simultaneous enable mode timing is
shown in Figure 41.
VIN
VPOS
TIME
VNEG
SI M ULTANEOUS ENABL E M ODE
(SE Q = HIGH, EN2 = HIGH)
16646-039
Figure 41. Simultaneous Enable Mode
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the EN1 pin or EN2 pin. Keep the other pin low. The secondary
supply is enabled when the primary supply completes soft start and
its feedback voltage reaches approximately 85% of the target
value. The sequential enable mode timing is shown in Figure 42.
TIME
TIME
VPOS
VNEG
VPOS
VNEG
1. VPOS FOLLOWED BY VNEG
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
2. VNEG FOLLOWED BY VPOS
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
VIN
VIN
16646-040
Figure 42. Sequential Enable Mode
ADP5072 Data Sheet
Rev. 0 | Page 16 of 24
APPLICATIONS INFORMATION
COMPONENT SELECTION
Feedback Resistors
The ADP5072 provides an adjustable output voltage for both boost
and inverting regulators. An external resistor divider sets the output
voltage where the divider output must equal the appropriate
feedback reference voltage, VFB1 or VFB2. To limit the output voltage
accuracy degradation due to feedback bias current, ensure that the
current through the divider is at least 10 times IFB1 or IFB2.
Set the positive output for the boost regulator by
1
FT1
POS FB1
FB1
R
VV R
= ×+
where:
VPOS is the positive output voltage.
VFB1 is the FB1 reference voltage.
RFT1 is the feedback resistor from VPOS to FB1.
RFB1 is the feedback resistor from FB1 to AGND.
Set the negative output for the inverting regulator by
( )
FT2
NEG FB2 REF FB2
FB2
R
V V VV
R
=−−
where:
VNEG is the negative output voltage.
VFB2 is the FB2 reference voltage.
RFT2 is the feedback resistor from VNEG to FB2.
RFB2 is the feedback resistor from FB2 to VREF.
VREF is the VREF pin reference voltage.
Table 8. Recommended Feedback Resistor Values
Desired Output
Voltage (V)
Boost Regulator Inverting Regulator
RFT1 (MΩ) RFB1 (kΩ)
Calculated
Output Voltage (V) RFT2 (MΩ) RFB2 (kΩ)
Calculated
Output Voltage (V)
±4.2 0.432 102 4.188 0.715 115 −4.174
±5 0.604 115 5.002 1.15 158 −5.023
±9 1.24 121 8.998 1.62 133 −8.944
±12 1.4 100 12.000 1.15 71.5 −12.067
±13 2.1 137 13.063 2.8 162 −13.027
±15 2.43 137 14.990 2.32 118 −14.929
±18 2.15 100 18.000 2.67 113 −18.103
±20 2.55 107 19.865 2.94 113 −20.014
±24 3.09 107 23.903 3.16 102 −23.984
±30 3.65 100 30.000 4.12 107 −30.004
Data Sheet ADP5072
Rev. 0 | Page 17 of 24
OUTPUT CAPACITORS
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range and
dc bias conditions. X5R or X7R dielectrics with a voltage rating of
25 V or 50 V (depending on output) are recommended for optimal
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
Calculate the worst case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
where:
CEFFECTIVE is the effective capacitance at the operating voltage.
CNOMINAL is the nominal data sheet capacitance.
TEMPCO is the worst-case capacitor temperature coefficient.
DCBIASCO is the dc bias coefficient derating at the output
voltage.
To l e r an c e is the worst case component tolerance.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Note that the use of large output capacitors can require a slower
soft start to prevent reaching the current limit during startup. A
10 µF capacitor is suggested as a ideal balance between perfor-
mance and size.
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response.
To minimize supply noise, place the input capacitor as close as
possible to the AVIN pin and PVIN pin. A low ESR capacitor is
recommended.
The effective capacitance needed for stability is a minimum of 10 µF.
If the power pins are individually decoupled, it is recommended
to use a minimum of a 5.6 µF capacitor on the PVIN pin and a
3.3 µF capacitor on the AVIN pin to prevent reaching the current
limit. The minimum values specified exclude dc bias, temperature,
and tolerance effects that are application dependent and must be
taken into consideration.
VREF Capacitor
A 1.0 µF ceramic capacitor (CVREF) is required between the VREF
pin and AGND.
Soft Start Resistor
A resistor can be connected between the SS pin and the AGND pin
to increase the soft start time. The soft start time can be set by the
resistor between 4 ms (268 k) and 32 ms (50 k). Leaving the
SS pin open selects the fastest time of 4 ms. Figure 43 shows the
behavior of this operation. Calculate the soft start time using the
following formula:
tSS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (Ω)
where 50 kΩ ≤ RSS ≤ 268 kΩ.
SS PIN OPEN
SOFT START
TIMER
SOF T START
RESISTOR
R1R2
32ms
4ms
16646-041
Figure 43. Soft Start Behavior
Diodes
A Schottky diode with low junction capacitance is recommended
for D1 and D2, diodes for VPOS and VNEG, respectively. At higher
output voltages and especially at higher switching frequencies, the
junction capacitance is a significant contributor to efficiency.
Higher capacitance diodes also generate more switching noise. As a
guide, a diode with less than 40 pF junction capacitance is preferred
when the output voltage is greater than 5 V.
Inductor Selection for the Boost Regulator
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In general,
lower inductance values have higher saturation current and
lower series resistance for a given physical size. However, lower
inductance results in a higher peak current that can lead to reduced
efficiency and greater input and/or output ripple and noise. A
peak-to-peak inductor ripple current close to 30% of the maximum
dc input current for the application typically yields an optimal
compromise.
ADP5072 Data Sheet
Rev. 0 | Page 18 of 24
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VPOS) voltages
determine the switch duty cycle (DUTY1) by the following
equation:
DIODE1
POS IN
1POS DIODE1
V VV
DUTY VV
−+
=
+
where VDIODE1 is the forward voltage drop of the Schottky diode
(D1).
The dc input current in CCM (IIN) can be determined by the
following equation:
(1 )
OUT1
IN
1
I
IDUTY
=−
Using the duty cycle (DUTY1) and switching frequency (fSW),
determine the on time (tON1) using the following equation:
1
ON1
SW
DUTY
tf
=
The inductor ripple current (∆IL1) in steady state is calculated by
IN ON1
L1
Vt
IL1
×
∆=
Solve for the inductance value (L1) using the following equation:
IN ON1
L1
Vt
L1 I
×
=∆
Assuming an inductor ripple current of 30% of the maximum
dc input current results in
(1 )
0.3
1IN ON1
OUT1
V t DUTY
L1 I
× ×−
=×
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is less than the
rated saturation current of the inductor. Likewise, ensure that
the maximum rated rms current of the inductor is greater than
the maximum dc input current to the regulator.
When the ADP5072 boost regulator is operated in CCM at duty
cycles greater than 50%, slope compensation is required to stabilize
the current mode loop. This slope compensation is built in to
the ADP5072. For stable current mode operation, ensure that
the selected inductance is equal to or greater than the minimum
calculated inductance, LMIN1, for the application parameters in
the following equation:
0.13 0.16
(1 )
MIN1 IN
1
L1 L V DUTY
>=× −
−
(µH)
Table 10 suggests a series of inductors to use with the ADP5072
boost regulator.
Inductor Selection for the Inverting Regulator
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current close to 30% of
the maximum dc current in the inductor typically yields an
optimal compromise.
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VNEG) voltages
determine the switch duty cycle (DUTY2) by the following
equation:
||
||
DIODE2
NEG
2
DIODE2
IN NEG
VV
DUTY VV V
+
=
++
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
The dc current in the inductor in CCM (IL2) can be determined
by the following equation:
(1 )
OUT2
L2
2
I
IDUTY
=−
Using the duty cycle (DUTY2) and switching frequency (fSW),
determine the on time (tON2) by the following equation:
2
ON2
SW
DUTY
tf
=
The inductor ripple current (∆IL2) in steady state is calculated by
IN ON2
L2
Vt
IL2
×
∆=
Solve for the inductance value (L2) by the following equation:
IN ON2
L2
Vt
L2 I
×
=∆
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor results in
(1 )
0.3
IN ON2 2
OUT2
V t DUTY
L2 I
× ×−
=×
Ensure that the peak inductor current (the maximum input current
plus half the inductor ripple current) is less than the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
Data Sheet ADP5072
Rev. 0 | Page 19 of 24
When the ADP5072 inverting regulator is operated in CCM at
duty cycles greater than 50%, slope compensation is required to
stabilize the current mode loop. For stable current mode operation,
ensure that the selected inductance is equal to or greater than
the minimum calculated inductance, LMIN2, for the application
parameters in the following equation:
0.13 0.16
(1 )
MIN2 IN
2
L2 L V DUTY
>=× −
−
(µH)
Table 11 suggests a series of inductors to use with the ADP5072
inverting regulator.
LOOP COMPENSATION
The ADP5072 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application.
Boost Regulator
The boost converter produces an undesirable right half plane
zero in the regulation feedback loop. This feedback loop requires
compensating the regulator such that the crossover frequency
occurs well below the frequency of the right half plane zero. The
right half plane zero is determined by the following equation:
2
(1 )
() 2
LOAD1 1
Z1
R DUTY
f RHP L1
π
−
=×
where:
fZ1(RHP) is the right half plane zero frequency.
RLOAD1 is the equivalent load resistance or the output voltage
divided by the load current.
DIODE1
POS IN
1POS DIODE1
V VV
DUTY VV
−+
=
+
where VDIODE1 is the forward voltage drop of the Schottky
diode (D1).
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
The boost regulator loop gain is
FB1 IN
VL1 M1 OUT1 COMP1 CS1 OUT1
POS POS
VV
A g R ||Z g Z
VV
= × ×× ××
where:
AVL1 is the loop gain.
VFB1 is the feedback regulation voltage
VPOS is the regulated positive output voltage.
VIN is the input voltage.
gM1 is the error amplifier transconductance gain.
ROUT1 is the output impedance of the error amplifier and is 33 MΩ.
ZCOMP1 is the impedance of the series resistor/capacitor (RC)
network from COMP1 to AGND.
gCS1 is the current sense transconductance gain (the inductor
current divided by the voltage at COMP1), which is internally
set by the ADP5072 and is 6.25 A/V.
ZOUT1 is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency (fC1), it is important to
note that, at that frequency, the compensation impedance (ZCOMP1)
is dominated by a resistor (RC1), and the output impedance (ZOUT1)
is dominated by the impedance of an output capacitor (COUT1).
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
11
2
FB1 IN
VL1 M1 C1 CS1
POS POS
C1 OUT1
VV
A g Rg
VV
πf C
= × × ×× ×
=
××
where fC1 is the crossover frequency.
To s olve for RC1, use the following equation:
2
2)
C1 OUT1 POS
C1
FB1 IN M1 CS1
f C (V
RVVg g
π
×× ×
=×××
where gCS1 = 6.25 A/V.
Using typical values for VFB1 and GM1 results in
2
4188 )
C1 OUT1 POS
C1
IN
f C (V
RV
×× ×
=
For improved accuracy, it is recommended to use the value of the
output capacitance, COUT1, expected for the dc bias conditions
under which it operates in the calculation for RC1.
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor, CC1 and RC1, to one-
fourth of the crossover frequency, or
2
C1
C1 C1
Cπf R
=××
where CC1 is the compensation capacitor value.
ERROR
AMPLIFIER
REF1 g
M1
FB1 COMP1
R
C1
C
C1
16646-042
Figure 44. Compensation Components
ADP5072 Data Sheet
Rev. 0 | Page 20 of 24
Inverting Regulator
The inverting converter, like the boost converter, produces an
undesirable right half plane zero in the regulation feedback loop.
This feedback loop requires compensating the regulator such that
the crossover frequency occurs well below the frequency of the
right half plane zero. The right half plane zero frequency is
determined by the following equation:
(1 )
2
2
LOAD2 2
Z2
2
R DUTY
f (RHP) π L2 DUTY
−
=××
where:
fZ2(RHP) is the right half plane zero frequency.
RLOAD2 is the equivalent load resistance or the output voltage
divided by the load current.
NEG DIODE2
2
IN NEG DIODE2
|V | V
DUTY V |V | V
+
=
++
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
The inverting regulator loop gain is
( 2 | |)
FB2 IN
VL2 M2
NEG IN NEG
OUT2 COMP2 CS2 OUT2
VV
Ag
|V | V V
R ||Z g Z
= × ××
+×
××
where:
AVL2 is the loop gain.
VFB2 is the feedback regulation voltage.
VNEG is the regulated negative output voltage.
VIN is the input voltage.
gM2 is the error amplifier transconductance gain.
ROUT2 is the output impedance of the error amplifier and is 33 MΩ.
ZCOMP2 is the impedance of the series RC network from COMP2
to AGND.
gCS2 is the current sense transconductance gain (the inductor
current divided by the voltage at COMP2), which is internally
set by the ADP5072 and is 6.25 A / V.
ZOUT2 is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency, it is important to note
that, at that frequency, the compensation impedance (ZCOMP2) is
dominated by a resistor, RC2, and the output impedance (ZOUT2)
is dominated by the impedance of the output capacitor, COUT2.
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
( 2 | |)
11
2
FB2 IN
VL2 M2
NEG IN NEG
C2 CS2
C2 OUT2
VV
Ag
|V | V V
Rg πf C
= × ××
+×
×× =
××
where fC2 is the crossover frequency.
To solve for RC2, use the following equation:
2 (2 | |)
C2 OUT2 NEG IN NEG
C2
FB2 IN M2 CS2
π f C |V | (V V
RV Vg g
× × × × +×
=×× ×
where GCS2 = 6.25 A / V.
Using typical values for VFB2 and GM2 results in
2
4188 | | ( (2 | |)
C2 OUT NEG IN NEG
C2
IN
fC V V V
RV
× × × × +×
=
For improved accuracy, it is recommended to use the value of the
output capacitance, COUT2, expected for the dc bias conditions
under which it operates in the calculation for RC2.
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor, CC2 and RC2, to one-
fourth of the crossover frequency, or
2
C2
C2 C2
Cπf R
=××
where CC2 is the compensation capacitor.
ERROR
AMPLIFIER
REF2 gM2
FB2 COMP2
RC2
CC2
16646-043
Figure 45. Compensation Component
Data Sheet ADP5072
Rev. 0 | Page 21 of 24
COMMON APPLICATIONS
Table 9 through Table 11 list a number of common component
selections for typical VIN, VPOS, and VNEG conditions. These
components have been bench tested and are recommended for
customer applications that are suited for these conditions. Note that
when pairing a boost and inverting regulator bill of materials,
choose the same VIN and switching frequency.
ADP5072
SS
SW1
SW1
COMP1
RC1
102kΩ
CC1
1nF
COMP2
RC2
61.9kΩ
CC2
2.2nF
EN1
ON
OFF
SYNC
SLEW
SEQ
EN2
AGND
PVIN
PVIN
AVIN
CIN
10µF
VIN
+5V
FB1
D1
PD3S140
L1
3.3µH
VIN
+5V
VIN
+5V
L2
6.8µF
RFB1
137kΩ
RFT1
2.43MΩ
VPOS
+15V
SW2
PGND
PGND
FB2
VREF
D2
PD3S140
RFB2
118kΩ
VNEG
–15V
CVREF
1µF
COUT1
10µF
COUT2
10µF
RFT2
2.32MΩ
ON
OFF
16646-044
Figure 46. Typical +5 V to ±15 V Application
Figure 46 shows the schematic referenced by Table 9 through
Table 11 with example component values for 5 V input voltage
to ±15 V output voltage generation. Table 9 shows the
components common to all of the VIN, VPOS, and VNEG
conditions.
Figure 47 shows the efficiency curves for the boost and
inverting regulator using the recommended, small size
components described in Table 9, Table 10, and Table 11
for VPOS = 15 V and VNEG = −15 V at VIN = 5 V.
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EFFICIENCY (%)
LO AD CURRE NT (A)
V
POS
= +15V, 1.2MHz
V
NEG
= –15V, 1. 2M Hz
V
POS
= +15V, 2.4MHz
V
NEG
= –15V, 2. 4M Hz
16646-047
Figure 47. Efficiency vs. Load Current for Boost Regulator and Inverting
Regulator, TA = 25°C
Table 10 and Table 11 are based on the smallest sized components.
The maximum output current is limited by the ISAT rating of the
2 mm × 2 mm inductor. A higher output current is possible by
using larger inductors with higher ISAT ratings, as long as the
inductor peak current remains below the appropriate current
limit specifications.
It is important to verify the thermal performance of the small
sized inductor at higher ambient temperature in actual application.
Table 9. Recommended Common Components Selections
Reference Designator Description Value (µF) Part Number Manufacturer
CIN Input capacitor on PVIN 10 GRM21BZ71C106KE15L Murata
CVREF VREF capacitor 1 GRM188R71C105KA12C Murata
ADP5072 Data Sheet
Rev. 0 | Page 22 of 24
Table 10. Recommended Boost Regulator Small Sized Components
VIN
(V)
VPOS
(V)
ILOAD1 (MAX)
(mA)
Freq.
(MHz)
L1
(µH)
L1 Manufacturer Part No.
(Coilcraft)
COUT1
(µF) COUT1, Murata Part No. D1
RFT1
(MΩ)
RFB1
(kΩ)
CC1
(nF)
RC1
(kΩ)
3.3 5 340 1.2 3.3 EPL2014-332ML_ 10 GRM21BR71A106KA73L PMEG2005AELD 0.604 115 0.82 15.8
3.3 5 360 2.4 2.2 EPL2014-222ML_ 10 GRM21BR71A106KA73L PMEG2005AELD 0.604 115 0.47 29.4
3.3 9 180 1.2 4.7 EPL2014-472ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.24 121 1.2 26.1
3.3 9 200 2.4 3.3 EPL2014-332ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.24 121 0.82 17.4
3.3 15 100 1.2 4.7 EPL2014-472ML_ 10 GRM31CR71E106MA12L PD3S140 2.43 137 1.5 14.3
3.3 15 110 2.4 4.7 EPL2014-472ML_ 10 GRM31CR71E106MA12L PD3S140 2.43 137 1.2 16.9
3.3 24 50 1.2 6.8 EPL2014-682ML_ 10 GRM32ER7YA106MA12L PD3S140 3.09 107 1.8 28.7
3.3 24 55 2.4 6.8 EPL2014-682ML_ 10 GRM32ER7YA106MA12L PD3S140 3.09 107 1.8 16.2
5 9 140 1.2 3.3 EPL2014-332ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.24 121 0.56 16.9
5 9 280 2.4 2.2 EPL2014-222ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.24 121 0.39 18.7
5
15
110
1.2
4.7
EPL2014-472ML_
10
GRM31CR71E106MA12L
PD3S140
2.43
137
1
18.2
5
15
170
2.4
3.3
EPL2014-332ML_
10
GRM31CR71E106MA12L
PD3S140
2.43
137
0.56
20.5
5
24
50
1.2
10
EPL2014-103ML_
10
GRM32ER7YA106MA12L
PD3S140
3.09
107
1.8
15.8
5 24 80 2.4 6.8 EPL2014-682ML_ 10 GRM32ER7YA106MA12L PD3S140 3.09 107 1.2 10
5 34 40 1.2 10 EPL2014-103ML_ 10 GRM32ER71H106KA12L PD3S140 4.22 102 1.5 25.5
5 34 45 2.4 8.2 EPL2014-822ML_ 10 GRM32ER71H106KA12L PD3S140 4.22 102 1.2 18.2
Table 11. Recommended Inverting Regulator Small Sized Components
VIN
(V)
VNEG
(V)
ILOAD2 (MAX)
(mA)
Freq.
(MHz)
L2
(µH)
L2 Manufacturer Part No.
(Coilcraft)
COUT2
(µF) COUT2, Murata Part No. D2
RFT2
(MΩ)
RFB2
(kΩ)
CC2
(nF)
RC2
(kΩ)
3.3 −5 120 1.2 6.8 EPL2014-682ML_ 10 GRM21BR71A106KA73L PMEG2005AELD 1.15 158 8.2 7.5
3.3 −5 130 2.4 4.7 EPL2014-472ML_ 10 GRM21BR71A106KA73L PMEG2005AELD 1.15 158 3.3 10.5
3.3 −9 70 1.2 4.7 EPL2014-472ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.62 133 3.9 8.06
3.3 −9 90 2.4 4.7 EPL2014-472ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.62 133 1.8 8.06
3.3 −15 50 1.2 8.2 EPL2014-822ML_ 10 GRM31CR71E106MA12L PD3S140 2.32 118 3.3 10.5
3.3 −15 55 2.4 6.8 EPL2014-682ML_ 10 GRM31CR71E106MA12L PD3S140 2.32 118 2.2 8.25
3.3 −24 30 1.2 10 EPL2014-103ML_ 10 GRM32ER7YA106MA12L PD3S140 3.16 102 3.3 10.5
3.3 −24 30 2.4 6.8 EPL2014-682ML_ 10 GRM32ER7YA106MA12L PD3S140 3.16 102 1.5 14.3
5 −9 90 1.2 8.2 EPL2014-822ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.62 133 5.6 4.87
5 −9 120 2.4 6.8 EPL2014-682ML_ 10 GRM21BZ71C106KE15L PMEG2005AELD 1.62 133 2.2 10
5 −15 60 1.2 8.2 EPL3015-822ML_ 10 GRM31CR71E106MA12L PD3S140 2.32 118 4.7 10
5 −15 80 2.4 8.2 EPL2014-822ML_ 10 GRM31CR71E106MA12L PD3S140 2.32 118 1.8 13.3
5 −24 40 1.2 10 EPL3015-103ML_ 10 GRM32ER7YA106MA12L PD3S140 3.16 102 4.7 10
5 −24 50 2.4 10 EPL2014-103ML_ 10 GRM32ER7YA106MA12L PD3S140 3.16 102 2.2 7.15
5
−30
30
1.2
10
EPL3015-103ML_
10
GRM32ER71H106KA12L
PD3S140
4.99
75
3.9
15.8
5
−30
35
2.4
8.2
EPL2014-822ML_
10
GRM32ER71H106KA12L
PD3S140
4.99
75
1.2
1.2
Data Sheet ADP5072
Rev. 0 | Page 23 of 24
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is particularly
important for regulators with high switching frequencies. To
achieve high efficiency, proper regulation, stability, and low
noise, a well designed PCB layout is required. Follow these
guidelines when designing PCBs (see Figure 48):
• Keep the input bypass capacitor, CIN, close to the PVIN pin
and the AVIN pin.
• Keep the high current paths as short as possible. These
paths include the connections between the following:
• CIN, L1, D1, COUT1, and PGND for the boost
regulator, the connections
• L2, D2, COUT2, and PGND for the inverting
regulator
• The connections of these components for both the
boost and inverting regulators to the ADP5072.
• Keep AGND and PGND separate on the top layer of the
board. This separation avoids pollution of AGND with
switching noise. Connect both AGND and PGND to the
board ground plane with vias. Ideally, connect PGND to the
plane at a point between the input and output capacitors.
• Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and EMI.
• Avoid routing high impedance traces near any node con-
nected to the SW1 and SW2 pins or near Inductors L1and
L2 to prevent radiated switching noise injection.
• Place the feedback resistors as close to the FB1 and FB2 pins as
possible to prevent high frequency switching noise injection.
• Place the top of the upper feedback resistors, RFT1 and RFT2,
as close as possible to the top of COUT1 and COUT2 for
optimum output voltage sensing, or route traces to the RFT1
and RFT2 resistors as close as possible from the top of
COUT1 and COUT2.
• Place the compensation components as close as possible
to COMP1 and COMP2. Do not share vias to the ground
plane with the feedback resistors to avoid coupling high
frequency noise into the sensitive COMP1 and COMP2 pins.
• Place the CVREF capacitor as close to the VREF pin as
possible. Ensure that short traces are used between VREF
and RFB2.
16646-045
Figure 48. Suggested Layout for VIN = 3.3 V, VPOS = 12 V, ILOAD1 = 100 mA and
VNEG = −3.2 V, ILOAD2 = 60 mA; Not to Scale
ADP5072 Data Sheet
Rev. 0 | Page 24 of 24
OUTLINE DIMENSIONS
A
B
C
D
E
2.220
2.180
2.140
1.650
1.610
1.570
1
2
3
4
TOP VI EW
(BALL SI DE DOWN)
SIDE VIEW
BOTTOM VIEW
(BALL SIDE UP)
BALLA1
IDENTIFIER
0.40
BSC
0.560
0.500
0.440
0.330
0.300
0.270
0.230
0.200
0.170
0.225
0.205
0.185
0.310
0.290
0.270
0.300
0.260
0.220
1.60 RE F
1.20 RE F
COPLANARITY
0.04
11-07-2017-A
PKG-003773
SEATING
PLANE
Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5072ACBZ-R7 −40°C to +125°C 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-14
ADP5072CB-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16646-0-1/19(0)
