Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
32-bit Microcontroller
CMOS
FR60 MB91460P Series
MB91F465PA, MB91F467PA
■DESCRIPTION
MB91460P series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs.
This series contains the LIN-USART and CAN controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Semiconductor Limited.
■FEATURES
1. FR60 CPU core
• 32-bit RISC, load/store architecture, five-stage pipeline
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed: 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions
suitable for embedded applications
• Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C
language
• Register interlock function: Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupts (save PC/PS) : 6 cycles (16 priority levels)
• Harvard architecture enabling program access and data access to be performed simultaneously
• Instructions compatible with the FR family
DS07-16615-2E
MB91460P Series
2DS07-16615-2E
2. Internal peripheral resources
• General-purpose ports : Maximum 141 ports
• DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously
2 transfer sources (internal peripheral/software)
Activation source can be selected using software
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (successive approximation type)
10-bit resolution: maximum 41 channels *
Conversion time: minimum 1 ms
• External interrupt inputs : 16 channels *
9 channels shared with CAN RX or I2C pins
• Bit search module (for REALOS)
Function to search the first bit position of ‘’1’’, ‘’0’’, ‘’changed’’ from the MSB (most significant bit) within one word
• LIN-USART (full duplex double buffer): 12 channels, 4 channels with FIFO *
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
•I
2C bus interface (supports 400 kbps): 4 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): up to 4 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• Sound generator : 1 channel
Tone frequency : PWM frequency divide-by-two (reload value + 1)
• 16-bit PPG timer : 32 channels *
• 16-bit PFM timer : 1 channel
• 16-bit reload timer: 16 channels
8 reload timers can be used as up to 4 32-bit reload timers (by cascading 2 reload timers each).
• 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU)
• Input capture: 8 channels (operates in conjunction with the free-run timer)
• Output compare: 8 channels (operates in conjunction with the free-run timer)
• Up/Down counter: 4 channels (4*8-bit or 2*16-bit) *
• Watchdog timer
• Real-time clock
• Low-power consumption modes : Sleep/stop mode function
• Low voltage detection circuit
Note: * The maximum channel count is given; the real number depends on port multiplexing.
(Continued)
MB91460P Series
DS07-16615-2E 3
(Continued)
• Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator,
etc.) when the oscillations stop.
• Clock modulator
• Clock monitor
• Sub-clock calibration
Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator
• Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
• Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
3. Package and technology
• Package : QFP-176
• CMOS 0.18 mm technology
• Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter)
• Operating temperature range: between - 40°C and + 125°C
MB91460P Series
4DS07-16615-2E
■PRODUCT LINEUP
Feature Emulation Devices MB91F465PA MB91F467PA
MB91V460A MB91FV460B
Max. core frequency (CLKB) 80 MHz 100 MHz 100 MHz 100 MHz
Max. resource frequency (CLKP) 40 MHz 50 MHz 50 MHz 50 MHz
Max. external bus frequency (CLKT) 40 MHz 50 MHz 50 MHz 50 MHz
Max. CAN frequency (CLKCAN) 20 MHz 50 MHz 50 MHz 50 MHz
Max. FlexRay frequency (SCLK)----
Technology 0.35μm0.18μm0.18μm0.18μm
Watchdog timer yes yes yes yes
Watchdog timer (RC osc. based) yes (disengageable) yes yes yes
Bit Search yes yes yes yes
Reset input (INITX) yes yes yes yes
Hardware standby input (HSTX) yes no no no
Clock Modulator yes yes yes yes
Clock Monitor yes yes yes yes
Low Power Mode yes yes yes yes
DMA 5 ch 5 ch 5 ch 5 ch
MMU/MPU MPU (16 ch)*1 MPU (16 ch)*1 MPU (8 ch)*1 MPU (8 ch)*1
Flash memory Emulation SRAM
32bit read data
Internal Flash memory
2112KB +
external emulation SRAM
with 64bit read data
544 KByte 1088 KByte
Satellite Flash memory - Data Flash 64 KByte - Data Flash 64 KByte
Flash Protection - yes yes yes
D-RAM 64 KByte 64 KByte 24 KByte 48 KByte
ID-RAM 64 KByte 64 KByte 16 KByte 32 KByte
Flash-Cache (Instruction cache) 16 KByte 16 KByte 8 KByte 8 KByte
Boot-ROM / BI-ROM 4 KByte fixed 16 KByte Boot Flash 4 KByte 4 KByte
RTC 1 ch 1 ch 1 ch 1 ch
Free Running Timer 8 ch 12 ch 8 ch*28 ch*2
ICU 8 ch 10 ch 8 ch*28 ch*2
OCU 8 ch 8 ch 8 ch*28 ch*2
Reload Timer 8 ch 16 ch 16 ch 16 ch
PPG 16-bit 16 ch 32 ch 32 ch*232 ch*2
PFM 16-bit 1 ch 1 ch 1 ch 1 ch
Sound Generator 1 ch 1 ch 1 ch 1 ch
Up/Down Counter (8/16 bit) 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit)*24 ch (8-bit) / 2 ch (16-bit)*2
C_CAN 6 ch (128msg) 6 ch (128msg) 3 ch (32msg) 4 ch (32msg)
LIN-USART 4 ch + 4 ch FIFO + 8 ch 16 ch FIFO 8 ch + 4 ch FIFO*28 ch + 4 ch FIFO*2
(2 more pin relocations)
I2C (400K) 4 ch 8 ch 4 ch*24 ch*2
MB91460P Series
DS07-16615-2E 5
*1: MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
*2: Maximum channel count is shown; function is multiplexed with external bus addresses.
FR external bus yes (32bit addr, 32bit data) yes (32bit addr, 32bit data) yes (24bit addr, 16bit data) yes (24bit addr, 16bit data)
External Interrupts 16 ch 16 ch 16 ch*216 ch*2
NMI Interrupts 1 ch 1 ch 1 ch 1 ch
General I/O ports 288 328 (24 non-multiplexed) 141 141
SMC 6 ch 328 (24 non-multiplexed) - -
LCD controller (40x4) 1 ch 1 ch - -
ADC (10-bit) 32 ch 32 ch + 22 ch
(2 ADC macros) 32 ch*232 ch *2 + 9 ch
(2 ADC macros)
Alarm Comparator 2 ch 2 ch - -
Supply Supervisor (low voltage detection) yes yes yes yes
Clock Supervisor yes yes yes yes
Main clock oscillator 4 MHz 4 MHz 4 MHz 4 MHz
Sub clock oscillator 32kHz 32kHz 32kHz 32kHz
RC oscillator 100kHz 100kHz / 2MHz 100kHz / 2MHz 100kHz / 2MHz
PLL x 20 x 25 x 25 x 25
DSU4 yes yes no no
EDSU yes (32 BP)*1 yes (32 BP)*1 yes (16 BP)*1 yes (16 BP)*1
Supply voltage 3V/5V 3V/5V 3V/5V 3V/5V
Regulator yes yes yes yes
Power consumption n.a. n.a. < 1.4 W < 1.4 W
Temperature Range (Ta) 0..70 C 0..70 C -40..125 C -40..125 C
Package BGA660 BGA896 LQFP-176 LQFP-176
Power on to PLL run < 20 ms < 20 ms < 20 ms < 20 ms
Flash Download Time n.a. < 8 sec. typical < 5 sec. typical < 6 sec. typical
Feature Emulation Devices MB91F465PA MB91F467PA
MB91V460A MB91FV460B
MB91460P Series
6DS07-16615-2E
■PIN ASSIGNMENT
1. MB91F465PA
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7
P23_6/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK
P10_1/ASX
P10_3/WEX
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
QFP-176
MB91460P Series
DS07-16615-2E 7
2. MB91F467PA
(TOP VIEW)
The pinout of MB91F467PA differs versus MB91F465PA at the following pins:
• Pins 50-55: Added re-located LIN-USART10/11
• Pins 92-93: Added CAN3 RX3,TX3
• Pins 118-126: Added ADC channels AN37-42, AN44-46
• Pins 99-100: X0/X1 are mirrored
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN46
P18_5/SOT7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN42
P18_1/SOT6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
QFP-176
MB91460P Series
8DS07-16615-2E
■PIN DESCRIPTION
1. MB91F465PA, MB91F467PA
Pin no. Pin name I/O I/O circuit
type*1Mux Function
2P21_4 I/O A — General-purpose input/output port
SIN1 Data input pin of USART1
3P21_5 I/O A — General-purpose input/output port
SOT1 Data output pin of USART1
4
P21_6
I/O A —
General-purpose input/output port
SCK1 Clock input/output pin of USART1
CK1 External clock input pin of free-run timer
1
5 P21_7 I/O A — General-purpose input/output port
6
P06_0 I/O A PPMUX.PS4=0 General-purpose input/output port
A8 Signal pin of external address bus (bit8)
OR
P21_0 I/O A PPMUX.PS4=1 General-purpose input/output port
SIN0 Data input pin of USART0
7
P06_1 I/O A PPMUX.PS4=0 General-purpose input/output port
A9 Signal pin of external address bus (bit9)
OR
P21_1 I/O A PPMUX.PS4=1 General-purpose input/output port
SOT0 Data output pin of USART0
8
P06_2 I/O A PPMUX.PS4=0 General-purpose input/output port
A10 Signal pin of external address bus (bit10)
OR
P21_2
I/O A PPMUX.PS4=1
General-purpose input/output port
SCK0 Clock input/output pin of USART0
CK0 External clock input pin of free-run timer
0
9
P06_3 I/O A PPMUX.PS4=0 General-purpose input/output port
A11 Signal pin of external address bus (bit11)
OR
P17_4 I/O A PPMUX.PS4=1 General-purpose input/output port
PPG4 Output pin of PPG timer
MB91460P Series
DS07-16615-2E 9
10 to 13
P06_4 to P06_7
I/O A PPMUX.PS4=0
General-purpose input/output ports
A12 to A15 Signal pins of external address bus
(bit12 to bit15)
OR
P14_4 to P14_7
I/O A PPMUX.PS4=1
General-purpose input/output ports
ICU4 to ICU7 Input capture input pins
TIN12/4 to
TIN15/7 External trigger input pins of reload timer
TTG28/20/12/4 to
TTG31/23/15/7 External trigger input pins of PPG timer
14
P05_0
I/O A PPMUX.PR10=0
General-purpose input/output port
A16 Signal pin of external address bus (bit16
to bit17)
OR
P16_0 I/O A PPMUX.PR10=1 General-purpose input/output port
PPG8 Output pin of PPG timer
15
P05_1
I/O A PPMUX.PR11=0
General-purpose input/output port
A17 Signal pin of external address bus (bit16
to bit17)
OR
P16_1 I/O A PPMUX.PR11=1 General-purpose input/output port
PPG9 Output pin of PPG timer
16
P05_2 I/O A PPMUX.PR12=0 General-purpose input/output port
A18 Signal pin of external address bus (bit18)
OR
P20_0
I/O A
PPMUX.PR12=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SIN2 Data input pin of USART2
AIN0 Up/down counter input pin
OR
P34_0
I/O A
PPMUX.PR12=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SIN10 Data input pin of USART10
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
10 DS07-16615-2E
17
P05_3 I/O A PPMUX.PR13=0 General-purpose input/output port
A19 Signal pin of external address bus (bit19)
OR
P20_1
I/O A
PPMUX.PR13=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SOT2 Data output pin of USART2
BIN0 Up/down counter input pin
OR
P34_1
I/O A
PPMUX.PR13=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SOT10 Data output pin of USART10
18
P05_4 I/O A PPMUX.PR14=0 General-purpose input/output port
A20 Signal pin of external address bus (bit20)
OR
P20_2
I/O A
PPMUX.PR14=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SCK2 Clock input/output pin of USART2
ZIN0 Up/down counter input pin
CK2 External clock input pin of free-run timer
2
OR
P34_2
I/O A
PPMUX.PR14=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SCK10 Clock input/output pin of USART10
19
P05_5 I/O A PPMUX.PR15=0 General-purpose input/output port
A21 Signal pin of external address bus (bit21)
OR
P20_4
I/O A
PPMUX.PR15=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SIN3 Data input pin of USART3
AIN1 Up/down counter input pin
OR
P34_4
I/O A
PPMUX.PR15=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SIN11 Data input pin of USART11
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 11
20
P05_6 I/O A PPMUX.PR16=0 General-purpose input/output port
A22 Signal pin of external address bus (bit22)
OR
P20_5
I/O A
PPMUX.PR16=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SOT3 Data output pin of USART3
BIN1 Up/down counter input pin
OR
P34_5
I/O A
PPMUX.PR16=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SOT11 Data output pin of USART11
21
P05_7 I/O A PPMUX.PR17=0 General-purpose input/output port
A23 Signal pin of external address bus (bit23)
OR
P20_6
I/O A
PPMUX.PR17=1
and
PP-
MUX.PRPS0=1
General-purpose input/output port
SCK3 Clock input/output pin of USART3
ZIN1 Up/down counter input pin
CK3 External clock input pin of free-run timer
3
OR
P34_6
I/O A
PPMUX.PR17=1
and
PP-
MUX.PRPS0=0
General-purpose input/output port
SCK11 Clock input/output pin of USART11
24 to 27
P01_0 to P01_3
I/O A PPMUX.PS3=0
General-purpose input/output ports
D16 to D19 Signal pins of external data bus (bit16 to
bit19)
OR
P17_0 to P17_3 I/O A PPMUX.PS3=1 General-purpose input/output ports
PPG0 to PPG3 Output pins of PPG timer
28 to 31
P01_4 to P01_7
I/O A PPMUX.PS3=0
General-purpose input/output ports
D20 to D23 Signal pins of external data bus (bit20 to
bit23)
OR
P15_4 to P15_7
I/O A PPMUX.PS3=1
General-purpose input/output ports
OCU4 to OCU7 Output compare output pins
TOT4 to TOT7 Reload timer output pins
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
12 DS07-16615-2E
32 to 39
P00_0 to P00_7
I/O A PPMUX.PR0=0
General-purpose input/output ports
D24 to D31 Signal pins of external data bus (bit24 to
bit31)
OR
P24_0 to P24_7 I/O A PPMUX.PR0=1 General-purpose input/output ports
INT0 to INT7 External interrupt input pins
40 P22_0 I/O A — General-purpose input/output port
INT12 External interrupt input pin
41 P22_1 I/O A — General-purpose input/output port
42 P22_2 I/O A — General-purpose input/output port
INT13 External interrupt input pin
43 P22_3 I/O A — General-purpose input/output port
46 to 49 P30_0 to P30_3 I/O A — General-purpose input/output ports
PPG16 to PPG19 Output pins of PPG timer
50
P10_0 I/O A — General-purpose input/output port
SYSCLK External bus clock output pin
OR (MB91F467PA only)
P34_0 I/O A PPMUX2.PR0=1 General-purpose input/output port
SIN10 Data input pin of USART10
51
P10_1 I/O A — General-purpose input/output port
ASX Address strobe output pin
OR (MB91F467PA only)
P34_1 I/O A PPMUX2.PR1=1 General-purpose input/output port
SOT10 Data output pin of USART10
52
P10_3 I/O A — General-purpose input/output port
WEX Write enable output pin
OR (MB91F467PA only)
P34_2 I/O A PPMUX2.PR2=1 General-purpose input/output port
SCK10 Clock input/output pin of USART10
53
P09_0 I/O A — General-purpose input/output port
CSX0 Chip select output pin
OR (MB91F467PA only)
P34_4 I/O A PPMUX2.PR3=1 General-purpose input/output port
SIN11 Data input pin of USART11
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 13
54
P09_1 I/O A — General-purpose input/output port
CSX1 Chip select output pin
OR (MB91F467PA only)
P34_5 I/O A PPMUX2.PR4=1 General-purpose input/output port
SOT11 Data output pin of USART11
55
P09_2 I/O A — General-purpose input/output port
CSX2 Chip select output pin
OR (MB91F467PA only)
P34_6 I/O A PPMUX2.PR5=1 General-purpose input/output port
SCK11 Clock input/output pin of USART11
56, 57 P08_0, P08_1 I/O A — General-purpose input/output ports
WRX0, WRX1 External write strobe output pins
58 P08_4 I/O A — General-purpose input/output port
RDX External read strobe output pin
59 P08_7 I/O A — General-purpose input/output port
RDY External ready input pin
60, 61 P16_2, P16_3 I/O A — General-purpose input/output ports
PPG10, PPG11 Output pins of PPG timer
62
P16_4
I/O A —
General-purpose input/output port
PPG12 Output pin of PPG timer
SGA SGA output pin of sound generator
63
P16_5
I/O A —
General-purpose input/output port
PPG13 Output pin of PPG timer
SGO SGO output pin of sound generator
64
P16_6
I/O A —
General-purpose input/output port
PPG14 Output pin of PPG timer
PFM Pulse frequency modulator output pin
65
P16_7
I/O A —
General-purpose input/output port
PPG15 Output pin of PPG timer
ATGX A/D converter external trigger input pin
68
P23_0
I/O A —
General-purpose input/output port
RX0 RX input pin of CAN0
INT8 External interrupt input pin
69 P23_1 I/O A — General-purpose input/output port
TX0 TX output pin of CAN0
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
14 DS07-16615-2E
70
P23_2
I/O A —
General-purpose input/output port
RX1 RX input pin of CAN1
INT9 External interrupt input pin
71 P23_3 I/O A — General-purpose input/output port
TX1 TX output pin of CAN1
72
P22_4
I/O C —
General-purpose input/output port
SDA0 I2C bus DATA input/output pin (open
drain)
INT14 External interrupt input pin
73
P22_5
I/O C —
General-purpose input/output port
SCL0 I2C bus clock input/output pin (open
drain)
74
P22_6
I/O C —
General-purpose input/output port
SDA1 I2C bus DATA input/output pin (open
drain)
INT15 External interrupt input pin
75
P22_7
I/O C —
General-purpose input/output port
SCL1 I2C bus clock input/output pin (open
drain)
76 to 79
P14_0 to P14_3
I/O A —
General-purpose input/output ports
ICU0 to ICU3 Input capture input pins
TIN8/0 to TIN11/3 External trigger input pins of reload timer
TTG24/16/8/0 to
TTG27/19/11/3 External trigger input pins of PPG timer
80 to 83
P15_0 to P15_3
I/O A —
General-purpose input/output ports
OCU0 to OCU3 Output compare output pins
TOT0 to TOT3 Reload timer output pins
84 to 87 P30_4 to P30_7 I/O A — General-purpose input/output ports
PPG20 to PPG23 Output pins of PPG timer
90
P23_4
I/O A —
General-purpose input/output port
RX2 RX input pin of CAN2
INT10 External interrupt input pin
91 P23_5 I/O A — General-purpose input/output port
TX2 TX output pin of CAN2
92
P23_6
I/O A —
General-purpose input/output ports
RX3 RX input pin of CAN3 *4
INT11 External interrupt input pin
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 15
93 P23_7 I/O A — General-purpose input/output port
TX3 TX output pin of CAN3 *4
94 MD_0 I G — Mode setting pin
95 MD_1 I G — Mode setting pin
96 MD_2 I G — Mode setting pin
97 MONCLK O M — Clock Monitor pin
98 MD_3 I G — Fast clock input pin
99 X1 —J1 — Clock (oscillation) output, F465PA
X0 Clock (oscillation) input, F467PA
100 X0 —J1 — Clock (oscillation) input, F465PA
X1 Clock (oscillation) output, F467PA
102 X0A — J2 — Sub clock (oscillation) input
103 X1A — J2 — Sub clock (oscillation) output
104 INITX I H — External reset input pin
105 NMIX I H — Non-maskable interrupt input pin
112 P19_0 I/O A — General-purpose input/output port
SIN4 Data input pin of USART4
113 P19_1 I/O A — General-purpose input/output port
SOT4 Data output pin of USART4
114
P19_2
I/O A —
General-purpose input/output port
SCK4 Clock input/output pin of USART4
CK4 External clock input pin of free-run timer
4
115 P19_4 I/O A — General-purpose input/output port
SIN5 Data input pin of USART5
116 P19_5 I/O A — General-purpose input/output port
SOT5 Data output pin of USART5
117
P19_6
I/O A —
General-purpose input/output port
SCK5 Clock input/output pin of USART5
CK5 External clock input pin of free-run timer
5
118
P18_0
I/O
A
or
B *2
—
General-purpose input/output port
SIN6 Data input pin of USART6
AIN2 Up/down counter input pin
AN40 Analog input pin of A/D converter 2 *3
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
16 DS07-16615-2E
119
P18_1
I/O
A
or
B *2
—
General-purpose input/output port
SOT6 Data output pin of USART6
BIN2 Up/down counter input pin
AN41 Analog input pin of A/D converter 2 *3
120
P18_2
I/O
A
or
B *2
—
General-purpose input/output port
SCK6 Clock input/output pin of USART6
ZIN2 Up/down counter input pin
CK6 External clock input pin of free-run timer
6
AN42 Analog input pin of A/D converter 2 *3
121
P18_4
I/O
A
or
B *2
—
General-purpose input/output port
SIN7 Data input pin of USART7
AIN3 Up/down counter input pin
AN44 Analog input pin of A/D converter 2 *3
122
P18_5
I/O
A
or
B *2
—
General-purpose input/output port
SOT7 Data output pin of USART7
BIN3 Up/down counter input pin
AN45 Analog input pin of A/D converter 2 *3
123
P18_6
I/O
A
or
B *2—
General-purpose input/output port
SCK7 Clock input/output pin of USART7
ZIN3 Up/down counter input pin
CK7 External clock input pin of free-run timer
7
AN46 Analog input pin of A/D converter 2 *3
124 to
126
P17_5 to P17_7
I/O
A
or
B *2
—
General-purpose input/output ports
PPG5 to PPG7 Output pin of PPG timer
AN37 to AN39 Analog input pins of A/D converter 2 *3
127, 128 P25_0, P25_1 I/O A — General-purpose input/output ports
134 P35_3 I/O A — General-purpose input/output port
PPG24 Output pin of PPG timer
135 P35_7 I/O A — General-purpose input/output port
PPG25 Output pin of PPG timer
136 P34_3 I/O A — General-purpose input/output port
PPG26 Output pin of PPG timer
137 P34_7 I/O A — General-purpose input/output port
PPG27 Output pin of PPG timer
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 17
138
P35_0 I/O B PPMUX.PS5=0 General-purpose input/output port
SIN8 Data input pin of USART8
OR
P29_0 I/O B PPMUX.PS5=1 General-purpose input/output port
AN0 Analog input pin of A/D converter
139
P35_1 I/O B PPMUX.PS5=0 General-purpose input/output port
SOT8 Data output pin of USART8
OR
P29_1 I/O B PPMUX.PS5=1 General-purpose input/output port
AN1 Analog input pin of A/D converter
140
P35_2 I/O B PPMUX.PS5=0 General-purpose input/output port
SCK8 Clock input/output pin of USART8
OR
P29_2 I/O B PPMUX.PS5=1 General-purpose input/output port
AN2 Analog input pin of A/D converter
141
P35_4 I/O B PPMUX.PS5=0 General-purpose input/output port
SIN9 Data input pin of USART9
OR
P29_3 I/O B PPMUX.PS5=1 General-purpose input/output port
AN3 Analog input pin of A/D converter
142
P35_5 I/O B PPMUX.PS5=0 General-purpose input/output port
SOT9 Data output pin of USART9
OR
P29_4 I/O B PPMUX.PS5=1 General-purpose input/output port
AN4 Analog input pin of A/D converter
143
P35_6 I/O B PPMUX.PS5=0 General-purpose input/output port
SCK9 Clock input/output pin of USART9
OR
P29_5 I/O B PPMUX.PS5=1 General-purpose input/output port
AN5 Analog input pin of A/D converter
144, 145 P29_6, P29_7 I/O B — General-purpose input/output ports
AN6, AN7 Analog input pins of A/D converter
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
18 DS07-16615-2E
146 to
149
P24_0 to P24_3
I/O B
PPMUX.PS2=0
and PP-
MUX.PR0=0
General-purpose input/output ports
INT0 to INT3 External interrupt input pins
OR
P28_0 to P28_3
I/O B
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output ports
AN8 to AN11 Analog input pins of A/D converter
150
P24_4 I/O D PPMUX.PS2=0
and PP-
MUX.PR0=0
General-purpose input/output port
INT4 External interrupt input pin
SDA2 I/O D I2C bus DATA input/output pin (open
drain)
OR
P28_4
I/O D
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
AN12 Analog input pin of A/D converter
151
P24_5 I/O D PPMUX.PS2=0
and PP-
MUX.PR0=0
General-purpose input/output port
INT5 External interrupt input pin
SCL2 I/O D I2C bus clock input/output pin (open
drain)
OR
P28_5
I/O D
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
AN13 Analog input pin of A/D converter
152
P24_6
I/O D
PPMUX.PS2=0
and PP-
MUX.PR0=0
General-purpose input/output port
INT6 External interrupt input pin
SDA3 I2C bus DATA input/output pin (open
drain)
OR
P28_6
I/O D
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
AN14 Analog input pin of A/D converter
153
P24_7
I/O C
PPMUX.PS2=0
and PP-
MUX.PR0=0
General-purpose input/output port
INT7 External interrupt input pin
SCL3 I2C bus clock input/output pin (open
drain)
OR
P28_7
I/O B
PPMUX.PS2=1
or
PPMUX.PR0=1
General-purpose input/output port
AN15 Analog input pin of A/D converter
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 19
156
P16_0
I/O A
PPMUX.PS1=0
and
PPMUX.PR10=0
General-purpose input/output port
PPG8 Output pin of PPG timer
OR
P27_0
I/O A
PPMUX.PS1=1
or
PPMUX.PR10=1
General-purpose input/output port
AN16 Analog input pin of A/D converter
157
P16_1
I/O A
PPMUX.PS1=0
and
PPMUX.PR11=0
General-purpose input/output port
PPG9 Output pin of PPG timer
OR
P27_1
I/O A
PPMUX.PS1=1
or
PPMUX.PR11=1
General-purpose input/output port
AN17 Analog input pin of A/D converter
158
P20_0
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR12=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SIN2 Data input pin of USART2
AIN0 Up/down counter input pin
OR
P27_2
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR12=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN18 Analog input pin of A/D converter
159
P20_1
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR13=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SOT2 Data output pin of USART2
BIN0 Up/down counter input pin
OR
P27_3
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR13=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN19 Analog input pin of A/D converter
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
20 DS07-16615-2E
160
P20_2
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR14=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SCK2 Clock input/output pin of USART2
ZIN0 Up/down counter input pin
CK2 External clock input pin of free-run timer
2
OR
P27_4
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR14=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN20 Analog input pin of A/D converter
161
P20_4
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR15=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SIN3 Data input pin of USART3
AIN1 Up/down counter input pin
OR
P27_5
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR15=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN21 Analog input pin of A/D converter
162
P20_5
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR16=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SOT3 Data output pin of USART3
BIN1 Up/down counter input pin
OR
P27_6
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR16=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN22 Analog input pin of A/D converter
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 21
163
P20_6
I/O A
PPMUX.PS1=0
and_not
(PP-
MUX.PR17=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
SCK3 Clock input/output pin of USART3
ZIN1 Up/down counter input pin
CK3 External clock input pin of free-run timer
3
OR
P27_7
I/O A
PPMUX.PS1=1
or
(PP-
MUX.PR17=1
and PP-
MUX.PRPS0=1)
General-purpose input/output port
AN23 Analog input pin of A/D converter
164
P07_0 I/O A PPMUX.PS0=0 General-purpose input/output port
A0 Signal pin of external address bus (bit0)
OR
P26_0 I/O A PPMUX.PS0=1 General-purpose input/output port
AN24 Analog input pin of A/D converter
165
P07_1 I/O A PPMUX.PS0=0 General-purpose input/output port
A1 Signal pin of external address bus (bit1)
OR
P26_1 I/O A PPMUX.PS0=1 General-purpose input/output port
AN25 Analog input pin of A/D converter
166
P07_2 I/O A PPMUX.PS0=0 General-purpose input/output port
A2 Signal pin of external address bus (bit2)
OR
P26_2 I/O A PPMUX.PS0=1 General-purpose input/output port
AN26 Analog input pin of A/D converter
167
P07_3 I/O A PPMUX.PS0=0 General-purpose input/output port
A3 Signal pin of external address bus (bit3)
OR
P26_3 I/O A PPMUX.PS0=1 General-purpose input/output port
AN27 Analog input pin of A/D converter
168
P07_4 I/O A PPMUX.PS0=0 General-purpose input/output port
A4 Signal pin of external address bus (bit4)
OR
P26_4 I/O A PPMUX.PS0=1 General-purpose input/output port
AN28 Analog input pin of A/D converter
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
22 DS07-16615-2E
*1: For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
*2: MB91F465PA has type A, MB91F467PA has type B
*3: A/D converter channels 37-42, 44-46 only available on MB91F467PA.
*4: CAN3 only available on MB91F467PA.
169
P07_5 I/O A PPMUX.PS0=0 General-purpose input/output port
A5 Signal pin of external address bus (bit5)
OR
P26_5 I/O A PPMUX.PS0=1 General-purpose input/output port
AN29 Analog input pin of A/D converter
170
P07_6 I/O A PPMUX.PS0=0 General-purpose input/output port
A6 Signal pin of external address bus (bit6)
OR
P26_6 I/O A PPMUX.PS0=1 General-purpose input/output port
AN30 Analog input pin of A/D converter
171
P07_7 I/O A PPMUX.PS0=0 General-purpose input/output port
A7 Signal pin of external address bus (bit7)
OR
P26_7 I/O A PPMUX.PS0=1 General-purpose input/output port
AN31 Analog input pin of A/D converter
172 P33_3 I/O A — General-purpose input/output port
PPG28 Output pin of PPG timer
173 P33_7 I/O A — General-purpose input/output port
PPG29 Output pin of PPG timer
174 P32_3 I/O A — General-purpose input/output port
PPG30 Output pin of PPG timer
175 P32_7 I/O A — General-purpose input/output port
PPG31 Output pin of PPG timer
Pin no. Pin name I/O I/O circuit
type*1Mux Function
MB91460P Series
DS07-16615-2E 23
[Power supply/Ground pins]
Pin no. Pin name I/O Function
1, 23, 45, 67, 89, 101,
106, 111, 133, 155 VSS5
Supply
Ground pins
66, 88, 110, 132, 154 VDD5 Power supply pins
108, 109 VDD5R Power supply pins for internal regulator
129 AVSS5 Analog ground pin for A/D converter
131 AVCC5 Power supply pin for A/D converter
130 AVRH5 Reference power supply pin for A/D converter
107 VCC18C Capacitor connection pin for internal regulator
22, 44, 176 VDD35 Power supply pins for external bus part of I/O ring
MB91460P Series
24 DS07-16615-2E
■I/O CIRCUIT TYPES
Type Circuit Remarks
A CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
B CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull-up control
R
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
pull- down control
driver strength
control
data line
standby control for
input shutdown
R
analog input
pull-up control
pull- down control
driver strength
control
data line
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
standby control for
input shutdown
MB91460P Series
DS07-16615-2E 25
C CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
D CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
Type Circuit Remarks
pull-up control
R
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
pull- down control
data line
standby control for
input shutdown
R
analog input
pull-up control
pull- down control
data line
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
standby control for
input shutdown
MB91460P Series
26 DS07-16615-2E
E CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
F CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
Type Circuit Remarks
pull-up control
R
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
pull- down control
driver strength
control
data line
standby control for
input shutdown
R
analog input
pull-up control
pull- down control
driver strength
control
data line
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
standby control for
input shutdown
MB91460P Series
DS07-16615-2E 27
G Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
H CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
J1 High-speed oscillation circuit:
• Programmable between oscillation mode
(external crystal or resonator connected
to X0/X1 pins) and
Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled or in FCI mode.
J2 Low-speed oscillation circuit:
• Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled.
Type Circuit Remarks
R
Hysteresis
inputs
R
Pull-up
Resistor
Hysteresis
inputs
X1
X0
R
R
Xout
FCI
0
1
FCI or osc disable
X1A
X0A
R
R
Xout
osc disable
MB91460P Series
28 DS07-16615-2E
K CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
L CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
Type Circuit Remarks
pull-up control
R
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
pull- down control
driver strength
control
data line
standby control for
input shutdown
LCD SEG/COM
R
pull-up control
pull- down control
driver strength
control
data line
CMOS hysteresis type1
Automotive inputs
TTL input
CMOS hysteresis type2
standby control for
input shutdown
VLCD
MB91460P Series
DS07-16615-2E 29
M CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
N
Analog input pin with protection
Type Circuit Remarks
tri-state control
data line
analog input line
MB91460P Series
30 DS07-16615-2E
■PORT MULTIPLEXING
1. PPMUX Register
MB91460P series uses port multiplexing. This means that there are more implemented resources than actual pins.
Which ports/resources are multiplexed to which pin depends on the PPMUX register setting.
The PPMUX register can only be written as a half-word. It is writable only once.
The PPMUX register is reset by INIT or by a soft reset (the initial value is 0x0000 then).
Note: Port relocation (via PRx) always has higher priority than Port Switching (via PSx).
2. PPMUX2 Register (MB91F467PA)
MB91F467PA has a second port multiplexing register, PPMUX2, for multiplexing of LIN-USART10,11.
The settings of PPMUX2 have priority over the settings of PPMUX.
The PPMUX2 register can only be written as a half-word. It is writable only once.
The PPMUX2 register is reset by INIT or by a soft reset (the initial value is 0x00 then).
0x049A 15 14 13 12 11 10 9 8
PR17 PR16 PR15 PR14 PR13 PR12 PR11 PR10
0x049B 76543210
PRPS0 PR0 PS5 PS4 PS3 PS2 PS1 PS0
0x049C 15 14 13 12 11 10 9 8
- - PR5 PR4 PR3 PR2 PR1 PR0
0x049D 76543210
--------
MB91460P Series
DS07-16615-2E 31
3. Multiplex Pinout MB91F465PA
MB91460P Series
32 DS07-16615-2E
4. Multiplex Pinout MB91F467PA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN42
P18_5/SOT7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN46
P18_1/SOT6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
QFP-176
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue
input,
digital input is then
disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS0)
to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
1 configbit
(PPMUX.PS4) to
switch between
external bus
(default)
or peripheral
function
(all 8 pins)
1 configbyte (PPMUX.PR17
to PPMUX.PR10) to
relocate peripheral function
(all 8 pins, but not ANxx),
external bus function is
disabled when relocated
1 configbit (PPMUX.PR0) to
relocate peripheral function
(all 8 pins, but not ANxx and
not I
2
C), external bus
function is disabled when
relocated
1 configbit
(PPMUX.PS3) to
switch between
external bus
(default) or
peripheral
function
(all 8 pins)
1 configbit
(PPMUX.PRPS0)
to
determine wether
PPMUX.PR17 to
PPMUX.PR12
relocate pins from
P20 or switch Pins
to P34
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
1 configbit
(PPMUX.PS1)
to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR) pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
if ANxx channel is enabled
(via PFR), pin is switched
to
analogue input, digital
input
is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS2)
to
switch between
the two port
layouts
1 configbit
(PPMUX.PS5)
to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
MB91V460A,
but
portfunction
PPG16-31
peripheral not
supported by
MB91V460A,
but portfunction
1 configbyte (PPMUX2.PR0
to PPMUX2.PR5) to
relocate peripheral function
(SIN10,SOT10,SCK10,
SIN11,SOT11,SCK11),
external bus function is
disabled when relocated
MB91460P Series
DS07-16615-2E 33
■RELOAD TIMER / NEW FEATURES
1. Overview
The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down.
The count length is 16 bits.
2. Features
Format: 16 bit down counter with reload register
Quantity: 16 (Output: 8 channels TOT[0 to 7])
Cascading clock mode: (only available for Reload timers 8,10,12,14)
• Count clock for Reload timer 8: Output of Reload timer 9
• Count clock for Reload timer 10: Output of Reload timer 11
• Count clock for Reload timer 12: Output of Reload timer 13
• Count clock for Reload timer 14: Output of Reload timer 15
Count active edge: When in external event mode, choose from 3 types.
• External trigger (rising /falling/both edges)
Interrupt: Request generated by underflow
Other 1: Counter stop in software/can be reopened
Other 2: Control of other peripheral functions possible
• PPG activation trigger source:
Reload timer 8 : PPG16, PPG17
Reload timer 9 : PPG18, PPG19
Reload timer 10 : PPG20, PPG21
Reload timer 11 : PPG22, PPG23
Reload timer 12 : PPG24, PPG25
Reload timer 13 : PPG26, PPG27
Reload timer 14 : PPG28, PPG29
Reload timer 15 : PPG30, PPG31
• A/D converter activation trigger source (Reload timer 7 : A/D)
MB91460P Series
34 DS07-16615-2E
3. Registers
3.1. TMCSR: Reload Timer Control Status Register
The control status register controls the operation mode of the reload timer and interrupts.
• TMCSR8 (Reload timer 8): Address: 00596H (Access: Byte, Half-word)
• TMCSR9 (Reload timer 9): Address: 0059EEH (Access: Byte, Half-word)
• TMCSR10 (Reload timer 10): Address: 005A6H (Access: Byte, Half-word)
• TMCSR11 (Reload timer 11): Address: 005AEH (Access: Byte, Half-word)
• TMCSR12 (Reload timer 12): Address: 005B6H (Access: Byte, Half-word)
• TMCSR13 (Reload timer 13): Address: 005BEH (Access: Byte, Half-word)
• TMCSR14 (Reload timer 14): Address: 005C6H (Access: Byte, Half-word)
• TMCSR15 (Reload timer 15): Address: 005CEH (Access: Byte, Half-word)
(O: can be rewritten, x: cannot be rewritten)
• bit12-10: Count clock selection CLKP: peripheral clock
15 14 13 12 11 10 9 8 bit
CSL2 CSL1 CSL0 MOD2 MOD1
---00000Initial Value
RX/WX RX/WX RX/WX R/W R/W R/W R/W0 R/W Attribute
Rewrite during
operation
76543 2 10 bit
MOD0 OULT RELD INTE UF CNTE TRG
0-000000Initial Value
R/W RX/WX R/W R/W R/W R(RM1),W R/W R0/W Attribute
OOO
Rewrite during
operation
CSL2 CSL1 CSL0 Count clock Remarks
0 0 0 Internal clock CLKP/2
0 0 1 Internal clock CLKP/8
0 1 0 Internal clock CLKP/32
0 1 1 External event (external clock)
1 0 1 Internal clock CLKP/64
1 1 0 Internal clock CLKP/128
1 1 1 RLT n+1 output only allowed for RLT 8, 10, 12, 14
MB91460P Series
DS07-16615-2E 35
3.2. TMR: Timer Register
• TMR8 (Reload timer 8): Address: 0592H (Access: Half-word)
• TMR9 (Reload timer 9): Address: 059AH (Access: Half-word)
• TMR10 (Reload timer 10): Address: 05A2H (Access: Half-word)
• TMR11 (Reload timer 11): Address: 05AAH (Access: Half-word)
• TMR12 (Reload timer 12): Address: 05B2H (Access: Half-word)
• TMR13 (Reload timer 13): Address: 05BAH (Access: Half-word)
• TMR14 (Reload timer 14): Address: 05C2H (Access: Half-word)
• TMR15 (Reload timer 15): Address: 05CAH (Access: Half-word)
3.3. TMRC: Consistent Timer Register
• TMR89 (Reload timer 8, 9): Address: 05D0H (Access: Word)
• TMR1011 (Reload timer 10, 11): Address: 05D4H (Access: Word)
• TMR1213 (Reload timer 12, 13): Address: 05D8H (Access: Word)
• TMR1415 (Reload timer 14, 15): Address: 05DCH (Access: Word)
The count values of cascaded reload timers can be read out through the timer register TMRC at the same time.
Upper halfword contain TMRn, lower halfword TMRn+1.
Please perform the read out using word access.
31 30 29 28 27 26 25 24 bit
D31 D30 D29 D28 D27 D26 D25 D24
XXXXXXXXInitial Value
R/WX R/WX R/WX R/WX R/WX R/WX R/WX R/WX Attribute
23 22 21 20 19 18 17 16 bit
D23 D22 D21 D20 D19 D18 D17 D16
XXXXXXXXInitial Value
R/WX R/WX R/WX R/WX R/WX R/WX R/WX R/WX Attribute
15 14 13 12 11 10 9 8 bit
D15 D14 D13 D12 D11 D10 D9 D8
XXXXXXXXInitial Value
R/WX R/WX R/WX R/WX R/WX R/WX R/WX R/WX Attribute
76543210 bit
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXXXInitial Value
R/WX R/WX R/WX R/WX R/WX R/WX R/WX R/WX Attribute
MB91460P Series
36 DS07-16615-2E
3.4. TMRLR: Reload register
• TMRLR8 (Reload timer 8): Address: 0590H (Access: Half-word)
• TMRLR9 (Reload timer 9): Address: 0598H (Access: Half-word)
• TMRLR10 (Reload timer 10): Address: 05A0H (Access: Half-word)
• TMRLR11 (Reload timer 11): Address: 05A8H (Access: Half-word)
• TMRLR12 (Reload timer 12): Address: 05B0H (Access: Half-word)
• TMRLR13 (Reload timer 13): Address: 05B8H (Access: Half-word)
• TMRLR14 (Reload timer 14): Address: 05C0H (Access: Half-word)
• TMRLR15 (Reload timer 15): Address: 05C8H (Access: Half-word)
4. Cascading Operation
In reload mode Reload timer 9 Output is set as Count event for Reload timer 8, both edge modes.
(1) TOUT9 signal change caused by underflow TMR9
(2) TMR8 decreased by TOUT9
(3) TOUT8 signal change caused by underflow of TMR8
n
m
0
10m
TMR
TMLR9
TMLR8
CLKP
TMR9
TOUT9
TOUT8
TMR8
n
(1)
(2) (2)
(3)
(1)
n-1
. . .
. . .
. . .
. . .
. . .
. . .
. . .
0nn-1
MB91460P Series
DS07-16615-2E 37
■ADDITIONAL PPGs
1. Register
1.1. PCSR: PPG Cycle Setting Register
Controls the cycle of the PPG.
• PCSR16 (PPG16): Address 0512h (Access: Half-word)
• PCSR17 (PPG17): Address 0518h (Access: Half-word)
• PCSR18 (PPG18): Address 0522h (Access: Half-word)
• PCSR19 (PPG19): Address 0528h (Access: Half-word)
• PCSR20 (PPG20): Address 0532h (Access: Half-word)
• PCSR21 (PPG21): Address 0538h (Access: Half-word)
• PCSR22 (PPG22): Address 0542h (Access: Half-word)
• PCSR23 (PPG23): Address 0548h (Access: Half-word)
• PCSR24 (PPG24): Address 0552h (Access: Half-word)
• PCSR25 (PPG25): Address 0558h (Access: Half-word)
• PCSR26 (PPG26): Address 0562h (Access: Half-word)
• PCSR27 (PPG27): Address 0568h (Access: Half-word)
• PCSR28 (PPG28): Address 0572h (Access: Half-word)
• PCSR29 (PPG29): Address 0578h (Access: Half-word)
• PCSR30 (PPG30): Address 0582h (Access: Half-word)
• PCSR31 (PPG31): Address 0588h (Access: Half-word)
1.2. PDUT: PPG Duty Setting Register
Sets the duty of the PPG output waveform.
• PDUT16 (PPG16): Address 0514h (Access: Half-word)
• PDUT17 (PPG17): Address 051Ch (Access: Half-word)
• PDUT18 (PPG18): Address 0524h (Access: Half-word)
• PDUT19 (PPG19): Address 052Ch (Access: Half-word)
• PDUT20 (PPG20): Address 0534h (Access: Half-word)
• PDUT21 (PPG21): Address 053Ch (Access: Half-word)
• PDUT22 (PPG22): Address 0544h (Access: Half-word)
• PDUT23 (PPG23): Address 054Ch (Access: Half-word)
• PDUT24 (PPG24): Address 0554h (Access: Half-word)
• PDUT25 (PPG25): Address 055Ch (Access: Half-word)
• PDUT26 (PPG26): Address 0564h (Access: Half-word)
• PDUT27 (PPG27): Address 056Ch (Access: Half-word)
• PDUT28 (PPG28): Address 0574h (Access: Half-word)
• PDUT29 (PPG29): Address 057Ch (Access: Half-word)
• PDUT30 (PPG30): Address 0584h (Access: Half-word)
• PDUT31 (PPG31): Address 058Ch (Access: Half-word)
1.3. PCN: PPG Control Status register
Controls the operations and status of PPGs.
• PCN16 (PPG16): Address 0516h (Access: Byte, Half-word)
• PCN17 (PPG17): Address 051Eh (Access: Byte, Half-word)
• PCN18 (PPG18): Address 0526h (Access: Byte, Half-word)
• PCN19 (PPG19): Address 052Eh (Access: Byte, Half-word)
• PCN20 (PPG20): Address 0536h (Access: Byte, Half-word)
• PCN21 (PPG21): Address 053Eh (Access: Byte, Half-word)
• PCN22 (PPG22): Address 0546h (Access: Byte, Half-word)
• PCN23 (PPG23): Address 054Eh (Access: Byte, Half-word)
• PCN24 (PPG24): Address 0556h (Access: Byte, Half-word)
MB91460P Series
38 DS07-16615-2E
• PCN25 (PPG25): Address 055Eh (Access: Byte, Half-word)
• PCN26 (PPG26): Address 0566h (Access: Byte, Half-word)
• PCN27 (PPG27): Address 056Eh (Access: Byte, Half-word)
• PCN28 (PPG28): Address 0576h (Access: Byte, Half-word)
• PCN29 (PPG29): Address 057Eh (Access: Byte, Half-word)
• PCN30 (PPG30): Address 0586h (Access: Byte, Half-word)
• PCN31 (PPG31): Address 058Eh (Access: Byte, Half-word)
1.4. GCN1: General Control register 1
Selects a trigger input to PPG0 PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31.
• GCN14 (PPG16-PPG19): Address 0500h (Access: Half-word)
• GCN15 (PPG20-PPG23): Address 0504h (Access: Half-word)
• GCN16 (PPG24-PPG27): Address 0505h (Access: Half-word)
• GCN17 (PPG28-PPG31): Address 050Ch (Access: Half-word)
1.5. GCN2: General Control register 2
Generates PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31 internal trigger levels using soft-
ware.
• GCN24 (PPG16-PPG19): Address 0503h (Access: Byte)
• GCN25 (PPG20-PPG23): Address 0507h (Access: Byte)
• GCN26 (PPG24-PPG27): Address 050Bh (Access: Byte)
• GCN27 (PPG28-PPG31): Address 050Fh (Access: Byte)
1.6. PTMR: PPG Timer Register
Reads the counts of PPGs.
• PTMR16 (PPG16): Address 0510h (Access: Half-word)
• PTMR17 (PPG17): Address 0518h (Access: Half-word)
• PTMR18 (PPG18): Address 0520h (Access: Half-word)
• PTMR19 (PPG19): Address 0528h (Access: Half-word)
• PTMR20 (PPG20): Address 0530h (Access: Half-word)
• PTMR21 (PPG21): Address 0538h (Access: Half-word)
• PTMR22 (PPG22): Address 0540h (Access: Half-word)
• PTMR23 (PPG23): Address 0548h (Access: Half-word)
• PTMR24 (PPG24): Address 0550h (Access: Half-word)
• PTMR25 (PPG25): Address 0558h (Access: Half-word)
• PTMR26 (PPG26): Address 0560h (Access: Half-word)
• PTMR27 (PPG27): Address 0568h (Access: Half-word)
• PTMR28 (PPG28): Address 0570h (Access: Half-word)
• PTMR29 (PPG29): Address 0578h (Access: Half-word)
• PTMR30 (PPG30): Address 0581h (Access: Half-word)
• PTMR31 (PPG31): Address 0588h (Access: Half-word)
MB91460P Series
DS07-16615-2E 39
■A/D CONVERTER / NEW FEATURES (MB91F467PA)
MB91F467PA has two 10-bit A/D Converter macros. The original ADC, which is available on all MB91460 series
devices, is now called “ADC 0”, the second macro is called “ADC 1”.
1. A/D Converter Features
• Both ADC 0 and ADC 1 are 10-bit / 1 μs macros used on other MB91460 series devices.
• Both ADCs have the new digital part with separated A/D Result registers and 4-channel Range Comparator,
see chapter ”A/D CONVERTER / RANGE COMPARATOR (MB91F467PA)’ on page 41.
• Both ADCs can be triggered from Reload Timer RLT7.
• Both ADCs can be triggered from the same external ATGX pin (GP16_7).
• On MB91F467PA, ADC0 and ADC1 share the same analog power and reference supply (AVCC5,AVRH5,AVSS).
2. Analog Input Connections
2.1. Global ADC Analog Channel Enable
The global ADC channel enable feature makes the ADC analog inputs independend of PFR/EPFR settings. It was
introduced for 2 reasons:
• Some new ADC channels are assigned to ports whose PFR/EPFR combinations are already used completely
for other resources.
• Customers may measure digital output signals with the ADC to check for external shortages.
PFR/EPFR settings for ADC always switch the digital port to HiZ mode.
The global ADC channel enable is controlled by bit ADCHE in PORTEN register:
PORTEN Register Address: 0x0498 Access: Byte
• Bit7-3: Reserved bits. Always write 0 to these bits.
• Bit2: ADCHE Global A/D Channel Enable.
This bit is cleared by software reset (RST) and can be written and read by CPU.
Note: For new ADC channels (AN32 to AN53, device depending), the ADCHE feature is always ON.
For old ADC channels (AN0 to AN31), the ADCHE feature is always OFF if the channels are re-located to
other pins. On MB91F467PA, the ADCHE feature is only available on the non-relocated ADC channels 6-7
on ports P29[6,7].
765432 1 0 Bit
-----ADCHE CPORTEN GPORTEN
XXXXX0 0 0Initial value
RX, W0 RX, W0 RX, W0 RX, W0 RX, W0 R, W R, W R, W Attribute
ADCHE Function
0 [initial]
Global A/D Channel Enable is OFF.
The ADC analog lines of channels 0-31 are enabled by setting of the ADC enable bits (ADEn)
in the ADERH,ADERL register and PFR/EPFR. PFR/EPFR will set the digital output to HiZ
mode and disable the digital input lines of the port.
1
Global A/D Channel Enable is ON.
The ADC analog lines of channels 6-7 are enabled by setting of the ADC enable bits (ADEn)
in the ADERH,ADERL register only. ADEn will disable the digital input lines of the port, but
the digital outputs are not changed. For analog measurement, the user has to switch the port
to input direction.
MB91460P Series
40 DS07-16615-2E
• Bit1:0: CPORTEN,GPORTEN Global Port Input Enable
- These bits are cleared by software reset (RST) and can be written and read by CPU.
- After execution of the Boot ROM the bits are in initial state.
2.2. ADC 0 Analog Inputs
ADC 0 serves the analog inputs AN0 to AN31. There are 2 methods for enabling the analog inputs:
• For all channels: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set PFR/EPFR of
the attached I/O port
• For channels 6-7: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set global ADC
channel enable, see ”Global ADC Analog Channel Enable’ on page 39.
Note : To use the channels AN0 to AN5 and AN8 to AN31, port multiplexing must be set. See chapter ”PORT
MULTIPLEXING’ on page 30 and chapter ”PIN DESCRIPTION’ on page 8 for details. The ADC channel
enable feature ADCHE is not available on the re-located channels.
2.3. ADC 1 Analog Inputs
ADC 1 serves the analog inputs AN37 to AN42, AN44 to AN46.
The analog inputs are enabled just by setting the ADC channel enable bits ADEn in the AD1ERH, AD1ERL regis-
ters. The Global ADC Analog Channel Enable feature is fixed ON here.
CPORTEN GPORTEN Function
0 [initial] 0 [initial] All port input lines are disabled.
10
The Port Input for LIN-USART 4 is enabled. This functionality is used by the
Boot ROM to establish a serial communication with Softune for flash pro-
gramming.
X 1 All port input lines are enabled.
MB91460P Series
DS07-16615-2E 41
■A/D CONVERTER / RANGE COMPARATOR (MB91F467PA)
The new A/D Converter with Range Comparator is available on MB91FV460B and MB91F467PA and is backward
compatible to the A/D converter used on older devices.
This chapter provides an overview of the A/D converter, describes the register structure and functions, and
describes the operation of the A/D converter.
1. Overview of A/D Converter and A/D Range Comparator
The A/D converter converts analog input voltages into digital values and provides the following features. Any
ADC channel can be assigned to one of 4 Range Comparators.
1.1. Features of the A/D converter:
• Conversion time: minimum 1μs per channel.
• RC type successive approximation conversion with sample & hold circuit
• 10-bit or 8-bit resolution
• Program section analog input from 32 channels
• 1 common result data register and 32 dedicated channel result data registers
• Single conversion mode: Convert the specified channel(s) only once.
• Continuous mode: Repeatedly convert the specified channels.
• Scan conversion mode: Continuous conversion of multiple channels, programmable for up to 32 channels
• Stop mode: Convert one channel, then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
• A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that
is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to
memory.
• A/D conversion of all enabled channels (scan conversion) can be followed by an A/D End of Scan interrupt
request to CPU. The data is stored into dedicated channel result registers, which can be read out using DMA
transfer.
• Conversion startup may be by software, external trigger (falling edge) or timer (rising edge).
1.2. Features of the A/D Range Comparator (RCO):
• 4 conversion result Range Comparator channels, comparing the upper 8 bit of the conversion result with an
upper and a lower threshold. The thresholds are programmable for the 4 comparators independently.
• Any ADC channel can be assigned to one of the 4 range comparators.
• The comparison results will set “overflow” and “interrupt” flags per ADC channel, depending on the configu-
ration. It is possible to configure the comparison for:
- “out of range”: The flags are set if the A/D result is below the lower OR above the upper threshold.
- “inside range”: The flags are set if the A/D result is above the lower AND below the upper threshold.
• The configuration can be set individually per ADC channel.
• Range comparison can be followed by an A/D Range Comparator interrupt request to CPU.
2. A/D Converter Input Impedance
The following figure shows the sampling circuit of the A/D converter:
Analog
signal
source
Rext Rin
Cin
ADC
ANx
Analog SW
Do not set Rext over maximum sampling time (Tsamp).
Rext = Tsamp / (7*Cin) - Rin
MB91460P Series
42 DS07-16615-2E
3. Block Diagram of A/D Converter
The following figure shows block diagram of A/D converter.
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN1 0
AN1 1
AN1 2
AN1 3
AN1 4
AN1 5
AN1 6
AN1 7
AN1 8
AN1 9
AN2 0
AN2 1
AN2 2
AN2 3
AN2 4
AN2 5
AN2 6
AN2 7
AN2 8
AN2 9
AN3 0
AN3 1
MPX
Input Circuit
D/ A co n ve rt e r
A/ D d a t a r e g is t e r
Se q u e n t ia l
comparison register
R - Bus
Comparator
Sam p le & Hold
circuit
A/D control register 0
A/D control register 1
Prescaler
ADC S 0 / 1
Operating
Clock
AVCC AVRH AVRL AVSS
ATGX
16- b it
Re lo a d Tim e r
CLKP
Decoder
A/D control register 2
32
A/D channel
data registers
ADCD00
to
ADCD31
ADC
Range
Comparator
4 digital
comparators
with upper
and lower
threshold
32 * 2 flags
(2 flags per
ADC channel)
RCO INT
INT2
INT
RCO Flags
MB91460P Series
DS07-16615-2E 43
4. Registers of the A/D Converter
The A/D converter with Range Comparator has the following registers:
Address
(ADC 0)
Address
(ADC 1)
x=0 or 1 for ADC0, ADC1 respectively Register
+0 +1 +2 +3
0001A0H0005E0HADxERH ADxERL A/D channel Enable register
0001A4H0005E4HADxCS1 ADxCS0 ADxCR1 ADxCR0 A/D Control / Status register 0 + 1,
A/D Conversion Result register
0001A8H0005E8HADxCT1 ADxCT0 ADxSCH ADxECH
Sampling timer setting register,
Start Channel setting register,
End Channel setting register
0006B0H0006DCHADxCS2 - - - A/D Control / Status register 2
000688H0006B4HRCOxH0 RCOxL0 RCOxH1 RCOxL1 Range Comparator 0,1 High/Low threshold
registers
00068CH0006B8HRCOxH2 RCOxL2 RCOxH3 RCOxL3 Range Comparator 2,3 High/Low threshold
registers
000690H0006BCHRCOxIRS Range Comparator Inverted Range Select
control
000694H0006C0HRCOxOF Range Comparator Overflow flags
000698H0006C4HRCOxINT Range Comparator Interrupt flags
0006A0H0006CCHADxCC0 ADxCC1 ADxCC2 ADxCC3 Channel control for ch 0 to 7
0006A4H0006D0HADxCC4 ADxCC5 ADxCC6 ADxCC7 Channel control for ch 8 to 16
0006A8H0006D4HADxCC8 ADxCC9 ADxCC10 ADxCC11 Channel control for ch 16 to 23
0006ACH0006D8HADxCC12 ADxCC13 ADxCC14 ADxCC15 Channel control for ch 24 to 31
0006E0H000720HADCxD0 ADCxD1 ADC Channel Data register, channel 0,1
0006E4H000724HADCxD2 ADCxD3 ADC Channel Data register, channel 2,3
0006E8H000728HADCxD4 ADCxD5 ADC Channel Data register, channel 4,5
0006ECH00072CHADCxD6 ADCxD7 ADC Channel Data register, channel 6,7
0006F0H000730HADCxD8 ADCxD9 ADC Channel Data register, channel 8,9
0006F4H000734HADCxD10 ADCxD11 ADC Channel Data register, channel 10,11
0006F8H000738HADCxD12 ADCxD13 ADC Channel Data register, channel 12,13
0006FCH00073CHADCxD14 ADCxD15 ADC Channel Data register, channel 14,15
000700H000740HADCxD16 ADCxD17 ADC Channel Data register, channel 16,17
000704H000744HADCxD18 ADCxD19 ADC Channel Data register, channel 18,19
000708H000748HADCxD20 ADCxD21 ADC Channel Data register, channel 20,21
00070CH00074CHADCxD22 ADCxD23 ADC Channel Data register, channel 22,23
000710H000750HADCxD24 ADCxD25 ADC Channel Data register, channel 24,25
000714H000754HADCxD26 ADCxD27 ADC Channel Data register, channel 26,27
000718H000758HADCxD28 ADCxD29 ADC Channel Data register, channel 28,29
00071CH00075CHADCxD30 ADCxD31 ADC Channel Data register, channel 30,31
MB91460P Series
44 DS07-16615-2E
4.1. A/D Input Enable Register (ADER)
This register enables the analog input functions of the A/D converter. On MB91F467PA, additionally the bit
ADCHE in PORTEN register influences the enabling of analog input.
•ADERH : Access: Word, Half-word, Byte
•ADERL : Access: Word, Half-word, Byte
[ADE31-0]: A/D Input Enable
• Software reset (RST) clears ADEn and PORTEN.ADCHE to 0.
• Be sure to set start channel and end channel to cover all enabled channels.
31 30 29 28 27 26 25 24 Bit
ADE31 ADE30 ADE29 ADE28 ADE27 ADE26 ADE25 ADE24
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
23 22 21 20 19 18 17 16 Bit
ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
15 14 13 12 11 10 9 8 Bit
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
76543210Bit
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
ADEn PORTEN.ADCHE Function
0 [initial] X Analog input of A/D channel n is disabled.
The ADC will not sample/convert this channel.
1
0 [initial]
Analog input of the channel n is enabled. Additionally, the port function register
(PFR,EPFR) of the corresponding port must be set . The PFR/EPFR will switch
the port to input direction (output driver = HiZ) and disable the digital input lines.
1
Analog input of the channel n is enabled. Setting the port function register(s) is
not necessary. ADEn will disable the digital input lines of the ports, but it does
not change the port’s direction.
MB91460P Series
DS07-16615-2E 45
4.1. A/D Control Status Registers (ADCS2, ADCS1, ADCS0)
The A/D control status registers control and show the status of A/D converter. Do not overwrite ADCS0 register
during A/D converting.
•ADCS2 : Access: Byte
[bits 15:12] BUSY, INT, INTE, PAUS
These bits are a mirror of the corresponding bits in ADCS1, intended to quickly read out all status and interrupt
information using only one register access. To write the bits, access them via ADCS1.
[bits 11:10] -
These bits do not exist. Read operation returns 0.
[bit 9] INT2 (End of Scan Flag)
The End of Scan flag is set when conversion data of the last channel is stored in ADCR, whereas the last channel
is defined by ADECH register setting.
• If bit 8 (INTE2) is "1" when this bit is set, and the ADC runs in continuous conversion mode, an End of Scan
interrupt request is generated or, if activation of DMA is enabled, DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a reset.
• If DMA is used, this bit is cleared at the end of DMA transfer.
• Read-modify-write operations read this bit as “1”.
[bit 8] INTE2 (Enable End of Scan Interrupt)
INTE2 enables the End of Scan interrupt in continuous conversion mode. In the other conversion modi, this bit
has no effect.
Additionally, setting INTE2 changes the protect function of converted data (see description of ADCS1.PAUS).
15 14 13 12 11 10 9 8 Bit
BUSY INT INTE PAUS - - INT2 INTE2
00000000Initial value
R R R R R0 R0 R/W R/W Attribute
INTE2 Function
0 [initial] Disable End of Scan interrupt,
ADC result protection protects the ADCR register data.
1
Enable End of Scan interrupt,
ADC result protection protects the ADCD0...ADCD31 register data
(in continuous conversion mode only)
MB91460P Series
46 DS07-16615-2E
•ADCS1 : Access: Half-word, Byte
[bit 15] BUSY (busy flag and stop)
• Read-modify-write instructions read the bit as "1".
• Cleared on the completion of A/D conversion in single conversion mode.
• In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".
• Initialized to "0" by a software reset (RST).
• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 14] INT (End of Conversion Interrupt flag)
This bit is set when conversion data is stored in ADCR.
• If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is enabled,
DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a software reset (RST).
• If DMA is used, this bit is cleared at the end of DMA transfer.
[bit 13] INTE (End of Conversion Interrupt enable)
This bit is enables or disables the conversion completion interrupt.
• Cleared by a software reset (RST).
15 14 13 12 11 10 9 8 Bit
BUSY INT INTE PAUS STS1 STS0 STRT reserved
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
BUSY Function
Reading A/D converter operation indication bit. Set on activation of A/D conversion
and cleared on completion.
Writing Writing "0" to this bit during A/D conversion forcibly terminates conversion.
Use to forcibly terminate in continuous and stop modes.
INTE Function
0 Disable interrupt [Initial value]
1 Enable interrupt
MB91460P Series
DS07-16615-2E 47
[bit 12] PAUS (A/D converter pause)
This bit is set when A/D conversion temporarily halts.
The A/D converter has one register to store the conversion result (ADCR) and additionally 32 ADC channel data
registers. If a conversion is finished and the data of the previous conversion has not been read out before,
previous data would be overwritten.
To avoid this problem, the next conversion data is not stored in the data registers until the previous value has
been read out (e.g. by DMA). A/D conversion halts during this time. A/D conversion resumes when the ADC
interrupt flag ADCR1.INT is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
• In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for
writing to the registers, but IRQ2 (End of Scan interrupt) is active.
• In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,
but IRQ (End of Conversion) is active.
• PAUS is cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting
condition of DMA transfer, this bit cannot be cleared.
• Regarding protect function of converted data, see Section “6. Operation of A/D Converter".
[bit 11, 10] STS1, STS0 (Start source select)
These bits select the A/D activation source.
• These bits are initialized "00" by software reset (RST).
• In multiple-activation modes, the first activation to occur starts A/D conversion.
• The activation source changes immediately on writing to the register. Therefore care is required when switching
activation mode during A/D operation.
• The A/D converter detects falling edges on the external trigger pin. When external trigger level is "L" and if
these bits are changed to external trigger activation mode, A/D converting may starts.
• Selecting the timer selects the 16-bit reload timer 7.
Mode INTE2 Function
Single,
Stop X Protect ADCR (the common result register)
Continuous 0 Protect ADCR (the common result register)
1 Protect ADCD0...ADCD31 (the dedicated channel data registers)
STS1 STS0 Function
0 0 Software activation [Initial value]
0 1 External trigger pin activation and software activation
1 0 Timer activation and software activation
1 1 External trigger pin activation, timer activation and software activation
MB91460P Series
48 DS07-16615-2E
[bit 9] STRT (Start)
Writing "1" to this bit starts A/D conversion (software activation).
• Write "1" again to restart conversion.
• Initialized to "0" by a software reset (RST).
• In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate conversion
after clearing.)
• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 8] reserved bit
Always write "0" to this bit.
•ADCS0 : Access: Half-word, Byte
[bit 7, 6] MD1, MD0 (A/D converter mode set)
These bits the operation mode.
• Single mode: A/D conversion is continuous performed from the selected start channel (ADSCH)
to the selected end channel (ADECH). The conversion stops once it has been done
for all these channels.
• Continuous mode: A/D conversion is repeatedly performed from the selected start channel (ADSCH)
to the selected end channel (ADECH) in a row.
• Stop mode: A/D conversion is performed from the selected start channel (ADSCH) to
the selected end channel (ADECH), followed by a pause after each channel.
The conversion is resumed upon activation.
When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped
by the BUSY bit.
Conversion is stopped by writing "0" to the BUSY bit.
On activation after forcibly stopping, conversion starts from the start channel, selected by ADSCH register.
Reactivation during A/D conversion is disabled for any of the timer, external trigger and software start sources
in single mode 2, continuous and stop mode.
76543210Bit
MD1 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 /
ACHMD
00000000Initial value
R/WR/WR/WRRRRR,W Attribute
MD1 MD0 Operating mode
0 0 Single mode 1 (Reactivation during A/D conversion is allowed)
0 1 Single mode 2 (Reactivation during A/D conversion is not allowed)
1 0 Continuous mode (Reactivation during A/D conversion is not allowed)
1 1 Stop mode (Reactivation during A/D conversion is not allowed)
MB91460P Series
DS07-16615-2E 49
[bit 5] S10
This bit defines resolution of A/D conversion. If this bit set "0", the resolution is 10-bit. In the other case, resolution
is 8-bit and the conversion result is stored to ADCR0 and in the lower 8 bits of the dedicated ADC result registers.
• Initialized to "0" by a reset.
[bit 4 to 0] ACH4-0 (Analog convert select channel, read-only)
These bits show the number of the currently or previously converted analog channel, depending on bit ACHMD
(see below).
• Writing these bits has no effect (bit 0 is writable with special function ADCHMD).
• Initialized to "0000" by software reset (RST).
[bit 0] ACHMD (ACH register mode, write-only)
For reading out the ACH4-0 register bits (see below), there is a direct mode and a latched mode.
In direct mode, ACH4-0 shows the number of the ADC channel which is currently in conversion, e.g. the internal
conversion channel pointer. This pointer is incremented immediately after a conversion is finished.
In latched mode, ACH4-0 shows the number of the ADC channel whose conversion was finished previously.
After a conversion is finished, the conversion channel pointer is latched and the latched data can be read in this
mode. At the end of the next conversion, the latch is overwritten if no PAUSE condition exists.
• ACHMD is a write-only bit.
• Read- or read-modify-write access returns the value of bit ACH0, see below.
• Initial value is 0.
ACH4 ACH3 ACH2 ACH1 ACH0 Converted channel
00000 AN0
00001 AN1
... ...
11110 AN30
11111 AN31
ACHMD Function
0 Direct ACH register mode [Initial value]
1 Latched ACH register mode
MB91460P Series
50 DS07-16615-2E
4.2. Common Data Register (ADCR1, ADCR0)
These registers store the conversion results of the A/D converter. ADCR0 stores lower 8-bit. ADCR1 stores
upper 2-bit. The register values are updated at the completion of each conversion. The registers normally store
the results of the previous conversion.
•ADCR1 : Access: Word, Half-word, Byte
•ADCR0 : Access: Word, Half-word, Byte
• Bit 15 to 10 of ADCR1 are read as "0".
• The A/D converter has a conversion data protection function. See the "Operation" section for further informa-
tion.
4.3. Dedicated A/D Channel Data Register (ADCD0 to ADCD31)
There are 32 ADC result data registers, one per channel. The registers are written by hardware at the end of
conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
•ADCD0 ... ADCD31 : Access: Word, Half-word, Byte
• Bit 15 to 10 of the ADCD registers are read as "0".
• The A/D converter has a conversion data protection function. In continuous conversion mode, the protection
function can be changed to protect the A/D Channel Data registers rather then the A/D Data Register (ADCR1).
See section “6.6. Protection of the ADC Channel Data Registers" for further information.
15 14 13 12 11 10 9 8 Bit
------D9D8
000000XXInitial value
R0, W0 R0, W0 R0, W0 R0, W0 R0, W0 R0, W0 R R Attribute
76543210Bit
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXXXInitial value
RRRRRRRRAttribute
15 14 13 12 11 10 9 8 Bit
------D9D8
000000XXInitial value
R0 R0 R0 R0 R0 R0 R R Attribute
76543210Bit
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXXXInitial value
RRRRRRRRAttribute
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DS07-16615-2E 51
4.4. Sampling Timer Setting Register (ADCT)
ADCT register controls the sampling time and comparison time of analog input. This register sets A/D conversion
time. Do not update value of this register during A/D conversion operation.
•ADCT1: Access: Word, Half-word, Byte
•ADCT0: Access: Word, Half-word, Byte
[bit 15 to 10] CT5-0 (A/D comparison time set)
These bits specify clock division of comparison time.
• Setting "000001" means one division (=CLKP).
• Do not set these bits "000000".
• Initialized these bits to "000100" by software reset (RST).
• Comparison time = CT value * CLKP cycle * 10 + (4 * CLKP)
• Do not set comparison time over 500 μs.
[bit 9 to 0] ST9-0 (Analog input sampling time set)
These bits specify sampling time of analog input.
• Initialized these bits to "0000101100" by software reset (RST).
• Sampling time = ST value * CLKP cycle
• Do not set sampling time below 1.2 μs when AVCC is below 4.5 V.
Necessary sampling time and ST value are calculated by following.
• Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7
• ST9 to ST0 = Tsamp / CLKP cycle
ST has to be set that sampling time is over Tsamp.
Example: CLKP = 32MHz, AVCC >= 4.5V, Rext = 200KΩ
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [μs]
ST = 15.17-6 / 31.25-9 = 485.44
ST has to be set over 486D (111100110B).
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.
15 14 13 12 11 10 9 8 Bit
CT5CT4CT3CT2CT1CT0ST9ST8
00010000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
76543210Bit
ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
00101100Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
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52 DS07-16615-2E
4.5. A/D Channel Setting Register (ADSCH, ADECH)
These registers specify the channels for the A/D converter to convert. Do not update these registers while the
A/D converting is operating.
•ADSCH: Access: Word, Half-word, Byte
•ADECH : Access: Word, Half-word, Byte
These bits set the start and end channel for A/D converter.
• Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 specifies conversion for that channel only.
(Single conversion)
• In continuous or stop mode, conversion is performed up to the channel specified by ANE4 to ANE0. Conversion
then starts again from the start channel specified by ANS4 to ANS0.
• If ANS > ANE, conversion starts with the channel specified by ANS, continuous up to channel 31, starts again
from channel 0, and ends with the channel specified by ANE.
• Initialized to ANS="00000", ANE="00000" by a software reset (RST).
Example: Channel Setting ANS=30ch, ANE=3ch, single conversion mode
Operation : Conversion channel 30ch -> 31ch -> 0ch -> 1ch -> 2ch -> 3ch end
[bit 12 to 8] ANS4-0 (Analog start channel set)
[bit 4 to 0] ANE4-0 (Analog end channel set)
15 14 13 12 11 10 9 8 Bit
- - - ANS4 ANS3 ANS2 ANS1 ANS0
- - -00000Initial value
RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Attribute
76543210Bit
- - - ANE4 ANE3 ANE2 ANE1 ANE0
- - -00000Initial value
RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Attribute
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0 Start / End Channel
00000 AN0
00001 AN1
00010 AN2
00011 AN3
... ...
11101 AN29
11110 AN30
11111 AN31
MB91460P Series
DS07-16615-2E 53
5. Range Comparator
5.1. Range Comparator Structure
The Range Comparator has 4 comparison groups with an upper and a lower threshold register each. The 32
ADC channels can be enabled for range comparison and assigned to one of the 4 comparators individually. If
enabled, the comparison will set up to 2 flags for this ADC channel:
• An interrupt flag RCOINT, signalling that the ADC result is outside the range or, by “inverted” configuration,
inside the range.
• An overflow flag RCOOF, showing that the range violation was an overflow and no underflow.
Furthermore, each ADC channel can be enabled to send an interrupt request to the CPU, if the RCOINT flag is set.
RCOH0[7:0]
RCOL0[7:0]
>
<
Upper/lower threshold regs Comparators
Flag
setting
logic
RCOH1[7:0]
RCOL1[7:0]
>
<
RCOH2[7:0]
RCOL2[7:0]
>
<
RCOH3[7:0]
RCOL3[7:0]
>
<
A/D Conversion result SAR[9:2]
AS[4:0] A/D Conversion current channel number
A/D Conversion result register load pulse (strobe)
ADCC0 : RCOIE, RCOE, RCOS[1:0]
A/D Channel Control registers (per ADC channel)
ADCC1 : RCOIE, RCOE, RCOS[1:0]
ADCC2 : RCOIE, RCOE, RCOS[1:0]
ADCC3 : RCOIE, RCOE, RCOS[1:0]
ADCC30 : RCOIE, RCOE, RCOS[1:0]
ADCC31 : RCOIE, RCOE, RCOS[1:0]
...
RCOS[1:0]: Select one of the 4 comparators for this channel
RCOE : Enable Comparision for this ADC channel
RCOIE: Enable Comparision Interrupt for this ADC channel
RCOOF
[0:31]
32
Overflow
flags
RCOINT
[0:31]
32
Interrupt
flags
OR RCOIRQ
to R-Bus
to R-Bus
RCOIE[0:31]
ADE[31:0] A/D Channel Enable AND
RCOIRS[0:31]
Inverted Range Selection register:
Set the ags, if the ADC result is
inside upper and lower threshold,
instead of outside upper or lower
threshold (default).
MB91460P Series
54 DS07-16615-2E
5.2. Range Comparator Registers
The Range Comparator (RCO) has the following registers:
• RCOHx[7:0] : Upper threshold register, one register per comparator block (x = 0...3)
• RCOLx[7:0] : Lower threshold register, one register per comparator block (x = 0...3)
• ADCCm[7:0] : ADC channel control, one register per 2 ADC channels (m = 0...15)
• RCOIRS[0:31] : RCO Inverted Range Selection, one bit per ADC channel
• RCOOF[0:31] : RCO Overflow Flags, one bit per ADC channel, read-only
• RCOINT[0:31] : RCO Interrupt Flags, one bit per ADC channel
5.2.1. Range Comparator Threshold registers (RCOH0/L0 to RCOH3/L3)
•RCOH0-3 : Higher threshold, access: Word, Half-word, Byte
[bit 7:0] RCOH[7:0] (Range Comparator High threshold)
The RCOH bits define the higher comparison threshold of the Range Comparator channel.
The upper Range Comparator compares that the upper 8 bits of the ADC conversion result are higher then
RCOH[7:0] .
•RCOL0-3 : Lower threshold, access: Word, Half-word, Byte
[bit 7:0] RCOL[7:0] (Range Comparator Low threshold)
The RCOL bits define the lower comparison threshold of the Range Comparator channel.
The lower Range Comparator compares that the upper 8 bits of the ADC conversion result are lower then
RCOL[7:0] .
15 14 13 12 11 10 9 8 Bit
RCOH7 RCOH6 RCOH5 RCOH4 RCOH3 RCOH2 RCOH1 RCOH0
11111111Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
76543210Bit
RCOL7 RCOL6 RCOL5 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
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DS07-16615-2E 55
5.2.2. A/D Converter Channel Control registers (ADCC0 to ADCC15)
The A/D channel control registers serve 2 ADC channels per register and control the range comparison for these
channels.
ADCC0 register controls A/D channels 0 + 1,
ADCC1 register controls A/D channels 2 + 3,
...
ADCC15 register controls A/D channels 30 + 31
•ADCC0-15: Access: Word, Half-word, Byte
[bit 7,3] RCOIE1, RCOIE0 (Range Comparator Interrupt enable)
The RCOIE bits enable the Range Comparator interrupt for the corresponding ADC channel.
[bit 6,2] RCOE1, RCOE0 (Range Comparator operation enable)
The RCOE bits enable the Range Comparison for the corresponding ADC channel:
[bits 5:4,1:0] RCOS1[1:0], RCOS0[1:0] (converter channel select)
These bits select the A/D converter channel to be assigned to the Range Comparator channel:
76543210Bit
RCOIE1 RCOE1 RCOS11 RCOS10 RCOIE0 RCOE0 RCOS01 RCOS00
00000000Initial value
R/WR/WR/WR/WR/WR/WR/WR/WAttribute
Bits 7:4 control A/D channels 1,3,5,7,...31 Bits 3:0 control A/D channels 0,2,4,6,...,30
RCOIE Function
0 RCO interrupt for this ADC channel is disabled [default]
1 RCO interrupt for this ADC channel is enabled
RCOE Function
0RCO disabled,
RCO flags for this ADC channel will not be set [default]
1 RCO enabled for this ADC channel
RCOS[1:0] Function
00 Select range comparator channel 0 for this ADC channel [default]
01 Select range comparator channel 1 for this ADC channel
10 Select range comparator channel 2 for this ADC channel
11 Select range comparator channel 3 for this ADC channel
MB91460P Series
56 DS07-16615-2E
5.2.3. Inverted Range Selection register
The RCOIRS register controls that the comparison should check for “out of range” or “inside range”.
The 32 bits of RCOIRS is organized “per ADC channel”. ADC channel 0 is located on the MSB of the register
and ADC channel 31 is on the LSB.
•RCOnIRS : Access: Word, Half-word, Byte
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOIRS[0:31] (Inverted Range Select)
The RCOIRS bits control how the Range Comparator result flags are set.
• If the RCOIRS[n] is 0, the flags are set when the ADC result is above the upper threshold
OR below the lower threshold. That is called “out of range” mode.
• If the RCOIRS[n] is 1, the flags are set when the ADC result is below or equal the upper threshold
AND above or equal the lower threshold. That is called “inside range” mode.
31 30 29 28 27 26 259 24 Bit
RCOIRS0 RCOIRS1 RCOIRS2 RCOIRS3 RCOIRS4 RCOIRS5 RCOIRS6 RCOIRS7
00000000Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
23 22 21 20 19 18 17 16 Bit
RCOIRS8 RCOIRS9 RCOIRS10 RCOIRS11 RCOIRS12 RCOIRS13 RCOIRS14 RCOIRS15
00000000Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
15 14 13 12 11 10 9 8 Bit
RCOIRS16 RCOIRS17 RCOIRS18 RCOIRS19 RCOIRS20 RCOIRS21 RCOIRS22 RCOIRS23
00000000Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
76543210Bit
RCOIRS24 RCOIRS25 RCOIRS26 RCOIRS27 RCOIRS28 RCOIRS29 RCOIRS30 RCOIRS31
00000000Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
RCOIRSn Function
0 Range comparison for this ADC channel checks for “out of range” (default)
1 Range comparison for this ADC channel checks for “inside range”
MB91460P Series
DS07-16615-2E 57
5.2.4. Range Comparator Result Flags
The result of range comparison is stored in 2 flag registers:
• RCOINT[0:31]: Range comparison interrupt flags
• RCOOF[0:31]: Range comparison overflow flags
The Range Comparator Result flags are organized “per ADC channel”. There are 32 Range Comparator overflow
flags and 32 interrupt flags. In case of a RCO interrupt, all interrupt flags can be read out by one 32-bit read
operation and analyzed using the Bit Search Unit. The Bit Search Unit will return the number of the interrupting
channel. Since bit search works from MSB to LSB (from left to right), ADC channel 0 is located on the MSB of
the registers and ADC channel 31 is on LSB.
•RCOnINT : Access: Word, Half-word, Byte
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOINT[0:31] (Range Comparator Interrupt flags)
The RCOINT flags show that a “out of range” or “inside range” condition has been found on the ADC channel.
The bits are set under the following condition:
• the ADC channel is enabled ADER.ADE[i] is set and
• the range comparison for this channel is enabled ADCCn.RCOE[i] is set and
• the conversion of the ADC channel is just finished and
• an interrupt condition was found (see the table on next page).
• The bits are cleared by writing 0 or by software reset (RST). Writing 1 has no effect.
• Read-modify-write operations read 1.
31 30 29 28 27 26 259 24 Bit
RCOINT0 RCOINT1 RCOINT2 RCOINT3 RCOINT4 RCOINT5 RCOINT6 RCOINT7
00000000Initial value
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute
23 22 21 20 19 18 17 16 Bit
RCOINT8 RCOINT9 RCOINT10 RCOINT11 RCOINT12 RCOINT13 RCOINT14 RCOINT15
00000000Initial value
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute
15 14 13 12 11 10 9 8 Bit
RCOINT16 RCOINT17 RCOINT18 RCOINT19 RCOINT20 RCOINT21 RCOINT22 RCOINT23
00000000Initial value
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute
76543210Bit
RCOINT24 RCOINT25 RCOINT26 RCOINT27 RCOINT28 RCOINT29 RCOINT30 RCOINT31
00000000Initial value
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute
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58 DS07-16615-2E
The interrupt condition depends on the comparison results and the RCOIRS setting for this channel:
Note: The upper threshold comparator returns 1 if the upper 8 bits of the ADC result are greater then the threshold
value in RCOH[7:0].
The lower threshold comparator returns 1 if the upper 8 bits of the ADC result are smaller then the threshold
value in RCOL[7:0].
•RCOnOF : Access: Read-only, Word, Half-word, Byte
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOOF[0:31] (Range Comparator Overflow flag)
The RCOOF read-only flags store the output signal of the upper threshold comparator at the time when an
interrupt condition (see above) appeared and the corresponding RCOINT flag was not set. So the RCOOF flags
indicate the upper comparator state when the RCOINT flag had the last rising edge.
Mode RCOIRS
Upper
threshold
comparator
Lower
threshold
comparator
Interrupt condition
out of
range 0
1 x INT condition: above range, RCOOF is set
00-
x 1 INT condition: below range, RCOOF is cleared
inside
range 1
1x-
0 0 INT condition: inside range
x1-
31 30 29 28 27 26 259 24 Bit
RCOOF0 RCOOF1 RCOOF2 RCOOF3 RCOOF4 RCOOF5 RCOOF6 RCOOF7
00000000Initial value
RRRRRRRRAttribute
23 22 21 20 19 18 17 16 Bit
RCOOF8 RCOOF9 RCOOF10 RCOOF11 RCOOF12 RCOOF13 RCOOF14 RCOOF15
00000000Initial value
RRRRRRRRAttribute
15 14 13 12 11 10 9 8 Bit
RCOOF16 RCOOF17 RCOOF18 RCOOF19 RCOOF20 RCOOF21 RCOOF22 RCOOF23
00000000Initial value
RRRRRRRRAttribute
76543210Bit
RCOOF24 RCOOF25 RCOOF26 RCOOF27 RCOOF28 RCOOF29 RCOOF30 RCOOF31
00000000Initial value
RRRRRRRRAttribute
MB91460P Series
DS07-16615-2E 59
The RCOOF flag for a ADC channel is loaded with the upper threshold comparator output signal under the
following condition:
• the corresponding RCOINT flag is not yet setand
• the corresponding RCOINT flag has a set condition in this cycle.
The flags are initialized by software reset (RST).
5.3. Range Comparator Interrupt request
The Range Comparator has one interrupt output line RCOIRQ. The interrupt output line becomes active if at
least one of the Range Comparator interrupt flags RCOINT[31:0] is set and the corresponding interrupt enable
bit in the ADCC registers is set.
It is not possible to activate a DMA request from the range comparator interrupts.
RCOOFn Function
0 The output of the upper threshold comparator was 0 [default]
1 The output of the upper threshold comparator was 1
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6. Operation of A/D Converter
The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. There is
one 16-bit register provided to store conversion results (ADCR), which is updated each time conversion com-
pletes. Additionally, there is one ADC Channel Data register per channel (ADCD0...31), which is updated each
time the assigned channel is converted. The Channel Data registers especially improve the continuous conversion
mode.
It is recommended to use the DMA service. The following describes the operation modes.
6.1. Single Mode
In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted in
order until the completion of conversion on the end channel determined by the ANE bits. A/D conversion then
ends. If the start channel and end channel are the same (ANS=ANE), only a single channel conversion is
performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
• ANS=00010b, ANE=00010b
Start -> AN2 -> End
6.2. Continuous Mode
In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in order until
the completion of conversion on the end channel determined by the ANE bits, then the converter returns to the
ANS channel for analog input and repeats the process continuously. When the start and end channels are the
same (ANS=ANE), conversion is performed continuously for that channel.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 ... -> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> AN2 -> AN2 ... -> repeat
In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit forcibly
stops the conversion operation.) Note that forcibly terminating operation halts the current conversion during mid-
conversion. (If operation is forcibly terminated, the value in the conversion register is the result of the most
recently completed conversion.)
6.3. Stop Mode
In stop mode the analog input signal selected by the ANS bits and ANE bits are converted in order, but conversion
operation pauses after each channel. The pause is released by applying another start signal.
At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the
ANS channel for analog input signal and repeats the conversion process continuously. When the start and end
channel are the same (ANS=ANE), only a signal channel conversion is performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> stop -> start -> AN1 -> stop -> start -> AN2 -> stop -> start -> AN3 -> stop -> start -> AN0 ...
-> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> stop -> start -> AN2 -> stop -> start -> AN2 ... -> repeat
MB91460P Series
DS07-16615-2E 61
In stop mode the startup source is the source determined by the STS1, STS0 bits. This mode enables synchro-
nization of the conversion start signal.
6.4. Single-shot Conversion
The following figure shows the operation of A/D converter in Single-shot conversion mode
(1) Channel selection
(2) A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)
(3) INT flag clear, BUSY flag set
(4) Sample hold
(5) Conversion (Conversion a + Conversion b + Conversion c)
(6) Conversion end, INT flag set, BUSY flag clear
(7) Buffers the conversion value. Buffered data storage
(8) Software-based INT flag clear
Channel
selection
Activation
(trigger)
AN input
Internal level
Conversion
value
Conversion
aConversion
bConversion
c
Sample
hold
Buffer
(ADT)
Conversion end
(INT)
BUSY
Flag clear
(A/D conversion
activation,
or software)
(1)
(2)
(3)
(4) (5)
(6)
(7)
(8)
Flag clear on A/D conversion activation
Conversion time
Conversion in progress Finalized
Previous conversion value New conversion value
MB91460P Series
62 DS07-16615-2E
6.5. Scan Conversion
The following figure shows the operation of A/D converter in Scan conversion mode
(1) Activation channel selection
(2) A/D activation (Trigger: Software trigger/Reload timer/External trigger)
(3) INT flag clear, PAUS flag clear
(4) AN0 conversion
a. Sample hold, conversion (conversion a + conversion b + conversion c)
b. Conversion end
c. Buffers the conversion value.
(5) AN1 conversion
(6) AN2 conversion
(7) AN3 conversion
(8) INT2 (End of Scan) flag is set, AN0 conversion starts
(9) Because INT2 has not been cleared yet, the ADC protects the result register of AN0
against overwriting and enters PAUSE state.
(10)INT2 flag cleared by DMA or by software, the ADC stores the result of AN0 and continues sampling AN1.
6.6. Protection of the ADC Channel Data Registers
There are 32 ADC result data registers, one register per channel. The registers are written by hardware at the
end of conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
The CPU can read the data registers any time.
Scan start
channel
selection
Activation
(trigger)
AN input
Result registers
End of Scan INT
PAUS
AN1 AN2 AN3
ADCD0
ADCD1
ADCD2
ADCD3
a, b, c
AN0 AN1 AN2 AN3
AN0
(6)
(5)
(4)
(3)
(2)
(1)
(7)
(8)
(9)
(10)
AN1 conversion value
AN2 conversion value
AN3 conversion value
AN0 conversion value
Sample hold
AN0
(5)
(4)
AN0 next conversion value
AN1 next value
AN0
AN2 next value
MB91460P Series
DS07-16615-2E 63
If a conversion is finished and the data of the previous conversion has not been read out before, previous data
would be overwritten. To avoid this problem, the next conversion data is not stored in the data registers until the
previous value has been read out (e.g. by DMA). A/D conversion halts during this time and the PAUS flag is set.
A/D conversion restarts when the ADC interrupt flag ADCR1.INT is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
6.6.1. Protection of ADCD0...31
In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for
writing to the registers, but IRQ2 (End of Scan interrupt) is already active.
Example: Start channel =4, end channel=7, continous mode, ADCS1.INTE=0, ADCS2.INTE2=1
Start by CPU --> convert channel 4 + safe data to ADCD4,
convert channel 5 + safe data to ADCD5,
convert channel 6 + safe data to ADCD6,
convert channel 7 + safe data to ADCD7 ---> End of Scan interrupt (IRQ2),
convert channel 4 + set PAUS (protect ADCD4...7).
After the CPU or DMA have read the data registers and cleared IRQ2, the scan conversion continues.
6.6.2. Protection of ADCR
In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,
but IRQ (End of Conversion) is active. Because in this mode the protection function is active after each single
conversion, the ADCR register is protected.
7. ADC Interrupt Generation and DMA Access
There are 2 ADC interrupt sources: End of Conversion and End of Scan.
7.1. End of Conversion
The End of Conversion (EoC) interrupt is enabled by ADCS1.INTE bit and is compatible to the A/D converts in
old devices of MB91460 series. If EoC is enabled, it appears after any conversion cycle. It is recommended to
use DMA transfer to read out the data from ADCR.
7.2. End of Scan
The End of Scan (EoS) interrupt is enabled by ADCS2.INTE2 bit. If EoS is enabled, it appeares after the
conversion of the end channel, which is defined by the setting of ADECH register.
If the End of Conversion interrupt is enabled in parallel, both interrupt bits are set. In this case it is recommended
that the interrupt routine reads out ADCS2 register (containing mirrored bits of ADCS1[7:4]) to check where the
interrupt comes from.
7.3. DMA Transfer
DMA transfer can be triggered by End of Conversion interrupt or by End of Scan interrupt. The interrupts are
assigned to separate DMA resource numbers (please refer to the Interrupt Vector Table).
The automatic interrupt clear after DMA transfer works for End of Conversion and for End of Scan separately.
Mode INTE2 Function
Single, Stop X Protection of ADCR
Continuous 0 Protection of ADCR
1 Protection of ADCD0...ADCD31
MB91460P Series
64 DS07-16615-2E
■HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 *1) or less than (VSS5 or
HVSS5 *1) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power
supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting
in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute
maximum ratings.
Note *1: HVDD5, HVSS5 are available only on devices having Stepper Motor Controller.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR)
before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or
VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.
3. Power supply pins
In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins
necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up.
All of the power supply pins and ground pins must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of
the MB91460 series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between
power supply pin and ground pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic
capacitor) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass
capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and
X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
5. Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In
the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible.
(Continued)
MB91460P Series
DS07-16615-2E 65
(Continued)
Example of using opposite phase supply
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-
running operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
X0 (X0A)
X1 (X1A)
MB91460P Series
66 DS07-16615-2E
■NOTES ON DEBUGGER
1. Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the
main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base
timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base
timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debug-
ging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not
set the access to the areas containing the address of system stack pointer as a target of data event break.
4. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
•The following behavior may occur if any of the following occurs in the instruction
immediately after a DIV0U/DIV0S instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed
and the D0 and D1 flags are updated to the same values as those in 1.
• The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed
to enable a user interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register
is updated to the same value as in 1.
MB91460P Series
DS07-16615-2E 67
■BLOCK DIAGRAM
1. MB91F465PA, MB91F467PA
AIN0 to AIN3
BIN0 to BIN3
ZIN0 to ZIN3
TTG0/8 to TTG23/31
PPG0 to PPG31
TIN0/8 to TIN7/15
TOT0 to TOT7
CK0 to CK7
ICU0 to ICU7
OCU0 to OCU7
PFM
SDA0 to SDA3
SCL0 to SCL3
AN0 to AN31
ATGX
SGA
SGO
SIN0 to SIN11
SOT0 to SOT11
SCK0 to SCK11
ASX
RDX
WRX0 to WRX1
SYSCLK
CSX0 to CSX2
A0 to A23
D16 to D31
RX0 to RX2,RX3
TX0 to TX2,TX3
R-bus
16
I-bus
32
D-bus
32
FR60 CPU
core
Flash-Cache
8 Kbytes
Flash memory
544 KByte (MB91F465PA)
1088 KByte (MB91F467PA)
ID-RAM
16 KByte (MB91F465PA)
32 KByte (MB91F467PA)
Bus converter
D-RAM
24 KByte (MB91F465PA)
48 KByte (MB91F467PA)
Bit search
CAN
3/4 channels
32 <-> 16
bus adapter
External
bus
interface
DMAC
5 channels
WEX
Clock modulator
Clock monitor MONCLK
Interrupt controller
INT0 to INT15
External interrupt
16 channels
Clock supervisor
Clock control
PPG timer
32 channels
Reload timer
16 channels
Free-run timer
8 channels
Input capture
8 channels
Output compare
8 channels
Up/down counter
4 channels
PFM timer
1 channel
LIN-USART
12 channels
4 channels
IC
2
Real time clock
A/D converter
32 channels
Sound generator
1 channel
RDY
AN37 to AN42,
AN44 to AN46
A/D converter 2
9 ch., MB91F467PA only
Data Flash
64 KByte / 8 bit
(MB91F467PA)
MB91F465PA: 3 channels
MB91F467PA: 4 channels
MB91460P Series
68 DS07-16615-2E
■CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
2. Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent
of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and
peripheral resources.
•A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
MB91460P Series
DS07-16615-2E 69
3. Programming model
3.1. Basic programming model
ILM SCR CCR
FP
SP
AC
. . .
. . .
. . .
. . .
XXXX XXXXH
0000 0000H
XXXX XXXXH
. . .
. . .
. . .
R0
R1
R12
R13
R14
R15
PC
RS
RP
TBR
SSP
USP
MDL
MDH
. . .
. . .
32 bits
Initial value
General-purpose registers
Program counter
Program status
Table base register
Return pointer
System stack pointer
User stack pointer
Multiply & divide registers
MB91460P Series
70 DS07-16615-2E
4. Registers
4.1. General-purpose register
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2. PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
FP
SP
AC
. . .
. . .
. . .
. . .
XXXX XXXXH
0000 0000H
XXXX XXXXH
. . .
. . .
. . .
R0
R1
R12
R13
R14
R15
. . .
. . .
32 bits
Initial value
Bit position →
bit 20 bit 0bit 7bit 8bit 10bit 16
ILM SCR CCR
bit 31
MB91460P Series
DS07-16615-2E 71
4.3. CCR (Condition Code Register)
SV : Supervisor flag
S : Stack flag
I : Interrupt enable flag
N : Negative enable flag
Z : Zero flag
V : Overflow flag
C : Carry flag
4.4. SCR (System Condition Register)
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
4.5. ILM (Interrupt Level Mask register)
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
4.6. PC (Program Counter)
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
- 000XXXX
B
bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7
CVZNISSV
Initial value
bit 10 bit 8bit 9
D1 D0 T XX0
B
Initial value
bit 18 bit 16bit 17
ILM2 ILM1 ILM0 01111
B
ILM3ILM4
bit 20 bit 19
Initial value
bit 0bit 31
XXXXXXXX
H
Initial value
MB91460P Series
72 DS07-16615-2E
4.7. TBR (Table Base Register)
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
4.8. RP (Return Pointer)
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
4.9. USP (User Stack Pointer)
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
bit 0bit 31
000FFC00
H
Initial value
bit 0bit 31
XXXXXXXX
H
Initial value
bit 0bit 31
XXXXXXXX
H
Initial value
bit 0
MDL
bit 31
MDH
MB91460P Series
DS07-16615-2E 73
■EMBEDDED PROGRAM/DATA MEMORY (FLASH)
1. Flash features
• MB91F465PA: 544 KBytes (8 × 64 Kbytes + 4 × 8 KBytes = 4.25 Mbits)
• MB91F467PA: 1088 KBytes (16 × 64 Kbytes + 8 × 8 KBytes = 8.5 Mbits)
• Programmable wait states for read/write access
• Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
• Boot security
• Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
2. Operation modes:
(1) 64-bit CPU mode (available on MB91F467PA only) :
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode:
• CPU reads and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode:
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in word (16-bit) length units.
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start
address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access
Mode Switching".
MB91460P Series
74 DS07-16615-2E
3. Flash access in CPU mode
3.1. Flash configuration
3.1.1. Flash memory map MB91F465PA
ROMS7
Legend
Memory not available in this area
addr+3
addr+4
0009:FFFFh
0008:0000h
0007:FFFFh
0006:0000h
0005:FFFFh
0004:0000h
SA12 (64KB)
SA13 (64KB)
0014:7FFFh
0014:4000h
0014:3FFFh
0014:0000h
000F:FFFFh
000E:0000h
SA15 (64KB)
000D:FFFFh
000C:0000h
000B:FFFFh
000A:0000h
SA17 (64KB)
SA14 (64KB)
SA22 (64KB)
SA20 (64KB)
0013:FFFFh
0012:0000h
0011:FFFFh
0010:0000h
SA18 (64KB)
SA7 (8KB)
SA5 (8KB)
SA3 (8KB)
SA1 (8KB)
SA23 (64KB)
SA6 (8KB)
SA4 (8KB)
SA2 (8KB)
Addr
0014:FFFFh
0014:C000h
0014:BFFFh
0014:8000h
addr+7
addr+2
SA0 (8KB)
SA16 (64KB)
SA10 (64KB)
SA21 (64KB)
SA19 (64KB)
dat[15:0]
16bit read/write
32bit read
ROMS2
dat[31:16]
dat[15:0]
dat[31:0]
dat[31:0]
dat[31:16]
ROMS1
ROMS0
addr+6
ROMS5
ROMS4
ROMS6
ROMS3
Memory available in this area
addr+5
SA11 (64KB)
SA8 (64KB)
SA9 (64KB)
addr+0
addr+1
MB91460P Series
DS07-16615-2E 75
3.1.2. Flash memory map MB91F467PA
ROMS1
ROMS0
addr+6
ROMS5
ROMS4
ROMS6
ROMS7
ROMS3
ROMS2
dat[31:16]
dat[15:0]
dat[31:0]
dat[31:0]
dat[31:16]
dat[15:0]
16bit read/write
32bit read/write
dat[63:0]
64bit read
addr+7
addr+2
SA0 (8KB)
SA16 (64KB)
SA10 (64KB)
SA21 (64KB)
SA19 (64KB)
Address
0014:FFFFh
0014:C000h
0014:BFFFh
0014:8000h
SA7 (8KB)
SA5 (8KB)
SA3 (8KB)
SA1 (8KB)
SA23 (64KB)
SA6 (8KB)
SA4 (8KB)
SA2 (8KB)
SA22 (64KB)
SA20 (64KB)
0013:FFFFh
0012:0000h
0011:FFFFh
0010:0000h
SA18 (64KB)
0014:7FFFh
0014:4000h
0014:3FFFh
0014:0000h
000F:FFFFh
000E:0000h
SA15 (64KB)
000D:FFFFh
000C:0000h
000B:FFFFh
000A:0000h
addr+5
SA11 (64KB)
SA8 (64KB)
SA9 (64KB)
addr+0
addr+1
addr+3
addr+4
0009:FFFFh
0008:0000h
0007:FFFFh
0006:0000h
0005:FFFFh
0004:0000h
SA17 (64KB)
SA14 (64KB)
SA12 (64KB)
SA13 (64KB)
MB91460P Series
76 DS07-16615-2E
3.2. Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1. Flash read timing settings (synchronous read)
3.2.2. Flash write timing settings (synchronous write)
Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark
to 24 MHz 0 0 0 - 1
to 48 MHz 0 0 1 - 2
to 100 MHz 1 1 3 - 4
Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark
to 16 MHz 0 - - 0 3
to 32 MHz 0 - - 0 4
to 48 MHz 0 - - 0 5
to 64 MHz 1 - - 0 6
to 96 MHz 1 - - 0 7
to 100 MHz 1 - - 1 8
MB91460P Series
DS07-16615-2E 77
3.3. Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1. Address mapping MB91F465PA
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set offset by keeping FA[20] = 1 as described in section “Parallel Flash programming mode”.
3.3.1. Address mapping MB91F467PA
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
CPU Address
(addr) Condition Flash
sectors FA (flash address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0 SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 -
(addr/2)%4 + addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1 SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 +
00:2000h - (addr/2)%4 + addr%4 - 0D:0000h
08:0000h
to
13F:FFFFh
addr[2]==0 SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 -
(addr/2)%4 + addr%4
08:0000h
to
13F:FFFFh
addr[2]==1 SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 +
01:0000h - (addr/2)%4 + addr%4
CPU Address
(addr) Condition Flash
sectors FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0 SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1 SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
MB91460P Series
78 DS07-16615-2E
4. Parallel Flash programming mode
4.1. Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F465PA MB91F467PA
SA0 (8KB)
FA[1:0]=00
FA[1:0]=10
SA2 (8KB)
SA1 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
SA3 (8KB)
0017:DFFFh
0017:C000h
0017:BFFFh
0017:A000h
SA6 (8KB)
SA5 (8KB)
0017:FFFFh
0017:E000h
SA8 (64KB)
SA7 (8KB)
SA10 (64KB)
SA9 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
SA11 (64KB)
001A:FFFFh
001A:0000h
0019:FFFFh
0019:0000h
SA14 (64KB)
SA13 (64KB)
001C:FFFFh
001C:0000h
001B:FFFFh
001B:0000h
SA16 (64KB)
SA15 (64KB)
001E:FFFFh
001E:0000h
001D:FFFFh
001D:0000h
SA17 (64KB)
001F:FFFFh
001F:0000h
SA19 (64KB)
SA18 (64KB)
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
16bit write mode
Legend
Memory available in this area
Memory not available in this area
FA[20:0]
Remark: Always keep FA[0] = 0 and FA[21] = 1
16bit write mode
DQ[15:0]
DQ[15:0]
SA20 (64KB)
SA19 (64KB)
SA18 (64KB)
FA[21:0]
003E:FFFFh
003E:0000h
003D:FFFFh
003D:0000h
003F:FFFFh
003F:0000h
SA23 (64KB)
SA22 (64KB)
SA21 (64KB)
003C:FFFFh
003C:0000h
003B:FFFFh
003B:0000h
003A:FFFFh
003A:0000h
0039:FFFFh
0039:0000h
SA17 (64KB)
0038:FFFFh
0038:0000h
0037:FFFFh
0037:0000h
SA16 (64KB)
SA15 (64KB)
0036:FFFFh
0036:0000h
0035:FFFFh
0035:0000h
SA14 (64KB)
SA13 (64KB)
0034:FFFFh
0034:0000h
0033:FFFFh
0033:0000h
SA12 (64KB)
SA11 (64KB)
0032:FFFFh
0032:0000h
0031:FFFFh
0031:0000h
SA10 (64KB)
SA9 (64KB)
0030:FFFFh
0030:0000h
002F:FFFFh
002F:E000h
SA8 (64KB)
SA7 (8KB)
002F:7FFFh
002F:6000h
SA4 (8KB)
SA3 (8KB)
002F:DFFFh
002F:C000h
002F:BFFFh
002F:A000h
SA6 (8KB)
SA5 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
FA[1:0]=00
FA[1:0]=10
002F:5FFFh
002F:4000h
002F:3FFFh
002F:2000h
SA2 (8KB)
SA1 (8KB)
002F:9FFFh
002F:8000h
MB91460P Series
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4.2. Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set
when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash
memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MBM29LV400TC
External pins FR-CPU mode
MB91F465PA, MB91F467PA external pins
Comment
Flash memory
mode Normal function Pin number
- INITX - INITX 104
RESET - FRSTX NMIX 105
- - MD_2 MD_2 96 Set to ‘1’
- - MD_1 MD_1 95 Set to ‘1’
- - MD_0 MD_0 94 Set to ‘1’
RY/BY FMCS:RDY bit RY/BYX P19_0 112
BYTE Internally fixed to ‘H’ BYTEX P19_2 114
WE
Internal control sig-
nal + control via inter-
face circuit
WEX P18_0 118
OE OEX P19_6 117
CE CEX P19_5 116
- ATDIN MD_3 98 Set to ‘0’
- EQIN MONCLK 97 Set to ‘0’
- TESTX P19_4 115 Set to ‘1’
- RDYI P19_1 113 Set to ‘0’
A-1
Internal address bus
FA0 P17_5 124 Set to ‘0’
A0 to A7 FA1 to FA8 P06_0 to P06_7 6 to 13
A8 to A15 FA9 to FA16 P05_0 to P05_7 14 to 21
A16 to A18 FA17 to FA19 P18_1, P18_2,
P18_4 119, 120, 121
A19 FA20 P18_5 122 Set to ‘1’ on
MB91F465PA
⎯FA21 P18_6 123
Not needed on
MB91F465PA;
Set to ‘1’ on
MB91F467PA
DQ0 to DQ7 Internal data bus DQ0 to DQ7 P01_0 to P01_7 24 to 31
DQ8 to DQ15 DQ8 to DQ15 P00_0 to P00_7 32 to 39
MB91460P Series
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5. Poweron Sequence in parallel programming mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security
Vector fetch:
• Minimum wait time after VDD5/VDD5R power on: 2.76 ms
• Minimum wait time after INITX rising: 1.0 ms
6. Flash Security
6.1. Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)
controlling the protection functions of the Flash Security Module:
FSV1: 0x14:8000 BSV1: 0x14:8004
FSV2: 0x14:8008 BSV2: 0x14:800C
6.2. Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the
individual write protection of the 8 Kbytes sectors.
6.2.1. FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[31:19]
FSV1[18]
Write Protection
Level
FSV1[17]
Write Protection
FSV1[16]
Read Protection Flash Security Mode
set all to ‘0’ set to ‘0’ set to ‘0’ set to ‘1’ Read Protection (all device modes, ex-
cept INTVEC mode MD[2:0]=”000”)
set all to ‘0’ set to ‘0’ set to ‘1’ set to ‘0’ Write Protection (all device modes, with-
out exception)
set all to ‘0’ set to ‘0’ set to ‘1’ set to ‘1’
Read Protection (all device modes, ex-
cept INTVEC mode MD[2:0]=”000”) and
Write Protection (all device modes)
set all to ‘0’ set to ‘1’ set to ‘0’ set to ‘1’ Read Protection (all device modes, ex-
cept INTVEC mode MD[2:0]=”000”)
set all to ‘0’ set to ‘1’ set to ‘1’ set to ‘0’ Write Protection (all device modes, ex-
cept INTVEC mode MD[2:0]=”000”)
set all to ‘0’ set to ‘1’ set to ‘1’ set to ‘1’
Read Protection (all device modes, ex-
cept INTVEC mode MD[2:0]=”000”) and
Write Protection (all device modes except
INTVEC mode MD[2:0]=”000”)
MB91460P Series
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6.2.2. FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the
8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1[15:0]
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to
write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section “Flash access in CPU mode” for an overview about the sector organization of the Flash
Memory.
FSV1 bit Sector Enable Write
Protection
Disable Write
Protection Comment
FSV1[0] SA0 (MB91F467PA) set to “0” set to “1” not available
FSV1[1] SA1 (MB91F467PA) set to “0” set to “1” not available
FSV1[2] SA2 (MB91F467PA) set to “0” set to “1” not available
FSV1[3] SA3 (MB91F467PA) set to “0” set to “1” not available
FSV1[4] SA4 set to “0” ⎯Write protection is
mandatory!
FSV1[5] SA5 set to “0” set to “1”
FSV1[6] SA6 set to “0” set to “1”
FSV1[7] SA7 set to “0” set to “1”
FSV1[8] ⎯set to “0” set to “1” not available
FSV1[9] ⎯set to “0” set to “1” not available
FSV1[10] ⎯set to “0” set to “1” not available
FSV1[11] ⎯set to “0” set to “1” not available
FSV1[12] ⎯set to “0” set to “1” not available
FSV1[13] ⎯set to “0” set to “1” not available
FSV1[14] ⎯set to “0” set to “1” not available
FSV1[15] ⎯set to “0” set to “1” not available
MB91460P Series
82 DS07-16615-2E
6.3. Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the
64 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
7. Notes About Flash Memory CRC Calculation
The Flash Security macro contains a feature to calculate the 32-bit checksum over addresses located in the Flash
Memory address space. This feature is described in the MB91460 Series Hardware Manual, chapter 55.4.1 “Flash
Security Control Register”.
Additional notes are given here:
The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz
for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the
CRC calculation may not start correctly.
FSV2 bit Sector Enable Write
Protection
Disable Write
Protection Comment
FSV2[0] SA8 (MB91F467PA) set to “0” set to “1”
FSV2[1] SA9 (MB91F467PA) set to “0” set to “1”
FSV2[2] SA10 (MB91F467PA) set to “0” set to “1”
FSV2[3] SA11 (MB91F467PA) set to “0” set to “1”
FSV2[4] SA12 set to “0” set to “1”
FSV2[5] SA13 set to “0” set to “1”
FSV2[6] SA14 set to “0” set to “1”
FSV2[7] SA15 set to “0” set to “1”
FSV2[8] SA16 set to “0” set to “1”
FSV2[9] SA17 set to “0” set to “1”
FSV2[10] SA18 set to “0” set to “1”
FSV2[11] SA19 set to “0” set to “1”
FSV2[12] SA20 (MB91F467PA) set to “0” set to “1”
FSV2[13] SA21 (MB91F467PA) set to “0” set to “1”
FSV2[14] SA22 (MB91F467PA) set to “0” set to “1”
FSV2[15] SA23 (MB91F467PA) set to “0” set to “1”
FSV2[31:16] ⎯set to “0” set to “1” not available
MB91460P Series
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■EMBEDDED DATA FLASH (MB91F467PA)
MB91F467PA contains a 64 KByte internal data flash.
1. Data Flash Features
• MB91F467PA: 64 Kbytes (4 × 16 Kbytes + 1 × 256 bytes security sector)
• Data width of flash macro: 8 bit
• Synchronous flash interface and flash macro
• 2 access modes (direct access, command sequencer access)
• Read access 8/16/32-bit by internal sequencer hardware
• Write access 8-bit in direct access mode, 8/16/32-bit in command sequencer write mode
• Programmable wait states for read/write access
• Data Flash Security feature (read and write protection)
• CRC calculation feature
• Interrupt- and DMA request, DMA stop request
2. Data Flash Block Diagram
The Data Flash consists of the flash macro and interface, control, status, command sequencer and security logic.
On MB91460 series devices, the Data Flash is connected to the X-Bus in parallel to the External Bus interface:
ASX
RDX
WRX0 to WRX3
MCLKI
BGRNTX
CSX0 to CSX7
A0 to A31
D0 to D31
External
bus
interface
BRQ
MCLKE
MCLKO
WEX
BAAX
SYSCLK
RDY
32
Data
Flash
bus
interface
Data Flash
Control/Status
Registers
Data Flash
Write Command
Sequencer
Data
Flash
macro
interface
Data
Flash
Security Data
Flash
macro
&
mask
32
8
8
32 88
8
direct mode write data
read data
RDY
Data Flash
X-bus
Interrupt Request
DMA Request
DMA STOP Request
DMA Interrupt Clear
MB91460P Series
84 DS07-16615-2E
3. Data Flash Operation Modes
The data flash is located in the top address space of external bus area. Per default (after software reset RST),
the data flash is disabled and does not accept any read/write access. The data flash can be enabled by setting
the bit DFCS:FLASHEN (DFCS is the Data Flash Control/Status register).
3.1. Direct Access mode:
The Direct Access mode provides data flash access similar to the access of the embedded program/data flash
(main flash). For write/program operations, the flash command sequences must be written by the CPU. The
command sequences are the same as used for the embedded program/data flash (main flash).
• CPU reads data in byte, halfword or word (8/16/32-bit) length units, whereas 16- or 32-bit read operations are
split into 2 or 4 sequential 8-bit flash macro read accesses by hardware.
• CPU writes data in byte (8-bit) width units.
• For write/program operations, the flash command sequences must be written by the CPU.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) can only be activated
in direct access mode.
• Direct access mode is the default mode after software reset (RST).
3.2. Command Sequencer Mode:
In command sequencer mode, the flash macro command sequences for data write operation are generated by
hardware.
• CPU reads data in byte, halfword or word (8/16/32-bit) length units (same as in direct access mode).
• CPU writes data in byte, halfword or word (8/16/32-bit) length units using normal “store” instructions. The flash
macro command sequences are generated by internal command sequencer hardware. For 16- or 32-bit write,
2 or 4 command sequences are generated, respectively.
• The data flash interface will not issue wait states after a command sequencer write operation was started. The
CPU can continue working during data flash programming.
•If a command sequencer write operation is ongoing, and the CPU writes data again, this second write
request is ignored! The error flag DFWS:PAERF is set in case of such a prohibited access. It is recommended
to use the data flash interrupts, which indicate that the proceeding write sequence was finished and successful.
• If a command sequencer write operation is ongoing, and the CPU tries to read data, 0x00 is returned
and the error flag DFWS:PAERF is set.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) cannot be activated.
• Command Sequencer mode is enabled by setting the bit DFWC:WE (Data Flash Write Control register).
• After software reset (RST), the command sequencer mode is disabled.
3.3. Parallel Programming mode:
• The parallel programming mode works similar to the main flash memory. The function/timing of some external
control lines are different.
• In parallel programming mode, it is not necessary to set the Data Flash enable bit (DFCS:FLASHEN).
• Data Flash Memory access is performed in byte (8-bit) length units.
MB91460P Series
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4. Data Flash access in CPU mode
4.1. Data Flash memory map MB91F467PA
The Data Flash macro is 8 bit wide. It is located in the top address space of external bus area:
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical
addresses of the flash macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in ”Auto Program Algorithms’ on page 86 . However, toggle flags cannot be read using the
dummy addresses.
4.2. Data Flash and External Bus
If the Data Flash is disabled (see ”Data Flash Operation Modes’ on page 84), the complete address space can
be used for the external bus.
If the Data Flash is enabled, the user should take care that no external bus chip select area overlaps the address
range of the Data Flash.
If a chip select area overlaps the Data Flash addresses, the following scenario may appear:
• Write operations will be sent to data flash and external bus in parallel. This may cause heavy problems,
especially if the data flash is written in direct mode, where the CPU sends the command sequences for
programming (see ”Direct Access mode:’ on page 84).
• Read operations will return unpredictable results.
FFFC 0000H
FFFD 0000H
External bus area
FFFF FFFFH
0050 0000H
FFFB FF00H
FFFC C000H
FFFC 4000H
FFFC 8000H
External bus area
Data Flash Security Sector (256 Byte)
Data Flash Sector 3 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 0 (16 KB) 01 0000H
01 FFFFH
00 FF00H
01 C000H
01 4000H
01 8000H
CPU
address
Parallel
programming
mode
address
FFFB F000HDummy addresses for auto algorithm
MB91460P Series
86 DS07-16615-2E
4.3. Flash access timing settings in CPU mode
The Data Flash can be accessed up to CLKB = 100 MHz. For timing and wait state setup, please refer to the
description of the bits TMG2, TMG1, TMG0 in ”Data Flash Control and Status Register’ on page 89 .
Although the data flash is located in the address space of external bus, there is no dependency between external
bus timing and data flash timing.
4.4. Auto Program Algorithms
The auto program algorithms can only be applied in direct access mode, while the “Program” sequence can be
generated by hardware if the Command Sequencer Mode is used.
The data flash supports command sequences similar to the main flash:
PA: Program Address PD: Program Data. Data to be programmed at location PA.
RA: Read Address RD: Data to read at location RA.
SA: Sector Address (points into the sector to be erased)
It is recommended that the addresses “AA8” and “554” point to the sector which is to be programmed.
For example, to program a byte into sector SAS, the following sequence should be used:
Address PA=0xFFFBFF83 is inside sector SAS.
1. write addr=0xFFFBFAA8 data=0xAA
2. write addr=0xFFFBF554 data=0x55
3. write addr=0xFFFBFAA8 data=0xA0
4. write addr=0xFFFBFF83 =PA data=PD
Note: The address for the write sequence (1., 2., 3. write) points into the “Dummy addresses for auto algorithm”
here. For polling of toggle bits, an address pointing inside the programmed sector has to be used, for example
the programmed address (PA) itself.
1st bus
Write cycle
2nd bus
Write cycle
3rd bus
Write cycle
4th bus
Write cycle
5th bus
Write cycle
6th bus
Write cycle
Command
Sequenc
e
Bus
Write
Cycle Address D a t a Address D a t a Addr ess D a t a Address D a t a Address D a t a
Read/Reset 1 XXX F0 RA RD
Read/Reset 3 AA8 AA 554 55 AA8 F0 RA RD
Program 4 AA8 AA 554 55 AA8 A0 PA PD
Chip Erase 6 AA8 AA 554 55 AA8 80 AA8 AA 554 55 AA8 10
Sector Erase 6 AA8 AA 554 55 AA8 80 AA8 AA 554 55 SA 30
Sector Erase Suspend Sector Erase Suspend by input of address “XXX" and data “B0”
Sector Erase Resume Sector Erase Resume by input of address “XXX" and data “30”
Unlock
Bypass
set
3 AA8 AA 554 55 AA8 20
Unlock
Bypass
program
2 XXX A0 PA PD
Unlock
Bypass
Reset
2 XXX 90 XXX
F0/
00
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4.5. Data Flash Hardware Sequence Flags (Toggle Bits)
In direct access mode, the data flash returns toggle bits shown in the following table.
In command sequencer mode, it is not necessary to read the toggle bits because they are observed by the
command sequencer automatically.
Note: For polling of toggle bits, an address pointing inside the programmed sector has to be used, for example the
programmed address itself. Do not use a “Dummy addresses for auto algorithm”.
Status DQ7 DQ6 DQ5 DQ4 DQ3 DQ2
Embedded Program Algorithm ~DQ7 Toggle 0 0 0 1
Busy to suspend 1
Embedded Erase Algorithm
(Erase Suspended Sector) Ready to suspend
0 Toggle 0
0
1 Toggle
Busy to suspend 1
Embedded Erase Algorithm
(Non-Erase Suspended Sector) Ready to suspend
0 Toggle 0
0
1 1
Erase Suspend Read
(Erase Suspended Sector) 1 1 0 0 0 Toggle
Erase Suspend Read
(Non-Erase Suspended Sector) Data Data Data Data Data Data
I
n
P
rogress
Erase Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector) ~DQ7 Toggle 0 0 0 1
Embedded Program Algorithm ~DQ7 Toggle 1 0 0 1
Embedded Erase Algorithm 0 Toggle 1 N/A 1 N/A
E
xceeded
T
ime
L
imits Erase Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector) ~DQ7 Toggle 1 0 0 N/A
MB91460P Series
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5. Data Flash Registers
The Data Flash has the following control/status registers:
DFCS : Data Flash Control and Status Register
DFWC : Data Flash Write Command Sequencer Control Register
DFWS : Data Flash Write Command Sequencer Status Register
DFSCR0 : Data Flash Security Control Register 0
DFSCR1 : Data Flash Security Control Register 1
Address3130292827262524 bit
07114HRDYI TMG2 TMG1 TMG0 FLASHEN INTE RDYINT RDY
01110001
Initial val-
ue
R/W R/W R/W R/W R/W R/W R/W0 R Attribute
Address2322212019181716 bit
07115H- - - ERINTE FININTE IDLINTE IDLD-
MAE WE
xxx00000
Initial val-
ue
- - - R/W R/W R/W R/W R/W Attribute
Address151413121110 9 8 bit
07116HPAERF WIERINT WERINT TOERINT FININT IDLINT ST1 ST0
00000000
Initial val-
ue
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R R Attribute
Address 31:24 23:16 15:8 7:0 bit
07118HDFSCR0[31:0]
1111 1111 1111 1111 1111 1111 1111 1111 Initial val-
ue
R/W, RRRRAttribute
Address 31:24 23:16 15:8 7:0 bit
0711CHDFSCR1[31:0]
0 - - - 0001 0000 0000 0000 0000 0000 0000 Initial val-
ue
R, R/W R, R/W R, R/W R, R/W Attribute
MB91460P Series
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5.1. Data Flash Control and Status Register
This section explains the Data Flash Control and Status register.
DFCS : Data Flash Control and Status register
• This bit is cleared by software reset (RST).
• Always write 0 to this bit.
• These bits control the number of wait cycles for read and write operations.
• The bits are set to “111” by software reset (RST) and can be read and written
• This bit is cleared by software reset (RST) and can be read and written
• Before setting this bit, the user has to take care that no External Bus Chip Select area overlaps the data flash
address space.
Addr: 0x07114
31 30 29 28 27 26 25 24 bit
RDYI TMG2 TMG1 TMG0 FLASHEN INTE RDYINT RDY
01110001initial
R/WR/WR/WR/WR/WR/WR/W0 Rattribute
RDYI Ready Inversion
0 (default) Normal flash operation
1Setting this bit to ’1’ activates the RDYI input of the Flash. As a result, the RDY output of
the Flash goes to ’0’ (used for test purposes only). Always write 0 to this bit.
TMG2 TMG1 TMG0
Data Flash Timing Control
CLKB Frequency
up to
CLKB Cycles per
Read Operation
CLKB Cycles per
Write Operation
0 0 0 6.2 MHz 3 3
0 0 1 16.7 MHz 4 3
0 1 0 33.3 MHz 5 3
0 1 1 50 MHz 6 3
1 0 0 66.6 MHz 8 4
1 0 1 83.3 MHz 9 5
1 1 0 100 MHz 10 6
1 1 1 (default) 100 MHz 11 6
FLASHEN Data Flash Enable
0 (default) Data Flash is disabled and does not accept read and write access
1 Data Flash is enabled and can be read and written depending on data flash security settings.
MB91460P Series
90 DS07-16615-2E
• If this bit is cleared, no interrupt is generated when the RDYINT flag is set.
• If this bit is set, the interrupt by RDYINT flag is enabled.
• This bit is cleared by software reset (RST) and can be read and written.
• This bit is set after a rising edge of the RDY status line of the flash macro.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
• This bit shows the RDY status line of the flash macro after a certain response time tBUSY:
In direct access mode, tBUSY is minimum 90 ns after the last write access of a program sequence.
In write sequencer mode, the command sequencer cares about RDY signal. There is no need to poll RDY.
• This bit is read-only.
INTE Ready Interrupt Enable
0 (default) Disable the interrupt of the RDYINT flag
1 Enable the interrupt of the RDYINT flag
RDYINT Ready Interrupt Flag
0 (default) The flash macro has not entered the READY state
1 The flash macro has entered the READY state
RDY Flash Macro Ready Status
0Indicates that a program/erase command is currently executed. Only the reset and suspend
commands are accepted in this state.
1(default) Indicates that no program/erase command is currently executed. Any command
can be written to the Flash.
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5.2. Data Flash Write Command Sequencer Control Register
This section explaines the Data Flash Sequencer Control register
DFWC : Data Flash Write Command Sequencer Control
• Always write 0 to the bits 7:5.
• If this bit is cleared, no interrupt is generated when a error flag (TOERINT, WERINT and WIERINT) is set.
• If this bit is set, an interrupt is generated when one of the error flags is set.
• This bit is cleared by software reset (RST) and can be read and written.
• If this bit is cleared, no interrupt is generated when the FININT flag is set.
• If this bit is set, an interrupt is generated when the FININT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
• If this bit is cleared, no interrupt is generated when the IDLINT flag is set.
• If this bit is set, an interrupt is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
• If this bit is cleared, no DMA transfer request is generated when the IDLINT flag is set.
• If this bit is set, an DMA transfer request is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
Addr: 0x07115
23 22 21 20 19 18 17 16 bit
- - - ERINTE FININTE IDLINTE IDLDMAE WE
xxx00000initial
- - - R/W R/W R/W R/W R/W attribute
ERINTE Error Interrupt Enable
0 (default) Disable the interrupt of the error flags
1 Enable the interrupt of the error flag
FININTE Finish Interrupt Enable
0 (default) Disable the interrupt of the FININT flag
1 Enable the interrupt of the FININT flag
IDLINTE Idle Interrupt Enable
0 (default) Disable the interrupt of the IDLINT flag
1 Enable the interrupt of the IDLINT flag
IDLDMAE Idle DMA Enable
0 (default) Disable the DMA transfer request
1 Enable the DMA transfer request if the IDLINT flag is set
MB91460P Series
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• This bit enables the Command Sequencer mode.
• This bit is cleared by software reset (RST) and can be read and written.
WE Write Command Sequencer Enable
0 (default) Disable the Write Command Sequencer, Data Flash operates in direct mode
1 Enable the Write Command Sequencer Mode
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5.3. Data Flash Write Command Sequencer Status Register
This section explaines the Data Flash Command Sequencer Status register.
DFWS : Data Flash Write Command Sequencer Status
The command sequencer status flags are only set if the command sequencer is enabled (DFWC:WE=1).
• This flag is set if the CPU tried to read or write into the Data Flash area while the Data Flash is accessed by
the Command Sequencer.
• This flag cannot generate an interrupt.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
• This flag is set when the command sequencer is disabled (set DFWC:WE=0) in "not idle" state .
• If this flag is 0, it is no guarantee that the write operation was successful. Use the FININT flag!
• This flag can generate an interrupt if DFWC:ERINTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
• This flag is set after a write access returned error:
- tried to write to an erase-suspended or write-protected sector,
- tried to write a bit “1” although it is already “0” in flash.
• This flag can generate an interrupt if DFWC:ERINTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
Addr: 0x07116
15 14 13 12 11 10 9 8 bit
PAERF WIERINT WERINT TOERINT FININT IDLINT ST1 ST0
00000000initial
R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R R attribute
PAERF Prohibited Access Error Flag
0 (default) No prohibited access detected
1 Prohibited access detected
WIERINT Write Incomplete Error Flag
0 (default) Command sequencer write operation was completed
1 Command sequencer was disabled while a write operation was ongoing
WERINT Write Error Flag
0 (default) No write error detected
1 Write operation returned error
TOERINT Timeout Error Flag
0 (default) No timeout error detected
1 A write operation ended with timeout error
MB91460P Series
94 DS07-16615-2E
• This flag is set after a write operation ended in timeout state.
• This flag can generate an interrupt if DFWC:ERINTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
• This flag is set after a command sequencer write operation was finished successfully.
• This flag can generate an interrupt if DFWC:FININTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• This bit is also cleared after a DMA transfer (caused by IDLINT) was finished.
• Read-modify-write operations will read 1.
• This flag is set after the command sequencer was enabled (set DFWC:WE=1) or entered the IDLE state after
a write operation was finished.
• This flag can generate an interrupt if DFWC:INTE is set.
• This flag can generate a DMA transfer request if DFWC:IDLDMAE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• This bit is also cleared after a DMA transfer was finished.
• Read-modify-write operations will read 1.
• Status bit {ST1,ST0} =2’b11 show that the command sequencer was disabled in "not idle" state and direct
access to Flash is not yet permitted (wait for proceeding Flash sequence to finish). Max duration of this wait
can be 11 clock cycle after disabling Command Sequencer.
5.4. Data Flash security Control Register 0,1
Please refer to ”Data Flash Security Registers’ on page 102 .
FININT Command Sequence Finished Flag
0 (default) Write command was not (yet) finished successfully
1 Write command was finished successfully
IDLINT Command Sequencer Idle Flag
0 (default) Command sequencer is disabled or not in IDLE state
1 Command sequencer entered the IDLE state
ST1 ST0 Command Sequencer Status Flags
0 0 (default) Command sequencer is disabled or in IDLE state
0 1 Command sequencer is submitting the write command
1 0 Command sequencer is waiting for Flash program finish
1 1 Command sequencer was disabled in "not idle" state
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6. Data Flash Interrupts and DMA Access
If a command sequencer write operation is ongoing, and the CPU writes data again, this second write
request is ignored! Therefore, it is recommended to use the data flash interrupts or DMA, which indicates that
the write sequence is finished and successful.
6.1. Data Flash Interrupt Flag Overview
The Data Flash interface has 6 interrupt flags with certain relationship to the 3 output lines for interrupt / DMA
request:
Interrupt Flags:
• IDLINT IDLE flag, indicates that the command sequencer has entered the IDLE state
after a write sequence. This flag is also set just after the command sequencer was
enabled by setting DFWC:WE.
• RDYINT READY flag, indicates that the flash macro has entered READY state.
• FININT FINISH flag, indicates that the command sequencer finished a write sequence successfully.
• TOERINT TIMEOUT Error flag, indicates that a command sequencer write sequence
ended in TIMEOUT error state.
• WERINT Suspend Sector Write Error flag, indicates that there was a write request to a sector which is
erase suspended or write-protected and not ready for writing.
• WIERINT Write Incomplete Error flag, indicates that the command sequencer was disabled
(DFWC:WE = 0) while a write sequence was ongoing.
• PAERF Prohibited Access Error flag, indicates that the CPU tried a read or write access while a
command sequencer write was ongoing. PAERF is a status flag and cannot generate
an interrupt.
The following picture shows the interrupt flags and their enable bits.
TOERINT
WIERINT
WERINT
ERINTE
FININT
FININTE
IDLINT
IDLINTE
RDYINT
INTE
IDLDMAE
IDLINT
DMA Request
Interrupt Request to CPU
DMA Stop Request
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The DMA request can be activated by the IDLE flag only and has a separate enable bit (DFWC:IDLDMAE).
DMA Stop request is activated by the error flags.
The CPU interrupt can be activated by all interrupt flags.
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7. Data Flash parallel programming mode
Note: The currently available parallel flash programmers do not support the programming of the data flash. The
programmers may be updated on request. This chapter is for information only.
7.1. Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F467PA
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical
addresses of the flash macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in ”Auto Program Algorithms’ on page 86 .
7.2. Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to data flash macro addresses which are used
in parallel programming.
7.2.1. Address mapping MB91F467PA
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
CPU Address
(addr) Condition Flash
sectors FA (flash address) Calculation
FFFB:FF00h
to
FFFC:FFFFh
-SAS, SA0, SA1, SA2, SA3
(256 Byte + 64 Kbyte) FA := addr - 0B:0000h
FFFC 0000H
FFFD 0000H
External bus area
FFFF FFFFH
0050 0000H
FFFB FF00H
FFFC C000H
FFFC 4000H
FFFC 8000H
External bus area
Data Flash Security Sector (256 Byte)
Data Flash Sector 3 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 0 (16 KB) 01 0000H
01 FFFFH
00 FF00H
01 C000H
01 4000H
01 8000H
CPU
address
Parallel
programming
mode
address
FFFB F000HDummy addresses for auto algorithm
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7.3. Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to General Purpose Ports. Please see table below for signal mapping.
In this mode, the Data Flash memory appears to the external pins as a stand-alone unit. This mode is generally
set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the Data Flash
memory’s Auto Algorithms are available.
Correspondence between flash macro and Flash Memory Control Signasl
Data Flash
macro pins FR-CPU mode
MB91F467PA external pins Comment
⎯INITX ⎯INITX 104
FRSTX ⎯FRSTX NMIX 105
⎯⎯MD_2 MD_2 96 Set to ‘1’
⎯⎯MD_1 MD_1 95 Set to ‘1’
⎯⎯MD_0 MD_0 94 Set to ‘1’
RDY FMCS:RDY bit RY/BYX P19_0 112
FCLK FCLK P19_2 114 Clock input
WEX
Internal control signal
+ control via interface
circuit
WEX P18_0 118
OEX OEX P19_6 117
CEX CEX P19_5 116
RAS RAS MD_3 98
EQIN EQIN MONCLK 97
LTIN LTIN P23_0 68 Set to ‘0’
⎯TESTX P19_4 115 Set to ‘1’
⎯RDYI P19_1 113 Set to ‘0’
FA0 Internal address bus FA0 P17_5 125
FA1 to FA8 FA1 to FA8 P06_0 to P06_7 6 to 13
FA9 to FA16
Internal address bus
FA9 to FA16 P05_0 to P05_7 14 to 21
⎯FA17 to FA19 P18_1, P18_2,
P18_4
119, 120,
121 Set to ‘0’
⎯FA20,FA21 P18_5, P18_6 122, 123 Set to “10”
DI0 to DI7,
DO0 to DO7 Internal data bus DQ0 to DQ7 P01_0 to P01_7 24 - 31
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7.4. Wait time before data flash access in parallel programming mode
After power-on or the end of a Setting Initialization Request (INITX), the internal data flash security module fetches
the security information. The parallel programmer cannot access the flash until the security vector fetch is finished
and has to wait for the following time:
• Min waittime after VDD5/VDD5R power on : 2.9 ms
• Min waittime after INITX rising : 1.0 ms
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8. Data Flash Security
8.1. Data Flash Security Operation
The data flash security protects the flash against unauthorized read and write access.
•A read access to protected flash will return data=0x00 without notification. There is no flag indicating that the
read access was masked by data flash security module.
•A write access to a write-protected sector will be cancelled.
The flash macro will be put into RESET state, and the security macro will re-fetch the security information.
It may take up to 600μs until the data flash can be accessed again.
In direct access mode, the toggle bits will not change and the bit DFCS:RDY will not go to low state.
In command sequencer mode, the flag DFWS:WERINT is set, indicating that the write operation was not
successful.
• The only possible write operation to a protected sector is Chip Erase.
• The data flash security can be disabled by setting the external pin FSC_DISABLE = 1.
• After INIT, please wait 3 ms before accessing the data flash. This time is needed for the security vector fetch
as well as internal signal synchronization. This time is valid also if FSC_DISABLE = 1.
•
8.1. Security Vectors
Two 16-bit Data Flash Security Vectors (DFSV1, DFSV2) are located in the 256 byte security sector, controlling
the protection functions of the Data Flash Security module:
DFSV1[15:0]: 0xFFFB:FF00
DFSV2[15:0]: 0xFFFB:FF02
8.2. Security Vector DFSV1 (bit15 to bit0)
The setting of the Flash Security Vector DFSV1 is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector DFSV1 [15:0]
Vectors
Address+0+1+2+3Block
FFFBFF00HDFSV1[15:0] DFSV2[15:0] Data Flash
Security Vectors
DFSV1[15:3]
DFSV1[2]
Write
Protection
Level
DFSV1[1]
Write
Protection
DFSV1[0]
Read
Protection
Flash Security Mode
set all to “0” set to “0” set to “0” set to “1” Read Protection (all device modes, except INTVEC 1 )
1. INTVEC mode is the Internal Vector Fetch mode (MD[2:0] = “000”)
set all to “0” set to “0” set to “1” set to “0” Write Protection (all device modes, without exception)
set all to “0” set to “0” set to “1” set to “1” Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, without exception)
set all to “0” set to “1” set to “0” set to “1” Read Protection (all device modes, except INTVEC)
set all to “0” set to “1” set to “1” set to “0” Write Protection (all device modes, except INTVEC)
set all to “0” set to “1” set to “1” set to “1” Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, except INTVEC)
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Note : If Read Protection is set and the device is not in INTVEC mode and the data flash is written using the
Command Sequencer write access, then the command sequencer will set the error flag because it cannot
check that the flash programming was successful.
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8.3. Security Vector DFSV2
The setting of the Flash Security Vector DFSV2 bits [15:0] is responsible for the individual write protection of
the Data Flash sectors. It is only evaluated if write protection bit DFSV1 [1] is set.
Explanation of the bits in the Flash Security Vector DFSV2[15:0]
Note : It is mandatory to always set the sector where the Flash Security Vectors DFSV1 and DFSV2 are located to
write protected (here sector SAS). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section ”Data Flash access in CPU mode’ on page 85 for an overview about the sector organisation of
the Flash Memory.
8.4. Data Flash Security Registers
The Data Flash Security module can be used to calculate a CRC over the Data Flash contents. And it is possible
to force a security vector re-fetch by using the following registers.
8.4.1. DFSCR0 : Data Flash Security Control Register 0
• Continuously writing “A5H”, “5AH” in the DFSCR0[31:24] register will start a Flash Security Vector Re-fetch
sequence immediately after writing “5AH”. There is no time restrictions between “A5H” and “5AH”, but if “A5H” is
written followed by the one other than “5AH”, it must be written “A5H” again. If not, the Re-Fetch sequence
cannot be started even if “5AH” is written.
• Continuously writing “F0H”, “0FH” in the DFSCR0[31:24] register will start a CRC32 checksum sequence im-
mediately after writing “0FH”. There is no time restrictions between “F0H” and “0FH”, but if “F0H” is written followed
by the one other than “0FH”, it must be written “F0H” again. If not, the CRC checksum sequence cannot be
started even if “0FH” is written.
DFSV2 bit Sector Enable Write
Protection
Disable Write
Protection Comment
DFSV2[0] SA0 set to “0” set to “1”
DFSV2[1] SA1 set to “0” set to “1”
DFSV2[2] SA2 set to “0” set to “1”
DFSV2[3] SA3 set to “0” set to “1”
DFSV2[7:4] ⎯⎯⎯sectors not available
DFSV2[8] SAS set to “0” ⎯write protection is mandatory!
DFSV2[15:9] ⎯⎯⎯sectors not available
Address 31:24 23:16 15:8 7:0 bit
07118HS[7:0]
CRC[31:24] CRC[23:0]
1111 1111 1111 1111 1111 1111 1111 1111 Initial
value
W, RRRRAttribute
S[7:0] Sequence Activation
0xA5 --> 0x5A Start of a Flash Security Vector Re-Fetch Sequence (write only)
0xF0 --> 0x0F Start of a Flash Memory CRC32 Checksum Sequence (write only)
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• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog and can be written only.
Note: The Flash Security Vector Re-Fetch sequence is especially intended to be used after a chip erase command
to update the security status without the need of applying an external INITX reset or after changing the status
of the DFSV1 security vector.
Note: The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to
2 MHz for shortening the calculation time. However, the CPU clock (CLKB) must be faster then RC clock,
otherwise the CRC calculation may not start correctly.
• This register contains the CRC32 checksum result after completion of the CRC32 checksum sequence (the
sequence completion is indicated by DFSCR1.RDY). The CRC checksum is calculated in a standard
CRC32/AAL5 algorithm with the polygon
x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
• These bits are set to 0xFFFFFFFF by an INIT signal from external pin (INITX) or hardware watchdog and can
be read only.
8.4.2. DFSCR1 : Data Flash Security Control Register 1
• Bit30-25: Reserved bits. The read value is always “X”.
• Bit23-20: Reserved bits. The read value is always “0”.
Bit 31:
Bit 24:
Bit 19-16:
CRC[31:0] CRC checksum result
CRC checksum result (read only)
Address 31:24 23:16 15:8 7:0 bit
0711CHSVF_RDY--- --- RDY - - - - CSZ[3:0] CSA[15:0]
0xxx xxx1 0000 0000 0000 0000 0000 0000 Initial
value
R/Wx R, R/W R/W R/W Attribute
SVF_RDY Security Vector Fetch Ready (flag)
0The security vector has not been fetched. The data flash is protected against read and
write access. Read operations to data flash return 0x00. Write operations are ignored.
1The security vector has been done. The data flash can be accessed according to the se-
curity settings.
RDY CRC Sequence Ready (flag)
0 CRC sequence running or not yet started
1 CRC sequence ready (data in the DFSCR0 register is valid)
CSZ[3:0] CRC Size Mask
0000 CRC size mask is 256 Byte
0001 CRC size mask is 512 Byte
0010 CRC size mask is 1 KByte
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• CSZ3-0 is used as an OR-mask for the address given by CSA15-0. See address calculation below.
• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog.
Bit 15-0
Notes: The values given above are just examples. The addresses to be written in this register are flash memory
addresses like used in the flash parallel programming mode and not the mapped addresses which are used
in CPU mode. See ”Address mapping from CPU to parallel programming mode’ on page 97 .
• The CSA register contains the CRC start address which is aligned to 256 Byte addresses. It is only possible
to calculate the CRC checksum over addresses located in the Data Flash Memory address space. Other
addresses are invalid and might lead to wrong checksums.
8.4.3. Calculation of the CRC Start- and End-addresses
The CSZ3-0 setting is first translated into a mask value:
• CRC Start address = CSA[15:0] << 8 + 0x00
• CRC End address = (CSA[15:0] or MASK ) << 8 + 0xFF
0011 CRC size mask is 2 KByte
0100 CRC size mask is 4 KByte
0101 CRC size mask is 8 KByte
0110 CRC size mask is 16 KByte
0111 CRC size mask is 32 KByte
1000 CRC size mask is 64 KByte
1001 - 1111 Not supported
CSA[15:0] CRC Calculation Start Address
0x00FF CRC start address is 0x0FF00 (sector SAS start)
0x0100 CRC start address is 0x10000 (sector SA0 start)
0x0140 CRC start address is 0x14000 (sector SA1 start)
CSZ3-0 MASK
0000 0000_0000_0000_0000
0001 0000_0000_0000_0001
0010 0000_0000_0000_0011
0011 0000_0000_0000_0111
0100 0000_0000_0000_1111
0101 0000_0000_0001_1111
0110 0000_0000_0011_1111
0111 0000_0000_0111_1111
1000 0000_0000_1111_1111
1001-1111 and so on...
CSZ[3:0] CRC Size Mask
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■MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
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■MEMORY MAPS
1. MB91F465PA, MB91F467PA
MB91F465PA MB91F467PA
00000000
H
00000400
H
I/O (direct addressing area)
I/O
00002000
H
00004000
H
Flash-Cache (8 KBytes)
00001000
H
DMA
00006000
H
00007000
H
Flash memory control
00008000
H
0000B000
H
Boot ROM (4 Kbytes)
0000C000
H
CAN
0000D000
H
0002A000
H
D-RAM (0 wait, 24 Kbytes)
00030000
H
ID-RAM (16 Kbytes)
00034000
H
00040000
H
Flash memory (512 Kbytes)
00150000
H
00180000
H
External bus area
00500000
H
External data bus
FFFFFFFF
H
Note: Access prohibited areas
00148000
H
Flash memory (32 Kbytes)
00100000
H
External bus area
External bus area
00080000
H
00000000
H
00000400
H
I/O (direct addressing area)
I/O
00002000
H
00004000
H
Flash-Cache (8 KBytes)
00001000
H
DMA
00006000
H
00007000
H
Flash memory control
00008000
H
0000B000
H
Boot ROM (4 KBytes)
0000C000
H
CAN
0000D000
H
00024000
H
D-RAM (0 wait, 48 KBytes)
00030000
H
ID-RAM (32 KBytes)
00038000
H
00040000
H
Flash memory (1088 KBytes)
00150000
H
00180000
H
External bus area
Note: Access prohibited areas
00500000
H
FFFFFFFF
H
FFFBFF00
H
Data Flash 64KB + 256Byte /
External bus area
FFFCFFFF
H
FFFBF000
H
External bus area
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■I/O MAP
1. MB91F465PA, MB91F467PA
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
Address Register Block
+ 0+ 1+ 2+ 3
000000HPDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
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108 DS07-16615-2E
Address Register Block
+0 +1 +2 +3
000000HPDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX Reserved Reserved
R-bus
Port Data
Register
000004HReserved PDR05 [R/W]
XXXXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008HPDR08 [R/W]
X - - X - -XX
PDR09 [R/W]
- - - - - XXX
PDR10 [R/W]
- - - - X - XX Reserved
00000CHReserved Reserved PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
XXXXXXXX
000010HPDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014HPDR20 [R/W]
- XXX - XXX
PDR21 [R/W]
XXXX - XXX
PDR22 [R/W]
XXXXXXXX
PDR23 [R/W]
XXXXXXXX
000018HPDR24 [R/W]
XXXXXXXX
PDR25 [R/W]
- - - - - - XX
PDR26 [R/W]
XXXXXXXX
PDR27 [R/W]
XXXXXXXX
00001CHPDR28 [R/W]
- -XXXXX
PDR29 [R/W]
XXXXXXXX
PDR30 [R/W]
XXXXXXXX Reserved
000020HPDR32 [R/W]
X - - - X - - -
PDR33 [R/W]
X - - - X - - -
PDR34 [R/W]
XXXXXXXX
PDR35 [R/W]
XXXXXXXX
000024H
to
00002CH
Reserved
000030HEIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
(INT 0 to INT 7)
NMI
000034HEIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
(INT 8 to INT 15)
000038HDICR [R/W]
- - - - - - - 0
HRCL [R/W]
0 - - 11111 Reserved Delay interrupt
00003CHReserved
000040HSCR00 [R/W,W]
00000000
SMR00 [R/W,W]
00000000
SSR00 [R/W,R]
00001000
RDR00/TDR00
[R/W]
00000000 LIN-USART
0
000044HESCR00 [R/W]
00000X00
ECCR00
[R/W,R,W]
-00000XX
Reserved
000048HSCR01 [R/W,W]
00000000
SMR01 [R/W,W]
00000000
SSR01 [R/W,R]
00001000
RDR01/TDR01
[R/W]
00000000 LIN-USART
1
00004CHESCR01 [R/W]
00000X00
ECCR01
[R/W,R,W]
-00000XX
Reserved
MB91460P Series
DS07-16615-2E 109
000050HSCR02 [R/W,W]
00000000
SMR02 [R/W,W]
00000000
SSR02 [R/W,R]
00001000
RDR02/TDR02
[R/W]
00000000 LIN-USART
2
000054HESCR02 [R/W]
00000X00
ECCR02
[R/W,R,W]
-00000XX
Reserved
000058HSCR03[R/W,W]
00000000
SMR03 [R/W,W]
00000000
SSR03 [R/W,R]
00001000
RDR03/TDR02
[R/W]
00000000 LIN-USART
3
00005CHESCR03 [R/W]
00000X00
ECCR03
[R/W,R,W]
-00000XX
Reserved
000060HSCR04 [R/W,W]
00000000
SMR04 [R/W,W]
00000000
SSR04 [R/W,R]
00001000
RDR04/TDR04
[R/W]
00000000 LIN-USART
4
with FIFO
000064HESCR04 [R/W]
00000X00
ECCR04
[R/W,R,W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000068HSCR05 [R/W,W]
00000000
SMR05 [R/W,W]
00000000
SSR05 [R/W,R]
00001000
RDR05/TDR05
[R/W]
00000000 LIN-USART
5
with FIFO
00006CHESCR05 [R/W]
00000X00
ECCR05
[R/W,R,W]
-00000XX
FSR05 [R]
- - - 00000
FCR05 [R/W]
0001 - 000
000070HSCR06 [R/W,W]
00000000
SMR06 [R/W,W]
00000000
SSR06 [R/W,R]
00001000
RDR06/TDR06
[R/W]
00000000 LIN-USART
6
with FIFO
000074HESCR06 [R/W]
00000X00
ECCR06
[R/W,R,W]
-00000XX
FSR06 [R]
- - - 00000
FCR06 [R/W]
0001 - 000
000078HSCR07 [R/W,W]
00000000
SMR07 [R/W,W]
00000000
SSR07 [R/W,R]
00001000
RDR07/TDR07
[R/W]
00000000 LIN-USART
7
with FIFO
00007CHESCR07 [R/W]
00000X00
ECCR07
[R/W,R,W]
-00000XX
FSR07 [R]
- - - 00000
FCR07 [R/W]
0001 - 000
000080HBGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
Baudrate
Generator
LIN-USART
0 to 7
000084HBGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088HBGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CHBGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
110 DS07-16615-2E
000090H
to
0000CCH
Reserved
0000D0HIBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
I2C 00000D4HITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8HReserved IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111 Reserved
0000DCHIBCR1 [R/W]
00000000
IBSR1 [R]
00000000
ITBAH1 [R/W]
- - - - - - 00
ITBAL1 [R/W]
00000000
I2C 10000E0HITMKH1 [R/W]
00 - - - - 11
ITMKL1 [R/W]
11111111
ISMK1 [R/W]
01111111
ISBA1 [R/W]
- 0000000
0000E4HReserved IDAR1 [R/W]
00000000
ICCR1 [R/W]
- 0011111 Reserved
0000E8H
to
0000FCH
Reserved
000100HGCN10 [R/W]
00110010 00010000 Reserved GCN20 [R/W]
- - - - 0000
PPG Control
0 to 3
000104HGCN11 [R/W]
00110010 00010000 Reserved GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108HGCN12 [R/W]
00110010 00010000 Reserved GCN22 [R/W]
- - - - 0000
PPG Control
8 to 11
000110HPTMR00 [R]
11111111 11111111
PCSR00 [W]
XXXXXXXX XXXXXXXX PPG 0
000114HPDUT00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
000118HPTMR01 [R]
11111111 11111111
PCSR01 [W]
XXXXXXXX XXXXXXXX PPG 1
00011CHPDUT01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
000120HPTMR02 [R]
11111111 11111111
PCSR02 [W]
XXXXXXXX XXXXXXXX PPG 2
000124HPDUT02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
000128HPTMR03 [R]
11111111 11111111
PCSR03 [W]
XXXXXXXX XXXXXXXX PPG 3
00012CHPDUT03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 111
000130HPTMR04 [R]
11111111 11111111
PCSR04 [W]
XXXXXXXX XXXXXXXX PPG 4
000134HPDUT04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
000138HPTMR05 [R]
11111111 11111111
PCSR05 [W]
XXXXXXXX XXXXXXXX PPG 5
00013CHPDUT05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
000140HPTMR06 [R]
11111111 11111111
PCSR06 [W]
XXXXXXXX XXXXXXXX PPG 6
000144HPDUT06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
000148HPTMR07 [R]
11111111 11111111
PCSR07 [W]
XXXXXXXX XXXXXXXX PPG 7
00014CHPDUT07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
000150HPTMR08 [R]
11111111 11111111
PCSR08 [W]
XXXXXXXX XXXXXXXX PPG 8
000154HPDUT08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
000158HPTMR09 [R]
11111111 11111111
PCSR09 [W]
XXXXXXXX XXXXXXXX PPG 9
00015CHPDUT09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
000160HPTMR10 [R]
11111111 11111111
PCSR10 [W]
XXXXXXXX XXXXXXXX PPG 10
000164HPDUT10 [W]
XXXXXXXX XXXXXXXX
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
000168HPTMR11 [R]
11111111 11111111
PCSR11 [W]
XXXXXXXX XXXXXXXX PPG 11
00016CHPDUT11 [W]
XXXXXXXX XXXXXXXX
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
000170H
P0TMCSRH
[R/W]
- 0000000
P0TMCSRL
[R/W]
01000000
P1TMCSRH
[R/W]
- 0000000
P1TMCSRL
[R/W]
01000000 Pulse
Frequency Modula-
tor
000174HP0TMRLR [W]
XXXXXXXX XXXXXXXX
P0TMR [R]
XXXXXXXX XXXXXXXX
000178HP1TMRLR [W]
XXXXXXXX XXXXXXXX
P1TMR [R]
XXXXXXXX XXXXXXXX
00017CHReserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
112 DS07-16615-2E
000180HReserved ICS01 [R/W]
00000000 Reserved ICS23 [R/W]
00000000
Input
Capture
0 to 3
000184HIPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188HIPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CHOCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
Output
Compare
0 to 3
000190HOCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194HOCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198HSGCRH [R/W]
0000 - - 00
SGCRL [R/W]
- - 0 - - 000
SGFR [R/W, R]
XXXXXXXX XXXXXXXX Sound
Generator
00019CHSGAR [R/W]
00000000 Reserved SGTR [R/W]
XXXXXXXX
SGDR [R/W]
XXXXXXXX
0001A0HADERH [R/W]
00000000 00000000
ADERL [R/W]
00000000 00000000
A/D
Converter 0
0001A4 ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8HADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACHReserved
0001B0HTMRLRC0 [W]
XXXXXXXX XXXXXXXX
TMRC0 [R]
XXXXXXXX XXXXXXXX Reload Timer 0
(PPG 0-1)
0001B4HReserved
TMCSRCH0
[R/W]
- - - 00000
TMCSRCL0
[R/W]
0 - 000000
0001B8HTMRLRC1 [W]
XXXXXXXX XXXXXXXX
TMRC1 [R]
XXXXXXXX XXXXXXXX Reload Timer 1
(PPG 2-3)
0001BCHReserved
TMCSRCH1
[R/W]
- - - 00000
TMCSRCL1
[R/W]
0 - 000000
0001C0HTMRLRC2 [W]
XXXXXXXX XXXXXXXX
TMRC2 [R]
XXXXXXXX XXXXXXXX Reload Timer 2
(PPG 4-5)
0001C4HReserved
TMCSRCH2
[R/W]
- - - 00000
TMCSRCL2
[R/W]
0 - 000000
0001C8HTMRLRC3 [W]
XXXXXXXX XXXXXXXX
TMRC3 [R]
XXXXXXXX XXXXXXXX Reload Timer 3
(PPG 6-7)
0001CCHReserved
TMCSRCH3
[R/W]
- - - 00000
TMCSRCL3
[R/W]
0 - 000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 113
0001D0HTMRLRC4 [W]
XXXXXXXX XXXXXXXX
TMRC4 [R]
XXXXXXXX XXXXXXXX Reload Timer 4
(PPG 8 to 9)
0001D4HReserved
TMCSRCH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
0001D8HTMRLRC5 [W]
XXXXXXXX XXXXXXXX
TMRC5 [R]
XXXXXXXX XXXXXXXX Reload Timer 5
(PPG10 to 11)
0001DCHReserved
TMCSRCH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
0001E0HTMRLRC6 [W]
XXXXXXXX XXXXXXXX
TMRC6 [R]
XXXXXXXX XXXXXXXX Reload Timer 6
(PPG 8 to 9)
0001E4HReserved
TMCSRCH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
0001E8HTMRLR7 [W]
XXXXXXXX XXXXXXXX
TMRC7 [R]
XXXXXXXX XXXXXXXX Reload Timer 7
(PPG 14 to 15)
0001ECHReserved
TMCSRCH7
[R/W]
- - - 00000
TMCSRCL7
[R/W]
0 - 000000
0001F0HTCDT0 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS0 [R/W]
00000000
Free Running
Timer 0
(ICU 0 to 1)
0001F4HTCDT1 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS1 [R/W]
00000000
Free Running
Timer 1
(OCU 2 to 3)
0001F8HTCDT2 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0 to 1)
0001FCHTCDT3 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2 to 3)
Address Register Block
+0 +1 +2 +3
MB91460P Series
114 DS07-16615-2E
000200HDMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMAC
000204HDMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208HDMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CHDMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210HDMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214HDMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218HDMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CHDMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220HDMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224HDMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240HDMACR [R/W]
00 - - 0000 Reserved
000244H
to
00027CH
Reserved
000280HSCR08 [R/W,W]
00000000
SMR08 [R/W,W]
00000000
SSR08 [R/W,R]
00001000
RDR08/TDR08
[R/W]
00000000 LIN-USART
8
000284HESCR08 [R/W]
00000X00
ECCR08
[R/W,R,W]
-00000XX
Reserved
000288HSCR09 [R/W,W]
00000000
SMR09 [R/W,W]
00000000
SSR09 [R/W,R]
00001000
RDR09/TDR09
[R/W]
00000000 LIN-USART
9
00028CHESCR09 [R/W]
00000X00
ECCR09
[R/W,R,W]
-00000XX
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 115
000290HSCR10 [R/W,W]
00000000
SMR10 [R/W,W]
00000000
SSR10 [R/W,R]
00001000
RDR10/TDR10
[R/W]
00000000 LIN-USART
10
000294HESCR10 [R/W]
00000X00
ECCR10
[R/W,R,W]
-00000XX
Reserved
000298HSCR11 [R/W,W]
00000000
SMR11 [R/W,W]
00000000
SSR11 [R/W,R]
00001000
RDR11/TDR11
[R/W]
00000000 LIN-USART
11
00029CHESCR11 [R/W]
00000X00
ECCR11
[R/W,R,W]
-00000XX
Reserved
0002A0H
to
0002BCH
Reserved
0002C0HBGR108 [R/W]
00000000
BGR008 [R/W]
00000000
BGR109 [R/W]
00000000
BGR009 [R/W]
00000000 Baudrate
Generator
LIN-USART
8 to 11
0002C4HBGR110 [R/W]
00000000
BGR010 [R/W]
00000000
BGR111 [R/W]
00000000
BGR011 [R/W]
00000000
0002C8H
to
0002CCH
Reserved
0002D0HReserved ICS45 [R/W]
00000000 Reserved ICS67 [R/W]
00000000
Input
Capture
4 to 7
0002D4HIPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8HIPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCHOCS45 [R/W]
- - -0 - -00 0000 - -00
OCS67 [R/W]
- - -0 - -00 0000 - -00
Output
Compare
4 to 7
0002E0HOCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
0002E4HOCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
0002E8H
to
0002ECH
Reserved
0002F0HTCDT4 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4 to 5)
0002F4HTCDT5 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS5 [R/W]
00000000
Free Running
Timer 5
(ICU 6 to 7)
Address Register Block
+0 +1 +2 +3
MB91460P Series
116 DS07-16615-2E
0002F8HTCDT6 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS6 [R/W]
00000000
Free Running
Timer 6
(OCU 4 to 5)
0002FCHTCDT7 [R/W]
XXXXXXXX XXXXXXXX Reserved TCCS7 [R/W]
00000000
Free Running
Timer 7
(OCU 6 to 7)
000300HUDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
Up/Down
Counter
0 to 1
000304HUDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00000000 Reserved UDCS0 [R/W]
00000000
000308HUDCCH1 [R/W]
00000000
UDCCL1 [R/W]
00000000 Reserved UDCS1 [R/W]
00000000
00030CHReserved
000310HUDRC3 [W]
00000000
UDRC2 [W]
00000000
UDCR3 [R]
00000000
UDCR2 [R]
00000000
Up/Down
Counter
2 to 3
000314HUDCCH2 [R/W]
00000000
UDCCL2 [R/W]
00000000 Reserved UDCS2 [R/W]
00000000
000318HUDCCH3 [R/W]
00000000
UDCCL3 [R/W]
00000000 Reserved UDCS3 [R/W]
00000000
00031CHReserved
000320HGCN13 [R/W]
00110010 00010000 Reserved GCN23 [R/W]
- - - - 0000
PPG Control
12 to 15
000324H
to
00032CH
Reserved
000330HPTMR12 [R]
11111111 11111111
PCSR12 [W]
XXXXXXXX XXXXXXXX PPG 12
000334HPDUT12 [W]
XXXXXXXX XXXXXXXX
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
000338HPTMR13 [R]
11111111 11111111
PCSR13 [W]
XXXXXXXX XXXXXXXX PPG 13
00033CHPDUT13 [W]
XXXXXXXX XXXXXXXX
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
000340HPTMR14 [R]
11111111 11111111
PCSR14 [W]
XXXXXXXX XXXXXXXX PPG 14
000344HPDUT14 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
000348HPTMR15 [R]
11111111 11111111
PCSR15 [W]
XXXXXXXX XXXXXXXX PPG 15
00034CHPDUT15 [W]
XXXXXXXX XXXXXXXX
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 117
000368HIBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
I2C 200036CHITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370HReserved IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111 Reserved
000374HIBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
- - - - - - 00
ITBAL3 [R/W]
00000000
I2C 3000378HITMKH3 [R/W]
00 - - - - 11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
- 0000000
00037CHReserved IDAR3 [R/W]
00000000
ICCR3 [R/W]
- 0011111 Reserved
000380H
to
00038CH
Reserved
000390HROMS [R]
11111111 01000011 Reserved ROM Select Register
000394H
to
0003ECH
Reserved
0003F0HBSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search Module
0003F4HBSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8HBSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCHBSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
118 DS07-16615-2E
000440HICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
Interrupt
Control
Unit
000444HICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448HICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CHICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450HICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454HICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458HICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CHICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460HICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464HICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468HICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CHICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470HICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474HICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478HICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CHICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480HRSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX – 00
CTBR [W]
XXXXXXXX Clock
Control
Unit
000484HCLKR [R/W]
---- 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488HReserved Reserved
00048CHPLLDIVM [R/W]
- - - 00000
PLLDIVN [R/W]
- - - 00000
PLLDIVG [R/W]
- - - 00000
PLLDIVG [W]
00000000 PLL Clock
Gear Unit
000490HPLLCTRL [R/W]
- - - - 0000 Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 119
000494HOSCC1 [R/W]
- - - - - 010
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
Main/Sub
Oscillator
Control
000498HPORTEN [R/W]
- - - - - 000 Reserved PPMUX [R/W] *1
00000000 00000000
Port Input
Enable Control /
PortMux Control
00049CHPPMUX2 [R/W] *2
- - 00 0000 - - - - - - - - Reserved PortMux Control 2
(MB91F467PA)
0004A0HReserved WTCER [R/W]
- - - - - - 00
WTCR [R/W]
00000000 000 – 00 – 0
Real Time Clock
(Watch Timer)
0004A4HReserved WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004A8HWTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000 Reserved
0004ACHCSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
Clock-
Supervisor / Selector
/
Monitor
0004B0HCUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000 Calibration Unit of
Sub Oscillation
0004B4HCUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8HCMPR [R/W]
- - 000010 11111101 Reserved CMCR [R/W]
- 001 - - 00 Clock
Modulation
0004BCHCMT1 [R/W]
00000000 1 - - - 0000
CMT2 [R/W]
- - 000000 - - 000000
0004C0HCANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
- - - - 0000 *3Reserved Reserved CAN Clock Control
0004C4HLVSEL [R/W]
00000111
LVDET [R/W]
0000 0 - 00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W,W]
00011000
LV Detection /
Hardware-
Watchdog
0004C8HOSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/Sub-Oscilla-
tion Stabilization
Timer
0004CCHOSCCR [R/W]
- - - - - - 00 Reserved REGSEL [R/W]
- - 000110
REGCTR [R/W]
- - - 0 - - 00
Main- Oscillation
Standby Control
Main/Sub Regulator
Control
000500HGCN14 [R/W]
00110010 00010000 Reserved GCN24 [R/W]
- - - - 0000
PPG Control
16 to 19
000504HGCN15 [R/W]
00110010 00010000 Reserved GCN25 [R/W]
- - - - 0000
PPG Control
20 to 23
000508HGCN16 [R/W]
00110010 00010000 Reserved GCN26 [R/W]
- - - - 0000
PPG Control
24 to 27
Address Register Block
+0 +1 +2 +3
MB91460P Series
120 DS07-16615-2E
00050CHGCN17 [R/W]
00110010 00010000 Reserved GCN27 [R/W]
- - - - 0000
PPG Control
28 to 31
000510HPTMR16 [R]
11111111 11111111
PCSR16 [W]
XXXXXXXX XXXXXXXX PPG 16
000514HPDUT16 [W]
XXXXXXXX XXXXXXXX
PCNH16 [R/W]
0000000 -
PCNL16 [R/W]
000000 - 0
000518HPTMR17 [R]
11111111 11111111
PCSR17 [W]
XXXXXXXX XXXXXXXX PPG 17
00051CHPDUT17 [W]
XXXXXXXX XXXXXXXX
PCNH17 [R/W]
0000000 -
PCNL17 [R/W]
000000 - 0
000520HPTMR18 [R]
11111111 11111111
PCSR18 [W]
XXXXXXXX XXXXXXXX PPG 18
000524HPDUT18 [W]
XXXXXXXX XXXXXXXX
PCNH18 [R/W]
0000000 -
PCNL18 [R/W]
000000 - 0
000528HPTMR19 [R]
11111111 11111111
PCSR19 [W]
XXXXXXXX XXXXXXXX PPG 19
00052CHPDUT19 [W]
XXXXXXXX XXXXXXXX
PCNH19 [R/W]
0000000 -
PCNL19 [R/W]
000000 - 0
000530HPTMR20 [R]
11111111 11111111
PCSR20 [W]
XXXXXXXX XXXXXXXX PPG 20
000534HPDUT20 [W]
XXXXXXXX XXXXXXXX
PCNH20 [R/W]
0000000 -
PCNL20 [R/W]
000000 - 0
000538HPTMR21 [R]
11111111 11111111
PCSR21 [W]
XXXXXXXX XXXXXXXX PPG 21
00053CHPDUT21 [W]
XXXXXXXX XXXXXXXX
PCNH21 [R/W]
0000000 -
PCNL21 [R/W]
000000 - 0
000540HPTMR22 [R]
11111111 11111111
PCSR22 [W]
XXXXXXXX XXXXXXXX PPG 22
000544HPDUT22 [W]
XXXXXXXX XXXXXXXX
PCNH22 [R/W]
0000000 -
PCNL22 [R/W]
000000 - 0
000548HPTMR23 [R]
11111111 11111111
PCSR23 [W]
XXXXXXXX XXXXXXXX PPG 23
00054CHPDUT23 [W]
XXXXXXXX XXXXXXXX
PCNH23 [R/W]
0000000 -
PCNL23 [R/W]
000000 - 0
000550HPTMR24 [R]
11111111 11111111
PCSR24 [W]
XXXXXXXX XXXXXXXX PPG 24
000554HPDUT24 [W]
XXXXXXXX XXXXXXXX
PCNH24 [R/W]
0000000 -
PCNL24 [R/W]
000000 - 0
000558HPTMR25 [R]
11111111 11111111
PCSR25 [W]
XXXXXXXX XXXXXXXX PPG 25
00055CHPDUT25 [W]
XXXXXXXX XXXXXXXX
PCNH25 [R/W]
0000000 -
PCNL25 [R/W]
000000 - 0
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 121
000560HPTMR26 [R]
11111111 11111111
PCSR26 [W]
XXXXXXXX XXXXXXXX PPG 26
000564HPDUT26 [W]
XXXXXXXX XXXXXXXX
PCNH26 [R/W]
0000000 -
PCNL26 [R/W]
000000 - 0
000568HPTMR27 [R]
11111111 11111111
PCSR27 [W]
XXXXXXXX XXXXXXXX PPG 27
00056CHPDUT27 [W]
XXXXXXXX XXXXXXXX
PCNH27 [R/W]
0000000 -
PCNL27 [R/W]
000000 - 0
000570HPTMR28 [R]
11111111 11111111
PCSR28 [W]
XXXXXXXX XXXXXXXX PPG 28
000574HPDUT28 [W]
XXXXXXXX XXXXXXXX
PCNH28 [R/W]
0000000 -
PCNL28 [R/W]
000000 - 0
000578HPTMR29 [R]
11111111 11111111
PCSR29 [W]
XXXXXXXX XXXXXXXX PPG 29
00057CHPDUT29 [W]
XXXXXXXX XXXXXXXX
PCNH29 [R/W]
0000000 -
PCNL29 [R/W]
000000 - 0
000580HPTMR30 [R]
11111111 11111111
PCSR30 [W]
XXXXXXXX XXXXXXXX PPG 30
000584HPDUT30 [W]
XXXXXXXX XXXXXXXX
PCNH30 [R/W]
0000000 -
PCNL30 [R/W]
000000 - 0
000588HPTMR31 [R]
11111111 11111111
PCSR31 [W]
XXXXXXXX XXXXXXXX PPG 31
00058CHPDUT31 [W]
XXXXXXXX XXXXXXXX
PCNH31 [R/W]
0000000 -
PCNL31 [R/W]
000000 - 0
000590HTMRLR8 [W]
XXXXXXXX XXXXXXXX
TMR8 [R]
XXXXXXXX XXXXXXXX Reload Timer 8
(PPG 16 to 19)
000594HReserved
TMCSRH8
[R/W]
- - 000000
TMCSRL8
[R/W]
0 - 000000
000598HTMRLR9 [W]
XXXXXXXX XXXXXXXX
TMR9 [R]
XXXXXXXX XXXXXXXX Reload Timer 9
(PPG 16 to 19)
00059CHReserved
TMCSRH9
[R/W]
- - 000000
TMCSRL9
[R/W]
0 - 000000
0005A0HTMRLR10 [W]
XXXXXXXX XXXXXXXX
TMR10 [R]
XXXXXXXX XXXXXXXX Reload Timer 10
(PPG 20 to 23)
0005A4HReserved
TMCSRH10
[R/W]
- - 000000
TMCSRL10
[R/W]
0 - 000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
122 DS07-16615-2E
0005A8HTMRLR11 [W]
XXXXXXXX XXXXXXXX
TMR11 [R]
XXXXXXXX XXXXXXXX Reload Timer 11
(PPG 20 to 23)
0005ACHReserved
TMCSRH11
[R/W]
- - 000000
TMCSRL11
[R/W]
0 - 000000
0005B0HTMRLR12 [W]
XXXXXXXX XXXXXXXX
TMR12 [R]
XXXXXXXX XXXXXXXX Reload Timer 12
(PPG 24 to 27)
0005B4HReserved
TMCSRH12
[R/W]
- - 000000
TMCSRL12
[R/W]
0 - 000000
0005B8HTMRLR13 [W]
XXXXXXXX XXXXXXXX
TMR13 [R]
XXXXXXXX XXXXXXXX Reload Timer 13
(PPG 24 to 27)
0005BCHReserved
TMCSRH13
[R/W]
- - 000000
TMCSRL13
[R/W]
0 - 000000
0005C0HTMRLR14 [W]
XXXXXXXX XXXXXXXX
TMR14 [R]
XXXXXXXX XXXXXXXX Reload Timer 14
(PPG 28 to 31)
0005C4HReserved
TMCSRH14
[R/W]
- - 000000
TMCSRL14
[R/W]
0 - 000000
0005C8HTMRLR15 [W]
XXXXXXXX XXXXXXXX
TMR15 [R]
XXXXXXXX XXXXXXXX Reload Timer 15
(PPG 28 to 31)
0005CCHReserved
TMCSRH15
[R/W]
- - 000000
TMCSRL15
[R/W]
0 - 000000
0005D0HTMR89 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload Timers 8 + 9
0005D4HTMR1011 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 10 +
11
0005D8HTMR1213 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 12 +
13
0005DCHTMR1415 [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload Timers 14 +
15
0005E0HAD1ERH [R/W]
00000000 00000000
AD1ERL [R/W]
00000000 00000000
A/D Converter 1 *4
(MB91F467PA)
0005E4HAD1CS1 [R/W]
00000000
AD1CS0 [R/W]
00000000
AD1CR1 [R]
000000XX
AD1CR0 [R]
XXXXXXXX
0005E8HAD1CT1 [R/W]
00010000
AD1CT0 [R/W]
00101100
AD1SCH
[R/W]
- - - 00000
AD1ECH
[R/W]
- - - 00000
0005ECH
to
00063FH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 123
000640HASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00100000 *5
External Bus
Unit
000644HASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648HASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CHASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650HASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654HASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658HASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CHASR7 [R/W]
XXXXXXXX XXXXXXXX
ACR7 [R/W]
XXXXXXXX XXXXXXXX
000660HAWR0 [R/W]
01111111 11111011
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664HAWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668HAWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CHAWR6 [R/W]
XXXXXXXX XXXXXXXX
AWR7 [R/W]
XXXXXXXX XXXXXXXX
000670HMCRA [R/W]
XXXXXXXX
MCRB [R/W]
XXXXXXXX Reserved
000674HReserved
000678HIORW0 [R/W]
XXXXXXXX
IORW1 [R/W]
XXXXXXXX
IORW2 [R/W]
XXXXXXXX Reserved
00067CHReserved
000680HCSER [R/W]
00000001
CHER [R/W]
11111111 Reserved TCR [R/W]
0000**** *6
000684HRCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
124 DS07-16615-2E
000688HRCO0H0 [R/W]
11111111
RCO0L0 [R/W]
0000 0000
RCO0H1 [R/W]
1111111
RCO0L1 [R/W]
0000 0000
A/D Converter 0
Range Comparator
*7
(MB91F467PA)
00068CHRCO0H2 [R/W]
1111111
RCO0L2 [R/W]
0000 0000
RCO0H3 [R/W]
1111111
RCO0L3 [R/W]
0000 0000
000690HRCO0IRS [R/W]
00000000 00000000 00000000 00000000
000694HRCO0OF [R]
00000000 00000000 00000000 00000000
000698HRCO0INT [R/W0]
00000000 00000000 00000000 00000000
00069CHreserved
0006A0HAD0CC0 [R/W]
0000 0000
AD0CC1 [R/W]
0000 0000
AD0CC2 [R/W]
0000 0000
AD0CC3 [R/W]
0000 0000
A/D Converter 0
Channel Control
(MB91F467PA)
0006A4HAD0CC4 [R/W]
0000 0000
AD0CC5 [R/W]
0000 0000
AD0CC6 [R/W]
0000 0000
AD0CC7 [R/W]
0000 0000
0006A8HAD0CC8 [R/W]
0000 0000
AD0CC9 [R/W]
0000 0000
AD0CC10 [R/W]
0000 0000
AD0CC11 [R/W]
0000 0000
0006ACHAD0CC12 [R/W]
0000 0000
AD0CC13 [R/W]
0000 0000
AD0CC14 [R/W]
0000 0000
AD0CC15 [R/W]
0000 0000
0006B0HAD0CS2 [RW]
0000 - - 00 reserved
A/D Converter 0
Control register 2
(MB91F467PA)
0006B4HRCO1H0 [R/W]
11111111
RCO1L0 [R/W]
0000 0000
RCO1H1 [R/W]
11111111
RCO1L1 [R/W]
0000 0000
A/D Converter 1
Range Comparator
(MB91F467PA)
0006B8HRCO1H2 [R/W]
11111111
RCO1L2 [R/W]
0000 0000
RCO1H3 [R/W]
11111111
RCO1L3 [R/W]
0000 0000
0006BCHRCO1IRS [R/W]
00000000 00000000 00000000 00000000
0006C0HRCO1OF [R]
00000000 00000000 00000000 00000000
0006C4HRCO1INT [R/W0]
00000000 00000000 00000000 00000000
0006C8Hreserved
0006CCHAD1CC0 [R/W]
0000 0000
AD1CC1 [R/W]
0000 0000
AD1CC2 [R/W]
0000 0000
AD1CC3 [R/W]
0000 0000
A/D Converter 1
Channel Control
(MB91F467PA)
0006D0HAD1CC4 [R/W]
0000 0000
AD1CC5 [R/W]
0000 0000
AD1CC6 [R/W]
0000 0000
AD1CC7 [R/W]
0000 0000
0006D4HAD1CC8 [R/W]
0000 0000
AD1CC9 [R/W]
0000 0000
AD1CC10 [R/W]
0000 0000
AD1CC11 [R/W]
0000 0000
0006D8HAD1CC12 [R/W]
0000 0000
AD1CC13 [R/W]
0000 0000
AD1CC14 [R/W]
0000 0000
AD1CC15 [R/W]
0000 0000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 125
0006DCHAD1CS2 [RW]
0000 - - 00 reserved
A/D Converter 1
Control register 2
(MB91F467PA)
0006E0HADC0D0 [R]
- - - - - - XX XXXXXXXX
ADC0D1 [R]
- - - - - - XX XXXXXXXX
A/D Converter 0
Channel Data regis-
ters *8
(MB91F467PA)
0006E4HADC0D2 [R]
- - - - - - XX XXXXXXXX
ADC0D3 [R]
- - - - - - XX XXXXXXXX
0006E8HADC0D4 [R]
- - - - - - XX XXXXXXXX
ADC0D5 [R]
- - - - - - XX XXXXXXXX
0006ECHADC0D6 [R]
- - - - - - XX XXXXXXXX
ADC0D7 [R]
- - - - - - XX XXXXXXXX
0006F0HADC0D8 [R]
- - - - - - XX XXXXXXXX
ADC0D9 [R]
- - - - - - XX XXXXXXXX
0006F4HADC0D10 [R]
- - - - - - XX XXXXXXXX
ADC0D11 [R]
- - - - - - XX XXXXXXXX
0006F8HADC0D12 [R]
- - - - - - XX XXXXXXXX
ADC0D13 [R]
- - - - - - XX XXXXXXXX
0006FCHADC0D14 [R]
- - - - - - XX XXXXXXXX
ADC0D015 [R]
- - - - - - XX XXXXXXXX
000700HADC0D16 [R]
- - - - - - XX XXXXXXXX
ADC0D17 [R]
- - - - - - XX XXXXXXXX
000704HADC0D18 [R]
- - - - - - XX XXXXXXXX
ADC0D19 [R]
- - - - - - XX XXXXXXXX
000708HADC0D20 [R]
- - - - - - XX XXXXXXXX
ADC0D21 [R]
- - - - - - XX XXXXXXXX
00070CHADC0D22 [R]
- - - - - - XX XXXXXXXX
ADC0D23 [R]
- - - - - - XX XXXXXXXX
000710HADC0D24 [R]
- - - - - - XX XXXXXXXX
ADC0D25 [R]
- - - - - - XX XXXXXXXX
000714HADC0D26 [R]
- - - - - - XX XXXXXXXX
ADC0D27 [R]
- - - - - - XX XXXXXXXX
000718HADC0D28 [R]
- - - - - - XX XXXXXXXX
ADC0D29 [R]
- - - - - - XX XXXXXXXX
00071CHADC0D30 [R]
- - - - - - XX XXXXXXXX
ADC0D31 [R]
- - - - - - XX XXXXXXXX
Address Register Block
+0 +1 +2 +3
MB91460P Series
126 DS07-16615-2E
000720HADC1D0 [R]
- - - - - - XX XXXXXXXX
ADC1D1 [R]
- - - - - - XX XXXXXXXX
A/D Converter 1
Channel Data regis-
ters
(MB91F467PA)
000724HADC1D2 [R]
- - - - - - XX XXXXXXXX
ADC1D3 [R]
- - - - - - XX XXXXXXXX
000728HADC1D4 [R]
- - - - - - XX XXXXXXXX
ADC1D5 [R]
- - - - - - XX XXXXXXXX
00072CHADC1D6 [R]
- - - - - - XX XXXXXXXX
ADC1D7 [R]
- - - - - - XX XXXXXXXX
000730HADC1D8 [R]
- - - - - - XX XXXXXXXX
ADC1D9 [R]
- - - - - - XX XXXXXXXX
000734HADC1D10 [R]
- - - - - - XX XXXXXXXX
ADC1D11 [R]
- - - - - - XX XXXXXXXX
000738HADC1D12 [R]
- - - - - - XX XXXXXXXX
ADC1D13 [R]
- - - - - - XX XXXXXXXX
00073CHADC1D14 [R]
- - - - - - XX XXXXXXXX
ADC1D015 [R]
- - - - - - XX XXXXXXXX
000740HADC1D16 [R]
- - - - - - XX XXXXXXXX
ADC1D17 [R]
- - - - - - XX XXXXXXXX
000744HADC1D18 [R]
- - - - - - XX XXXXXXXX
ADC1D19 [R]
- - - - - - XX XXXXXXXX
000748HADC1D20 [R]
- - - - - - XX XXXXXXXX
ADC1D21 [R]
- - - - - - XX XXXXXXXX
00074CHADC1D22 [R]
- - - - - - XX XXXXXXXX
ADC1D23 [R]
- - - - - - XX XXXXXXXX
000750HADC1D24 [R]
- - - - - - XX XXXXXXXX
ADC1D25 [R]
- - - - - - XX XXXXXXXX
000754HADC1D26 [R]
- - - - - - XX XXXXXXXX
ADC1D27 [R]
- - - - - - XX XXXXXXXX
000758HADC1D28 [R]
- - - - - - XX XXXXXXXX
ADC1D29 [R]
- - - - - - XX XXXXXXXX
00075CHADC1D30 [R]
- - - - - - XX XXXXXXXX
ADC1D31 [R]
- - - - - - XX XXXXXXXX
000760H
to
0007F8H
Reserved
0007FCHReserved MODR [W]
XXXXXXXX Reserved Reserved Mode Register
000800H
to
000BFCH
Reserved
000C00Hreserved IOS [R/W] *9
- - - - - -10I-Unit
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 127
000C04H
to
000CFCH
reserved
000D00HPDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX Reserved Reserved
R-bus
Port Data
Direct Read
Register
000D04HReserved PDRD05 [R]
XXXXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08HPDRD08 [R]
X - -X - -XX
PDRD09 [R]
- - - - - XXX
PDRD10 [R]
- - - - X - XX Reserved
000D0CHReserved Reserved PDRD14 [R]
XXXXXXXX
PDRD15 [R]
XXXXXXXX
000D10HPDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14HPDRD20 [R]
- XXX - XXX
PDRD21 [R]
XXXX - XXX
PDRD22 [R]
XXXXXXXX
PDRD23 [R]
XXXXXXXX
000D18HPDRD24 [R]
XXXXXXXX
PDRD25 [R]
- - - - - - XX
PDRD26 [R]
XXXXXXXX
PDRD27 [R]
XXXXXXXX
000D1CHPDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
PDRD30 [R]
XXXXXXXX Reserved
000D20HPDRD32 [R]
X - - - X - - -
PDRD33 [R]
X - - - X - - -
PDRD34 [R]
XXXXXXXX
PDRD35 [R]
XXXXXXXX
000D24H
to
000D3CH
Reserved
000D40HDDR00 [R/W]
00000000
DDR01 [R/W]
00000000 Reserved Reserved
R-bus
Port Direction
Register
000D44HReserved DDR05 [R/W]
00000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48HDDR08 [R/W]
0 - - 0 - - 00
DDR09 [R/W]
- - - - - 000
DDR10 [R/W]
- - - - 0 - 00 Reserved
000D4CHReserved Reserved DDR14 [R/W]
00000000
DDR15 [R/W]
00000000
000D50HDDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54HDDR20 [R/W]
- 000 - 000
DDR21 [R/W]
0000 - 000
DDR22 [R/W]
00000000
DDR23 [R/W]
00000000
000D58HDDR24 [R/W]
00000000
DDR25 [R/W]
- - - - - - 00
DDR26 [R/W]
00000000
DDR27 [R/W]
00000000
000D5CHDDR28 [R/W]
00000000
DDR29 [R/W]
00000000
DDR30 [R/W]
00000000 Reserved
000D60HDDR32 [R/W]
0 - - - 0 - - -
DDR33 [R/W]
0 - - - 0 - - -
DDR34 [R/W]
00000000
DDR35 [R/W]
00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
128 DS07-16615-2E
000D64H
to
000D7CH
Reserved
000D80HPFR00 [R/W]
00000000 *10
PFR01 [R/W]
00000000 Reserved Reserved
R-bus
Port Function
Register
000D84HReserved PFR05 [R/W]
00000000
PFR06 [R/W]
00000000
PFR07 [R/W]
00000000
000D88HPFR08 [R/W]
0 - - 0- - 00
PFR09 [R/W]
- - - - - 000
PFR10 [R/W]
- - - - 0 - 00 Reserved
000D8CHReserved Reserved PFR14 [R/W]
00000000
PFR15 [R/W]
00000000
000D90HPFR16 [R/W]
00000000
PFR17 [R/W]
00000000
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94HPFR20 [R/W]
- 000 - 000
PFR21 [R/W]
- 000 - 000
PFR22 [R/W]
00000000
PFR23 [R/W]
00000000
000D98HPFR24 [R/W]
00000000
PFR25 [R/W]
- - - - - - 00
PFR26 [R/W]
00000000
PFR27 [R/W]
00000000
000D9CHPFR28 [R/W]
00000000
PFR29 [R/W]
00000000
PFR30 [R/W]
00000000 Reserved
000DA0HPFR32 [R/W]
0 - - - 0 - - -
PFR33 [R/W]
0 - - - 0 - - -
PFR34 [R/W]
00000000
PFR35 [R/W]
00000000
000DA4H
to
000DBCH
Reserved
000DC0H
to
000DC8H
Reserved
000DCCHReserved Reserved EPFR10 [R/W]
- - - - - - - 0 Reserved
R-bus Port
Extra Function
Register
000DCCHReserved Reserved EPFR14 [R/W]
00000000
EPFR15 [R/W]
00000000
000DD0HEPFR16 [R/W]
0000 - - - -
EPFR17 [R/W]
00000000
EPFR18 [R/W]
- 000 - 000
EPFR19 [R/W]
- 0 - - - 0 - -
000DD4HEPFR20 [R/W]
- 000 - 000
EPFR21 [R/W]
- 0 - - - 0 - - Reserved Reserved
000DD8HEPFR24 [R/W]
0000 - - - - Reserved EPFR26 [R/W]
00000000
EPFR27 [R/W]
00000000
000DDCHReserved Reserved EPFR30 [R/W]
00000000 Reserved
000DE0HEPFR32 [R/W]
0 - - - 0 - - -
EPFR33 [R/W]
0 - - - 0 - - -
EPFR34 [R/W]
00000000
EPFR35 [R/W]
00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 129
000DE4H
to
000DFCH
Reserved
000E00HPODR00 [R/W]
00000000
PODR01 [R/W]
00000000 Reserved Reserved
R-bus Port
Output Drive Select
Register
000E04HReserved PODR05 [R/W]
00000000
PODR06 [R/W]
00000000
PODR07 [R/W]
00000000
000E08HPODR08 [R/W]
0 - -0 - - 00
PODR09 [R/W]
- - - - - 000
PODR10 [R/W]
- - - - 0 - 00 Reserved
000E0CHReserved Reserved PODR14 [R/W]
00000000
PODR15 [R/W]
00000000
000E10HPODR16 [R/W]
00000000
PODR17 [R/W]
00000000
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14HPODR20 [R/W]
- 000 - 000
PODR21 [R/W]
0000 - 000
PODR22 [R/W]
00000000
PODR23 [R/W]
00000000
000E18HPODR24 [R/W]
00000000
PODR25 [R/W]
- - - - - - 00
PODR26 [R/W]
00000000
PODR27 [R/W]
00000000
000E1CHPODR28 [R/W]
0000000
PODR29 [R/W]
00000000
PODR30 [R/W]
00000000 Reserved
000E20HPODR32 [R/W]
0 - - - 0 - - -
PODR33 [R/W]
0 - - - 0 - - -
PODR34 [R/W]
00000000
PODR35 [R/W]
00000000
000E24H
to
000E3CH
Reserved
000E40HPILR00 [R/W]
00000000
PILR01 [R/W]
00000000 Reserved Reserved
R-bus Port
Input Level Select
Register
000E44HReserved PILR05 [R/W]
00000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48HPILR08 [R/W]
0 - - 0 - - 00
PILR09 [R/W]
- - - - - 000
PILR10 [R/W]
- - - - 0 - 00 Reserved
000E4CHReserved Reserved PILR14 [R/W]
00000000
PILR15 [R/W]
00000000
000E50HPILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
- 000 - 000
PILR19 [R/W]
- 000 - 000
000E54H
PILR20 [R/W]
- 000 - 000
PILR21 [R/W]
0000 - 000
PILR22 [R/W]
00000000
PILR23 [R/W]
00000000
000E58HPILR24 [R/W]
00000000
PILR25 [R/W]
- - - - - - 00
PILR26 [R/W]
00000000
PILR27 [R/W]
00000000
000E5CHPILR28 [R/W]
00000000
PILR29 [R/W]
00000000
PILR30 [R/W]
00000000 Reserved
000E60HPILR32 [R/W]
0 - - - 0 - - -
PILR33 [R/W]
0 - - - 0 - - -
PILR34 [R/W]
00000000
PILR35 [R/W]
00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
130 DS07-16615-2E
000E64H
to
000E7CH
Reserved
000E80HEPILR00 [R/W]
00000000
EPILR01 [R/W]
00000000 Reserved Reserved
R-bus Port
Extra Input Level Se-
lect
Register
000E84HReserved EPILR05 [R/W]
00000000
EPILR06 [R/W]
00000000
EPILR07 [R/W]
00000000
000E88HEPILR08 [R/W]
0 - - 0 - - 00
EPILR09 [R/W]
- - - - - 000
EPILR10 [R/W]
- - - - 0 - 00 Reserved
000E8CHReserved Reserved EPILR14 [R/W]
00000000
EPILR15 [R/W]
00000000
000E90HEPILR16 [R/W]
00000000
EPILR17 [R/W]
00000000
EPILR18 [R/W]
- 000 - 000
EPILR19 [R/W]
- 000 - 000
000E94HEPILR20 [R/W]
- 000 - 000
EPILR21 [R/W]
0000 - 000
EPILR22 [R/W]
00000000
EPILR23 [R/W]
00000000
000E98HEPILR24 [R/W]
00000000
EPILR25 [R/W]
- - - - - - 00
EPILR26 [R/W]
00000000
EPILR27 [R/W]
00000000
000E9CHEPILR28 [R/W]
00000000
EPILR29 [R/W]
00000000
EPILR30 [R/W]
00000000 Reserved
000EA0HEPILR32 [R/W]
0 - - - 0 - - -
EPILR33 [R/W]
0 - - - 0 - - -
EPILR34 [R/W]
00000000
EPILR35 [R/W]
00000000
000EA4H
to
000EBCH
Reserved
000EC0HPPER00 [R/W]
00000000
PPER01 [R/W]
00000000 Reserved Reserved
R-bus Port
Pull-Up/Down En-
able
Register
000EC4HReserved PPER05 [R/W]
00000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8HPPER08 [R/W]
0 - - 0 - - 00
PPER09 [R/W]
- - - - - 000
PPER10 [R/W]
- - - - 0 - 00 Reserved
000ECCHReserved Reserved PPER14 [R/W]
00000000
PPER15 [R/W]
00000000
000ED0HPPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4HPPER20 [R/W]
- 000 - 000
PPER21 [R/W]
0000 - 000
PPER22 [R/W]
00000000
PPER23 [R/W]
00000000
000ED8HPPER24 [R/W]
00000000
PPER25 [R/W]
- - - - - - 00
PPER26 [R/W]
00000000
PPER27 [R/W]
00000000
000EDCHPPER28 [R/W]
0000000
PPER29 [R/W]
00000000
PPER30 [R/W]
00000000 Reserved
000EE0HPPER32 [R/W]
0 - - - 0 - - -
PPER33 [R/W]
0 - - - 0 - - -
PPER34 [R/W]
00000000
PPER35 [R/W]
00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 131
000EE4H
to
000EFCH
Reserved
000F00HPPCR00 [R/W]
00000000
PPCR01 [R/W]
00000000 Reserved Reserved
R-bus Port
Pull-Up/Down Con-
trol
Register
000F04HReserved PPCR05 [R/W]
00000000
PPCR06 [R/W]
00000000
PPCR07 [R/W]
00000000
000F08HPPCR08 [R/W]
0 - - 0 - - 00
PPCR09 [R/W]
- - - - - 000
PPCR10 [R/W]
- - - - 0 - 00 Reserved
000F0CHReserved Reserved PPCR14 [R/W]
00000000
PPCR15 [R/W]
00000000
000F10HPPCR16 [R/W]
00000000
PPCR17 [R/W]
00000000
PPCR18 [R/W]
- 000 - 000
PPCR19 [R/W]
- 000 - 000
000F14HPPCR20 [R/W]
- 000 - 000
PPCR21 [R/W]
0000 - 000
PPCR22 [R/W]
00000000
PPCR23 [R/W]
00000000
000F18HPPCR24 [R/W]
00000000
PPCR25 [R/W]
- - - - - - 00
PPCR26 [R/W]
00000000
PPCR27 [R/W]
00000000
000F1CHPPCR28 [R/W]
0000000
PPCR29 [R/W]
00000000
PPCR30 [R/W]
00000000 Reserved
000F20HPPCR32 [R/W]
0 - - - 0 - - -
PPCR33 [R/W]
0 - - - 0 - - -
PPCR34 [R/W]
00000000
PPCR35 [R/W]
00000000
000F24H
to
000FFCH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
132 DS07-16615-2E
001000HDMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
001004HDMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008HDMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CHDMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010HDMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014HDMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018HDMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CHDMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020HDMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024HDMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
001FFCH
Reserved
002000H
to
006FFCH
MB91F465PA: Flash-cache size is 8 Kbytes : 004000H to 005FFCH
MB91F467PA: Flash-cache size is 8 Kbytes : 004000H to 005FFCH
Flash-cache /
I-RAM area
007000HFMCS [R/W]
01101000
FMCR [R]
- - - 00000
FCHCR [R/W]
- - - - - - 00 10000011 Flash Memory/
F - Cache
Control
Register
007004HFMWT [R/W]
11111111 11111111
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
007008HFMAC [R]
00000000 00000000 00000000 00000000
00700CHFCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000 I-Cache Non-cache-
able area setting
Register
007010HFCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
to
0070FCH
Reserved
007100HFSCR0 [R/W, R]
11111111 11111111 11111111 11111111 Flash Security CRC
Control
register
007104HFSCR1 [R , R/W]
0 - - - 0001 00000000 00000000 00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 133
007108H
to
007110H
Reserved
007114HDFCS [R/W]
0000 000X
DFWC [R/W]
- - - 0 0000
DFWS [R/W,R]
0000 0000 reserved Data Flash Control
register
007118HDFSCR0 [R/W, R]
11111111 11111111 11111111 11111111 Data Flash
Security CRC control
00711CHDFSCR1 [R , R/W]
0 - - - 0000 00000000 00000000 00000000
007120H
to
007FFCH
Reserved
008000H
to
00BFFCH
MB91F465PA: Boot-ROM size is 4Kbytes: 00B000H to 00BFFCH
MB91F467PA: Boot-ROM size is 4Kbytes: 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 waitcycle)
Boot ROM area
00C000HCTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
CAN 0
Control
Register
00C004HERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008HINTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CHBRPE0 [R/W]
00000000 00000000 Reserved
00C010HIF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
CAN 0
IF 1 Register
00C014HIF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018HIF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CHIF1MCTR0 [R/W]
00000000 00000000 Reserved
00C020HIF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024HIF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H
to
00C02CH
Reserved
00C030HIF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034HIF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
134 DS07-16615-2E
00C038H
to
00C03CH
Reserved
00C040HIF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
CAN 0
IF 2 Register
00C044HIF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048HIF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CHIF2MCTR0 [R/W]
00000000 00000000 Reserved
00C050HIF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054HIF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H
to
00C05CH
Reserved
00C060HIF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064HIF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to
00C07CH
Reserved
00C080HTREQR20 [R]
00000000 00000000
TREQR10 [R]
00000000 00000000
CAN 0
Status Flags
00C084H
to
00C08CH
Reserved
00C090HNEWDT20 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
00C094H
to
00C09CH
Reserved
00C0A0HINTPND20 [R]
00000000 00000000
INTPND10 [R]
00000000 00000000
00C0A4H
to
00C0ACH
Reserved
00C0B0HMSGVAL20 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 135
00C0B4H
to
00C0FCH
Reserved
00C100HCTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
CAN 1
Control
Register
00C104HERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108HINTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CHBRPE1 [R/W]
00000000 00000000 Reserved
00C110HIF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
CAN 1
IF 1 Register
00C114HIF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118HIF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CHIF1MCTR1 [R/W]
00000000 00000000 Reserved
00C120HIF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124HIF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H
to
00C12CH
Reserved
00C130HIF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134HIF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
00C138H
to
00C13CH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
136 DS07-16615-2E
00C140HIF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
CAN 1
IF 2 Register
00C144HIF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148HIF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CHIF2MCTR1 [R/W]
00000000 00000000 Reserved
00C150HIF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154HIF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H
to
00C15CH
Reserved
00C160HIF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164HIF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to
00C17CH
Reserved
00C180HTREQR21 [R]
00000000 00000000
TREQR11 [R]
00000000 00000000
CAN 1
Status Flags
00C184H
to
00C18CH
Reserved
00C190HNEWDT21 [R]
00000000 00000000
NEWDT11 [R]
00000000 00000000
00C194H
to
00C19CH
Reserved
00C1A0HINTPND21 [R]
00000000 00000000
INTPND11 [R]
00000000 00000000
00C1A4H
to
00C1ACH
Reserved
00C1B0HMSGVAL21 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
00C1B4H
to
00C1FCH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 137
00C200HCTRLR2 [R/W]
00000000 00000001
STATR2 [R/W]
00000000 00000000
CAN 2
Control
Register
00C204HERRCNT2 [R]
00000000 00000000
BTR2 [R/W]
00100011 00000001
00C208HINTR2 [R]
00000000 00000000
TESTR2 [R/W]
00000000 X0000000
00C20CHBRPE2 [R/W]
00000000 00000000 Reserved
00C210HIF1CREQ2 [R/W]
00000000 00000001
IF1CMSK2 [R/W]
00000000 00000000
CAN 2
IF 1 Register
00C214HIF1MSK22 [R/W]
11111111 11111111
IF1MSK12 [R/W]
11111111 11111111
00C218HIF1ARB22 [R/W]
00000000 00000000
IF1ARB12 [R/W]
00000000 00000000
00C21CHIF1MCTR2 [R/W]
00000000 00000000 Reserved
00C220HIF1DTA12 [R/W]
00000000 00000000
IF1DTA22 [R/W]
00000000 00000000
00C224HIF1DTB12 [R/W]
00000000 00000000
IF1DTB22 [R/W]
00000000 00000000
00C228H
to
00C22CH
Reserved
00C230HIF1DTA22 [R/W]
00000000 00000000
IF1DTA12 [R/W]
00000000 00000000
00C234HIF1DTB22 [R/W]
00000000 00000000
IF1DTB12 [R/W]
00000000 00000000
00C238H
to
00C23CH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
138 DS07-16615-2E
00C240HIF2CREQ2 [R/W]
00000000 00000001
IF2CMSK2 [R/W]
00000000 00000000
CAN 2
IF 2 Register
00C244HIF2MSK22 [R/W]
11111111 11111111
IF2MSK12 [R/W]
11111111 11111111
00C248HIF2ARB22 [R/W]
00000000 00000000
IF2ARB12 [R/W]
00000000 00000000
00C24CHIF2MCTR2 [R/W]
00000000 00000000 Reserved
00C250HIF2DTA12 [R/W]
00000000 00000000
IF2DTA22 [R/W]
00000000 00000000
00C254HIF2DTB12 [R/W]
00000000 00000000
IF2DTB22 [R/W]
00000000 00000000
00C258H
to
00C25CH
Reserved
00C260HIF2DTA22 [R/W]
00000000 00000000
IF2DTA12 [R/W]
00000000 00000000
00C264HIF2DTB22 [R/W]
00000000 00000000
IF2DTB12 [R/W]
00000000 00000000
00C268H
to
00C27CH
Reserved
00C280HTREQR22 [R]
00000000 00000000
TREQR12 [R]
00000000 00000000
CAN 2
Status Flags
00C284H
to
00C28CH
Reserved
00C290HNEWDT22 [R]
00000000 00000000
NEWDT12 [R]
00000000 00000000
00C294H
to
00C29CH
Reserved
00C2A0HINTPND22 [R]
00000000 00000000
INTPND12 [R]
00000000 00000000
00C2A4H
to
00C2ACH
Reserved
00C2B0HMSGVAL22 [R]
00000000 00000000
MSGVAL12 [R]
00000000 00000000
00C2B4H
to
00C2FCH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 139
00C300HCTRLR3 [R/W]
00000000 00000001
STATR3 [R/W]
00000000 00000000
CAN 3
Control
Register
(MB91F467PA)
00C304HERRCNT3 [R]
00000000 00000000
BTR3 [R/W]
00100011 00000001
00C308HINTR3 [R]
00000000 00000000
TESTR3 [R/W]
00000000 X0000000
00C30CHBRPE3 [R/W]
00000000 00000000 Reserved
00C310HIF1CREQ3 [R/W]
00000000 00000001
IF1CMSK3 [R/W]
00000000 00000000
CAN 3
IF 1 Register
(MB91F467PA)
00C314HIF1MSK23 [R/W]
11111111 11111111
IF1MSK13 [R/W]
11111111 11111111
00C318HIF1ARB23 [R/W]
00000000 00000000
IF1ARB13 [R/W]
00000000 00000000
00C31CHIF1MCTR3 [R/W]
00000000 00000000 Reserved
00C320HIF1DTA13 [R/W]
00000000 00000000
IF1DTA23 [R/W]
00000000 00000000
00C324HIF1DTB13 [R/W]
00000000 00000000
IF1DTB23 [R/W]
00000000 00000000
00C328H
to
00C32CH
Reserved
00C330HIF1DTA23 [R/W]
00000000 00000000
IF1DTA13 [R/W]
00000000 00000000
00C334HIF1DTB23 [R/W]
00000000 00000000
IF1DTB13 [R/W]
00000000 00000000
00C338H
to
00C33CH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
140 DS07-16615-2E
00C340HIF2CREQ3 [R/W]
00000000 00000001
IF2CMSK3 [R/W]
00000000 00000000
CAN 3
IF 2 Register
(MB91F467PA)
00C344HIF2MSK23 [R/W]
11111111 11111111
IF2MSK13 [R/W]
11111111 11111111
00C348HIF2ARB23 [R/W]
00000000 00000000
IF2ARB13 [R/W]
00000000 00000000
00C34CHIF2MCTR3 [R/W]
00000000 00000000 Reserved
00C350HIF2DTA13 [R/W]
00000000 00000000
IF2DTA23 [R/W]
00000000 00000000
00C354HIF2DTB13 [R/W]
00000000 00000000
IF2DTB23 [R/W]
00000000 00000000
00C358H
to
00C35CH
Reserved
00C360HIF2DTA23 [R/W]
00000000 00000000
IF2DTA13 [R/W]
00000000 00000000
00C364HIF2DTB23 [R/W]
00000000 00000000
IF2DTB13 [R/W]
00000000 00000000
00C368H
to
00C37CH
Reserved
00C380HTREQR23 [R]
00000000 00000000
TREQR13 [R]
00000000 00000000
CAN 3
Status Flags
(MB91F467PA)
00C384H
to
00C38CH
Reserved
00C390HNEWDT23 [R]
00000000 00000000
NEWDT13 [R]
00000000 00000000
00C394H
to
00C39CH
Reserved
00C3A0HINTPND23 [R]
00000000 00000000
INTPND13 [R]
00000000 00000000
00C3A4H
to
00C3ACH
Reserved
00C3B0HMSGVAL23 [R]
00000000 00000000
MSGVAL13 [R]
00000000 00000000
00C3B4H
to
00EFFCH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 141
00F000HBCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
EDSU / MPU
00F004HBSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008HBIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CHBOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010HBIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
00F014H
to
00F01CH
Reserved
00F020HBCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024HBCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028HBCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CHBCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
Address Register Block
+0 +1 +2 +3
MB91460P Series
142 DS07-16615-2E
00F080HBAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDSU / MPU
00F084HBAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088HBAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CHBAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090HBAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094HBAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098HBAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CHBAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0HBAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4HBAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8HBAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACHBAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0HBAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4HBAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8HBAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCHBAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
023FFCH
Reserved
024000H
to
02FFFCH
MB91F467PA: D-RAM size is 48Kbytes: 024000H to 02FFFCH
MB91F465PA: D-RAM size is 24Kbytes: 02A000H to 02FFFCH
(data access is 0 wait cycles)
D-RAM
area
030000H
to
037FFCH
MB91F465PA: ID-RAM size is 16Kbytes: 030000H to 033FFCH
MB91F467PA: ID-RAM size is 32Kbytes: 030000H to 037FFCH
(instruction access is 0 waitcycles, data access is 1 wait cycle)
ID-RAM area
1. Writable only once and only as half-word. PPMUX is reset by INIT and RST.
Address Register Block
+0 +1 +2 +3
MB91460P Series
DS07-16615-2E 143
2. PPMUX2 is available on MB91F467PA only. Writable only once and only as half-word,
reset by INIT and RST.
3. Depends on the number of available CAN channels:
MB91F465PA has 3 CAN channels - bits[2:0] exist
MB91F467PA has 4 CAN channels - bits[3:0] exist
4. ADC1 is only available on MB91F467PA.
5. ACRO[11:10] depends on Modevector fetch information on buswidth.
6. TCR [3:0] INIT value = 0000, keeps value after RST.
7. Range Comparator for ADC0, ADC1 are only available on MB91F467PA.
8. ADC0, ADC1 channel data registers are only available on MB91F467PA.
9. On MB91F467PA, always write 1 to bit IOS[1].
10. PFR initial values for ports 00--10 depend on the selected mode at the modepins MD_0--MD_2:
internal vector fetch mode (MD=000): PFR00--PFR10 initialized to all '0'
external vector fetch mode (MD=001): PFR00--PFR10 initialized to all '1'
MB91460P Series
144 DS07-16615-2E
2. Flash Memory, Data Flash and External Bus Area
32bit
read/write *1dat[31:0] dat[31:0]
Block
16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0]
Address Register
+ 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7
040000H
to
05FFFCH
SA8 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA9 (64KB, MB91F467PA)
External bus (MB91F465PA) ROMS0
060000H
to
07FFFCH
SA10 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA11 (64KB, MB91F467PA)
External bus (MB91F465PA) ROMS1
080000H
to
09FFFCH
SA12(64kB) SA13(64kB) ROMS2
0A0000H
to
0BFFFCH
SA14(64kB) SA15(64kB) ROMS3
0C0000H
to
0DFFFCH
SA16(64kB) SA17(64kB) ROMS4
0E0000H
to
0FFFF4H
SA18(64kB) SA19(64kB)
ROMS5
0FFFFCHFMV [R] *2
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H
to
11FFF8H
SA20 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA21 (64KB, MB91F467PA)
External bus (MB91F465PA)
ROMS6
120000H
to
13FFF8H
SA22 (64KB, MB91F467PA)
External bus (MB91F465PA)
SA23 (64KB, MB91F467PA)
External bus (MB91F465PA)
140000H
to
143FFCH
SA0 (8KB, MB91F467PA)
Reserved (MB91F465PA)
SA1 (8KB, MB91F467PA)
Reserved (MB91F465PA)
ROMS7
144000H
to
17FFCH
SA2 (8KB, MB91F467PA)
Reserved (MB91F465PA)
SA3 (8KB, MB91F467PA)
Reserved (MB91F465PA)
148000H
to
14BFFCH
SA4(8kB) SA5(8kB)
14C000H
to
14FFFCH
SA6(8kB) SA7(8kB)
MB91460P Series
DS07-16615-2E 145
150000H
to
17FFFCH
Reserved ROMS7
(continued)
180000H
to
1BFFFCH
External Bus Area
ROMS8
1C0000H
to
1FFFFCH
ROMS9
200000H
to
27FFFCH
ROMS10
280000H
to
2FFFFCH
ROMS11
300000H
to
37FFFCH
ROMS12
380000H
to
3FFFFCH
ROMS13
400000H
to
47FFFCH
ROMS14
480000H
to
4FFFFCH
ROMS15
500000H
-
FFFBEFFCH
External Bus Area External Bus
FFFBF000H
-
FFFCFFFCH
Data Flash area (if enabled) or External Bus area,
Data Flash on MB91F467PA is 64 KB + 256 Byte
Data Flash
area *3
FFFD0000H
-
FFFFFFFCH
External Bus Area External bus
area
1. 32-bit write to flash memory only available on MB91F467PA.
2. Write operations to address 0FFFF8H and 0FFFFCH are not possible.
When reading these addresses, the values shown above will be read.
3. Data Flash is only available on MB91F467PA.
32bit
read/write *1dat[31:0] dat[31:0]
Block
16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0]
Address Register
+ 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7
MB91460P Series
146 DS07-16615-2E
3. Data Flash memory sector organisation
The Data Flash sectors can be accessed only after the data flash has been enabled by setting DFCS:FLASHEN.
If the data flash is enabled, the user must ensure that no chip select area overlaps the data flash address space.
MB91F467PA
32bit access dat[31:0]
16bit access dat[31:16] dat[15:0]
8bit access dat[7:0] dat[7:0] dat[7:0] dat[7:0]
Address + 0 + 1 + 2 + 3 Comments
... to
FFFB EFFCHExternal bus area
FFFB F000H
to
FFFB FEFCH
Dummy area for flash auto algorithm
addressing (write sequences)
Data Flash
FFFB FF00H
to
FFFB FFFCH
SAS (256 Byte)
Security Sector
FFFC 0000H
to
FFFC 3FFCH
SA0 (16 KB)
FFFC 4000H
to
FFFC 7FFCH
SA1 (16 KB)
FFFC 8000H
to
FFFC BFFCH
SA2 (16 KB)
FFFC C000H
to
FFFC FFFCH
SA3 (16 KB)
FFFD 0000H
to
FFFF FFFCH
External bus area
MB91460P Series
DS07-16615-2E 147
■INTERRUPT VECTOR TABLE
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
Reset 000 — —3FCH000FFFFC —
Mode vector 101 — —3F8H000FFFF8 —
System reserved 202 — —3F4H000FFFF4 —
System reserved 303 — —3F0H000FFFF0 —
System reserved 404 — —3ECH000FFFEC —
CPU supervisor mode
(INT #5 instruction) *5 505 — —3E8H000FFFE8 —
Memory Protection exception *5 606 — —3E4H000FFFE4 —
System reserved 707 — —3E0H000FFFE0 —
System reserved 808 — —3DCH000FFFDC —
System reserved 909 — —3D8H000FFFD8 —
System reserved 10 0A — — 3D4H000FFFD4 —
System reserved 11 0B — — 3D0H000FFFD0 —
System reserved 12 0C — — 3CCH000FFFCC —
System reserved 13 0D — — 3C8H000FFFC8 —
Undefined instruction
exception 14 0E — — 3C4H000FFFC4 —
NMI request 15 0F FH fixed 3C0H000FFFC0 —
External Interrupt 0 16 10 ICR00 440H
3BCH000FFFBC 0, 16
External Interrupt 1 17 11 3B8H000FFFB8 1, 17
External Interrupt 2 18 12 ICR01 441H
3B4H000FFFB4 2, 18
External Interrupt 3 19 13 3B0H000FFFB0 3, 19
External Interrupt 4 20 14 ICR02 442H
3ACH000FFFAC 20
External Interrupt 5 21 15 3A8H000FFFA8 21
External Interrupt 6 22 16 ICR03 443H
3A4H000FFFA4 22
External Interrupt 7 23 17 3A0H000FFFA0 23
External Interrupt 8 24 18 ICR04 444H
39CH000FFF9C —
External Interrupt 9 25 19 398H000FFF98 —
External Interrupt 10 26 1A ICR05 445H
394H000FFF94 —
External Interrupt 11 27 1B 390H000FFF90 —
External Interrupt 12 28 1C ICR06 446H
38CH000FFF8C —
External Interrupt 13 29 1D 388H000FFF88 —
MB91460P Series
148 DS07-16615-2E
External Interrupt 14 30 1E ICR07 447H
384H000FFF84 —
External Interrupt 15 31 1F 380H000FFF80 —
Reload Timer 0
Reload Timer 8 32 20
ICR08 448H
37CH000FFF7C 4, 32
128
Reload Timer 1
Reload Timer 9 33 21 378H000FFF78 5, 33
129
Reload Timer 2
Reload Timer 10 34 22
ICR09 449H
374H000FFF74 34
130
Reload Timer 3
Reload Timer 11 35 23 370H000FFF70 35
131
Reload Timer 4
Reload Timer 12 36 24
ICR10 44AH
36CH000FFF6C 36
132
Reload Timer 5
Reload Timer 13 37 25 368H000FFF68 37
133
Reload Timer 6
Reload Timer 14 38 26
ICR11 44BH
364H000FFF64 38
134
Reload Timer 7
Reload Timer 15 39 27 360H000FFF60 39
135
Free Run Timer 0 40 28 ICR12 44CH
35CH000FFF5C 40
Free Run Timer 1 41 29 358H000FFF58 41
Free Run Timer 2 42 2A ICR13 44DH
354H000FFF54 42
Free Run Timer 3 43 2B 350H000FFF50 43
Free Run Timer 4 44 2C ICR14 44EH
34CH000FFF4C 44
Free Run Timer 5 45 2D 348H000FFF48 45
Free Run Timer 6 46 2E ICR15 44FH
344H000FFF44 46
Free Run Timer 7 47 2F 340H000FFF40 47
CAN 0 48 30 ICR16 450H
33CH000FFF3C —
CAN 1 49 31 338H000FFF38 —
CAN 2 50 32 ICR17 451H
334H000FFF34 —
CAN 3 *651 33 330H000FFF30 —
Reserved 52 34 ICR18 452H
32CH000FFF2C —
Reserved 53 35 328H000FFF28 —
LIN-USART 0 RX 54 36 ICR19 453H
324H000FFF24 6, 48
LIN-USART 0 TX 55 37 320H000FFF20 7, 49
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
MB91460P Series
DS07-16615-2E 149
LIN-USART 1 RX 56 38 ICR20 454H
31CH000FFF1C 8, 50
LIN-USART 1 TX 57 39 318H000FFF18 9, 51
LIN-USART 2 RX 58 3A ICR21 455H
314H000FFF14 52
LIN-USART 2 TX 59 3B 310H000FFF10 53
LIN-USART 3 RX 60 3C ICR22 456H
30CH000FFF0C 54
LIN-USART 3 TX 61 3D 308H000FFF08 55
System reserved 62 3E ICR23 *3 457H
304H000FFF04 —
Delayed Interrupt 63 3F 300H000FFF00 —
System reserved *4 64 40 (ICR24) (458H)2FCH000FFEFC —
System reserved *4 65 41 2F8H000FFEF8 —
LIN-USART (FIFO) 4 RX 66 42 ICR25 459H
2F4H000FFEF4 10, 56
LIN-USART (FIFO) 4 TX 67 43 2F0H000FFEF0 11, 57
LIN-USART (FIFO) 5 RX 68 44 ICR26 45AH
2ECH000FFEEC 12, 58
LIN-USART (FIFO) 5 TX 69 45 2E8H000FFEE8 13, 59
LIN-USART (FIFO) 6 RX 70 46 ICR27 45BH
2E4H000FFEE4 60
LIN-USART (FIFO) 6 TX 71 47 2E0H000FFEE0 61
LIN-USART (FIFO) 7 RX 72 48 ICR28 45CH
2DCH000FFEDC 62
LIN-USART (FIFO) 7 TX 73 49 2D8H000FFED8 63
I2C 0 / I2C 2 74 4A ICR29 45DH
2D4H000FFED4 —
I2C 1 / I2C 3 75 4B 2D0H000FFED0 —
LIN-USART 8 RX 76 4C ICR30 45EH
2CCH000FFECC 64
LIN-USART 8 TX 77 4D 2C8H000FFEC8 65
LIN-USART 9 RX 78 4E ICR31 45FH
2C4H000FFEC4 66
LIN-USART 9 TX 79 4F 2C0H000FFEC0 67
LIN-USART 10 RX 80 50 ICR32 460H
2BCH000FFEBC 68
LIN-USART 10 TX 81 51 2B8H000FFEB8 69
LIN-USART 11 RX 82 52 ICR33 461H
2B4H000FFEB4 70
LIN-USART 11 TX 83 53 2B0H000FFEB0 71
Reserved 84 54 ICR34 462H
2ACH000FFEAC 72
Reserved 85 55 2A8H000FFEA8 73
Reserved 86 56 ICR35 463H
2A4H000FFEA4 74
Reserved 87 57 2A0H000FFEA0 75
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
MB91460P Series
150 DS07-16615-2E
Reserved 88 58 ICR36 464H
29CH000FFE9C 76
Reserved 89 59 298H000FFE98 77
Reserved 90 5A ICR37 465H
294H000FFE94 78
Reserved 91 5B 290H000FFE90 79
Input Capture 0 92 5C ICR38 466H
28CH000FFE8C 80
Input Capture 1 93 5D 288H000FFE88 81
Input Capture 2 94 5E ICR39 467H
284H000FFE84 82
Input Capture 3 95 5F 280H000FFE80 83
Input Capture 4 96 60 ICR40 468H
27CH000FFE7C 84
Input Capture 5 97 61 278H000FFE78 85
Input Capture 6 98 62 ICR41 469H
274H000FFE74 86
Input Capture 7 99 63 270H000FFE70 87
Output Compare 0 100 64 ICR42 46AH
26CH000FFE6C 88
Output Compare 1 101 65 268H000FFE68 89
Output Compare 2 102 66 ICR43 46BH
264H000FFE64 90
Output Compare 3 103 67 260H000FFE60 91
Output Compare 4 104 68 ICR44 46CH
25CH000FFE5C 92
Output Compare 5 105 69 258H000FFE58 93
Output Compare 6 106 6A ICR45 46DH
254H000FFE54 94
Output Compare 7 107 6B 250H000FFE50 95
Sound Generator 108 6C ICR46 46EH
24CH000FFE4C —
Phase Frequency Modulator 109 6D 248H000FFE48 —
System reserved 110 6E ICR47 *3 46FH
244H000FFE44 —
System reserved 111 6F 240H000FFE40 —
PPG0
PPG16 112 70
ICR48 470H
23CH000FFE3C 15, 96
144
PPG1
PPG17 113 71 238H000FFE38 97
145
PPG2
PPG18 114 72
ICR49 471H
234H000FFE34 98
146
PPG3
PPG19 115 73 230H000FFE30 99
147
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
MB91460P Series
DS07-16615-2E 151
PPG4
PPG20 116 74
ICR50 472H
22CH000FFE2C 100
148
PPG5
PPG21 117 75 228H000FFE28 101
149
PPG6
PPG22 118 76
ICR51 473H
224H000FFE24 102
150
PPG7
PPG23 119 77 220H000FFE20 103
151
PPG8
PPG24 120 78
ICR52 474H
21CH000FFE1C 104
152
PPG9
PPG25 121 79 218H000FFE18 105
153
PPG10
PPG26 122 7A
ICR53 475H
214H000FFE14 106
154
PPG11
PPG27 123 7B 210H000FFE10 107
155
PPG12
PPG28 124 7C
ICR54 476H
20CH000FFE0C 108
156
PPG13
PPG29 125 7D 208H000FFE08 109
157
PPG14
PPG30 126 7E
ICR55 477H
204H000FFE04 110
158
PPG15
PPG31 127 7F 200H000FFE00 111
159
Up/Down Counter 0 128 80 ICR56 478H
1FCH000FFDFC —
Up/Down Counter 1 129 81 1F8H000FFDF8 —
Up/Down Counter 2 130 82 ICR57 479H
1F4H000FFDF4 —
Up/Down Counter 3 131 83 1F0H000FFDF0 —
Real Time Clock 132 84 ICR58 47AH
1ECH000FFDEC —
Calibration Unit 133 85 1E8H000FFDE8 —
A/D Converter 0
A/D Converter 0 End of Scan *6134 86
ICR59 47BH
1E4H000FFDE4 14, 112
120 *6
A/D Converter 1 *6
A/D Converter 1 End of Scan *6135 87 1E0H000FFDE0 113 *6
121 *6
Reserved 136 88 ICR60 47CH
1DCH000FFDDC —
Reserved 137 89 1D8H000FFDD8 —
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
MB91460P Series
152 DS07-16615-2E
Notes:
*1 The The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for
each interrupt request. An ICR is provided for each interrupt request.
*2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table
base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table
are for the default TBR value (000FFC00H). The TBR is initialized to this value by a reset. The TBR is set to
000FFC00H after the internal boot ROM is executed.
*3 ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
*4 Used by REALOS
*5 Memory Protection Unit (MPU) support
*6 CAN 3, Data Flash, ADC1 and ADC0 (End of Scan) interrupts are available on MB91F467PA only.
Low Voltage Detection 138 8A ICR61 47DH
1D4H000FFDD4 —
Reserved 139 8B 1D0H000FFDD0 —
Timebase Overflow 140 8C
ICR62 47EH
1CCH000FFDCC —
PLL Clock Gear
Data Flash Write Complete *6141 8D 1C8H000FFDC8 —
195 *6
DMA Controller 142 8E ICR63 47FH
1C4H000FFDC4 —
Main/Sub OSC stability wait 143 8F 1C0H000FFDC0 —
Security vector 144 90 — — 1BCH000FFDBC —
Used by the INT instruction 145
to
255
91
to
FF
——
1B8H to
000H
000FFDB8
to
000FFC00
—
Interrupt
Interrupt num-
ber Interrupt level *1Interrupt vector *2
DMA
Resource
number
Deci-
mal
Hexa-
deci-
mal
Setting
Register
Register
address Offset Default vec-
tor address
MB91460P Series
DS07-16615-2E 153
■RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F465PA the core base clock frequencies are valid in the 1.8V operation mode of the
Main regulator and Flash .
Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
Frequency Parameter Clockgear Parameter
PLL
Output (X)
[MHz]
Core Base
Clock
[MHz] Remarks
DIVM DIVN DIVG MULG MULG
4 2 25 16 24 200 100
4 2 24 16 24 192 96
4 2 23 16 24 184 92
4 2 22 16 24 176 88
4 2 21 16 20 168 84
4 2 20 16 20 160 80
4 2 19 16 20 152 76
4 2 18 16 20 144 72
4 2 17 16 16 136 68
4 2 16 16 16 128 64
4 2 15 16 16 120 60
4 2 14 16 16 112 56
4 2 13 16 12 104 52
4 2 12 16 12 96 48
4 2 11 16 12 88 44
4 4 10 16 24 160 40
449162414436
448162412832
447162411228
466162414424
485162816020
4 10 4 16 32 160 16
4 12 3 16 32 144 12
MB91460P Series
154 DS07-16615-2E
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from
32MHz up to 88MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings
should be set according to base clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1 3 026F 88 79.5 98.5
1 3 026F 84 76.1 93.8
1 3 026F 80 72.6 89.1
1 5 02AE 80 68.7 95.8
2 3 046E 80 68.7 95.8
1 3 026F 76 69.1 84.5
1 5 02AE 76 65.3 90.8
1 7 02ED 76 62 98.1
2 3 046E 76 65.3 90.8
3 3 066D 76 62 98.1
1 3 026F 72 65.5 79.9
1 5 02AE 72 62 85.8
1 7 02ED 72 58.8 92.7
2 3 046E 72 62 85.8
3 3 066D 72 58.8 92.7
1 3 026F 68 62 75.3
1 5 02AE 68 58.7 80.9
1 7 02ED 68 55.7 87.3
1 9 032C 68 53 95
2 3 046E 68 58.7 80.9
2 504AC685395
3 3 066D 68 55.7 87.3
4 3 086C 68 53 95
1 3 026F 64 58.5 70.7
1 5 02AE 64 55.3 75.9
1 7 02ED 64 52.5 82
1 9 032C 64 49.9 89.1
1 11 036B 64 47.6 97.6
2 3 046E 64 55.3 75.9
2 5 04AC 64 49.9 89.1
3 3 066D 64 52.5 82
MB91460P Series
DS07-16615-2E 155
4 3 086C 64 49.9 89.1
5 3 0A6B 64 47.6 97.6
1 3 026F 60 54.9 66.1
1 5 02AE 60 51.9 71
1 7 02ED 60 49.3 76.7
1 9 032C 60 46.9 83.3
1 11 036B 60 44.7 91.3
2 3 046E 60 51.9 71
2 5 04AC 60 46.9 83.3
3 3 066D 60 49.3 76.7
4 3 086C 60 46.9 83.3
5 3 0A6B 60 44.7 91.3
1 3 026F 56 51.4 61.6
1 5 02AE 56 48.6 66.1
1 7 02ED 56 46.1 71.4
1 9 032C 56 43.8 77.6
1 11 036B 56 41.8 84.9
1 13 03AA 56 39.9 93.8
2 3 046E 56 48.6 66.1
2 5 04AC 56 43.8 77.6
2 7 04EA 56 39.9 93.8
3 3 066D 56 46.1 71.4
3 5 06AA 56 39.9 93.8
4 3 086C 56 43.8 77.6
5 3 0A6B 56 41.8 84.9
6 3 0C6A 56 39.9 93.8
1 3 026F 52 47.8 57
1 5 02AE 52 45.2 61.2
1 7 02ED 52 42.9 66.1
1 9 032C 52 40.8 71.8
1 11 036B 52 38.8 78.6
1 13 03AA 52 37.1 86.8
1 15 03E9 52 35.5 96.9
2 3 046E 52 45.2 61.2
2 5 04AC 52 40.8 71.8
2 7 04EA 52 37.1 86.8
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
MB91460P Series
156 DS07-16615-2E
3 3 066D 52 42.9 66.1
3 5 06AA 52 37.1 86.8
4 3 086C 52 40.8 71.8
5 3 0A6B 52 38.8 78.6
6 3 0C6A 52 37.1 86.8
7 3 0E69 52 35.5 96.9
1 3 026F 48 44.2 52.5
1 5 02AE 48 41.8 56.4
1 7 02ED 48 39.6 60.9
1 9 032C 48 37.7 66.1
1 11 036B 48 35.9 72.3
1 13 03AA 48 34.3 79.9
1 15 03E9 48 32.8 89.1
2 3 046E 48 41.8 56.4
2 5 04AC 48 37.7 66.1
2 7 04EA 48 34.3 79.9
3 3 066D 48 39.6 60.9
3 5 06AA 48 34.3 79.9
4 3 086C 48 37.7 66.1
5 3 0A6B 48 35.9 72.3
6 3 0C6A 48 34.3 79.9
7 3 0E69 48 32.8 89.1
1 3 026F 44 40.6 48.1
1 5 02AE 44 38.4 51.6
1 7 02ED 44 36.4 55.7
1 9 032C 44 34.6 60.4
1 11 036B 44 33 66.1
1 13 03AA 44 31.5 73
1 15 03E9 44 30.1 81.4
2 3 046E 44 38.4 51.6
2 5 04AC 44 34.6 60.4
2 7 04EA 44 31.5 73
2 9 0528 44 28.9 92.1
3 3 066D 44 36.4 55.7
3 5 06AA 44 31.5 73
4 3 086C 44 34.6 60.4
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
MB91460P Series
DS07-16615-2E 157
4 5 08A8 44 28.9 92.1
5 3 0A6B 44 33 66.1
6 3 0C6A 44 31.5 73
7 3 0E69 44 30.1 81.4
8 3 1068 44 28.9 92.1
1 3 026F 40 37 43.6
1 5 02AE 40 34.9 46.8
1 7 02ED 40 33.1 50.5
1 9 032C 40 31.5 54.8
1 11 036B 40 30 59.9
1 13 03AA 40 28.7 66.1
1 15 03E9 40 27.4 73.7
2 3 046E 40 34.9 46.8
2 5 04AC 40 31.5 54.8
2 7 04EA 40 28.7 66.1
2 9 0528 40 26.3 83.3
3 3 066D 40 33.1 50.5
3 5 06AA 40 28.7 66.1
3 7 06E7 40 25.3 95.8
4 3 086C 40 31.5 54.8
4 5 08A8 40 26.3 83.3
5 3 0A6B 40 30 59.9
6 3 0C6A 40 28.7 66.1
7 3 0E69 40 27.4 73.7
8 3 1068 40 26.3 83.3
9 3 1267 40 25.3 95.8
1 3 026F 36 33.3 39.2
1 5 02AE 36 31.5 42
1 7 02ED 36 29.9 45.3
1 9 032C 36 28.4 49.2
1 11 036B 36 27.1 53.8
1 13 03AA 36 25.8 59.3
1 15 03E9 36 24.7 66.1
2 3 046E 36 31.5 42
2 5 04AC 36 28.4 49.2
2 7 04EA 36 25.8 59.3
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
MB91460P Series
158 DS07-16615-2E
2 9 0528 36 23.7 74.7
3 3 066D 36 29.9 45.3
3 5 06AA 36 25.8 59.3
3 7 06E7 36 22.8 85.8
4 3 086C 36 28.4 49.2
4 5 08A8 36 23.7 74.7
5 3 0A6B 36 27.1 53.8
6 3 0C6A 36 25.8 59.3
7 3 0E69 36 24.7 66.1
8 3 1068 36 23.7 74.7
9 3 1267 36 22.8 85.8
1 3 026F 32 29.7 34.7
1 5 02AE 32 28 37.3
1 7 02ED 32 26.6 40.2
1 9 032C 32 25.3 43.6
1 11 036B 32 24.1 47.7
1 13 03AA 32 23 52.5
1 15 03E9 32 22 58.6
2 3 046E 32 28 37.3
2 5 04AC 32 25.3 43.6
2 7 04EA 32 23 52.5
2 9 0528 32 21.1 66.1
2 11 0566 32 19.5 89.1
3 3 066D 32 26.6 40.2
3 5 06AA 32 23 52.5
3 7 06E7 32 20.3 75.9
4 3 086C 32 25.3 43.6
4 5 08A8 32 21.1 66.1
5 3 0A6B 32 24.1 47.7
5 5 0AA6 32 19.5 89.1
6 3 0C6A 32 23 52.5
7 3 0E69 32 22 58.6
8 3 1068 32 21.1 66.1
9 3 1267 32 20.3 75.9
10 3 1466 32 19.5 89.1
Modulation
Degree (k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
MB91460P Series
DS07-16615-2E 159
■ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter Symbol Rating Unit Remarks
Min Max
Power supply slew rate ⎯⎯ 50 V/ms
Power supply voltage 1*1VDD5R - 0.3 + 6.0 V
Power supply voltage 2*1VDD5 - 0.3 + 6.0 V
Power supply voltage 3*1VDD35 - 0.3 + 6.0 V
Relationship of the supply
voltages AVCC5
VDD5-0.3 VDD5+0.3 V
At least one of the pins
P07, P16, P20, P24, or
P29 (ANn) is used as
digital input or output.
VSS5-0.3 VDD5+0.3 V
All pins of the ports P07,
P16, P20, P24, or P29
(ANn) follow the condition
of VIA
Analog power supply voltage*1AVCC5 - 0.3 + 6.0 V *2
Analog reference
power supply voltage*1AVRH - 0.3 + 6.0 V *2
Input voltage 1*1VI1 Vss5 - 0.3 VDD5 + 0.3 V
Input voltage 2*1VI2 Vss5 - 0.3 VDD35 + 0.3 V External bus
Analog pin input voltage*1VIA AVss5 - 0.3 AVcc5 + 0.3 V
Output voltage 1*1VO1 Vss5 - 0.3 VDD5 + 0.3 V
Output voltage 2*1VO2 Vss5 - 0.3 VDD35 + 0.3 V External bus
Maximum clamp current ICLAMP - 4.0 + 4.0 mA *3
Total maximum clamp current Σ |ICLAMP|⎯ 20 mA *3
“L” level maximum
output current*4IOL ⎯10 mA
“L” level average
output current*5IOLAV ⎯8mA
“L” level total maximum
output current ΣIOL ⎯100 mA
“L” level total average
output current*6ΣIOLAV ⎯50 mA
“H” level maximum
output current*4IOH ⎯ - 10 mA
“H” level average
output current*5IOHAV ⎯ - 4 mA
“H” level total maximum
output current ΣIOH ⎯ - 100 mA
“H” level total average output
current*6ΣIOHAV ⎯ - 25 mA
MB91460P Series
160 DS07-16615-2E
*1 : The parameter is based on VSS5 = AVSS5 = 0.0 V.
*2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V.
*3 : •Use within recommended operating conditions.
•Use with DC voltage (current).
•+B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by
connecting a limiting resistor between the +B signal and the microcontroller.
•The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal
is input.
•Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting
other devices.
•Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through
the +B input pin; therefore, the microcontroller may partially operate.
•Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset
may not function in the power supply voltage.
Permitted operating frequency
fmax, CLKB ⎯100
MHz TA < 105 °C
fmax, CLKP ⎯50
fmax, CLKT ⎯50
fmax, CLKCAN ⎯50
Permitted operating frequency
fmax, CLKB ⎯96
MHz TA < 125 °C
fmax, CLKP ⎯48
fmax, CLKT ⎯48
fmax, CLKCAN ⎯48
Permitted power dissipation *7 PD
⎯ 1250 *8 mW TA < 85 °C
⎯ 630 *8 mW TA < 105 °C
⎯ 1400 *8 mW TA < 105 °C, no Flash pro-
gram/erase *9
⎯1100 *8 mW TA < 115 °C, no Flash pro-
gram/erase *9
⎯ 780 *8 mW TA < 125 °C, no Flash pro-
gram/erase *9
Operating temperature TA - 40 + 125 °C
Storage temperature Tstg - 55 + 150 °C
Parameter Symbol Rating Unit Remarks
Min Max
MB91460P Series
DS07-16615-2E 161
•Do not leave +B input pins open.
•Example of recommended circuit :
*4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*5 : Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 100 ms period.
*6 : Total average output current is defined as the value of the average current flowing through all of the
corresponding pins for a 100 ms period.
*7 : The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL * IOL + VOH + IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VDD5R * ICC + AVCC5 * IA + AVRH5 * IR (internal power dissipation)
*8 : Worst case value for the QFP package mounted on a 4-layer PCB at specified TA without air flow.
*9 : Please contact Fujitsu for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
• Input/output equivalent circuit
+B input (0 V to 16 V)
Limiting
resistor
Protective diode
MB91460P Series
162 DS07-16615-2E
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage
VDD53.0 ⎯5.5 V
VDD5R 3.0 ⎯5.5 V Internal regulator
VDD35 3.0 ⎯5.5 V External bus
AVCC53.0 ⎯5.5 V A/D converter
Smoothing capacitor at
VCC18C pin CS⎯4.7 ⎯μF
Use a X7R ceramic capacitor or
a capacitor that has similar fre-
quency characteristics.
Power supply slew rate ⎯⎯50 V/ms
Main Oscillation
stabilisation time 10 ms
Lock-up time PLL
(4 MHz ->16 ...100MHz) 0.6 ms
ESD Protection
(Human body model) Vsurge 2kV
Rdischarge = 1.5kΩ
Cdischarge = 100pF
RC Oscillator fRC100kHz
fRC2MHz
50
1
100
2
200
4
kHz
MHz VDDCORE > 1.65V
C
S
AVSS5
VSS5
VCC18C
MB91460P Series
DS07-16615-2E 163
3. DC characteristics
Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins.
In the following tables, “VSS” means ground Pins VSS5 for the other pins.
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input “H”
voltage
VIH
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
0.8 × VDD ⎯VDD + 0.3 V
CMOS
hysteresis
input
⎯
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
0.7 × VDD ⎯VDD + 0.3 V 4.5 V < VDD < 5.5 V
0.74 × V DD ⎯VDD + 0.3 V 3 V < VDD < 4.5 V
⎯
AUTOMOTIVE
Hysteresis input is
selected
0.8 × VDD ⎯VDD + 0.3 V
⎯Port inputs if TTL
input is selected 2.0 ⎯VDD + 0.3 V
VIHR INITX ⎯0.8 × VDD ⎯VDD + 0.3 V
INITX input pin
(CMOS
Hysteresis)
VIHM MD_2 to
MD_0 ⎯VDD - 0.3 ⎯VDD + 0.3 V Mode input pins
VIHX0S X0, X0A ⎯2.5 ⎯VDD + 0.3 V External clock in
“Oscillation mode”
VIHX0F X0 ⎯0.8 × VDD ⎯VDD + 0.3 V
External clock in
“Fast Clock Input
mode”
Input “L”
voltage
VIL
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
VSS - 0.3 ⎯0.2 × VDD V
⎯
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
VSS - 0.3 ⎯0.3 × VDD V
⎯
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS - 0.3 ⎯0.5 × VDD V4.5 V < VDD < 5.5 V
VSS - 0.3 ⎯0.46 × VDD V3 V < VDD < 4.5 V
⎯Port inputs if TTL
input is selected VSS - 0.3 ⎯0.8 V
VILR INITX ⎯VSS - 0.3 ⎯0.2 × VDD V
INITX input pin
(CMOS
Hysteresis)
VILM MD_2 to
MD_0 ⎯VSS - 0.3 ⎯VSS + 0.3 V Mode input pins
VILXDS X0, X0A ⎯VSS - 0.3 ⎯0.5 V External clock in
“Oscillation mode”
MB91460P Series
164 DS07-16615-2E
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Typ Max
Input “L”
voltage VILXDF X0 ⎯VSS - 0.3 ⎯0.2 × VDD V
External clock in
“Fast Clock Input
mode”
Output “H”
voltage
VOH2 Normal
outputs
4.5V VDD 5.5V,
IOH = - 2mA VDD - 0.5 ⎯⎯VDriving strength
set to 2 mA
3.0V VDD 4.5V,
IOH = - 1.6mA
VOH5 Normal
outputs
4.5V VDD 5.5V,
IOH = - 5mA VDD - 0.5 ⎯⎯VDriving strength
set to 5 mA
3.0V VDD 4.5V,
IOH = - 3mA
VOH3 I2C
outputs
3.0V VDD 5.5V,
IOH = - 3mA VDD - 0.5 ⎯⎯V
Output “L”
voltage
VOL2 Normal
outputs
4.5V VDD 5.5V,
IOL = + 2mA ⎯⎯0.4 V Driving strength
set to 2 mA
3.0V VDD 4.5V,
IOL = + 1.6mA
VOL5 Normal
outputs
4.5V VDD 5.5V,
IOL = + 5mA ⎯⎯0.4 V Driving strength
set to 5 mA
3.0V VDD 4.5V,
IOL = + 3mA
VOL3 I2C
outputs
3.0V VDD 5.5V,
IOL = + 3mA ⎯⎯0.4 V
Input leak-
age current IIL Pnn_m
*1
3.0V VDD 5.5V
VSS5 < VI < VDD
TA=25 °C
- 1 ⎯ + 1
μA
3.0V VDD 5.5V
VSS5 < VI < VDD
TA=125 °C
- 3 ⎯ + 3
Analog in-
put leak-
age current
IAIN ANn *2
3.0V VDD 5.5V
TA=25 °C - 1 ⎯ + 1 μA
3.0V VDD 5.5V
TA=125 °C - 3 ⎯ + 3 μA
Pull-up
resistance RUP
Pnn_m
*3,
INITX
3.0V VDD 3.6V 40 100 160
kΩ
4.5V VDD 5.5V 25 50 100
Pull-down
resistance RDOWN Pnn_m
*4
3.0V VDD 3.6V 40 100 180 kΩ
4.5V VDD 5.5V 25 50 100
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
≤
MB91460P Series
DS07-16615-2E 165
Input
capaci-
tance
CIN
All ex-
cept
VDD5,
VDD5R,
VSS5,
AVCC5,
AVSS5,
AVRH5
f = 1 MHz - 5 15 pF
Power
supply
current
MB91-
F465PA
ICC VDD5R
CLKB: 100 MHz
CLKP: 50 MHz
CLKT: 50 MHz
CLKCAN: 50 MHz
- 110 140 mA Code fetch from
Flash
ICCH VDD5R
TA = + 25 °C - 30 150 μA
At stop mode *5
TA = + 105 °C - 0.3 2.0 mA
TA = + 125 °C - 0.75 5.0 mA
TA = + 25 °C - 100 500 μA
RTC :
4 MHz mode *5
TA = + 105 °C - 0.5 2.4 mA
TA = + 125 °C - 0.85 5.4 mA
TA = + 25 °C - 50 250 μA
RTC :
100 kHz mode *5
TA = + 105 °C - 0.4 2.2 mA
TA = + 125 °C - 0.8 5.2 mA
ILVE VDD5⎯⎯70 150 μAExternal low volt-
age detection
ILVI VDD5R ⎯⎯50 100 μAInternal low volt-
age detection
IOSC VDD5
- - 250 500 μAMain clock
(4 MHz)
- - 20 40 μASub clock
(32 kHz)
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Typ Max
MB91460P Series
166 DS07-16615-2E
Power
supply
current
MB91-
F467PA *6
ICC VDD5R
CLKB: 100 MHz
CLKP: 50 MHz
CLKT: 50 MHz
CLKCAN: 50 MHz
- 130 160 mA
Code fetch from
Flash, Data
Flash enabled
ICCH VDD5R
TA = + 25 °C - 30 150 μA
At stop mode *7
TA = + 105 °C - 0.3 2.0 mA
TA = + 125 °C - 0.75 5.0 mA
TA = + 25 °C - 100 500 μA
RTC :
4 MHz mode
TA = + 105 °C - 0.5 2.4 mA
TA = + 125 °C - 0.85 5.4 mA
TA = + 25 °C - 50 250 μA
RTC :
100 kHz mode
TA = + 105 °C - 0.4 2.2 mA
TA = + 125 °C - 0.8 5.2 mA
ILVE VDD5⎯⎯70 150 μAExternal low volt-
age detection
ILVI VDD5R ⎯⎯50 100 μAInternal low volt-
age detection
IOSC VDD5
- - 250 500 μAMain clock
(4 MHz)
- - 20 40 μASub clock
(32 kHz)
1. Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.
2. ANn includes all pins where AN channels are enabled.
3. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
4. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
5. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
6. MB91F467PA target data
7. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Typ Max
MB91460P Series
DS07-16615-2E 167
4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
(Continued)
Note : The accuracy gets worse as AVRH - AVRL becomes smaller
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯ ⎯ 10 bit
Total error ⎯⎯ - 3 ⎯ + 3 LSB
Nonlinearity error ⎯⎯ - 2.5 ⎯ + 2.5 LSB
Differential nonlinearity
error ⎯⎯ - 1.9 ⎯ + 1.9 LSB
Zero reading voltage VOT ANn AVRL-1.5
LSB
AVRL + 0.5
LSB
AVRL + 2.5
LSB V
Full scale reading voltage VFST ANn AVRH-3.5
LSB
AVRH-1.5
LSB
AVRH + 0.5
LSB V
Compare time Tcomp ⎯
0.6 ⎯16,500 μs4.5 V < AVCC5 <
5.5
2.0 ⎯⎯μs3.0 V < AVCC5 <
4.5 V
Sampling time Tsamp ⎯
0.4 ⎯⎯μs
4.5 V < AVCC5 <
5.5 V,
REXT < 2 kΩ
1.0 ⎯⎯μs
3.0 V < AVCC5 <
4.5 V,
REXT < 1 kΩ
Conversion time Tconv ⎯
1.0 ⎯⎯μs4.5 V < AVCC5 <
5.5 V
3.0 ⎯⎯μs3.0 V < AVCC5 <
4.5 V
Input capacitance CIN ANn ⎯⎯11 pF
Input resistance RIN ANn
⎯⎯2.6 kΩ4.5 V < AVCC5 <
5.5 V
⎯⎯12.1 kΩ3.0 V < AVCC5 <
4.5 V
Analog input leakage
current IAIN ANn − 1 ⎯ + 1 μAT
A = + 25 °C
− 3 ⎯ + 3 μAT
A = + 125 °C
Analog input voltage range VAIN ANn AVRL ⎯AVRH V
Offset between input chan-
nels ⎯ANn ⎯⎯ 4LSB
MB91460P Series
168 DS07-16615-2E
(Continued)
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating,
(VDD5 = AVCC5 = AVRH = 5.0 V)
*2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
*3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the
current values have to be multiplied by the number of macros.
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V < AVCC5 < 5.5V
Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V < AVCC5 < 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by the A/D converter.
• Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
• Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error,
full scale transition error, and nonlinearity error.
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Reference voltage range
AVRH AVRH5 0.75 ×
AVCC5⎯AVCC5V
AVRL AVSS5AVSS5⎯AVCC5 ×
0.25 V
Power supply current
per ADC macro *3
IAAVCC5⎯2.5 5 mA A/D Converter
active
IAH AVCC5⎯⎯ 5μAA/D Converter
not operated *1
Reference voltage current
per ADC macro *3
IRAVRH5 ⎯0.7 1 mA A/D Converter
active
IRH AVRH5 ⎯⎯ 5μAA/D Converter
not operated *2
MB91460P Series
DS07-16615-2E 169
(Continued)
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVSS5 AVRH
0.5 LSB'
{1 LSB’ (N - 1) + 0.5 LSB’}
1.5 LSB’
Analog input
Total error
Digital output
Actual conversion
characteristics
VNT
(
measurement value)
Ideal characteristics
Actual conversion
characteristics
Total error of digital output N = 1 LSB'
VNT - {1 LSB' × (N - 1) + 0.5 LSB'}
N : A/D converter digital output value
VOT' (ideal value) = AVSS5 + 0.5 LSB' [V]
VFST' (ideal value) = AVRH - 1.5 LSB' [V]
VNT : Voltage at which the digital output changes from (N + 1) H to NH
1LSB' (ideal value) = 1024
AVRH - AVSS5[V]
MB91460P Series
170 DS07-16615-2E
(Continued)
(N+1)
H
N
H
(N-1)
H
(N-2)
H
AV
SS
5 AVRH
3FFH
3FEH
3FDH
004H
003H
002H
001H
AV
SS
5 AVRH
{1 LSB (N - 1) + V
OT
}
Analog inputAnalog input
Differential nonlinearity errorNonlinearity error
Digital output
Digital output
Actual conversion characteristics
VFST
(measure-
ment value)
VNT
(measure-
ment value)
Actual conversion
characteristics
Ideal characteristics
VTO (measurement value)
Actual conversion characteristics
VNT
(measure-
ment value)
VFST
(measure-
ment value)
Nonlinearity error of digital output N = 1LSB
VNT - {1LSB × (N - 1) + VOT}[LSB]
Differential nonlinearity error of digital output N = 1LSB
V (N + 1) T - VNT - 1 [LSB]
1LSB = 1022
VFST - VOT [V]
N : A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
Actual conversion
characteristics
Ideal
characteristics
MB91460P Series
DS07-16615-2E 171
5. FLASH memory program/erase characteristics
5.1. MB91F465PA
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
5.2. MB91F467PA
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
Parameter Value Unit Remarks
Min Typ Max
Sector erase time - 0.9 3.6 s Erasure programming time not
included
Chip erase time - n*0.9 n*3.6 s n is the number of Flash sector
of the device
Word (16-bit width) pro-
gramming time - 23 370 μsSystem overhead time not in-
cluded
Programme/Erase cycle 10 000 cycle
Flash data retention time 20 year *1
Parameter Value Unit Remarks
Min Typ Max
Sector erase time - 0.5 2.0 s Erasure programming time not
included
Chip erase time - n*0.5 n*2.0 s n is the number of Flash sector
of the device
Word (16 or 32-bit width)
programming time - 6 100 μsSystem overhead time not in-
cluded
Program/Erase cycle 10 000 cycle
Flash data retention time 20 year *1
MB91460P Series
172 DS07-16615-2E
5.3. MB91F467PA DATA FLASH
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = -40 oC to + 105 oC)
Parameter Value Unit Remarks
Min Typ Max
Sector erase time
-0.52.0s
Erasure programming time not
included
-0.83.6s
Erasure programming time is
included
Bye programming time - 15 100 μsSystem overhead time not in-
cluded
Word programming time
(32bit width command
sequencer write *1)
1. The time from CPU write access until the interrupt flag DFWS:FININT is set.
It includes 4 byte programming times + 180 CLKB cycles for write sequence, RDY
polling and result verification done by the command sequencer. Does not include
the interrupt latency time of the CPU.
- 63 403 μs
System overhead time is in-
cluded
CLKB = 64 MHz
Program/Erase cycle 100 000 cycle at Tj=<105 oC /
10,000 cycle at Tj>105 oC
MB91460P Series
DS07-16615-2E 173
6. AC characteristics
6.1. Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 oC to + 125 oC)
• Clock timing condition
Parameter Symbol Pin name Value Unit Condition
Min Typ Max
Clock frequency fC
X0
X1 3.5 4 16 MHz Opposite phase external
supply or crystal
X0A
X1A 32 32.768 100 kHz
0.8 V
CC
0.2 V
CC
P
WH
P
WL
t
C
X0,
X1,
X0A,
X1A
MB91460P Series
174 DS07-16615-2E
6.2. Reset input ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 oC to + 125 oC)
Parameter Symbol Pin name Condition Value Unit
Min Max
INITX input time
(at power-on) tINTL INITX ⎯
8⎯ms
INITX input time
(other than the above) 20 ⎯μs
0.2 VCC
tINTL
INITX
MB91460P Series
DS07-16615-2E 175
6.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = -40 ×C to +125 ×C
- Cl = 50 pF (load capacity value of pins when testing)
- VOL = 0.2 x VDD5
- VOH = 0.8 x VDD5
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 oC to + 125 oC)
* : Parameter m depends on tSCYCI and can be calculated as :
• if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
• if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes : • The above values are AC characteristics for CLK synchronous mode.
• tCLKP is the cycle time of the peripheral clock.
Parameter Symbol Pin name Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Unit
Min Max Min Max
Serial clock
cycle time tSCYCI SCKn
Internal
clock
operation
(master
mode)
4 tCLKP ⎯4 tCLKP ⎯ns
SCK ↓ → SOT
delay time tSLOVI SCKn
SOTn - 30 30 - 20 20 ns
SOT → SCK ↓
delay time tOVSHI SCKn
SOTn
m ×
tCLKP - 30* ⎯m ×
tCLKP - 20* ⎯ns
Valid SIN →
SCK ↑ setup time tIVSHI SCKn
SINn tCLKP + 55 ⎯tCLKP + 45 ⎯ns
SCK ↑ → valid
SIN hold time tSHIXI SCKn
SINn 0⎯0⎯ns
Serial clock
“H” pulse width tSHSLE SCKn
External
clock
operation
(slave
mode)
tCLKP + 10 ⎯tCLKP + 10 ⎯ns
Serial clock
“L” pulse width tSLSHE SCKn tCLKP + 10 ⎯tCLKP + 10 ⎯ns
SCK ↓ → SOT
delay time tSLOVE SCKn
SOTn ⎯2 tCLKP +
55 ⎯2 tCLKP + 45 ns
Valid SIN →
SCK ↑ setup time tIVSHE SCKn
SINn 10 ⎯10 ⎯ns
SCK ↑ → valid
SIN hold time tSHIXE SCKn
SINn tCLKP + 10 ⎯tCLKP + 10 ⎯ns
SCK rising time tFE SCKn ⎯20 ⎯20 ns
SCK falling time tRE SCKn ⎯20 ⎯20 ns
MB91460P Series
176 DS07-16615-2E
• Internal clock mode (master mode)
• External clock mode (slave mode)
tIVSHI
VIH
tSHIXI
tSLOVI
tSCYCI
VOL
SOTn
SCKn
for ESCR:SCES = 0
SCKn
for ESCR:SCES = 1
tOVSHI
VOL
VOL
VIL
VOL
VIL
VIH
VOH
VOH
VOH VOH
SINn
t
IVSHE
V
IH
t
SHIXE
t
SLOVE
t
SLSHE
V
OL
SOTn
SCKn
for ESCR:SCES = 0
SCKn
for ESCR:SCES = 1
V
OL
V
IL
V
OL
V
IL
V
IH
V
OH
V
OH
V
OL
V
OH
V
OH
V
OH
SINn
t
SHSLE
V
OL
t
RE
V
OH
t
FE
V
OL
MB91460P Series
DS07-16615-2E 177
6.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
-IO
drive = 3 mA
-V
DD5 = 3.0 V to 5.5 V, Iload = 3 mA
-V
SS5 = 0 V
- Ta = - 40 °C to + 125 °C
-C
l = 50 pF
- VOL = 0.3 × VDD5
- VOH = 0.7 × VDD5
- EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
Fast mode:
(VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
*1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles
of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
Parameter Symbol Pin name Value Unit Remark
Min Max
SCL clock frequency fSCL SCLn 0 400 kHz
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
tHD;STA SCLn, SDAn 0.6 ⎯μs
LOW period of the SCL clock tLOW SCLn 1.3 ⎯μs
HIGH period of the SCL clock tHIGH SCLn 0.6 ⎯μs
Setup time for a repeated START
condition tSU;STA SCLn, SDAn 0.6 ⎯μs
Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 μs
Data setup time tSU;DAT SCLn SDAn 100 ⎯ns
Rise time of both SDA and SCL
signals trSCLn, SDAn 20 + 0.1Cb300 ns
Fall time of both SDA and SCL
signals tfSCLn, SDAn 20 + 0.1Cb300 ns
Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 ⎯μs
Bus free time between a STOP
and START condition tBUF SCLn, SDAn 1.3 ⎯μs
Capacitive load for each bus line CbSCLn, SDAn ⎯400 pF
Pulse width of spike suppressed
by input filter tSP SCLn, SDAn 0 (1..1.5) ×
tCLKP ns *1
MB91460P Series
178 DS07-16615-2E
SDA
SSr PS
SCL
t
HD;STA
tr
tr
t
SP
t
SU;STO
t
SU;STA
t
SU;DAT
t
HD;DAT
t
HD;STA
t
LOW
t
HIGH
t
BUF
tf
tf
MB91460P Series
DS07-16615-2E 179
6.5. Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Note : tCLKP is the cycle time of the peripheral clock.
6.6. Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 125 °C)
Note : tCLKP is the cycle time of the peripheral clock.
Parameter Symbol Pin name Condition Value Unit
Min Max
Input pulse width tTIWH
tTIWL CKn ⎯4tCLKP ⎯ns
Parameter Symbol Pin name Condition Value Unit
Min Max
Input capture input trigger tINP ICUn ⎯5tCLKP ⎯ns
A/D converter trigger tATGX ATGX ⎯5tCLKP ⎯ns
tTIWH tTIWL
CKn V
IH
V
IH
V
IL
V
IL
ICUn,
ATGX
tATGX, tINP
MB91460P Series
180 DS07-16615-2E
6.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
-IO
drive = 5 mA
-V
DD35 = 4.5 V to 5.5 V, Iload = 5 mA
-V
SS5 = 0 V
- Ta = - 40 °C to + 125 °C
-C
l = 50 pF
- VOL = 0.2 × VDD35
- VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
6.7.1. Basic Timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Note : tCLKT is the cycle time of the external bus clock.
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK tCLCH SYSCLK 1/2 × tCLKT - 4 1/2 × tCLKT + 2 ns
tCHCL 1/2 × tCLKT - 2 1/2 × tCLKT + 4 ns
SYSCLK ↓ to CSXn delay time tCLCSL
SYSCLK
CSXn
⎯12 ns
tCLCSH ⎯9ns
SYSCLK ↑ to CSXn delay time
(Addr → CS delay) tCHCSL 38ns
SYSCLK ↓ to ASX delay time tCLASL SYSCLK
ASX
⎯13 ns
tCLASH ⎯12 ns
SYSCLK ↓ to Address valid delay time tCLAV SYSCLK
A23 to A0 ⎯13 ns
MB91460P Series
DS07-16615-2E 181
SYSCLK
CSXn
delayed CSXn
ASX
ADDRESS
BAAX
t
CHCSL
t
CLASL
t
CLAV
t
CLBAL
t
CLASH
t
CLCSL
t
CLCH
t
CHCL
t
CYC
t
CLCSH
t
CLBAH
MB91460P Series
182 DS07-16615-2E
6.7.2. Synchronous/Asynchronous read access
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↑ to RDX delay time TCHRL SYSCLK
RDX
27ns
TCHRH 2 9 ns
Data valid to RDX ↑ setup time TDSRH RDX
D31 to D16 20 ⎯ns
RDX ↑ to Data valid hold time TRHDX RDX
D31 to D16 0⎯ns
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRL SYSCLK
WRXn
⎯12 ns
TCLWRH 3 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯12 ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
(as byte enable)
RDX
DATA IN
tDSRH tRHDX
tCHRH
tCHRL
tCLWRL tCLWRH
tCLCSH
tCLCSL
MB91460P Series
DS07-16615-2E 183
6.7.3. Synchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↓ to WEX delay time TCLWL SYSCLK
WEX
⎯12 ns
TCLWH 2 ⎯ns
Data valid to WEX ↓ setup time TDSWL WEX
D31 to D16 - 2 ⎯ns
WEX ↑ to Data valid hold time TWHDH WEX
D31 to D16 tCLKT - 9 ⎯ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL SYSCLK
WRXn
⎯12 ns
TCLWRH 3 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯12 ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
(as byte enable)
WEX
DATA OUT
t
CLWH
t
CLWL
t
CLWRL
t
DSWL
t
WHDH
t
CLWRH
t
CLCSH
t
CLCSL
MB91460P Series
184 DS07-16615-2E
6.7.4. Synchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↓ to WRXn delay time TCLWRL SYSCLK
WRXn
⎯12 ns
TCLWRH 3 ⎯ns
Data valid to WRXn ↓ setup time TDSWRL WRXn
D31 to D16 - 1 ⎯ns
WRXn ↑ to Data valid hold time TWRHDH WRXn
D31 to D16 tCLKT - 9 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯12 ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
DATA OUT
t
CLWRH
t
CLWRL
t
DSWRL
t
WRHDH
t
CLCSH
t
CLCSL
MB91460P Series
DS07-16615-2E 185
6.7.5. Asynchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
WEX ↓ to WEX ↑ pulse width TWLWH WEX tCLKT - 8 ⎯ns
Data valid to WEX ↓ setup time TDSWL WEX
D31 to D16 1/2 × tCLKT - 1 ⎯ns
WEX ↑ to Data valid hold time TWHDH WEX
D31 to D16 1/2 × tCLKT - 9 ⎯ns
WEX to WRXn delay time TWRLWL WEX
WRXn
⎯1/2 × tCLKT + 1 ns
TWHWRH 1/2 × tCLKT - 0 ⎯ns
WEX to CSXn delay time TCLWL WEX
CSXn
⎯1/2 × tCLKT + 7 ns
TWHCH 1/2 × tCLKT - 1 ⎯ns
CSXn
WRXn
(as byte enable)
WEX
DATA OUT
t
WHDH
t
WHWRH
t
WHCH
t
WRLWL
t
WLWH
t
CLWL
t
DSWL
MB91460P Series
186 DS07-16615-2E
6.7.6. Asynchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
WRXn ↓ to WRXn ↑ pulse width TWRLWRH WRXn tCLKT - 7 ⎯ns
Data valid to WRXn ↓ setup time TDSWRL WRXn
D31 to D16 1/2 × tCLKT - 1 ⎯ns
WRXn ↑ to Data valid hold time TWRHDH WRXn
D31 to D16 1/2 × tCLKT - 9 ⎯ns
WRXn to CSXn delay time TCLWRL WRXn
CSXn
⎯1/2 × tCLKT + 7 ns
TWRHCH 1/2 × tCLKT - 1 ⎯ns
CSXn
WRXn
DATA OUT
t
WRHDH
t
WRHCH
t
CLWRL
t
WRLWRH
t
DSWRL
MB91460P Series
DS07-16615-2E 187
6.7.7. RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
RDY setup time TRDYS SYSCLK
RDY 16 ⎯ns
RDY hold time TRDYH SYSCLK
RDY 0⎯ns
SYSCLK
RDY
t
RDYS
t
RDYH
MB91460P Series
188 DS07-16615-2E
6.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
-IO
drive = 5 mA
-V
DD35 = 3.0 V to 4.5 V, Iload = 3 mA
-V
SS5 = 0 V
- Ta = - 40 °C to + 125 °C
-C
l = 50 pF
-VOL = 0.2 × VDD35
-VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
6.8.1. Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK TCLCH SYSCLK 1/2 × tCLKT - 4 1/2 × tCLKT + 5 ns
TCHCL 1/2 × tCLKT - 5 1/2 × tCLKT + 4 ns
SYSCLK ↓ to CSXn delay time TCLCSL
SYSCLK
CSXn
⎯8ns
TCLCSH ⎯9ns
SYSCLK ↑ to CSXn delay time
(Addr → CS delay) TCHCSL 1 8 ns
SYSCLK ↓ to ASX delay time TCLASL SYSCLK
ASX
⎯8ns
TCLASH ⎯9ns
SYSCLK ↓ to Address valid delay
time TCLAV SYSCLK
A23 to A0 ⎯12 ns
MB91460P Series
DS07-16615-2E 189
SYSCLK
CSXn
delayed CSXn
ASX
ADDRESS
BAAX
t
CHCSL
t
CLASL
t
CLAV
t
CLBAL
t
CLASH
t
CLCSL
t
CLCH
t
CHCL
t
CYC
t
CLCSH
t
CLBAH
MB91460P Series
190 DS07-16615-2E
6.8.2. Synchronous/Asynchronous read access
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↑ to RDX delay time TCHRL SYSCLK
RDX
18ns
TCHRH 2 8 ns
Data valid to RDX ↑ setup time TDSRH RDX
D31 to D16 26 ⎯ns
RDX ↑ to Data valid hold time TRHDX RDX
D31 to D16 0⎯ns
SYSCLK ↓ to WRXn
(as byte enable) delay time
TCLWRL SYSCLK
WRXn
⎯9ns
TCLWRH 3 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯8ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
(as byte enable)
RDX
DATA IN
tDSRH tRHDX
tCHRH
tCHRL
tCLWRL tCLWRH
tCLCSH
tCLCSL
MB91460P Series
DS07-16615-2E 191
6.8.3. Synchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↓ to WEX delay time TCLWL SYSCLK
WEX
⎯9ns
TCLWH 3 ⎯ns
Data valid to WEX ↓ setup time TDSWL WEX
D31 to D16 - 6 ⎯ns
WEX ↑ to Data valid hold time TWHDH WEX
D31 to D16 tCLKT - 13 ⎯ns
SYSCLK ↓ to WRXn (as byte enable)
delay time
TCLWRL SYSCLK
WRXn
⎯9ns
TCLWRH 4 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯8ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
(as byte enable)
WEX
DATA OUT
t
CLWH
t
CLWL
t
CLWRL
t
DSWL
t
WHDH
t
CLWRH
t
CLCSH
t
CLCSL
MB91460P Series
192 DS07-16615-2E
6.8.4. Synchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
SYSCLK ↓ to WRXn delay time TCLWRL SYSCLK
WRXn
⎯9ns
TCLWRH 4 ⎯ns
Data valid to WRXn ↓ setup time TDSWRL WRXn
D31 to D16 - 6 ⎯ns
WRXn ↑ to Data valid hold time TWRHDH WRXn
D31 to D16 tCLKT - 15 ⎯ns
SYSCLK ↓ to CSXn delay time TCLCSL SYSCLK
CSXn
⎯8ns
TCLCSH ⎯9ns
SYSCLK
CSXn
WRXn
DATA OUT
t
CLWRH
t
CLWRL
t
DSWRL
t
WRHDH
t
CLCSH
t
CLCSL
MB91460P Series
DS07-16615-2E 193
6.8.5. Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
WEX ↓ to WEX ↑ pulse width TWLWH WEX tCLKT - 4 ⎯ns
Data valid to WEX ↓ setup time TDSWL WEX
D31 to D16 1/2 × tCLKT - 6 ⎯ns
WEX ↑ to Data valid hold time TWHDH WEX
D31 to D16 1/2 × tCLKT - 13 ⎯ns
WEX to WRXn delay time TWRLWL WEX
WRXn
⎯1/2 × tCLKT + 1 ns
TWHWRH 1/2 × tCLKT - 1 ⎯ns
WEX to CSXn delay time TCLWL WEX
CSXn
⎯1/2 × tCLKT + 1 ns
TWHCH 1/2 × tCLKT - 0 ⎯ns
CSXn
WRXn
(as byte enable)
WEX
DATA OUT
t
WHDH
t
WHWRH
t
WHCH
t
WRLWL
t
WLWH
t
CLWL
t
DSWL
MB91460P Series
194 DS07-16615-2E
6.8.6. Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
WRXn ↓ to WRXn ↑ pulse width TWRLWRH WRXn tCLKT - 2 ⎯ns
Data valid to WRXn ↓ setup time TDSWRL WRXn
D31 to D16 1/2 × tCLKT - 6 ⎯ns
WRXn ↑ to Data valid hold time TWRHDH WRXn
D31 to D16 1/2 × tCLKT - 14 ⎯ns
WRXn to CSXn delay time TCLWRL WRXn
CSXn
⎯1/2 × tCLKT + 1 ns
TWRHCH 1/2 × tCLKT - 0 ⎯ns
CSXn
WRXn
DATA OUT
TWRHDH
TWRHCH
TCLWRL
TWRLWRH
TDSWRL
MB91460P Series
DS07-16615-2E 195
6.8.7. RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 125 °C)
Parameter Symbol Pin name Value Unit
Min Max
RDY setup time TRDYS SYSCLK
RDY 21 ⎯ns
RDY hold time TRDYH SYSCLK
RDY 0⎯ns
SYSCLK
RDY
t
RDYS
t
RDYH
MB91460P Series
196 DS07-16615-2E
■ORDERING INFORMATION
Part number Package Remarks
MB91F465PAPMC-GSE2 176-pin plastic LQFP
(FPT-176P-M07) Lead-free package
MB91F467PAPMC-GSE2 176-pin plastic LQFP
(FPT-176P-M07) Lead-free package
MB91460P Series
DS07-16615-2E 197
■PACKAGE DIMENSION
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
176-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 24.0 × 24.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference) P-LQFP-0176-2424-0.50
176-pin plastic LQFP
(FPT-176P-M07)
(FPT-176P-M07)
C
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
Details of "A" part
0°~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
(Stand off)
(.004±.004)
0.10±0.10
1.50
+0.20
–0.10
+.008
–.004
.059 (Mounting height)
0.08(.003)
(.006±.002)
0.145±0.055
"A"
INDEX
1
LEAD No.
44
45
88
89132
133
176
0.50(.020) 0.22±0.05
(.009±.002)
M
0.08(.003)
*24.00±0.10(.945±.004)SQ
26.00±0.20(1.024±.008)SQ
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
MB91460P Series
198 DS07-16615-2E
■REVISION HISTORY
Version Date Remark
2.0 2008-06-10 Initial version
2.1 2008-08-15
Handling devices: Section Notes on PS Register changed for better
understanding
Interrupt Vector Table: corrected the footnotes
FLASH: Added note about the flash operation mode switching,
added section "Poweron Sequence in parallel programming mode"
Absolute maximum ratings: Removed the note that analog input/output
pins cannot accept +B signal input.
DC Characteristics: Updated PullUp/Down resistors, updated the footnotes
splitted ILV into external and internal LV detection
AD Converter characteristics updated (complete section)
2.2 2008-09-04
Added MB91F467PA with Data Flash and 2 ADC macros:
- added chapter A/D Converter / New Features
- added chapter A/D Converter / Range Comparator
- added chapter Embedded Data Flash
2.3 2008-09-23
A/D CONVERTER / NEW FEATURES (MB91F467PA):
The ADC Channel Enable feature is only available on the non-relocated
ADC channels 6-7.
IO MAP: Added IOS register (addr. 0xC03) with note
“always write 1 to IOS[1]”; Added bookmarks inside IO MAP; the IO MAP
is common for MB91F465PA and MB91F467PA.
EMBEDDED DATA FLASH (MB91F467PA):
Added info about read operation during Command Sequencer write is active.
3.0 2008-09-23
Data Flash: Corrected text about Command Sequencer Mode
(DFWC:WE bit); corrected TMG2,TMG1,TMG0=000 to max. 6.2MHz
Corrected notes about CRC calculation (CLKB faster then RC clock)
Embedded Program/Data Memory (Flash):
Added section 7 "Notes About Flash Memory CRC Calculation"
(CLKB must be faster then the RC clock)
Pin Assignment: Corrected “SYSCLK7”
Pin Description: Added X0/X1 pinning spec of F467PA
Added Ta=125C characteristics
3.1 not released
yet
Embedded Data Flash: Added 3 notes that “Dummy addresses for auto
algorithm” cannot be used for toggle bit polling.
DFCS register bit description: corrected INTEN into INTE,
Data flash security: Added information about FSC_DISABLE.
FLASH memory program/erase characteristics:
Added 5.3 MB91F467PA DATA FLASH (erase / programming times)
MB91460P Series
DS07-16615-2E 199
■MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Change Results
31 ■ PORT MULTIPLEXING Corrected the text bubbles in Figure “3. Multiplex Pinout MB91F465PA”.
32 Corrected the text bubbles in Figure “4. Multiplex Pinout MB91F467PA”.
MB91460P Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
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FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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Edited: Sales Promotion Department