IXMS150PSI - IXYS Corporation

I - 35

High Performance Dual PWM Microstepping Controller

Type Package Temperature Range

IXMS150 PSI 24-Pin Skinny DIP -40°C to +85°C

The IXMS150 is a high performance

monolithic 2-channel PWM controller.

Implemented in CMOS, the low power

IXMS150 precisely controls the current

in each of two separate power H-bridge

drivers using unique sampling and

signal processing techniques. Each

channel contains an error amplifier,

PWM, feedback amplifier, and protec-

tion circuitry. Protection features include

over/excess current shutdown, min/max

duty cycle clamp, under voltage lock-

out, dead time insertion, and a shutdown

input for over-temp or other external

fault circuitry. Other features include a

common oscillator, feedforward circuit

for motor supply compensation, and an

onchip negative bias generator.

The IXMS150 has been optimized for

microstep control of two phase step

motors. Due to its high level of accu-

racy, the IXMS150 will allow a designer

to implement a control system with a

resolution in excess of 250 microsteps

per step, or 50,000 steps per revolution

with a 200 step per revolution step

motor. The IXMS150 greatly improves

positioning accuracy and virtually

eliminates low speed velocity ripple and

resonance effects at a fraction of the cost

of a board level microstepping system.

Other applications which the IXMS150

is designed for include control of two

single-phase (DC) motors or control of

synchronous reluctance motors. The

IXMS150 is ideal for robotics, printers,

plotters, and x-y tables and can facilita-

te the construction of very sophisticated

positioning control systems while signi-

ficantly reducing component cost, board

space, design time and systems cost.

Features

lTwo complete, synchronous PWMs

lCommand input range ±2.0 V full

scale

l±0.625 V full scale current feedback

signal

l1% gain matching between channels

without external trim

l1.6% gain linearity

lFeedforward to compensate for

motor supply variations

lOnly one sense resistor per H-bridge

needed

lOnboard two level current limiting

lUndervoltage lockout assures proper

behavior on power up and power

down

lEnable input for external over

temperature or fault circuit input

lDuty cycles limited for AC coupled

gate drive

lWide range of built in dead time.

lOn board negative power supply

generator

lSingle +12 V supply operation

l24-pin DIP package

Applications

lFull, half quarter, or microstepping

2-phase step motor position

controller

lDual DC servo motor torque

controller

lSolenoid actuator force controller

lGeneral 2-channel current-

commanded PWM control

Block diagram of IXMS 150

Symbol Definition Max. Ratings

VDD Supply voltage -0.3...15 V

Operating range 10.8...13.2 V

Common-mode-range -15...15 V

Differential Input voltage ¬±30 V

VIN Input voltage ¬-15...15 V

VOOutput voltage -0.3...VDD+0.3 V

PDMaximum power dissipation 500 mW

TAAmbient temperature range -40...85 °C

Tstg Storage temperature range -55...125 °C

¬ Input voltage may not exceed either supply rail by more than 0.3 V at any time.

IXYS reserves the right to change limits, test conditions and dimensions.

IXMS 150

Symbol Definition/Condition Characteristic Values

(VDD = 12 V, TA = 25°C unless otherwise specified)

min. typ. max.

Oscillator

fOSC Frequency Co10 400 kHz

VA(p-p) Amplitude FFWD = OPEN 7 V

ZOUT Output Impedance ± IOUT = 400 µA 2.5 mΩ

Resistance Range Ro15 100 kΩ

Capacitance Range Co100 2000 pF

Feed Forward

VFFWD Feedforward FFWD = Open 3.5 V

Voltage

ZINFF Impedance to AGND 25 45 kΩ

Analog Inputs

VFS Input FullScale VINA DC ±2V

INB

ZIN1 VIN to Comp2DC 20 32 kΩ

Impedance

ZIN2 Comp1 to Comp2DC 12 20 kΩ

Impedance

Sense Inputs SENSEA

VSENSE Full Scale Input SENSEBDC ±0.625 V

ZINS Input Impedance DC 100 200 kΩ

Protection Circuit SENSEA

VOV-1 Over Current SENSEB0.8 0.95 1.0 V

Voltage

tOV-1 Reset Pulse Width 0.5 1 µs

VEX-1 Excess Current Voltage 3.45 3.6 3.75 V

tEX-1 Reset Pulse Width 300 ns

Under Voltage

VUV Minimum VDD OUTDIS 7.5 8 8.5 V

IIH Input High Current VIH = 11.5 V 100 µA

IIL Input Low Current VIL = 0.5 V 1.8 mA

Outputs

VOH Output High VOUTA, VOUTA IOH = -10 mA 8.0 11.2 V

Voltage

VOL Output Low VOUTB, VOUTB IOL = 10 mA 0.8 1.1 V

Voltage

trRise Time CL = 100 pF 35 50 ns

tfFall Time CL = 100 pF 35 50 ns

TDT Dead-Time Co = 180 pF 200 300 450 ns

TMIN Minimum Pulse Width Cp = 30 pF 0.6 0.8 1.5 µs

VBB Generator

VBBmin Minimum VBB OUTDIS -1.4 -1.9 V

Negative Bias = VDD

VBB Negative Bias IOUT = -3 mA -2.1 -2.4 V

Voltage

VREG Load Regulation fOSC 60 mV

= 100 kHz

VOH Output High Volt. CPUMP IOH = -10 mA 11.2 V

VOL Output Low Volt. IOL = 32 mA 0.8 V

Supply

IDD1 Idle Current VDD VIN = 0 16 26 mA

IDD2 Operating Current fOSC 15 45 mA

= 100 kHz

VBYPASS Bypass Voltage BYPASS 5.9 16.1 V

ZINBP Impedance to AGND 9 16 kΩ

Dimensions in inch (1" = 25.4 mm)

24-Pin Skinny DIP

I - 37

IXMS 150

Pin Description IXMS 150 Nomenclature of Dual PWM

Microstepping Controller

Sym. Pin Description

AGND 1 Analog Ground

COMP 2 Analog Compensation

4 (see application notes for

5 recommendations).

VIN 3 Analog Input: The analog

22 input range is ± 2 V. A low

output im pedance voltage

source should drive these

pins. The input is greater

than 20 kΩ.

SENSE 6 Analog Sense: Each of the

19 phases sense resistors are

connected to these pins.

Input range is +0.625 V.

FFWD 7 FFWD, for Motor High

Voltage Compensation: A

voltage on this pin sets the

oscillator amplitude. Input

range = 0.9-4 V (see

application notes for

recommendations).

BY- 8 Filter Cap: A capacitor on

PASS this pin provides filtering to

the internal bias network.

VOUT 9 Output Stage: To drive

10 buffered power MOSFET

15 H-Bridge.

VBB 11 Negative Bias Generator

Output: For internal use by

the IXMS 150.

DGND 12 Digital Ground

CPUMP 13 Charge Pump Capacitor:

Used by the internal

Negative Bias Generator.

OUTDIS 14 Digital ENABLE input and

STATUS output: Forcing this

pin low causes pins 9, 10,

15, and 16 to go low, disab-

ling the H-bridge. When uses

as an output, a low state on

this pin indicates an over

current, excess current, or

insufficient +VDD or VBB error

condition.

RO, CO17 Oscillator Frequency and

18 Dead-time set: Independent

adjustment can be made to

the oscillator frequency and

dead-time (see applications

notes).

VDD 24 Positive Supply Voltage

* Pin numbers in parantheses are

associated with channel B.

IXMS 150 PS I (Example)

IX IXYS

MS 150 Dual PWM Controller

Package Type

PS Plastic Skinny DIP

Temperature Range

IIndustrial

IXMS 150

Functional Description

Introduction

The IXMS150 is designed with mono-

lithic CMOS technology. The IC is

primarily intended for use with two-

phase step motors in the microstepping

mode but may also be used for control

of two DC motors, audio amplifiers, or

any application requiring two synchro-

nized PWMs. The IXMS150 simulta-

neously controls the currents in each of

two separate H-bridges. This device

utilizes both analog and digital functions.

The IC has five fundamental sections:

(1) oscillator and feedforward circuitry,

(2) analog section for control of the

motor currents, (3) a protection network

to protect the H-bridges and the motor

from abnormal conditions, (4) the digital

PWM logic for the control signals, and

(5) the power supply section which

includes a negative bias generator.

Oscillator

The IXMS150 contains an internal

oscillator which is controlled by

adjusting the values of RO and CO.

These two components determine the

switching frequency, amount of dead

time, and the minimum pulse width at

output pins 9, 10, 15 and 16. The

minimum and maximum values of RO

and CO are given in the Electrical

Characteristics.

The oscillator also sets the frequency of

the charge pump circuit in the internal

negative bias generator (VBB). At lower

frequencies (<40 kHz) the value of

CPUMP must be increased to assure

proper operation.

Feedforward Compansation

In all fixed frequency PWM control

systems open loop gain, motor current

slew rate, and motor current ripple are

proportional to the motor supply

voltage. Gain variations due to supply

voltage changes complicate the design

of such systems and restrict their band-

width to the minimum worst case

condition. For this reason, an advanced

adaptive compensation scheme is built-

in using a feedforward technique. This

feature has been designed such that

open loop gain is inversely proportional

to the voltage applied to the FFWD pin,

normally a fraction of the motor supply.

As a result, open loop gain can be

made independent of the high voltage

supply and system bandwidth can be

maximized.

Analog Section

The analog section of each channel of

the IXMS150 consists of a signal

processor and an error amplifier. The

signal processor is required since the

voltage developed across the sense

resistor often contains transients asso-

ciated with the switching characteristics

of the power devices. These transients

need to be properly filtered for the

system to operate with the desired

degree of precision. Because of this,

the IXMS150 uses proprietary analog

and digital signal processing techni-

ques that sense the true average phase

currents. Since this requires only one

sense resistor per H-bridge it avoids

mismatches in charge/discharge

currents associated with two sense

resistor per H-bridge topologies.

The instantaneous difference between

the motor current and the control input

is integrated via the E/A amp and fed to

the PWM comparator to generate the

appropriate signals for the H-bridges.

External compensation of the input and

sense signals is provided for via the

comp1, comp2 and comp3 pins.

Protection Circuitry

The IC has a two-level Over/Excess

Current protection circuit. Maximum

current is represented as 0.625 V at the

SENSE input. If the SENSE voltage

exceeds 0.9 volts for more than one

microsecond, the switching outputs

(VOUT) and OUTDIS will be forced low.

This represents a current that is 40 %

beyond full scale. If the SENSE voltage

exceeds 3.6 V, these outputs will be

forced low immediately. This repre-

sents a current that is 500% beyond full

scale. The time delay on the lower level

of overcurrent avoids erroneous

shutdowns as a result of noise spikes

that are coupled from the motors H-

bridges. Note that the threshold

voltages cited here assume a supply of

+12 V.

Undervoltage Lockout

A third protection mechanism is the

Under-Voltage Lockout. It assures

proper behavior on power-up and

power-down and avoids high power

dissipation in the H-bridge due to

insufficient gate voltage. It uses a zener

for reference and has a trip point set at

8 V. It will also check to make sure

there is sufficient negative bias to

insure proper operation. This is typically

-1.6 V. OUTDIS will be held low by the

UV Lockout circuit until VBB and VDD

reach these values.

Output Disable Feature

To enable external over-temperature

protection, the output disable pin

(OUTDIS) is available on the IXMS150.

When pulled low this disables the

output by forcing all output pins low.

The same output disable input pin is

also used as a status output. When it is

pulled low by the internal circuitry it

indicates an error condition such as

undervoltage (VDD), insufficient negative

bias voltage (VBB) or over/excess

current. This can be used as a status

indicator in smart systems.

PWM Section

The PWM comparator generates two

complementary signals based on the

output of the error amplifier. Dead-time

is then added which is adjusted by the

selection of the external oscillator

capacitor. There is also a minimum duty

cycle clamp circuit that allows the use

of an AC coupled H-bridge.

Supply Section

The main power supply (VDD) is applied

to pin 24. This is typically +12 V. Internal

bias circuitry presents a VDD/2 reference

voltage at pin 8, BYPASS. A 0.1 µF

capacitor should be connected from pin

8 to analog ground for noise immunity.

Negative Bias Generator

The IXMS150 samples both positive

and negative voltages at the motor

sense feedback resistor. In addition,

since errors in the input current around

zero are a major contributor to micro-

step positioning error, the input control

range is bipolar and specified as ±2 V

full scale. For these reasons it is desi-

rable to have both positive and nega-

tive power supplies. In order to enable

single 12 V supply operation, a negative

voltage generator and regulator are

built into the IC. This is a charge pump

circuit whose frequency is that of the

onboard oscillator. It utilizes an external

pair of capacitors and diodes to gene-

rate a negative bias equal to -VDD/5 or

approximately -2.4 V for VDD = 12 V.

I - 39

Application Information

Introduction

The advantages of step motors are well

known. They may be operated in an

open loop fashion, the accuracy of

which is mostly dependent on the

mechanical accuracy of the motor. They

move in quantized increments (steps)

which lends them easily to digitally

controlled motion systems. In addition,

their drive signals are square wave in

nature and are therefore easily gene-

rated with relatively high efficiency due

to their ON/OFF characteristics.

But step motors are not free of prob-

lems. Their large pulse drive wave-

forms create mechanical forces which

excite and aggravate the mechanical

resonances in the system. These are

load dependent and difficult to control

since step motors have very little

damping of their own. At resonance a

step motor system is likely to lose

synchronization and therefore skip or

gain a step. Being an open loop system,

this would imply loss of position infor-

mation and would be unacceptable. A

common method of solving this problem

is to avoid the band of resonance

frequencies altogether, but this might

put severe limitations on system

performance. Steppers have 200 steps

per revolution or 1.8 degrees per step.

The highest resolution commercially

available steppers have 400 steps per

revolution or 0.9 degrees per step.

Microstepping Mode

One way to circumvent the problems

associated with step motors while still

retaining their open loop advantages is

to use them in the microstepping mode.

In this mode each of the steps is subdi-

vided into smaller steps or microsteps".

Applying currents to both phases of the

motor creates a torque phaser which is

proportional to the vector sum of both

currents. When the phasor completes

one turn (360 electrical degrees), the

motor moves exactly four full steps or

one torque cycle. Similarly, when that

phasor moves 22.5 electrical degrees

the motor will move (22.5/90)  100 =

25 % of a full step. Thus the position of

the motor is determined by the angle of

the torque phasor. When used with an

appropriate motor a positioning accu-

racy of 2 % of a full step can be achie-

ved, equaling 0.036 degrees for a 200

full steps per revolution motor. In this

manner the motor can be positioned to

any arbitrary angle. A common way to

control the angle of the torque phasor is

by applying to the motors phases two

periodic waveforms shifted by 90

electrical degrees.

Let the phase current equations be:

iA = IO  cos θe (1)

iB = IO  sin θe (2)

Note that θe is the electrical position.

The resulting torque generated by the

corresponding phases would then be:

TA = K0  iA = K0  I0  cos θe (3)

TB = K0  iB = K0  I0  sin θe (4)

where K0 is the torque constant of the

motor. Substituting Eqs. (1), (2) into (3),

(4) and doing vector summation the

resulting total generated torque mea-

sured on the motor shaft is given by:

Tg = K0  I0(5)

Note that in this case we have zero

torque ripple.

Using this technique one can theore-

tically achieve infinite resolution with

any step motor. Since the drive current

waveforms are sinusoidal instead of

square, the step to step oscillations are

eliminated and the associated velocity

ripple. This greatly improves perfor-

mance at low rotational speeds and

helps avoid resonance problems. In an

actual application, the extent to which

these things are true depends on how

the two sinusoidal reference waveforms

are generated.

Seemingly we have lost the quantized

motion feature of a stepper when used

in this mode. This can be regained by

defining the term microsteps per step.

Each full step is subdivided into micro-

steps by applying to the motors phases

those intermediate current levels for

which their vector sum tracks the circle

of Fig. 2 and divides the full step (90

electrical degrees) into the require

number of microsteps. An example of

the required phase currents for full step

and four microstep per step operation

are shown in Fig. 1 and 2 respectively.

Phase Current Matching

Requirements

Assuming microstepping is being used

for resolution improvement and not as a

resonance avoidance technique, a step

motor can be selected knowing the

torque needed, its specified step

IXMS 150

Fig. 1 Full Step Drive Waveforms

accuracy, and the required resolution or

the number of microsteps per step.

Next, one must determine the accuracy

required of the phase currents to main-

tain the accuracy of the complete

system. Equations (1) - (4) clearly

indicate that errors in the absolute

value or phase of the phase currents

will impact positioning accuracy.

Another observation is that by keeping

the ratio of the phase currents iA/iB

constant, errors in their value will result

Fig. 2 Four Microstep per Step Drive

Waveforms

IXMS 150

the H-bridge that must be properly

filtered if the system is to operate with

the desired degree of precision.

This presents a significant engineering

challenge that has been solved by

IXYSs design team. Using proprietary

analog and digital signal processing

techniques, IXYS has developed a

control system that measures the true

average phase currents. Requiring only

one sense resistor per H-bridge, this

technique avoids errors due to mis-

matches in charge/discharge currents

associated with using one sense resi-

stor on each leg of the H-bridge. This

improves system performance as well

as minimizing component count. The

sense resistor for each H-bridge should

be selected based on the required peak

motor current:

RS = 0.625 V/Impk (9)

The voltage developed across this

resistor is then applied to the corres-

ponding sense input for each H-bridge.

Negative bias Generator

One of todays cost cutting trends is to

minimize the number of power supplies,

implying single supply operation for the

control section. Yet the current feed-

back and reference inputs are bipolar

signals. Level shifting has been used

for the reference input in the past, but

that can not be easily done for the

feedback signal without impacting

accuracy or efficiency. In practice one

finds that in order to generate true zero

voltage having low impedance drive

there must be a negative power supply.

Otherwise there will be a tradeoff

sacrificing accuracy for simpler system

design.

For these reasons the approach selec-

ted by IXYS was different. Taking

advantage of our CMOS design, we

opted to build into the chip a negative

bias generator. This does put stringent

demands on noise coupling but results

in the most flexible system having the

highest possible accuracy. The built in

charge pump circuit requires two capa-

citors and two diodes to be added

externally. The recommended compo-

nent values for an oscillator frequency

of 100 kHz are given below.

C1 = 0.047 µF

C2 = 100 µF

D1 = D2 = 1N4148

Note: VBB = -(VDD/5)

in torque value errors but no positioning

errors. The question is, what is the

upper bound on the current errors in

order to keep the position error within

some given angle ∆θ.

Referring to Fig. 3, assume the required

currents iA, iB are given by Equations

(1), (2) respectively such that their

vector sum points to position P. Let the

phase currents vary by a small amount

such that their vector sum lies within a

circle centered at point P and having

the radius i, as indicated in Fig. 3.

Fig. 3 Effect of Current Errors on

Position

If follows that the worst case position

error occurs for the cases where the

vector sum is tangent to the circle such

as point P1, at which:

tan (∆ θ) = ∆ i/l0(6)

For instance, to keep position error to

less than 1% of a full step, the electrical

angular error would be:

∆ θ = 0.01  90° = 0.9°(7)

This is assuming there are 90 electrical

degrees for a full step. Therefore total

current error must be:

i/I0 = tan (∆θ) = 0.016 or 1.6 %) (8)

Thus the current error must be kept to

less than 1.6 % of full scale or peak

current at each phase for 1 % maximum

position error. This upper bound on

error includes all error sources such as

zero offset errors and full scale matching

errors. Another interesting observation

is that in the vicinity of a full step (i.e.,

θe = 0), the phase having the bigger

impact on position error is the one

carrying the smaller current through it.

This has a strong impact on input

waveform generation.

Input waveform generation

It has been shown that the two input

signals, VINA and VINB, are sinusoidal

and 90° out of phase. This may be

accomplished by using two look-up

Fig. 4 Simple Reference Waveform

Generator

tables stored in ROM and two DACs

per Fig. 4. An up/down counter may be

used to generate the appropriate

address locations for the ROMs and the

data outputs used to control the DACs.

The user then need only supply up or

down pulses to the counter to control

the IXMS150 and hence the motor.

In higher performance systems a

microprocessor may be used in place

of the counter and the ROMs. The

micro can perform the look-up function

and calculate the appropriate system

responses, velocity profiles, etc.

necessary for total system operation.

An example of this configuration is

shown in Fig. 5.

Current Sensing Considerations

Most commercially available monolithic

PWM controllers monitor and control

the peak of the phase current by com-

paring the voltage across the sense

resistor with a ramp voltage. This

approach assumes that the ripple

current is fixed in amplitude. Results

shown later clearly indicate the varia-

tion of the ripple current with frequency.

But even in fixed frequency systems

the ripple current is directly proportional

to the motor supply voltage and to the

back EMF voltage of the motor. Ripple

current is not insignificant compared to

the full scale current and therefore

cannot be neglected in a precision

system. In addition, there are transients

associated with the turn on and turn off

characteristics of the power devices in

Fig. 5 Microprocessor Based

Referenced Waveform Generator

I - 41

Use the formula

C2 = 100 µF  100 kHz/fOSC

for other frequencies.

With VDD = 12 V and an oscillator fre-

quency of 100 kHz, the bias generator

should be able to source 3 mA at -2.4 V

using these component values. This

capability may be used to power other

external circuitry as long as there is

sufficient remaining negative bias to

allow the IXMS150 to operate properly.

Impact of PWM Frequency on

System Operation

PWM switching frequency has a

pronounced effect on ripple current

through the motor windings, the resul-

ting eddy current losses in the motor,

and system efficiency. As expected,

motor current ripple goes down as

frequency increases and therefore

losses resulting from ripple currents are

also reduced. Switching frequency also

impacts losses in the power stage.

These losses are associated with the

energy necessary to turn on and off the

power MOSFEts and are proportional

to the switching frequency. In addition,

the switching frequency has a limiting

effect on maximum current loop band-

width and therefore system bandwidth

and therefore system bandwidth and

maximum motor velocity.

Oscillator

The oscillator block diagram is shown

in Fig. 6.

The frequency is set by the values of

RO and CO:

fOSC = 1/RO  (CO + CP)) (10)

Note: CP is a 38 pF (typ.) internal

parasitic capacitor.

IXMS 150

1/FO

V(t)

2  V (PIN 7)

7 V (PIN 7 Open)

[]

VA =

1/fOSC = Ro  (Co + Cp)

Fig. 6a: Oscillator Block Diagram Fig. 6b: Oscillator Waveform Diagram

Feedforward

The amplitude of the oscillator wave-

form and overall system gain are modu-

lated by the voltage applied to the

feedforward pin (FFWD). This is nomi-

nally 3.5 V which should be divided

down from the motor high voltage

supply. This will allow system band-

width to be maximized by making

overall system gain inversely propor-

tional to the motor supply voltage.

Refer to Fig. 7 for an example of how

feedforward is connected to the motor

supply. It is recommended that a filter

capacitor be connected from FFWD to

AGND to filter noise spikes from the

motor supply. Its value should be

chosen so that the time constant of the

capacitor and the parallel combination

of Rff1 and Rff2 is such that switching

noise will be filtered but not variations

in the motor supply such as 120 Hz

ripple, etc.

Minimum Pulse Width

The minimum output pulse width can

also be modified by adjusting the oscil-

lator capacitor CO. The relationship is:

tpw(min) = Rmp  (CO + Cp)(11)

Note: Rmp is a 3.6 kΩ (typ.) internal

resistor, and Cp is a 38 pF (typ.) internal

parasitic capacitor.

Dead Time

Dead time is adjusted via the external

oscillator capacitor CO. There is an

internal resistor in the dead time circuit

as well. The relationship is:

tDT = RDT  (CO + Cp) (12)

Note: RDT is a 1.4 kΩ (typ.) internal

resistor and Cp is a 38 pF (typ.) internal

parasitic capacitor.

Fig. 7 Feedforward Connection

Diagram

Motor Slew Rate Limitations

The maximum motor velocity in a

microstepping application is determined

by the maximum rate of change of the

phase currents. Once this limit is

reached the system is slew rate

limited, at which point the peak

undistorted phase current times the

frequency of the input command is a

fixed value. The theoretical limit for the

maximum di/dt of the phase currents is

determined by the motor supply voltage

and the inductance of the motor:

di/dt (max) = VHV/Lm(13)

The limit does not take into account the

back EMF of the motor, the bandwidth

of the current loop driving the motor, or

the minimum pulse width. The motors

back EMF will tend to reduce the voltage

applied across the motor windings,

effectively reducing the maximum slew

rate. The bandwidth of the current loop

must also be high enough so as not to

degrade system performance.

Non-Circulating Operating Mode

The IXMS150 is designed to control an

H-bridge in the non-circulating mode.

The equivalent circuit for an H-bridge is

shown in Fig. 8. In the non-circulating

1/fOSC

IXMS 150

mode, either SW1 and SW4 are on (Vm

= VHV) or SW2 + SW3 are on (Vm = -

VHV). By appropriately controlling the

duty cycle of SW1//4 vs. SW2/3, the

average motor voltage can be controlled

such that:

Vm(avg) = 2  VHV (0.5-DUTY)

Note: DUTY is defined as the duty

cycle of VOUTA.

The IXMS150 can now regulate the

motor coil current by commanding the

voltage level and polarity required.

enhance the MOSFETs, with the top two

transistors (Q2, Q4) being destroyed

due to excessive power dissipation.

Therefore one has to limit the duty

cycle excursions. The solution selected

by IXYS limits the minimum output

pulse-width to 0.5 ms, which translates

to a duty cycle range of 5 % to 95 %

when operating at 100 kHz, or wider at

lower frequencies. There is a penalty of

slightly limiting the maximum slew rate

to (1-2  Min Duty) of the unrestricted

case, which translates to 90 % of the

ration with a particular motor. The basic

elements involved in the current loop

are illustrated in Fig. 11a. Referring to

Fig. 11b, the loop gain for this system

(the product of the forward and feed-

back gain terms) can be expressed as:

Gloop(s) = Ge/a(s)  Kpwm  Gm(s)  Gi(s) (14)

where

Ge/a(s) = error amplifier gain

Kpwm = cascade of pwm and output H-

bridge gain

Fig. 8 Simplified H-Bridge Diagram

SW1

SW3

SW2

SW4

D1 D2

D3 D4

The Power Stage:

An AC Coupled H-Bridge

Fig. 9 shows the power driver selected

for this application. Two of these are

required to drive the two phase step

motor. This circuit uses two N-channel

and two P-channel power MOSFETs as

opposed to an all N-channel architec-

ture. The drawback of using P-channel

transistors is that they are larger and

therefore more expensive than similarly

rated N-channel devices. But the

advantages are much simplified drive

and level shifting circuitry. This results

in a lower component count and

therefore higher reliability. It also lends

itself easily to hybridization. Other

advantages of this topology are: a) the

high efficiency associated with level

shifting by AC coupling since no power

is dissipated in the capacitors, and b)

the same circuit can be used for motor

applications ranging from 12 V to several

hundred volts, the only modification

being appropriately rated power tran-

sistors and coupling capacitors.

A limitation of this circuit is that it cannot

be used at duty cycle extremes. This

would require one input to be continu-

ously low while the other is continu-

ously high. Eventually the coupling

capacitors (C1, C2) would charge up to

a voltage that would no longer fully

Fig. 9 AC Coupled H-Bridge Diagram

Fig. 10a Simplified Microstepping System

unrestricted maximum slew rate for

100 kHz operation.

Loop Compensation Information

When used with the appropriate power

stage, each channel of the IXMS150

acts as a closed loop transconductance

amplifier. As such, it must be properly

compensated to guarantee stable ope-

Gm(s) = cascade of motor winding

impedance and H-bridge parasitic

resistance

Gi(s) = current sense resistor and

sampling amplifier gain

The value of each of these terms can

be determined from the Laplace

transform diagram in Fig. 11b:

I - 43

IXMS 150

Fig. 10b Input Offset Adjust Circuit

Lm= motor inductance

Rm= motor winding resistance

Rsw = power switch resistance

Rs= sense resistor

It is very important that the motor induc-

tance value used in the analysis is not

the value on the manufacturers data

sheet but rather the value observed in

actual operation. The PWM action

causes high frequency effects that can

change the apparent small signal

inductance significantly. These effects

are dependent upon voltage as well as

current and frequency. It is best to

measure the observed current ripple at

the motor supply voltage and switching

frequency you expect to use and

calculate the actual motor inductance

using:

Lm = VHV/((2  Fosc)(Imax-Imin)) (19)

It is also important to note that both Rm

and Rsw are temperature dependent.

The motor winding resistance can

increase by as much as 30 % at high

temperatures, and if FETs are used as

power devices, Rsw can increase to 2.2

times its value at room temperature.

Substituting equations 15 through 18

into equation 14 gives the expanded

loop gain equation (eq. 20):

(1+sRC)  2Vhv  1  2Rs

Gloop(s) =

sR2C  VA  (sLm+Rm+Rs+Rsw)

which can be written as (eq.21):

4  VHV  Rs

Gloop(s) = 

VA(Rm+Rs  Rsw)

(1+RC)

(sR2  C) [1+sLm/Rm+Rs+Rsw)]

Therefore the poles and zeros of the

system are:

pole at DC, with a 0dB intercept of:

4VHVRs/[VAR2C(Rm + Rs + Rsw)]

zero at 1/(R  C)

pole at (Rm + Rs + Rsw) /Lm

A simple Bode analysis can be per-

formed to provide the necessary infor-

mation to guarantee the stability of the

loop. A stable system will result when

the gain crossover occurs at a point

where the loop phase shift is less than -

180 degrees. The gain crossover point

is defined as the frequency where the

magnitude of Gloop(s) = 1 (0dB).

The Bode plot will show two figures of

merit that give an indication of the

behavior of the closed loop system,

gain margin and phase margin. Gain

margin is the amount of loop signal at-

tenuation at the point where the loop

phase has reached -180 degrees. It is a

qualitative measure of how susceptible

the loop is to noise outside its band-

width. Phase margin is the amount of

Fig. 10c Gain Adjust Circuit

Ge/a(s) = (1 + sRC)/(sR2C) (15)

Kpwm = 2  VHV/VA(16)

Gm(S) = 1/(sLm + Rm +Rsw +Rs) (17)

Gi(s) = 2  Rs

(ignoring sampling effects) (18)

where:

R, C = external compensation

components

R2= internal input resistor,

typically 20 kΩ

VHV = motor high voltage power supply

VA= oscillator amplitude, typically 7 V

Fig. 11a Loop Compensation Block Diagram

IXMS 150

Fig. 12 Complete Microstepping System

Q1, Q2: IRF9530

Q3, Q4: IRF532

D1, D2: MUR161OCT

D3, D4: MUR410

U1: 40498

U2: 40508

All Diodes are 1N4148 unless

otherwise specified

Fig. 11b Simplified laplace transform for stability analysis

phase shift left (i.e., 180 - (loop phase))

at the gain crossover. This number

gives the most intuitive feeling for how

the loop will respond to perturbations

and variations in system parameters.

Theoretically, a system with 1 degree of

phase margin is stable. However, a

step input to a system with small phase

margin will cause an underdamped,

ringly response or an oscillation that

dies out after a long time.

In a step motor, this overshoot and ring

in the current waveform is unaccep-

table. As the phase margin of a system

is increased, the response to a step

input slows down and the ringing is de-

creased. The response becomes more

damped. In a practical system, the

minimum acceptable phase margin is

about 30 degrees. More than 90

degrees slows the system response

with no significant improvement in sta-

bility. 60 degrees is usually considered

optimal, if no other constraints exist.

In a PWM motor drive amplifier, there

are several additional constraints that

apply. Because the levels of voltage

and current being switched are so high,

synchronous noise appears every-

where and can degrade system perfor-

mance. It is common to see apparent

instabilities that are simply loop ampli-

fication of subharmonic switching

transient noise. It is important to main-

tain at least 60 degrees of phase

margin and to maintain as much gain

margin as is practical. The PWM

comparator delays, power stage gate

drive delays, and the sampling tech-

nique used to generate the current

feedback signal also account for signifi-

cant phase delays when the switching

frequency is high, or when the excitation

approaches the switching frequency.

For these reasons it is usually advis-

able to design for a calculated 60 to 90

degree phase margin because of the

importance of the effects not accounted

for in the linearized circuit model.