[Ordering number : EN 5117] CMOS LSI LC6529N, 6529F, 6529L 4-Bit Microcomputer for Small-Scale Control Applications Preliminary Overview The LC6529N/F/L provides the basic architecture and instruction set of the Sanyo LC6500 Series of 4-bit single- chip microcomputers in a version specially for small-scale control applications involving circuits built with standard logic elements, applications using simple, comparator- based voltage or phase detectors, or other applications controlling a limited number of controls, The LC6529F is a replacement for the former LC6529H. (Certain functions differ, however.) The N (medium-speed) and L (power- saving) versions are new additions to the lineup. Features * Power-saving CMOS design (Standby mode accessed with HALT instruction included.) * Memory: 1 kilobyte of 8-bit ROM and 64 words of 4-bit RAM * Instruction set: 5t-member subset of LC6500 standard complement of 80 instructions + (L version) Wide range of operating voltages: 2.2 06.0 V * (F version) 0.92 j1s/3.0 V instruction cycle time * Flexible I/O ports Four ports with up to 16 lines Bidirectional I/O ports: 12 Dedicated input ports: 4 (These double as comparator inputs.) I/O voltage limit: max. +15 V (open-drain configuration) Output current: max, 20 mA sink current (capable of directly driving an LED) Choice of options to match system specifications Choice of open-drain or pull-up resistor output configurations at the bit level for all ports Choice of reset output levels for Ports C and D in groups of 4 bits each Port E configurable as four comparator inputs * Stack: Four levels Timers: 4-bit prescaler plus 8-bit programmable counter + Comparators: 4 channels (2 reference levels) Separator reference level for each channel pair Feedback resistor option for choice of input with or without hysteresis SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN * Choice of clock oscillator options to match system specifications Oscillator circuit options: 2-pin RC oscillator circuit (N and L versions) or 2-pin ceramic oscillator circuit (N, F, and L versions) Frequency divider options: Built-in 1/3 and 1/4 frequency dividers that eliminate the need for external frequency dividers 92995HA (OT) No. $117-1/39LC6529N, 6529F, 6529. Summary of Functions Item LO6529N LCes29F LC6529L [Memory] ROM 1024 x 8 bits 1624 x 8 bits 1024 x 6 bits RAM 64 x 4 bits 64 x 4 bits 64 x 4 bits Instruction set 51 51 5t [On-board functions] 4-bil prescaler plus 8-bit 4-bit prascaler plus 8-bit 4-bit prascaler plus 8-bit Timers programmable counter programmable counter programmable counter Stack levels 4 4 4 Standby mode onclandby places chip onatandby. places chip onetandby places chip Comparators 4 channels (2 reference levels) 4 channels (2 reference levels) 4 channels (2 reference levels} [VO ports] Number of ports 12 bidirectional VO pins, 4 input pins | 12 bidirectional /O pins, 4 input ping j 12 bidirectional VO pins, 4 input pins VO voltage fimit max. 15 V (ports A, C, and D) max. 15 V (ports A, C, and D)} max. 15 V (ports A, C, and D) Output current 10 mA typ. 20 mA max, 10 mA typ. 20 mA max. 10 mA typ. 20 mA max. VO circuit configuration Choice of open-drain output or pull-up resistors at the bit level for ports A, C, and D Reset output level Choice of high or low in groups of 4 bits each (ports C and D) Port function Port E configurable as four comparator inputs 2 MHz, 4 MHz) [Characteristics] Minimum cycle time 2.77 pS (Vpp 2 3.0 ) 0.92 ps (Vop 2 3.0 V) 3.94 ps (Vpp 2 2.2 ) Operating temperature -40 to +85C 40 to +B85C 40 to 485C Power supply voltage 3.00 6.0V 30W60V - 22060V Current drain 1.1 mA typ. 1.6 mA typ. 1.0 mA typ. {Clock] RC (850 kHz, 400 kHz typ.) RC (400 kHz typ.) Oscillator Ceramic oscillator (400 kHz, 800 kHz, | Ceramic oscillator (2 MHz, 4 MHz) Ceramic oscillator (400 kHz, 800 kHz, 2 MHz, 4 MHz) Frequency divider options V1, V3, 1/4 1A 1/1, 1/3, 14 [Miscellaneous] Package DIP24S, SSOP24, MFP30S DIP24S, SSOP24, MFP30S DIP248, SSOP24, MFP30S OTP Included Included Included Note: The oscillator constants will be announced once the recommended circuit design has been decided. No, 5117-2/39Pin Assignments MFP3058 RES PEO/CMPO PE1/CMP2 NC PE2/CMP2 PE3/CMP3 VREFO = oO PEE BEB LEO OEE OA DIP24S/SSOP24 RES PEG/CMPO PE1/CMP1 PE2/CMP2 PE3/CMP3 VREFO VREF 1 PAO PAl PA2 PAR DD LC6529N, 6529F, 6529L FEB EE AN SATE EB Al fel fel fel A fel ft fl el il + hm osecl o5C2 TEST VSS Po3 Phe Ppl PDO PC3 Pc2 See EE EES ee a Ps] Pcl [t3] Pco Top view Note: Do not use dip-soldering when mounting the SSOP package on the circuit board. Package Dimensions unit: mm 3073A-MFP30S [LC6529N, 6529F, 6529L] 0.25 ! . 16 an | 6 ao nl 7 5 x | ma] be 15.3 | x E o w SANYO: MFP30S unit: mm 3067-DIP24S [LC6529N, 6529F, 6529L] ng OOO MFO mM o POUUEUEUUUUS 21.2 0.25 _O pe 6b =n fen nah alle tf 95 0.48 095 1.78 SANYO: DIP24S 3.9 max 3.3 unit: mm 31754-SSOP24 [LC6529N, 6529F, 65291] 0.15 ANRARRRAARAG EERE EERE {40:65 0:22 S| SANYO: SSOP24 Note: The above diagrams give only the nominal dimensions. Contact Sanyo for drawings complete with tolerances. No. 5117-3/39LC6529N, 6529F, 6529L Pin Names OSC1,OSC2: Pins for RC or ceramic oscillator circuit TEST: RES: PAO to PA3: PCO to PC3: PDO to PD3: PEO to PE3: CMP0 to CMP3: Comparator input port, bits 0 to 3 VREFO, VREF1: Reference inputs Test pin Reset pin Bidirectional I/O port A, bits 0 to 3 Bidirectional I/O port C, bits 0 ta 3 Bidirectional I/O port D, bits 0 to 3 Unidirectional input port E, bits 0 to 3 System Block Diagram RAM: AC: ALU: DP: Osc: TM: STS: PC PAO~3 ROM (1 Kbyte} STACK1 STACK2 STACKS STACK PO~3 PIO~3 VO BUFFER PEO~3 CMPO + RES CMP1 TEST CMP2 *- VDD CMP3 +_ Y5S VREFO OSC1 ose osc2 VREF1 Data memory ROM: Program memory Accumulator PC: Program Counter Arithmetic and Logic Unit IR: Instruction Register Data pointer I.DEC: Instruction Decoder E register CF: Carry Flag Oscillator circuit ZF: Zero Flag Timer TMF: Timer overflow Flag Status register No. 5117-4/39LC6529N, 6529F, 6529L Pin Functions PinNo.| Symbol | 0 Function Output driver type Options State after reset 1 Voo | Power supply. Normally +5 V. ~_ 1 Vss | Power supply. OV. = _ 1. 2-pin RC oscillator circuit (1-pin external clock) 1 OSC1 | | Pins for attaching external system 2. 2-pin ceramic oscillator circuit 1 osc? | clock oscillator circuit (AC or ceramic) 7epin eircul 3. Frequency divider options: 1/1, 179, 1/4 * Bidirectional WO port AO to Aa: 4-bit vot : : : . N channel: sink input (IP instruction), 4-bit output (OP : . : va: current type instruction}, 1-bit conditionals (BP 1. Open-drain output PAO and BNP instructions), 1-bit set and | * YO voltage limit tor | pe p PA4 reset (SPB and RPB instructions) open-drain 2, Pull-up resistor High output (output 4 PAD Wo], PA3 also doubles as standby configuration: max. . Choice of configuration 1. or 2. at | N channel transistor : +15 V bit level off} PAa operation control. Poh Ie high Block chattering from entering PAS mpedance aihu during the HALT instruction pulrup execution cycle, ype * N channel: sink 1. Open-drain output ce current type : PCO Bidirectional I/O port CO to C3, VO voltage limit f 2, Pull-up resistor Functions the same as PAO to PAR ge limit tor : ; 3. High output after reset PC1 except that there is no the standby open-drain group ; ; 4 pc2 vO operation control. configuration: max. |] 4. Low output alter reset High or low (option) Option contrata whether output is +15 * Choice of configuration 1. or 2. at Poe high or low atter reset. P , P channel: low- . erevel configuration 3. or 4. at impedanca pull-up te ; nw ation 4. or 4. a type port (4-bit) level * Nchannet: sink 1, Open-drain output current type ; , 2. Pull-up resistor PDO VO voltage limit for ; PO Bidirectional /O port DO to D3. open-drain 3. High output after reset 4 VO | Functions and options the same as configuration; max. | 4. Low output after reset High or low (option) PD2 PCO to PC3. +15 V * Choice of configuration 1. or 2. at Pb3 * P channel: high- bilevel = impedance pull-up * Choice of configuration 3. or 4. at type port (4-bit) level When configured for comparator input: CMPO and CMP1 use reference voltage Vagr0; CMP2 and 1. Comparator input CMP3 use reference voltage Vac. . 4 i . . 2. Port E input PEOQAGMPO 4-bit (CMPO to 3) input (IP . . PEAICMP4 instruction) 3. Without feedback resistor + 1-bit conditionals (BP and BNP 4. With feedback resistor PE2/CMP2 instructions) ( * Choice of configuration 1. or 2. at whee eneneeee PESCMP3 cre pernvarrarecuncraninanecateccsyapacscycencurrenarec aria port {4-bit) level * When configured for port E input: * Options 3. and 4. only available 4 |" 4-bit (E0-3) input (IP instruction) with 1, 1-bit conditionals (BP and BNP instructions} * Comparator referenca level inputs: CMPO and CMP1 use reference 3 Vrer0 ; voltage Vagr0; CMP2 and CMP3 Vacrl use reference voltage Vacrt. Connect ta Vgg when PEO/CMPO to PE3/CMP3 configured as port E. System reset input + Connect external capacitor for power 1 RES I up reset. * Low level input for a minimum ot four clock cycles triggers a reset. 1 TEST | | Chip test pin. Normally connect to Vgg. No. SLI7-5/39LC6529N, 6529F, 6529L Oscillator Circuit Options Name Circuit diagram Conditions, ate. External clock Leave OSC2 open. 2-pin AC oscillator circuit 2-pin ceramic oscillator circuit Ceramic oscillator; Hr C2 Rd Frequency Divider Options Name Circuit diagram Conditions, ate. CK 28 . 5 & Available wi | i ircui i No traquenoy divider (1/1) z fosc YES vailadle with al three oscillater circuit options 2 =-5 (N, F, and L versions) a 2 a fs I ec ~ } & oe . . . a i 3 es Available only with external clock and ceramic 1/3 traquencey divider 2 Eo illator cireuit opti Nand L : gO 3 1/3 trequeney divider ES oscillator circuit options (N and L versions) LO | mo D-} 7 ps Available only wi = cos 1/4 frequency divider 3 Eosc > [4 ES vat eon wih external clock and ceramic 3 iva requaney divider i= 5 oscillator circuit options (N and L versions) Oo o Frequency Divider Options LC6529N : ae Frequency divider options Oscillator circuit Frequency (cycle time) Vop range Note 1/9 and 1/4 frequency divider options 400 kHz 4/1 (10 ps) 310 6V not available 11 (5 ps) 3to6V BGO kHz 1/9 (15 ps) 3106V Ceramic oscillator 1/4 (20 ps) 3to6V 1/3 (6 ps) 3106 V io . : 2 MHz 1/4 (8 us) 3106V 1/1 fraquency divider option not available 1/3 (3 ws) 3to6V os . , 4 MHz 1/4 (4 ps} ateBV 1/3 frequency divider option not available 200 k to 1444 kHz 11 (20 to 2.77 ps) 3tc6V eal crook ased on RC 600 k to 4330 kHz 1/3 (20 to 2.77 us) 3to6V CMBLOT CICUL 800 k lo 4330 kHz 1/4 (20 to 3.70 us) 3to6V Use 1/1 frequency divider and recommended constants or, if this is not possible, one of the RC oscillator circuit frequency, frequency divider option, and Voy range atov combinations listed for external clocks based on en RC oscillator circuit, External clock based on ceramic oscillator circuit This configuration not allowed. Use an external clock based on an RC oscillator circuit instead. No, 5117-6/39LC6529N, 6529F, 6529L LC6529F . _, Frequency divider options Oscillator circuit Frequency (cycle time} Vop range Note Ceramic oscillator 4 MHz 1/1 (1 ps) ato6V External clock based on RC oscillator circuit 200 k to 4330 kHz 1/1 (20 to 0.92 js) ato6 External clock based on ceramic . . . , ae oscillator circuit This configuration not allowed. Use an external clock based on an RC oscillator circuit instead. LC6529L ; amr Frequency divider options Oscillator cifeuit Frequency (eycte time} Voo range Note 1/3 and 1/4 frequency divider options 400 kHz 1/1 (10 ps) 2206V not available : 1/1 (5 ps} 2.2t06V 800 kHz 1/3 (15 ps) 2.206V Ceramic oscillator 1/4 (20 ps) 2.206V 143 (6 22t06vV a : : 2 MHz 14 8 Me) 29t06Y it frequency divider option not available 141 and 1/3 frequency divider options not 4 MHz 1/4 (4 ys} 2.2006V available 200 k to 1040 KHz 1/1 (20 to 3.84 ws) 22t06V Exremma lock based on AC 600 k 10 3120 kHz 1/3 (20 10 3.84 ps) 2.2106V senator circu 800 k 10.4160 kHz 1/4 (20 to 3.84 ps} 22t06V RC oscillator circuit Use 1/1 frequency divider and recommended constants cr, if this is not possible, one of the frequency, frequency divider option, and Vpp range combinations listed tor externa! clocks based on an AC oscillator circuit. 2.2006V External clock based on ceramic oscillator circuit This configuration not allowed. Use an external clock based on an RC oscillator circuit instead. Reset Level Options for Poris C and D The following two options are available for controlling the output levels of ports C and D in groups of four bits each. Option Conditions, eaic. High level output after reset Selection affects all bits of port Low level output after reset Selection affects all bits of port Comparator vs. Port E Configuration Option The four pins PEOQ/CMP0 to PE3/CMP3 may be configured for comparator input or as port E. Cotion Conditions, atc. Comparator input Selection affects all bits of port Port E input Selection affects all bits of port No. 5117-7/3LC6529N, 6529F, 65291. Comparator Options The comparators offer the following two configuration options. Name Circuit diagram Conditions, atc. Without feedback resistor CMP0 to 3L}-___>-_? VREFO.1 [}--______4> The comparator does not use hysteresis. With feedback resistor CMP to 307 + P _ VWREFO.1 []}_#-_- The comparator, in combination with an external resistor, uses hysteresis. Port Output Configurations The bidirectional I/O ports A, C, and D offer a choice of two output configurations. Name Circuit diagram Conditions, atc. Open drain (OD) UO be - With pull-up resistors (PU) This option adds a high-impedanee pull-up resistor for port A or D and a low-impedance one for port C. No. 5117-839LC6529N, 6529F, 6529L Specifications LC6529N Absolute Maximum Ratings at Ta = 25C, Vog = 0 V Parameter Symbol Conditions min typ max Unit Maximum supply voltage Vpp max | Vpp 4.3 +7.0 Vv Vit osci*! 4.3 Vpp + 0.3 Input voltage V2 TEST, RES 0.3 Vop +0.3 Vv vA Port E (PE) configuration 0.3 Vpp + 0.3 Output voltage Vo OSG2 Voltages up to that generated allowed. Vv Viol Open-drain (OD) configuration 43 #15 VO voltages = - Vv Vio2 Pull-up (PU) resistor configuration 03 Vop + 0.3 Peak output current lop PA, PC, PD -2 +20 mA loa PA, PC, PD: Average for pin over 100-ms interval -2 +20 Elga1 | PA: Total current for pins PAO to PA3*2 -6 +40 Average output current mA Eloa2 PG, PD: Total current for pins PCO to PC3 and -14 +90 PDO to PDS Pd maxi | Ta+-40 to +85C (DIP24S} 360 Allowable power dissipation Pd max2 | Ta=~40 to +85C (SSOP24) 165 mW Pd max3 | Ta=40 to +65C (MFP30S) 150 Operating temperature Topr 40 +85 C Storage temperature Tstg 55 +125 Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amptitude. 2, Averaged over 100-ms interval. Allowable Operating Ranges at Ta = 40 to +85C, Veg = 0 V, Vp = 3.0 to 6.0 V Parameter Symbol Conditions min typ max Unit Supply voltage Voo Voo 3.0 6.0 v Standby voltage Vet Vpp: Preserves contents of RAM and registers*. 1.8 6.0 Vv Viet pean drain (0) contiguration: With output N-channel 0.7 pp 13.5 Vin? Nae (PU) resistor configuration: With output 0.7 Yop Voo Input high leval voltage -channel transistor off Vind PE: Using port E configuration 0.7 Von Vop Vin4 RES: Vop =18to6V 0.8 Vop Voo Vind OSC1: Using external clock option 0.8 Vop Vpo Vit Vane Po van output N-channel transistor off, Vss 0.3Vpp ViL2 PA, PC, PD: With outpul N-channel transistor off Vss 0.25 Vpp ViL3 PE: Using port E configuration, Vpp = 4 106 V Vss 0.3 Vop ViL4 PE: Using port E configuration Vss 0.25 Vop Input low level voltage ViiS OSC1: Using external clock option, Vpp = 4 to 6 V Vsg 0.25 Voo v ViL6 OSC1: Using external clock option Vss 0.2 Vop Vil? TEST: Vop =4to6V Vss 0.3 Vop Vib TEST Vss 0.25 Vop Vio RES: Voo=4to6V Ves 0.25 Vop ViL16 RES Vss 0.2 Von oaletney en crore ming ine | buat Wy a Na frequency dividers extends 200 (20) 1444 (2.77) | kHz (us) Note: * Maintain the power supply voltage at Vpp until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle. Continued on next page. No. 5117-9/39LC6529N, 6529F, 6529L Continued from preceding page. Parameter | Symbol | Conditions | min | typ | max Unit [External clock conditions] : Frequency text 260 4330 kHz Pulse width textH, textL | OSC1: Ifthe clock frequency exceeds 1,444 MHz, use 69 Risefall times exh, text the built-in 1/3 or 1/4 frequency divider. Figure 1 SD ns [Oscillator guaranteed constants) Ceat OSC1, OSC2: Vop = 4 to 6 V, Figure 2 220+ 5% / . oo Cext OSC1, OSC2: Figure 2 220+ 5% pF 2-pin RC oscillator circuit - Rext OSC1, OSC2: Vp = 4 to 6 V, Figure 2 4.741% ko Rext O51, OSCe: Figure 2 12.04 1% Ceramic oscillator Figure 3 See Table 1. Electrical Characteristics at Ta = 40 to +85C, Vgs = 0 V, Vpp = 3.0 to 6.0 V Parameter Symbol Conditions min yp _ max Unit Open-drain (OD) configuration for port: With output ht N-channel transistor off. (Includes transistors leak 5.0 Input high level current current.) Vin = 13.5 yA Ine PE: Using port E configuration, Vy = Von 1.0 Nin OSC1: Using external clock option, Viy = Vpp 1.0 Open-drain (OD) configuration for port: With output Int N-channel transistor off. (Includes transistors leak -1.0 current.) Viq = Vsg . Pull-up (PU) resistor configuration for port A or D: nA Ip2 With output N-channel transistor off. (Includes -220 71,5 transistor's leak current.) Vin = Vgg Input low level current Pull-up (PU) resistor configuration for port C: Wd With output N-channel transistor off. (Includes -6.00 2.17 mA transistor's leak current.) Vin = Vgg M4 PE: Using port E configuration, Vij = Vgg -1.0 Ww RES: Vin = Vss 45 -10 pA 16 OSC1: Using external clock option, Viy = Vsg -1.0 Vout Pull-up (PU) resistor configuration for port C: Vv 12 ; OH InH = 300 pA, Vop = 4 10 BV DD-' Output high level voltage - = = Vv Veu2 Pull-up (PU) resistor configuration for port C: V 05 OH lon = 60 pA opT: Veit PA, PC, PD: lo, = 10 MA, Vpp = 4 10 8 V 15 Output low level voltage Vey 2 PA, PC, PD: With Io, for each port less than or equal 0 V OL | to 1 mA, Ig, = 1.8 mA 4 Ving! RES o1V Hysteresis voltage HS - = - BD v Vuis2 OSC1*: Using RC oscillator or external clock option 0.1 Vop Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1. No. 5117-10/39LC6529N, 6529F, 65291. Parameier Symbol Conditions | min typ | max | Unit [Current drain} l 1 | Vpp: Figure 2, 850 kHz 0.8 2.0 RC oscillator DO.OP DD 9 (ye) mA Ipp op2 | Yop: Figure 2, 400 kHz (typ) a4 1.0 lpp op3 | pp: Figure 3, 4 MHz, 1/3 frequency divider 1.6 4.0 ipo op4 =| Vpo: Figure 3, 4 MHz, 1/4 frequency divider : 1.6 4.0 I 5 | Vop: Figure 3, 2 MHz, 1/3 frequency divider 13 3.0 Ceramic oscillator BDF BO 2 ul mA lop op6 | Vpp: Figure 3, 2 MHz, 1/4 frequency divider 13 3.0 Ipp op? Vop: Figure 3, 800 kHz 4.1 2.6 lop op8 | Vop: Figure 3, 400 kHz 0.9 2.4 Vpp: 200 to 667 kHz, 1/1 frequency divider, lpp op9 =| G00 to 2000 kHz, 1/3 frequency divider, 1.0 2.5 800 to 2667 kHz, 1/4 frequency divider External clock mA Vpp! 200 to 1444 kHz, 1/1 frequency divider, Ipp op10 | 600 to 4330 kHz, 1/3 frequency divider, 1.6 4.2 800 to 4330 kHz, 1/4 frequency divider Vop: With output N-channel transistor off and Ino St | port level = Vpp, Vp = 6 V 0.05 10 Standby operation - pA lon st2 Vop: With output N-channel transistor off and 0.025 5 DD port level = Voo. Vop =3 . [Oscillator characteristics) (AC oscillator) 0$C1, OSC2: Figure 2, Cext = 220 pF + 5%, Oscllator requen , Rext = 12.0 kat 1% 309 400 577 ie scillator frequ z sveney MOSC [oSC1, OSC2: Figure 2, Cext = 220 pF # 5%, 560 350 +200 Rext = 4.7 kt 1%, Vop =4to6V [Oscillator characteristics] (Ceramic oscillator} - OSC1, OSC2: Figure 3, fg = 400 kHz 384 400 416 ; OSC1, OSC2: Figure 3, fg = 800 kHz 766 600 832 Oscillator frequency fcrose* kHz OSC1, OSC2: Figure 3, fg = 2 MHz 1926 2600 2080 OSC1, OSC2: Figure 3, Ip = 4 MHz 3840 4000 4160 Figure 4, fg = 400 kHz 10 Oscillator stabilization inte:val lors Figure 4, fq = 800 KHz, fo = 2 MHz, fg = 4 MHz, ms 143, 1/4 frequency divider 10 (Pull-up resistors] Pull-up (PU} resistor configuration for port A or D: RPP1 With output N-channel transistor off and Viy = Vss. 30 70 130 Vop =5 VO ports DD - = - Pull-up (PU) resistor configuration for port C: ka RPP2 With output N-channel transistor off and Viy = Vgs, 10 23 3.9 Vop = 5V Reset port Ru RES: Vin = Vss. Vpp = 5 200 500 725 External reset characteristic: t See Reset time RST Figure 6. . . f=1 MHz, Vin = gs ter pins other than one Pin capacitance Cp baing measured 10 pF Note: * forosc is the allowable oscillator frequency. Comparator Characteristics for Comparator Option at Ta = 40 to +85C, Veg = 0 V, Vpp = 3.0 to 6.0 V Parameter Symbol Conditions min typ max Unit Reference input voltage range VaFIN Vrero and Vaert : Veg +09 Vop - 1.5 v Inphase input voltage range Vemin | CMPO to CMP3 Vss Vop - 1.5 v Offset voltage Vorr Voemin = ss 1 Yop - 1-5 +50 +300 mv R d TRS1 Figure 5: Vpp = 4 to 6 1.6 5.0 fesponse spee P Pe TRS2 Figure 5 1.0 200 bs hy VaerO and Vreet 1.0 Input high tevel current 1H REF REF - - In CMPO to CMP3: Without leedback resistor option 1.0 1 Veer0 and Vacel -1.0 Input low level current te REF REF - - l2 CMP0 to CMP3: Without feedback resistor option -1.0 Feedback resistor RCMFB_ | CMP6O to CMP3: With feedback resistor option 460 ko No. $117-11/39LC6529N, 6529F, 6529L Table 1 Guaranteed Constants for Ceramic Osclilators Oscillator type Standard type Chip type Manufacturer | Oscillator | C1 { C2 | Ad Manufacturer] Oscillator | C1 | C2 [External capacitor] 4-MHz caramic Murata CSA400MG) |33pF 410% |99pF+10%] Murata CS AC4.00MGC| 33 pF + 10% [33 pF + 10% oscillator Kyocera KBR-4.0MSA |33pF 410% |3apF410%] _ _ _ 9.MHz ceramic Murata CSA200MG) [33 pF 410% |33pF+410% | Murata CS AC2.00MGC| 33 pF + 10% [33 pF + 10% oscillator Kyocera KBR-2.0MSA |33pF 410% |33pF210%] = _ = _ [Built-in capacitor] 4-MHz ceramic Murata CS A4.00MG _ _ _ Kyocera KBR-4.0MWS _ oscillator Kyocera KBR-4.0MSA _ _ _ _ ~ 2 Mit Ceramic Murata | CS A2.00MG ~ _ | kyocera | KBR-2.0MWS ~ _ 800-kHz ceramic Murata CS Badd! 100 pF + 10% [100 pF + 10% | 3.3 ke? _ _ - - oscillator Kyocera KBR-BOOFY = |150pF+10%[150pF 410%] _ _ = 400-kHz ceramic Murata CS B4agoP 220 pF + 10% | 220 pF + 10% | 3.9 kQ _ _ _ oscillator Kyocera KBR-400BKY |390 pF 210% (330 pF+10%| _ OSCl (OSC2) External clock - OPEN text Figure 1 External Clock Input Waveform No. 5117-1239LC6529N, 6529F, 6529L OSC] OSC2 OSC1 OSC2 +i t 4o}-F" Rext | Ceramic oscillator Cext qn on > Figure 2 2-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit VDD / Lower limit of Vp operating range worn res sere cero cc ce cn cc cc ese meereccrccs OV ose N RMAYSRLY hw eS Stable oscillation Oscillator stabilization interval tors Figure 4 Oscilator Stabilization Interval VCMIN VOFF VREF /\ VOFF VCMIN Comparator Output data TRS Figure 5 Comparator Response Speed (TRS) Timing No. 5117-1339LC6529N, 6529F, 6529L CRES (=0.1 uF) Note: When the power supply rising interval is zero, a vaiue of 0.1 pF for CRES produces a reset interval of 10 to 100 ms. It the ae power supply rising interval is larger, adjust CRES to produce a fminiraum interval of 10 ms for the oscillation to stabilize. Figure 6 Reset Circuit LC6529N RC Oscillator Characteristics Figure 7 gives the RC oscillator characteristics for the LC6529N, The frequency fluctuation ranges are as follows: 1. For Vpp = 3.0 to 6.0 V, Ta = 40 to +85C, Cext = 220 pF, and Rext = 12.0 kQ, 309 kHz $ fyrosc $ 577 kHz 2, For Vpp = 4.0 to 6.0 V, Ta = -40 to +85C, Cext = 220 pF, and Rext = 4.7 kQ, 660 kHz < fMosc <= 1229 kHz These results are only guaranteed for the above RC constants. If the above values are not available, keep the RC constants within the following ranges. (See Figure 7.) Rext = 3 to 20 kQ, Cext = 150 to 390 pF Note: 1, The oscillator frequency must be within the range between 350 and 750 kHz for Vpp = 5.0 V and Ta = 25C, 2, Make sure that the oscillator frequency remains well within the operating clock frequency range (See frequency divider option table.) for the two ranges Vpp = 3.0 to 6.0 V, Ta = -40 to +85C and Vpp = 4.0 to 6.0 V, Ta = 40 to +85C. f MOSC-Roext 1000 i 5 Thesa curves indicate represen- 4h tative values and not necessarily guaranteed characteristics. N 3 x x 2 oO 1000 = 4} 7 |e - 4 3 VDD= 5 (}; Ta= 25(C 100 2 3 45 10 2 3 45 100 Rext [kQ] Figure 7 RC Oscillator Frequency Data (Sample Values) No. 5117-1439LC6529N, 6529F, 6529L LC6529F Absolute Maximum Ratings at Ta = 25C, Ves =0V Parameter Symbol Conditions min typ max Unit Maximum supply voltage Vpp max | Voo 0.3 47.0 Vv 7 osci*1 03 Vpp + 0.3 Input voltage v2 TEST, RES 0.3 Vpp + 0.3 v V3 Port E (PE) configuration 03 Vop + 0.3 Output voltage Yo Osc2 Voltages up to thal generated allowed. v Viol Open-drain (OD) configuration 0.3 +15 VO voltages = = v Vig2 Pull-up (PU) resistor configuration 43 Voo + 0.3 Peak output current lop PA, PC, PD -2 +20 mA loa PA, PC, PD: Average for pin over 100-ms interval -2 +20 Average output current Loa! PA: Total current for pins PAO to PAQ*2 -6 +40 mA Eloa2 AOD ea roieg current for pins PCO to PC3 and 44 490 Pd maxi | Ta =~40 to +85C (DIP245) 360 Allowable power dissipation Pd max? | Ta =40 to +85C (SSOP24) 165 mw Pd max3 | Ta = -40 to +85C (MFP30S) 150 Operating temperature Topr -40 +85 26 Storage temperature Tstg -55 4125 Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2, Averaged over 100-ms interval. Allowable Operating Ranges at Ta = 40 to +85C, Vss =0V, Vpp =3.0 t0 6.0 V Parameter Symbol Conditions min typ max Unit Supply voltage Von Vop 3.0 6.0 Vv Standby voltage Vsr Vpp: Preservas contents of RAM and registers". 1.8 6.0 Vv Vit Deen crain (00) configuration: With output N-channel 0.7 Vpp 13.8 Vine Aue (PU} resistor configuration; With output 0.7 Vop Vp Input high level voltage -channel transistor off v Vins PE: Using port E configuration 0.7 Vop Vop Vind | RES: Vpp = 1.8 0 6 V 0.8 Vop Yop Vind OSC1: Using externa! clock option 0.8 Vop Vop Vit Vopea re ven output N-channel transistor off, Vsg 0.3 Vpp ViL2 PA, PC, PD: With output N-channel transistor off Vgg 0.25 Vop Vila PE: Using port E configuration, Vpp = 4 10 6 V Vss 0.3 Vop Vila PE: Using port E configuration Vg 0.25 Von Input low level voltage Vis O8C1: Using external clock option, Vpp = 4 to 6 V Vss 0.25 Vop v Vi.6 OSC1: Using external clock option Ves 0.2 Vop Vu? TEST: Vpn = 4 to 6 V Vs5 0.3 Vop Vi8 TEST Vss 0.25 Vop Vio BES: Vop =4t06V Vs5 0.25 Vop Vi,10 | RES Vsg 0.2Vop Operating frequency fop 200 4330| kHz (cycle time) (Tcyc) (20) (0.92)] {ys} (External clock conditions] Frequency text 200 4330] kHz Pulse width textH, textL | OSC1: Figure 1 69 ns Rise/talt times textR, textF 50 Oscilfator guaranteed constants Figure 2 See Table 1. Ceramic oscillator Note: * Maintain the power supply voltage af Vp until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle. No. 5117-15/39LC6529N, 6529F, 6529L Electrical Characteristics at Ta = 40 to +85C, Vgg = 0 V, Vpp = 3.0 to 6.0 V Parameter Symbol Conditions min typ max Unit Open-drain (OD) configuration for port: With output lin! N-channel transistor off. (Includes transistor's leak 5.0 Input high levet currant current.) Vin = 13.5 yA ly2 PE: Using port E configuration, Viy = Vop 1.0 ty OSC1: Using external clock option, Vi = Yop 1.0 Open-drain (OD} configuration for port: With output I N-channel transistor off. (Includes transistor's leak -1.0 current.) Vin = Vss Pull-up (PU) resister configuration for port: I2 With output N-channel transistor off. (Includes 220 71.5 transistor's leak current.) Vin = Vss Input low level current Pull-up (PU) resistor configuration for port C: Is With output N-channel transistor off. (Includes -6.00 2.17 mA transistor's leak current.) Viy = Vg h4 PE: Using port E configuration, Viy = Vs -1.0 WS RES: Vin = Ves 45 -10 pA 16 OSC1: Using external clock option, Viy = Ves -1.0 Pull-up {PU} resistor configuration for port C: Vou! Voo - 1.2 low = 300 HA, Vpp = 4 tO 6 Output high level voltage GH pA - BD - Vv Ve? Pull-up (PU} resistor configuration tor part C: Van -05 GH Igy = 60 pA ob 7 * Vow PA, PC, PD: lol = 10 MA, Vop = 4106 V 15 Output low level voltage Vew2 PA, PC, PD: With Ig, for each port less than or equal 0 Vv OL? to 1 mA, Ig, = 1.8.mA ; 4 Vung! RES 0.1 V, Hysteresis voltage Hs 7 , : oe v Vuis2 | OSC1*: Using RC oscillator or external clock option 0.1 Vo5 Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC 1. Parameter Symbol | Conditions min typ max Unit [Current drain] Ceramic oscillator Ipp op? | 20! Figure 2, 4 MHz, 200 to 4330 kHz, 1.6 40 1/1 frequency divider mA Note: With output N-channel transistor off and External clock loo op2 port level = Vp 1.6 4.2 Vpp: With output N-channel transistor off and loost! | port level = Veo. Vop = 6 V 9.05 10 Standby operation pA lam 2 Vop: With output N-channel transistor off and 0.025 5 DD st | port level = Vpp, Vpn = 3 V : [Oscillator characteristics] (Ceramic oscillator) Oscillator frequency logos | OSC1, OSC2: Figure 2, fg = 4 MHz* 3840 4000 4160 kHz Oscillator stabilization interval = icg Figure 3, fg = 4 MHz 10 ms [Putl-up resistors] Pull-up (PU) resistor contiguration for port A or D: RPP1 With output N-channel transistor off and Viy = Vgs, 30 70 130 Von = 5 VO ports , . . Pull-up (PU) resister configuration for port C: kQ RPP2 With output N-channel transistor off and Vij = Vgs, 1.0 23 3.9 Reset port Ru RES: Vin = Vss. Vpp = 5 200 500 725 External reset characteristic: t See Reset time RST Figure 5. . . f= 1 MHz, Vix = Vg for pins other than one Pin capacitance Cp being measured 10 pF Nete: * forage is the allowable oscillator frequency. No. 5117-16/39LC6529N, 6529F, 6529L Comparator Characterlstics for Comparator Option at Ta = 40 to +85C, Vgg = 0 V, Vopp = 3.0 to 6.0 V Parameter Symbol Conditions min typ max Unit Reference input voltage range Vaew | Veace. Vacet Vg5 +03 Vpp - 1.5 V Inphase input voltage range Vowun CMPO to CMP3 Vss Vop - 1.5 Vv Offset voltage Vorr VemiIn = Vs f0 Vpp - 1.5 +50 300 mv TRS Figure 4: Vpp = 4 10 6 V 1.0 5.0 Response speed - us TRS2 Figure 4 1.0 200 lit Vrer, Vacrt 1.6 Input high level current iW REF AREF - - - Ie CMPO to CMP3; Without feedback resistor option 1.0 Vi Vaeero. Veet =1.0 Input low level current Ie REF REF ; - = 2 CMP0 to CMP2: Without feedback resistor option 1.0 Feedback resistor RCMFB | CMPO to CMP3: With feedback resistor option 460 kQ Table 1. Guaranteed Constants for Ceramic Oscillators . Standard type Chip type Oscillator type - - Manufacturer] Oscillator | ci [C2 | Rd |Manutacturer} Oscillator | Ct } C2 (External capacitor] 4-MHz ceramic Murata CSA4.00MG [33 pF 410% 133 pF 410%) Murata CS AC4,.00MGC] 33 pF + 10% | 33 pF + 10% oscillator Kyocera KBR-4.0MSA [93 pF + 10% [33 pF + 10% | _ 7 _ = 2.MHz ceramic Murata CSA200MG |33pF 410% |83pF+10%]) Murata CS AC2.00MGC] 33 pF + 10% 133 pF + 10% oscillator Kyocera KBR-2.0MSA [339 pF 410% [33 pF 410%] _ - _ _ [Built-in capacitor] - 4-MHz ceramic Murata CS A4.00MG _ - _ Kyocera KBR-4.0MWS _ - oscillator Kyocera KBR-4.0MSA _ 2-MHz ceramic oscillator Murata C$ A2.00MG - - Kyocera KBR-2.0MWS _ Oscl (OS8C2) External clack OPEN | textF text Figure 1 External! Clock Input Waveform No. 5117-17/39LC6529N, 6529F, 6529L OSC1 OSC2 +{[]+4 Ceramic oscillator clo C2 ITH] ITH] Figure 2 Ceramic Oscillator Circuit Lower limit of Von operating range Osc 2 _ 2 Stable oscillation a . . Oscillator stabilization interval crs Figure 3 Oscillator Stabilization Interval VCMIN 4 VOFF VREF + VOFF VCMIN Comparator Output data TRS Figure 4 Comparator Response Speed (TRS) Timing No. 5117-18/39LC6529N, 6529F, 6529L CRES (=0.1ynF) Note: When the power supply rising interval is zero, a value of 0.1 uF for CRES produces a reset interval of 10 to 100 ms, It the power supply rising interval is larger, adjust CRES to produce a minimurn interval of 10 ms for the oscillation to stabilize. Figure 5 Reset Circuit No. 5117-19/99LC6529N, 6529F, 6529L LC6529L Absolute Maximum Ratings at Ta = 25C, Vgc =0 V Parameter Symbal Conditions min typ max Unit Maximum supply voltage Voo max | Von 0.3 +7.0 Vv v1 ose1"! 03 Vpp + 0.3 Input voltage V2 TEST, RES 0.3 Von + 0.3 Vv VS Port E (PE) configuration 03 Voo + 0.3 Output voltage Vo OSc2 Voltages up to that generated allowed. v VO voltages Viol Open-drain (00) configuration _ 0.3 +15 V Vig2 Pull-up (PU) resistor configuration ~0.3 Vop + 0.3 Peak output current lop PA, PC, PD -2 +20 mA loa PA, PC, PD: Average for pin over 100-ms interval ~2 +20 Average output current Elgat | PA: Total current for pins PAO to 32 -6 +40] A Soa? ee PD: Total current for pins PCO to PC3 and 44 490 to PD3 Pd maxi | Ta=40 to +85C (DIP24S) 360 Allowable power dissipation Pd max2 | Ta=40 to +85C (SSOP24) 165 mw Pd maxd | Ta=40 to +85C (MFP30S) 150 Operating temperature Topr 40 +85 C Storage temperature Tsig -55 +125 Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2, Averaged over 100-ms interval. Allowable Operating Ranges at Ta = -40 to +85C, Vss =0V, Vop = 2.2 to 6.0 V Parameter Symbol Conditions min typ max Unit Supply voltage Vop Vbp 2.2 60 Vv Standby voltage Ver Vpp: Preserves contents of RAM and registers*. 1.8 6.0 Vv Vaal Pper-drain {OD} configuration: With output N-channel 0.7 Vpp 138 lI- stor fi ion: With Input high tevel voltage Yui? Rchannelanistor of! mene 07op Yoo Vv Ving PE: Using port E configuration 0.7 Vpop Voo Vau4 RES: Vop = 1.80 6V 0.8 Vop Yop Vind OSC1: Using external clock option 0.8 Vop Voo Vit PA, PC, PD: With output N-channel transistor off Vss 0.2 Vop ViL2 PE: Using port E configuration Vss 0.2 Vop Input low level voltage ViL4 OSC1: Using external clock option Vss 0.15 Vop V Via | TEST Vsg 0.2 Vpp Vid RES Vss 0.15 Vop Operating frequency fop Using the built-in 1/3 or 1/4 frequency dividers extends 200 1040] kHz (cycle time) {Teyc) the maximum to 4.16 MHz. (20) (3.84)| (ys) {External clock conditions] Frequency text 200 4166 kHz Pulse width textH, texiL | OSC1: If the clock frequency exceeds 1.040 MHz, 120 Risa/fall times text, text use the built-in 1/3 of 1/4 frequency divider. Figure 1 100 ns [Oscillator guaranteed constants] . ; . Cext 08C1, OSC2: Figure 2 220 + 5% pF 2-pin AC oscillator circuit - Rexi 08C1, OSC2: Figure 2 12.041% ka Ceramic oscillator Figure 3 See Table 1. Note: * Maintain the power supply voltage at Vpp until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle. No. 5117-20/39LC6529N, 6529F, 6529L Electrical Characteristics at Ta = -40 to +85C, Vg = 0 V, Vpp = 2.2 to 6.0 V Parameter Symbol Conditions min typ max Unit Open-drain (OD) configuration for port: With output lint N-channel transistor off. (Includes transistors leak 5.0 Input high level current current) Vin = 13.5 V WA ly? PE: Using port E configuration, Vin = Voo 1.0 ly OSC1: Using external clock option, Vix) = Vpp 1.0 Open-drain (OD) contiguration for port: With output Nt N-channel transistor off. (Includes transistor's leak -1.0 current.) Vin = Vss yA Pull-up (PU) resistor configuration for port: M2 With output N-channel transistor off. (Includes -220 715 transistors leak currant.) Vin = Vgg Input fow level current Pull-up (PU) resistor configuration for port C: 4 With output N-channel transistor off. (includes -6.00 -2.17 mA transistor's laak current.) Vin = Vag 14 PE: Using port E configuration, Vij = Vss -1.0 15 RES: Vin =Vss 45 -10 pA Ne O$SC1: Using external clock option, Viq = Vss -4.0 : Pull-up (PU} resistor configuration for port C: Gutput high level voltage v Vpp - 0.5 v put nig! ig OH lou = ~50 WA oD Vo.1 | PA, PC, PD: Io, = 39 mA 15 Output low level voltage PA, PC, PD: With Ig, for each port less than v Vor2 0.4 or equal to 1 mA, Iqp = 1mA Vuig! RES O1V, Hysteresis voltage HIS - 7 : oo Vv Vuis2 OSC1*: Using AC oscillator or external clock option 0.1 Voo Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC 1. Parameter Symbol Conditions min typ max Unit [Current drain] RC oscillator Ipp op! | Von: Figure 2, 400 kHz (typ) 0.4 1.0 Ipp op2_| Vop: Figure 3, 4 MHz, 1/4 frequency divider 16 4.0 Vop' Figure 3, 4 MHz, 1/4 frequency divider, loo ops Vpp = 2.2 04 08 lop op4 =| Vpn: Figure 3, 2 MHz, 1/3 frequency divider 13 3.0 A mi Ceramic oscillator Ibo opS = | Ypp: Figure 3, 2 MHz, 1/4 frequency divider 1.9 3.0 Vpp: Figure 3, 2 MHz, 1/3, 1/4 frequency divider lbp op6 Vpp 22.2 03 0.6 lop op? | pp: Figure 9, 800 kHz 1 2.6 lop ope Vop: Figure 3, 400 kHz 09 24 Vpp: 200 to 667 kHz, 1/1 frequency divider, External clock Ipp op9 | 600 to 2000 kHz, 1/3 frequency divider, 1.0 25 mA 800 to 2667 kHz, 1/4 frequency divider Vopp: With output N-channel transistor off and Ino 81 | part level = Vpp. Vpp = 6 0.05 10 Standby operation yop Vpp: With output N-channel transistor off and HA Ino S!2 | port level = Vop. Vpp = 2.2 V 0.026 5 [Oscillator characteristics] , RC oscillator Oscillator frequency fuosc Boge Oe ree 2, Cext = 220 pF + 5%, 275 400 S77 kHz [Oscillator characteristics] (Ceramic oscillator) O$C1, OSC2: Figure 3, {9 = 400 kHz 384 400 416 O5C1, OSC2: Figure 3, fg = 800 kHz 768 800 832 Oscillator frequency fcrosc* | OSC1, OSC2: Figure 3, fg = 2 MHz 1920 2000 2080 kHz O8C1, OSC2: Figure 3, fg = 4 MHz, 1/4 frequency divider 3640 4000 4160 Figure 4, fo = 400 kHz 10 : om ten j Figure 4, fg = 800 kHz I Vlg ' Oscillator stabilization interval tors fo = 2 MHz, 1/3, 1/4 frequency divider, 10 ms fo = 4 MHz, 1/4 frequency divider Continued on next page. No. 5117-21 /39LC6529N, 6529F, 6529L Continued from preceding page. Parameter | Symbol Conditions min typ | max Unit [Pull-up resistors] Pull-up (PU) resistor configuration for port A or D: RPP1 With output N-channel transistor off and Viy = Ves, 3 70 130 Vop25V VO ports = = : Pull-up (PU) resister configuration for port C: ko RPP2 = | With output N-channel transistor off and Vyy = Vgs, 1.0 23 3.9 Vop aS V Reset port Ru AES: Viy=Vss. Vpp =5 200 500 725 External reset characteristic: t See Reset time RST Figure 6. . : f= 1 MHz, Viv = Vgg for pins other than one Pin capacitance Cp being measured 10 pF Note * fcrose is the allowable oscillator frequency. Comparator Characteristics for Comparator Option at Ta = -40 to +85C, Vgc = 0 V, Vpp = 3.0 to 6.0 V Parameter Symbol Conditions min typ . max Unit Reference input voltage range VRFIN Vacr. Vacri Vgg +03 Vpp - 1.5 v Inphase input voltage range Vemin | CMPO to CMP3 Vgs Vop - 1.4 Vv Offset voltage Vorr Vomin = s5 t0 Vpp - 1-5 50 #300] mV Response speed TRS Figure 5 1.0 206 ps Input high level current hit Vaer0, Vaert : 10 pA ly2 CMP6 to CMP3: Without feedback resistor option 1.0 Input low level current Mt Vaer0, Vaert - F , a6 pA I2 CMP0 to CMP3: Without feedback resistor option -1.0 Feedback resistor RCMFB | CMP to CMP3: With feedback resistor option 460 kQ Table 1 Guaranteed Constants for Ceramic Oscillators Oscillator type ~ Standard type - Chip type Manufacturer | Osciltator | C1 | C2 | Rd Manufacturer | Oscillator | C1 C2 ({Externat capacitor] 4-MHz ceramic Murata CS A4.00MG 33 pF +10% [33 pFt10% | Murata CS AC4.OOMGC | 33 pF + 10% 1933 pF + 10% oscillator Kyocera KBR-4.0MSA [33 pF + 10% |33pF+10% | = _ _ 2.MHz ceramic Murata CSAZ00MG 439 pF+10% [39 pF210%) Murata CS AC2.00MGC | 33 pF + 10% | 33 pF + 10% oscillator Kyocera KBR-2.0MSA (S33pF+10% (94pF410%| _ _ (Built-in capacitor] 4-MHz ceramic Murata CS A4.00MG - Kyocera KBR-4.0MWS _ osciltator Kyocera KBR-4.0MSA _ _ _ _ _ _ aM aramic Murata CS A2.00MG _ _ {Kyocera | KBR-2.0MWS _ - 800-kKHz ceramic Murata cS Baca 100 pF 4 10% | 100 pF + 10% | 3.9 kO - - - oscillator Kyocera KBR-B00F/ = 150 pF 410% ]150pFt10%] _ - 400-kHz ceramic Murata CS B400P 220 pF + 10% | 220 pF + 10% | 3.3 ka -_ _ - oscillator Kyocera KBR-400BK/Y [330pF 410% (3390 pF+10%| - _ _ No. 5117-2239LC652SN, 6529F, 6529L OSscl (OSC2) External clock OPEN text Figure 1 External Clock Input Waveform OSC1 OSc2 O5C1 OSC2 re tt 401-44 Rext Ceramic oscillator Cext _ 7 a C2 Figure 2. 2-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit No, $11 7-23/39LC6529N, 6529F, 65291. VDD / we eee ene eee ee ee en ence ee eee ce eee. Lower limit of Vag operating range aaa eee OV osc NN] RBA Ha a $e Stable oscillation Osciltater stabilization interval tors Figure 4 Oscillator Stabilization Interval VCMIN VOFF VREF - VOFF VCMIN Comparator Output data TRS Figure Comparator Response Speed (TRS) Timing CRES (=0.1yF) Note: When the power supply rising interval is zero, a value of 0.1 pF , for CRES produces a reset interval of 10 to 100 ms. If the power supply rising interval is larger, adjust CRES to produce a minimum interval of 10 ms for the oscillation to stabitize, a Figure 6 Reset Circuit No. 5117-24/39LC6529N, 6529F, 6529L LC6529L RC Oscillator Characteristics Figure 7 gives the RC oscillator characteristics for the LC6529L. The frequency fluctuation range is as follows: For Vpp = 2.2 to 6.0 V, Ta = -40 to +85C, Cext = 220 pF, and Rext = 12.0 kQ, 275 kHz S$ = fyose S = 577 kHz These results are only guaranteed for the above RC constants. If the above values are not available, keep the RC constants within the following ranges: (See Figure 7.) Rext = 3 to 20 kQ, Cext = 150 to 390 pF Note: 1. The oscillator frequency must be within the range between 350 and 750 kHz for Vpp = 5.0 V and Ta = 25C. 2. Make sure that the oscillator frequency remains well within the operating clock frequency range (See frequency divider option table.) for the range Vpp = 2.2 to 6.0 V, Ta = 40 to +85C. { MOSC -Rext These curves indicate represen- tative values and not necassarily quaranteed characteristics, f MOSC [kHz] VDD= 5 WV) Taz 25 (C) 2 #345 10 2 3945 100 Rext [kQ] Figure 7 RC Oscillator Frequency Data (Sample Values) No. 5117-25/39LC6529N, 6529F, 6529L LC6529N/F/L Instruction Table (by Function) Abbreviations: AC: Accumulator STACK = Stack register ACE Accumulator bit t TM: Timer CF: Carry flag TMF: Timer overflow flag DP: Data pointer ZF: Zero flag E: E register ( 3. 1]: Indicates the contents of a location M: Memory oar Transfer direction, result M(DP)}: Memory addressed by DP +: Addition P(DP,): 1/0 port specified by DP; - Subtraction PC: Program counter : Exclusive or Instruction cade 6 Affected Mnemonic 2 % a Operation Description status Note B Dz Dg Dg Dg Dy Da 0, Dg 2 > 3 = bits [Accumulator manipulation instructions] CLA Clear AC 1100/0000] t]1 /ACeoO Sat AC to zero. ZF * CLO Clear CF 11%40/1/000%1/1)]1 [CFeod Clear CF to zero. CF $Tc Set CF 1114770004] 1)1 [CFe1 Set CF to one. CF CMA Complement AC 7147 0f1 04747171 [ACe (AC) Take ones complement of AC. | ZF ING Increment AC 000041110) 1 4/1 JACe (AC) +1 Add one to AC. ZF, CF DEC Decrement AC o0000]71 11717 1 1 1 [AGE (AC)-1 Subtract one from AC. ZF, CF TAE Transter AC to E oo0007;/0 011] 141 [Ee {AC) Copy contents of AS to E. XAE |ExchangeACwithE|o 00 0]1 101/111 lace pega contents of [Memory manipulation instructions) iInm {lt M oo1o0l111044 M (OP) Add one to M (DP ZF, CF Increment 1 [M{DP)] +1 one to M (DP). , DEM Decrement M 0070/1113) 14471 M (DP) Subtract one from M (DP). ZF, CF [M(DP)] - 1 : : Sat bit specitied by Immediate SMB bit | Set M data bit 0006/1 OB, Bo 1 1 |M(DP, B, Bo) 1 data By By in M (DP) to one. Clear bit specified by RMB bit | Reset M data bit 00 10/1 0 B,Bo| 1 | 1 |M(DP,8, Bp) | immediate data By By in ZF M {DP} to zero, [Arilhmetic, logic and comparison instructions] Add contents of M (DP) to AD |Add MtoAC o1r1rojoooojs|s [ae one) + contents of AG and store 1 ZF, CF [M(DP)] result in AC. Add contents of M (DP) and : AG (AC) + ADC AddMtoACwihCFiO0 01070000] 1]1 M(DP CF CF to contents of AC and ZF, CF [M (DP)] + (CF) Store result in AC. Decimal adjust AC DAA in addition 4 11160/0 11 0/1 1 [AC <(AC)+6 Add 6 to contents of AC. ZF Decimal adjust AC DAS | in subtraction 1110/71 04 04171 JAGe (AC) +10 Add 10 to contents of AC. ZF XOR contents of AC with EXL |ExcusiveorMtoAC]1 1141/0 104]/1] 4 A. oo contents of M (DP) and store | ZF [M(DP)] result in AC, Compare contents of M (DP) with those of AC and set CF and ZF according to result. . Magnitude CM Compare ACwithM]1 1417/4 01 411 [1 [[M{DP) + (AC) +1 comparison CF] ZF | | 2F, CF ([M(DP}]>(AC) | o | 0 [M (DP)] = {AC) 171 [M (DP}] < {AC) 1], 0 Note: * The second and subsequent repetitions of an Lt or CLA instruction produce the same effects as an NOP instruction. Continued on next page. No. 5117-26/39LC6529N, 6529F, 6529L Continued from preceding page. instruction code 6 6 Alfected Mnemonic 8 o & s Operation Description status Note Dz Dg Ds Dg {D4 D2 Dy Dy 3S 35 bits [Accumulator manipulation instructions) Compare contents of Immediate data field (lg lp I la) with those of AC and set CF and ZF according to result. Compare AG with 0010/1160 7 Ci data immediate data O14 0 lg lo ly tp 2 2 lg lo ly lo + (AC} +1 Magnitude oF | zr ZF, CF comparison 13 Ip ly lp > AC ao] 0 Ig ly Iy Ip = AC 1] 1 lz lp ly lo <AC 1 0 (Load and store instructions] Load AC with Load AC with contents of . , \ LI data immediate data 110 Of] fy lo ly Io} 1 | 1 [ACH Igloly Ip kh. field ZF s Store AC to M 0000/0010] 1] 4 |M(DP)< (AC) Me ot AC to L Load AC from M 0010/0001] ft | 1 |ACe[M (DP)! Copy contents of M (D) to AC. | ZF [Data pointer manipulation instructions] Load DP, with zero LOZ [and DP with 10.00] ly lo bf + | 1 [OPH tone etn radiate date data | immediate data 3 2 1 DPLe lal lp fold (t ' Wy to OP, respectively iald (ly ' 11 Ig) to OP. Load DP), with Copy contents of immediate LHI dala | immediate data 0100/0 0h bh} t | t pDPHe lhl data field (Iq Ip) to DP,y. IND Increment DP, 1110/1714 07 141 [DPL (OP) +1 Add one to DP_. ZF DED Decrement DP, 14140711414 4] 14491 {DPL(DP,)-1 Subtract one from DP_. ZF TAL Transfer AC toDP, | 4 1 1 1/0 71 1 147 17 1 | DPL {AC} Copy contents of AC to DP,. TLA Transfer DP, toAC {4 11 0/1 001; 1 f 1 [ACe (DP) Copy contents of DP, to AC. | ZF [Jump and subroutine instructions] PC e Pg Pg P7 Pg | Jump to address in Immediate JMP | Jump O 1 1 0} 1 0 PoPal ola P,P Pz | data field (Py Pg Py Py Ps Pg addr Py Ps Ps Py Py Pp Py Py P, Pg Py Po P, Po}. STACK (PC) +1 a PGgq to PCg, PC), zp Call subroutine in 1:0 1:1 7PgPoPyP] 1] 1 |PCoeO Call subroutine in zero page. addr the zero page PCs to PCy Pg Po Py Po STACK (PC} +2 CAL ' 101671 O Pg Py Py to Pp 0 : addr Call subroutine Py Pg Ps Pa | Pg Po Py Po 2]|2 Pg Pg Pz Pg Ps Pa Call subroutine. Py Po Py Po RT Ret im rom 011070 6 41 G] 1 ]1 {PC (STACK) Return from subroutine. (Branch instructions] PG? to PC, Branch to specified address The mnemoni BAt or1rifort P> Ps PsP, | in same page (P10 Po) if bit includes decimal Branch on AC bit 1 lo) aj 2 76 64 in same page (P7 10 Po) | equivalent t of addr P7 Pg Ps Pa] Pa Po Py Po Pg Pa Py Po specified by immediate data immediate data ACY = 1 ty tg in AC is one. i.e., BAO to BAS, The mnemonic PC? to PCy Branch to specified address includes decimal BNAt , 10 017/060 0 & ty P+ Pg Pg Pa in same page (P7 to Po) if bit equivalent t of addr | Branch onno AC Bit |p. pop. P,P, P2P;Pp| 7 | 2 P3PzP,P, | specified by immediate data immediate data ifACt=0 ty ty in AC is zero. i.@., BNADO to BNA3. PC] to PCy : The mnemonic Pz Pg Ps Pa Branch to specified address includes decimal BMt . O17 17/0 1 t & in same page (P> to Po} If bit ddr |BvanchonMbit inp pep, |Ps PoP; Po| - | 2 3FaFiFo | specified by immediate data equivalent t of addr 7 Pe Ps Pal Pa Tari ro IFIM (DP, ty ta) ee OP | immediate data =1 4 fin M (DP) is one. i.e., @MO to BM3. Note: * The second and subsequent repetitions of an LI or CLA instruction produce the same effects as an NOP instruction. Continued on next page. No. 5117-27439LC6529N, 6529F, 6529L Continued trom preceding page. Instruction code. 3 6 Affected Mnemonic 2 wo 2 g Operation Description status Note D7 Dg Dg Dy | D5 020, Do 5 33 bits (Branch instructions) The mnemonic PCy oe p Branch to specified addrass includes decimal BNMt Branch M bit 091140 1 ty ty Pp. pe Pp p, in same page (Py to Po) if bit equivalent t of addr ranen on no MIDI Py Pg Ps Py] Pa Po Py Po OM TDR, totes) | SPemilied by immediate data immediate data mt (DP. ty toll 14, ty in M (DP) is zero. i.@., BNMO to ~ BNM3. PC? Pees p Branch to specified address ee emer 6 4 i fbi oe Branch on port bit . P P p p . 2 2 Pg Po Py Py n shed bei (Py i one equivalent | of a 7PefshalPareri ta if[P (DPL, ty to)] pee OD he, ate cata immediate data = 14g in P (DPL) is one. i.e., BPO to BPS. The mnemonic PCy on p Branch to specified address includes decimal BNPI ,JO0 1111 6 t ty 7 6 54 in same page {P7 to Py) if bit equivalent t of addr (| Branch on no portbit |p 5p py | Ps Pp Py Py i, ara t Fo | specified by immediate data immediate cata HU (PPL ts tolls, ty in P (DP) is zero, i.e., BNPO to ~ BNP3. PCy e oe Pp Branch to specified address 81M . aoiiat{i1100 Feo in same page (P; to Po) F addr | Branchontimer bg Pg Pg |Ps Po Py Pp Patahs Po | if TME is one, Clear TMF then TMF 0. | ' Zero. PCr , eo p Branch to specified address BNTM . ooi11}]1 100 7 ena! in same page (P, to Py) addr | Branchonnotimer Jo, 5p, Py| Pg Py Py Po raze y |W TMFiszero, Clear tme | "MF then TMF 0. | '9 28". PG> to PCy ., BC Branch on GF Gye P7 Pe Ps Pa inseme pace (P,toPs) addr Py Pg Ps Pg | Py Pp Py Py PaPoPi Po |tarig oa Foro itCF=1 . PC7 to Pp Branch to specified addrass BNC Branch on no CF Oovrye rad P7 Pe Ps Pa in sama page (Pz to Pp) addr Py Ps Ps Py Py Pa P, Po Ps Ps P, Pg if CF is zaro 7 Oo ifCF=0 , PCy 10 PCy Branch to specified address B2 Branch on 2F Ot Taya tr to P7 Pe Ps Pa in sama page (Py to Py) addr P7 Pg Ps Pe [Pg Po Py Po PyPoPyPo | oriscme ifZF=1 PCy to POy -_ age BNZ Branch on no ZF OO Tit 11 0 P7 Po Ps Pa ineame page (Plo P,) addr Py Pg Ps Py |P3 Po Py Po PgP2PyPp [itor pad 7109 ZF =0 [1/O instructions} is of IP Input port to AC 9000/1100 AC & [P (DP,}I Soecied by P Pon)%6 ac. (2 ts of A oP OutputACtopot fo11o0fo004 P (DP) (AC) spect by P oP.) "9 port Sat bit spacified by immediate Execution of this SPB bit | Set port bit 000 0]0 1 By Bo P (OP_,B, Bo) 1 | data 6, By in port spacitied invalidates by P (OP) to one. contents of E. Clear bit specified by exseuton of this RPS bit | Reset port bit 0010/0 1 By By P (DP,_, B, Bg) 0 | immediate data B, By in port | ZF an vee specified by P (DP) to zer invalidates p L . contents of E, [Cher instructions} / a gs TM {E), (AC) Copy contents of E and AC to WTTM = | Write timer 1177/1001 TMF 0 timar. Glaar TMF to zero. TMF Execution HALT Halt 1114/01 16 Halt Suspend all operations. requires that pin PA3 be high. . : , Do nothing but consume one NOP No operation 0000/0 00 06 No operation machine cycle No, 5117-28/39LC6529N, 6529F, 6529L The above subset excludes the following Instructions from the LC6523, 6526 set AND, BFn, BI, BNFn, BNI, CLI, JPEA, OR, RAL, RCTL, RFB, TRI, RTBL, SCTL, SFB, X, XAH, XAO, XAI, XA3, XD, XHO, XH1, XI, XLO, XL1, and XM. Specifying LC6529N/F/L User Options Specifying (Ordering) LC6529N/F/L User Options When developing the software or ordering the chip, the user must prepare an EPROM containing the user program, user option data, and fixed data. There are two ways of preparing these last two: with software provided by Sanyo and manually, This Section discusses both methods. Using Sanyos Option Specification Software SU60K, the software for specifying LC6529 options, interactively asks the user to specify the options and writes the results to a mask option file, file.OPT. The M60K macro assembler assembles the user program into an object file, file.OBJ. The L60K linker merges the mask option and object files to create an EVA file, file EVA. The EVA2HEX conversion tool converts the user program and mask options imside the EVA file to an object file in hexadecimal (HEX) format. The user use a PROM writer to download this HEX file to the EPROM submitted when ordering the chip. For further details, see Figure A below and refer to the LC65/66K Software Manual. Alternate Method 1. Overview If not using the software for specifying LC6529 options, the user must list the mask options using the coding procedures described below and then write these with the program to the EPROM regions shown in Figure A. When ordering, the user must submit an option table list as well as the EPROM. Figure B gives an example of such a list. The procedures for coding the mask options appear on the pages following Figure B. 000H _ + User program area 3EFH 400H; t- Mask option area 404H Figure A LC6529 ROM Data No. 5117-2939LC6529N, 6529F, 6529L 2. Sample option table list f Osc OPTION BITO BIT1 BIT2 BITS [FILE NAME] [COMMENTS ] L: SAMPLE. OPT PORT PORT A MASK OPTION PULL UP tok ok PORT D MASK OPTION OPEN DRAIN KEK KAK HE eeree bene RRR RN IK PULL UP OPEN DRAIN BITO RRR eee BITL s an waeaee FO IO IOI toe BIT2 RRR ERE vee eee aas BITS = aeeuces KOR I IO NX osc DIVIDER \ FOGG GOO ioododo LO6S99F MASK OPTION 1000 pic rig iG Gi OIOIOI iG i toi Oi i toto (94/11/11) ver, 1,*xxx 1/1 whe INPUT OPTION COMP & FB PORT C MASK OPTION BITO BIT] BIT2 BIT3 RaKAKKEER 1/3 1/4 OPEN DRAIN Re RK Figure B Sample Option Table List No. 5117-30/39LC6529N, 6529F, 6529L Coding LC6529N/L Mask Options Always place zeros in the unused bit positions. 2? 30 Oscillator circuit 400H pe . wee 00 + Invalid specification VL 01 + Invalid specification 10 2-pin RC oseillator or 1-pin external clock (2 port RG OSC, 1 port EXT) 1} 2-pin ceramic oscillator (2 port CF OSC) Frequency divider 00 1/1 (straight through) Ol 18 10) (1/4 11 + Invatid specification Port C levels after reset . ] High Port D levels after reset L 0 Low 1 High Comparator configuration L 0 Without feedback resistor 1 With feedback resistor Port input configuration oO Comparator input L 1 PortE 2? 20 401H PC3 PC2 Pcl PCO PA3 PA2 PAl PAO \ i \ / Port A output configuration a_i 0 Open drain Port output configuration ] With pull-up resistors oT QO Opendrain 1 With pull-up resistors 2? 90 402H 0 0 0 0 PD3 PD2 PD1 PDO | \ fe { Always fill with zeros. Port D output configuration TL QO Open drain 1 With pull-up resistors 2? 20 403H PC3 PC2 PC1 PCO 0 | 0 0 0 VL. AA 1 / Port output configuration Always fill with zeros. QO Open drain 9? 1 With pult-up resistors 50 404H 0 0 0 0 0 0 0 0 \ / T Always fill with zeros, No. 5117-31/39LC6529N, 6529F, 6529L Coding LC6529F Mask Options 400H 401H 402H 403H 404H Always place zeros in tha unused bit positions. 2? 20 Oscillator circuit type m= O00 + Invalid specification Ol ++ Invalid specification LA 10 1 (1 port EXT} , (2 port CF OSC} Frequency divider Port C levels after reset 00 1/1 {straight through} Ol +++ Invalid specification 10 +++ Invalid specification 1] ++ tnvalid specification Port D levels afler reset L 0 Low 1 High L 0 Low 1 High Comparator configuration 1 With feedback resistor Port input configuration L 0 Comparator input 1 Port 20 PC3 | PC2 PC1l | PCO | PAS | PA2 PAl | PAO / TT QO Open drain 1 With pull-up resistors a7 T Pert A output configuration Open drain With pull-up resistors 90 0 0 0 0 PD3 | PD2 PD! | PDO \ fv. Always fill with zeros. / Port D output configuration TL Q Open drain ] With pull-up resistors 2 20 PC3 PC2 PC1 | PCO 0 0 0 0 \ i 1 f Port C output configuration Always fill with zeros. Q Open drain 97 1 With pull-up resistors 20 0 0 0 0 0 0 0 0 \ / T Always fill with zeros. 1-pin external clock 1) 2 2pin ceramic oscillator L 0 Without feedback resistor No, 5117-32/39LC6529N, 6529F, 6529L Using Standby HALT Mode The LC6529N/F/L features a convenient HALT mode that reduces current drain while the chip is on standby. These standby functions involve the use of one instruction (HALT) and two control signal pins (PA3 and RES). For the functions to work properly, the design of external circuits and chip software must pay due attention to these three. Depending on how extensively the standby functions are used, the designer must consider and provide countermeasures that protect the design from the effects of power supply fluctuations, power interruptions, external noise, and other adverse conditions. ; This document discusses the circuit and program design issues related to the most frequent application of the standby functions, the detection and recovery from power outages. When using the standby functions, follow the sample circuits given in this document and carefully observe all warnings accompanying them. Departures from the design guidelines herein will warrant thorough testing and evaluation of the effects of such sudden changes in the operating environment as momentary power outages on application operation. 1. Entering and leaving the HALT mode Table 1 gives the conditions for entering and leaving the HALT mode. Table 1 Entering and Leaving the HALT Mode Entering HALT mode Leaving HALT mode 1, Reset signal (RES pin pulled low.) 2. PAS pulled low. Note: Thesecond method for leaving the HALT mode is only available when the design uses-an RC oscillator circuit. It may not work properly with a ceramic oscillater circuit. HALT instruction while PA is high. 2. Important notes Using the standby functions requires close attention to the following issues in application circuit and software design. * The power supply voltage must not fall below the rating while the chip is on standby. - Carefully observe all timing restrictions for the control signals during transitions to and from the HALT mode. * Make sure that a signal for leaving the HALT mode does not overlap the execution of the HALT instruction. This document demonstrates how to observe these restrictions by discussing both application circuits for a power failure recovery function and programming considerations. Such a power failure recovery function detects failure of the main power supply and causes the chip to execute a HALT instruction to put itself on standby. Reducing the current drain this way allows the backup capacitor to maintain the register contents for a longer period than otherwise possible. When the power is restored, the chip is reset and automatically resumes execution with the program counter set to COOH. The following examples discuss how the software can then distinguish this type of reset from a power on reset sequence along with issues related to dealing with momentary AC power outages. Example 1 The first example does not distinguish a power-on reset sequence from a reset trigger by a power failure. Circuit diagram Figure 2-1 gives the circuit diagram for this sample circuit. No. 5117-3389LC6529N, 6529F, 6529L Ol ye Feo} P 100V TT AC F180) el a (~1F) Voo R2(lok} PXxe " Yoo Aa47k} R (200k) 3 (TYP) RES Vss a Unit (resistance: 0) Note: All ports other than PA3 are configured as normal input ports. Figure 2-1 Power Outage Backup Example 1 Waveforms during operation Figure 2-2 gives the waveforms relevant to the operation of the above circuit, There are three main states: (a) power-on reset sequence, (b) momentary break in main power supply, and (c) recovery from power outage backup state. ye TTA Vee rt Vo, y wy } / = Pxx V a \ RES 4 i | 2 ' a Vi Pxx VK ViL Pxx +. eT / Vi. RES y a | te Vo | Indelermnaa Sale Reset Normal operation x Reset X Norma? operation Kh - | Reset Normal cperalion v ~ a {a) Power-on reset sequence {hb} Momentary break In main power supply (1), {li} \ {b) Momentary break in main power supply (iii) HALT insteuction Vai RES a a ie \ Va Pxx * Ve ee HALT mode Norma: oparation Wipe ------ ---4h------+---- Normal operation } Recovery [ror HALT Ingt=.chon {3} ty from power oulage backup slate Note: V*TRon = V* level at which transistor switches on and off Figure 2-2 Waveforms Relevant to Operation of Circuit Example 1 No. 5117-34/39LC6529N, 6529F, 6529L Main circuit states a: Power-on reset sequence Once the power supply voltage has reached the proper level, the chip automatically resets and begins execution with the program counter set to O00,. Caution: This circuit does not reset the chip until the power supply voltage is within the range specified for Vpp:; So leaves the chip in an indeterminate state. Momentary break in main power supply i. If only the RES pin and none of the Pxx pins drops below the threshold level V,,, the chip resets and Tepeats the power-on reset sequence. ii. Ifthe RES pin and the Pxx pins remain above the threshold level V1,, the chip continues normal execution, iii. If both the RES pin and the Pxx pins drop below the threshold level Vj, the chip resets if two consecutive polls fail to detect a low at Pxx or, if a low is found, enters the HALT mode and then, because the power has been restored, leaves the HALT mode. Recovery from power outage backup state Since the power has been restored, the chip leaves the HALT mode. Design considerations a: Vt nse time and C2 The V* rise time must be approximately ten times the RC constant for the reset circuit, C2 x R, where R is the internal resistance (typ. 200 k). It must also be no longer than approximately 20 ms. R1 and Cl values R1 must be as small as possible; C1, as large as possible to provide the longest backup time. At the same time, however, R1 must be large enough such that the C1 charging current does not exceed the power supply capacity. R2 and R3 values Choose these to make the Pxx high levels equal to Vpp. R4 value Select R4 and thus the RC constant for C2 and R4 so that C2 discharges sometime in the interval between the point at which V* falls below V*7pon (turning off the transistor) and the point at which Pxx falls below Vy. (Otherwise, the chip will enter the HALT mode and then not respond to a reset.) R5 and R6 values Select R5 and R6 so that V+ when the reset circuit operates, switching on the transistor (that is, when R5 and R6 produce a Vpg of approximately 0.6 V) is at least the minimum operating voltage (Vpp) plus the Vp for diode D1. To provide a rapid reset once the power is restored, however, keep this voltage as small as possible while still satisfying these conditions. Calculating backup time From the time that the chip detects the power outage at Pxx until # executes the HALT instruction, the chip operates normally so drains relatively large amounts of current. C1 must therefore be large enough to provide backup power not only for the set's backup period, but for this transitional period as well. Software considerations a b: Assign signals so that PA3 is maintained high during standby operation. The software should double-check a standby request by polling twice. Example: BP1 AAA : Poll once BP1 AAA : Poll twice HALT : Begin standby operation AAA: : No. 5117-35/39LC6529N, 6529F, 6529L * Example 2 The second example distinguishes a power-on reset sequence from a reset trigger by a power failure. Circuit diagram Figure 2-3 gives the circuit diagram for this sample circuit. BI Creat v REG > yoov AC 1h Rl f50) Voo PXX* {SENSE} cz C1 F) Vss TR) th Unit (resistance: 9) Note: All ports other than PA3 are configured as normal input ports. Figure 2-3 Power Outage Backup Example 2 Waveforms during operation Figure 2-4 gives the waveforms relevant to the operation of the above circuit. There are two main states: (a) power-on reset sequence and (b) recovery from power outage backup state. Indeterminate stale Reset Normal oparation {a} Power on rasel saquence Pxx="L" Normal operation i} ie de------ rH = Reset Narinal operation / | (c) Recovery (rom power culage backup sialg HALT moda Pxx Is hight Note: V+. = V+ level at which transistor switches on and off VitRon | TRI TAON Figure 2-4 Waveforms Relevant to Operation of Circult Example 2 No. 5117-36/39LC6529N, 6529F, 6529L Main circuit states a: Power-on reset sequence The operation and points to watch are the same as for the first example, The only difference is that the software interprets a low at Pxx as indicating an initial reset. b: Switch to standby operation The chip polls Pxx and, if it is low, enters the HALT mode. ec: Recovery from power outage backup state Since the power has been restored, the chip leaves the HALT made. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage, Caution: If the power supply voltage Vpp drops below the Vy, level for Pxx during the outage, this recovery routine will subsequently find that Pax is low and execute the routine for an initial reset instead. Design considerations a: R2 and R3 values Make R2 much greater than R1 and choose R3 to limit TR2s Ip. b: R4 value Since there are no momentary outages, the value is not critical, but select R4 so that C2 quickly discharges. In all other respects, the same considerations apply as in Example 1. Software considerations a: Assign signals so that PA3 is maintained high during standby operation. b: The software should check for a standby request by polling once. Example: - BP1 AAA : Poll port HALT : Begin standby operation AAA: : * Example 3 The third example adds support for momentary power outages. Circuit diagram Figure 2-5 gives the circuit diagram for this sample circuit. ve La 1oov P D1 AC RI 1504 TR2 G1 ~ IF Tt Voo PRxe (SENSE) Voo F(200k) (TYP} AES ss Unit (resistance: 22) Note: All ports other than PA3 are configured as normal input ports. Figure 2-5 Power Outage Backup Example 3 No. 5117-37/99LC6529N, 6529F, 6529L Waveforms during operation Figure 2-5 gives the waveforms relevant to the operation of the above circuit. There are three main states: (a) power-on reset sequence, (b} momentary break in main power supply, and (c) recovery from power outage backup state. VITRION .t a = _ 4 an + Vin FES ve P | | j a Vv 1H PKX 1 rt uf ey | | vo vw ofl 4 V*TRION | MS Pall vie Pax Vt TA30M 4 { | 7 4 c ff to wo a Vu Pax 7 v ue | Ly Indeterminate slate Rasal _ Raesal Normal operon -+ Resal MI Normal opsralion (a) Power-on recet sequenes | (>) Momentary braak in inain he Pex is high Ve (a) Memantary break Prx is high Paox ig ow power supply (1), (li) HALT instruction (Prox is LOW) in main power supply {I} = | HALT mode Normal operation WA ee ----- eee eH ee --( Fase YF} Normal operalion -_C OC Oe ee (c) Recovary Irom power oulage, HALT instruction (Pxx Is LOW) backup slate Pxx is high Note: V*+7a,on = V* level at which transistor TR1 switches on and off V*TRgoNn = V* level at which transistor TR3 switches on and off Figure 2-5 Waveforms Relevant to Operation of Circult Example 3 ~ Main circuit states a: Power-on reset sequence The operation and points to watch are the same as for the second example. b: Momentary break in main power supply i. If only the RES pin and none of the Pxx pins drops below the threshold level Vj,, the chip resets. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage. ii. If the RES pin and the Pxx pins remain above the threshold level Vj, , the chip continues normal execution. iii. If both the RES pin and the Pxx pins drop below the threshold level Vy , the chip resets if two consecutive polls fail to detect a low at Pxx or, if a low is found, enters the HALT mode and then, because the power has been restored, leaves the HALT mode. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage. c: Recovery from power outage backup state The operation and points to watch are the same as for the second example. Design considerations a: R3 value This serves as the bias resistor for transistor TR2. b: R7 and R8 values Select these so that transistor TR3 switches on and off at approximately 1.5 V, In all other respects, the same considerations apply as in Example 1. Software considerations The same considerations apply as in Example 1. No. 5117-38/39LC6529N, 6529F, 6529L B No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Mi Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and alt damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. @ Information {including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. No. 5117-39/39