LTC2324-12 Quad, 12-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC Description Features 2Msps/Ch Throughput Rate nn Four Simultaneously Sampling Channels nn Guaranteed 12-Bit, No Missing Codes nn 8V P-P Differential Inputs with Wide Input Common Mode Range nn 78dB SNR (Typ) at f = 500kHz IN nn -88dB THD (Typ) at f = 500kHz IN nn Guaranteed Operation to 125C nn Single 3.3V or 5V Supply nn Low Drift (20ppm/C Max) 2.048V or 4.096V Internal Reference nn 1.8V to 2.5V I/O Voltages nn CMOS or LVDS SPI-Compatible Serial I/O nn Power Dissipation 40mW/Ch (Typ) nn Small 52-Lead (7mm x 8mm) QFN Package The LTC(R)2324-12 is a low noise, high speed quad 12bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC232412 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2324-12 achieves 0.5LSB INL typical, no missing codes at 12 bits and 78dB SNR. nn The LTC2324-12 has an onboard low drift (20ppm/C max) 2.048V or 4.096V temperature-compensated reference. The LTC2324-12 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 2Msps per channel throughput with no latency makes the LTC2324-12 ideally suited for a wide variety of high speed applications. The LTC2324-12 dissipates only 40mW per channel and offers nap and sleep modes to reduce the power consumption to 26W for further power savings during inactive periods. Applications High Speed Data Acquisition Systems Communications nn Optical Networking nn Multiphase Motor Control nn nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective owners. Typical Application TRUE DIFFERENTIAL INPUTS NO CONFIGURATION REQUIRED 10F 32k Point FFT fSMPL = 2Msps, fIN = 500kHz 1F 3.3V OR 5V 1.8V TO 2.5V 0 IN+, IN - ARBITRARY 0V VDD DIFFERENTIAL 0V GND AIN1+ S/H AIN1- 12-BIT + SIGN SAR ADC AIN2+ S/H AIN2- 12-BIT + SIGN SAR ADC LTC2324-12 VDD 0V BIPOLAR VDD UNIPOLAR 0V AIN3+ S/H AIN3- 12-BIT + SIGN SAR ADC AIN4+ S/H AIN4- 12-BIT + SIGN SAR ADC REF FOUR SIMULTANEOUS SAMPLING CHANNELS REFOUT1 1F REFOUT2 10F 10F GND OVDD CMOS/LVDS SDR/DDR REFBUFEN AMPLITUDE (dBFS) VDD VDD SDO1 SDO2 SDO3 SDO4 CLKOUT SCK CNV SAMPLE CLOCK SNR = 78.5dB THD = -87.8dB -20 SINAD = 78.2dB SFDR = 95.9dB -40 -60 -80 -100 -120 -140 REFOUT3 REFOUT4 10F 10F 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 1 232412 TA01b 232412 TA01a 232412fa For more information www.linear.com/LTC2324-12 1 LTC2324-12 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) SCK/SCK+ DNC/SCK- REFBUFEN VDD REFOUT4 GND NC NC GND NC NC VDD TOP VIEW 52 51 50 49 48 47 46 45 44 43 42 41 AIN4- 1 40 DNC/SDOD- AIN4+ 2 39 SDO4/SDOD+ GND 3 38 GND AIN3- 4 37 OVDD AIN3+ 5 36 DNC/SDOC- 35 SDO3/SDOC+ REFOUT3 6 GND 7 34 CLKOUTEN/CLKOUT - 53 GND REF 8 33 CLKOUT/CLKOUT+ 32 GND REFOUT2 9 AIN2- 10 31 OVDD AIN2+ 11 30 DNC/SDOB- GND 12 29 SDO2/SDOB+ AIN1- 13 28 DNC/SDOA- + 27 SDO1/SDOA+ AIN1 14 GND CMOS/LVDS CNV SDR/DDR REFOUT1 VDD NC NC GND NC NC 15 16 17 18 19 20 21 22 23 24 25 26 VDD Supply Voltage (VDD)...................................................6V Supply Voltage (OVDD).................................................3V Analog Input Voltage AIN+, AIN - (Note 3).................... -0.3V to (VDD + 0.3V) REFOUT1,2,3,4........................ .-0.3V to (VDD + 0.3V) CNV........................................ -0.3V to (OVDD + 0.3V) Digital Input Voltage (Note 3)........................... (GND - 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)........................... (GND - 0.3V) to (OVDD + 0.3V) Operating Temperature Range LTC2324C................................................. 0C to 70C LTC2324I..............................................-40C to 85C LTC2324H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C UKG PACKAGE 52-LEAD (7mm x 8mm) PLASTIC QFN TJMAX = 150C, JA = 31C/W, JC = 2C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB Order Information http://www.linear.com/product/LTC2324-12#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2324CUKG-12#PBF LTC2324CUKG-12#TRPBF LTC2324UKG-12 52-Lead (7mm x 8mm) Plastic QFN 0C to 70C LTC2324IUKG-12#PBF LTC2324IUKG-12#TRPBF LTC2324UKG-12 52-Lead (7mm x 8mm) Plastic QFN -40C to 85C LTC2324HUKG-12#PBF LTC2324HUKG-12#TRPBF LTC2324UKG-12 52-Lead (7mm x 8mm) Plastic QFN -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL VIN+ VIN- VIN+ - VIN- VCM IIN CIN CMRR VIHCNV VILCNV IINCNV PARAMETER Absolute Input Range (AIN+ to AIN-) Absolute Input Range (AIN+ to AIN-) Input Differential Voltage Range Common Mode Input Range Analog Input DC Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio CNV High Level Input Voltage CNV Low Level Input Voltage CNV Input Current CONDITIONS (Note 5) (Note 5) VIN = VIN+ - VIN- VCM = (VIN+ - VIN-)/2 l l l l l MIN 0 0 -REFOUT1,2,3,4 0 -1 TYP MAX VDD VDD REFOUT1,2,3,4 VDD 1 UNITS V V V V A pF dB V V A 10 102 fIN = 500kHz l 1.5 0.5 10 l l -10 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN MAX UNITS Resolution l 12 Bits No Missing Codes l 12 Bits l -1 0 1 LSB l -0.25 0.1 0.25 LSB l -0.2 0 0.2 Transition Noise INL Integral Linearity Error DNL Differential Linearity Error BZE Bipolar Zero-Scale Error 0.2 (Note 6) (Note 7) Bipolar Zero-Scale Error Drift FSE TYP LSBRMS 0.01 Bipolar Full-Scale Error VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) (Note 7) Bipolar Full-Scale Error Drift VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) l -0.5 0 LSB LSB/C 0.5 15 LSB ppm/C Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS (Notes 4, 8). SYMBOL PARAMETER CONDITIONS SINAD Signal-to-(Noise + Distortion) Ratio fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference SNR Signal-to-Noise Ratio MIN TYP l 74 78 dB 78 dB l 75 78.5 dB 78.5 dB fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference THD Total Harmonic Distortion fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference -88 l fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference SFDR dB dB 93 dB dB -3dB Input Bandwidth 55 MHz Aperture Delay 500 ps Aperture Delay Matching 500 ps fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference Aperture Jitter Transient Response Full-Scale Step l 77.5 -77.5 UNITS 93 Spurious Free Dynamic Range fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference -88 MAX 1 psRMS 3 ns 232412fa For more information www.linear.com/LTC2324-12 3 LTC2324-12 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS VREFOUT1,2,3,4 Internal Reference Output Voltage 4.75V < VDD < 5.25V 3.13V < VDD < 3.47V l l VREF Temperature Coefficient (Note 14) l MIN TYP MAX UNITS 4.078 2.034 4.096 2.048 4.115 2.064 V V 3 20 REFOUT1,2,3,4 Output Impedance IREFOUT1,2,3,4 ppm/C 0.25 VREFOUT1,2,3,4 Line Regulation 4.75V < VDD < 5.25V 0.3 mV/V External Reference Current REFBUFEN = 0V REFOUT1,2,3,4 = 4.096V REFOUT1,2,3,4 = 2.048V (Notes 9, 10) 385 204 A A Digital Inputs And Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Digital Inputs and Outputs CMOS/LVDS = GND VIH High Level Input Voltage l VIL Low Level Input Voltage l IIN Digital Input Current CIN Digital Input Capacitance VOH High Level Output Voltage IO = -500A l VOL Low Level Output Voltage IO = 500A l IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l ISOURCE Output Source Current VOUT = 0V -10 mA ISINK Output Sink Current VOUT = OVDD 10 mA VIN = 0V to OVDD l 0.8 * OVDD V -10 0.2 * OVDD V 10 A 5 pF OVDD - 0.2 V -10 0.2 V 10 A LVDS Digital Inputs and Outputs CMOS/LVDS = OVDD VID LVDS Differential Input Voltage 100 Differential Termination OVDD = 2.5V l 240 600 mV VIS LVDS Common Mode Input Voltage 100 Differential Termination OVDD = 2.5V l 1 1.45 V VOD LVDS Differential Output Voltage 100 Differential Termination OVDD = 2.5V l 220 350 600 mV VOS LVDS Common Mode Output Voltage 100 Differential Termination OVDD = 2.5V l 0.85 1.2 1.4 V VOD_LP Low Power LVDS Differential Output Voltage 100 Differential Termination OVDD = 2.5V l 100 200 350 mV VOS_LP Low Power LVDS Common Mode Output Voltage 100 Differential Termination OVDD = 2.5V l 0.85 1.2 1.4 V 4 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS VDD Supply Voltage 5V Operation 3.3V Operation l l MIN IVDD Supply Current 2Msps Sample Rate (AIN+ = AIN- = 0V) l TYP 4.75 3.13 31 MAX UNITS 5.25 3.47 V V 36.5 mA 2.63 V CMOS I/O Mode CMOS/LVDS = GND OVDD Supply Voltage IOVDD Supply Current 2Msps Sample Rate (CL = 5pF) l 4.4 8 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 A PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate Nap Mode Sleep Mode l l l 102 18 20 130 21 288 mW mW W PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate Nap Mode Sleep Mode l l l 162 27 30 202 32 424 mW mW W 2.63 V l 1.71 LVDS I/O Mode CMOS/LVDS = OVDD, OVDD = 2.5V OVDD Supply Voltage IOVDD Supply Current 1.5Msps Sample Rate (CL = 5pF, RL = 100) l 26 31.5 mA INAP Nap Mode Current Conversion Done (IVDD) l 5.3 6.4 mA ISLEEP Sleep Mode Current Sleep Mode (IVDD + IOVDD) l 20 90 A PD_3.3V Power Dissipation VDD = 3.3V, 2Msps Sample Rate Nap Mode Sleep Mode l l l 151 52 80 185 56 288 mW mW W PD_5V Power Dissipation VDD = 5V, 2Msps Sample Rate Nap Mode Sleep Mode l l l 214 52 30 262 66 424 mW mW W l 2.37 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER fSMPL Maximum Sampling Frequency CONDITIONS MIN TYP tCYC Time Between Conversions tCONV tCNVH tACQUISITION Sampling Aperture (Note 11) tACQUISITION = tCYC - tCONV 250 ns tWAKE REFOUT1,2,3,4 Wake-Up Time CREFOUT1,2,3,4 = 10F 50 ms l (Note 11) tCYC = tCNVH + tCONV + tREADOUT MAX UNITS 2 Msps l 0.5 Conversion Time l 1000 s 220 ns CNV High Time l 30 ns CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND tSCK SCK Period (Note 13) l 9.1 ns tSCKH tSCKL SCK High Time l 4.1 ns SCK Low Time l 4.1 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT CL = 5pF (Note 12) l 0 1.5 ns (Note 12) l tDSCKCLKOUT SCK to CLKOUT Delay 2 4.5 ns 232412fa For more information www.linear.com/LTC2324-12 5 LTC2324-12 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDCNVSDOZ Bus Relinquish Time After CNV (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV (Note 11) l 0 ns CMOS I/O Mode, DDR CMOS/LVDS = GND, SDR/ DDR = OVDD tSCK SCK Period l 18.2 ns tSCKH SCK High Time l 8.2 ns tSCKL SCK Low Time l 8.2 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4.5 ns tDCNVSDOZ Bus Relinquish Time After CNV (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV (Note 11) l 0 ns LVDS I/O Mode, SDR CMOS/LVDS = OVDD, SDR/DDR = GND tSCK SCK Period l 3.3 ns tSCKH SCK High Time l 1.5 ns tSCKL SCK Low Time l 1.5 ns tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV (Note 11) l 0 ns LVDS I/O Mode, DDR CMOS/LVDS = OVDD, SDR/DDR = OVDD = 2.5V tSCK SCK Period l 6.6 ns tSCKH SCK High Time l 3 ns tSCKL SCK Low Time l 3 ns tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT CL = 5pF (Note 12) l 0 1.5 ns tDSCKCLKOUT SCK to CLKOUT Delay (Note 12) l 2 4 ns tDSCKHCNVH SCK Delay Time to CNV (Note 11) l 0 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground, or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground, or above VDD or OVDD, without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 2MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from -0.5LSB when the output code flickers between 0 0000 0000 0000 and 1 1111 1111 1111. Full-scale bipolar error is the worst-case of -FS or +FS 6 ns untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale 4.096V input with REF = 4.096V. Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer must be turned off by setting REFBUFEN = 0V. Note 10: fSMPL = 2MHz, IREFOUT1,2,3,4 varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V. Note 13: tSCK of 9.1ns allows a shift clock frequency up to 110MHz for rising edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 15: CNV is driven from a low jitter digital source, typically at OVDD logic levels. 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 ADC Timing Characteristics 0.8 * OVDD tWIDTH 0.2 * OVDD tDELAY tDELAY 0.8 * OVDD 0.8 * OVDD 0.2 * OVDD 0.2 * OVDD 50% 50% 232412 F01 Figure 1. Voltage Levels for Timing Specifications 232412fa For more information www.linear.com/LTC2324-12 7 LTC2324-12 Typical Performance Characteristics = 4.096V, fSMPL = 2Msps, unless otherwise noted. Integral Nonlinearity vs Output Code TA = 25C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 Differential Nonlinearity vs Output Code 1.0 DC Histogram 250000 1.0 225000 200000 0.5 0 175000 COUNTS DNL ERROR (LSB) INL ERROR (LSB) 0.5 = 0.25 0 150000 125000 100000 75000 -0.5 -0.5 -1.0 -4096 -1.0 -4096 50000 25000 -2048 0 2048 OUTPUT CODE 4096 -2048 0 2048 OUTPUT CODE 232412 G01 -80 -100 -120 -140 80.0 -80 79.6 -84 79.2 78.8 SNR 78.4 SINAD 78.0 77.6 77.2 76.8 76.4 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 1 76.0 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 79 THD -89 -92 -95 HD3 -98 -101 -104 HD2 HD3 -100 -104 HD2 -108 -112 0 f = 500kHz SNR 78 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 76 75 74 73 72 -110 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 INPUT COMMON MODE (V) 70 0.5 1 32k Point FFT, IMD, fSMPL = 2Msps, AIN+ = 500kHz, AIN- = 1.3MHz THD = 84dB VCM = 800kHz, 4VP-P -20 SINAD 77 71 8 -96 232412 G06 SNR, SINAD vs Reference Voltage, fIN = 500kHz -107 232412 G07 10 THD -92 -120 1 AMPLITUDE (dBFS) -86 80 f = 500kHz SNR, SINAD LEVEL (dBFS) THD, HARMONICS LEVEL (dBFS) -83 -88 232412 G05 THD, Harmonics vs Input Common Mode 8 -116 232412 G04 -80 6 THD, Harmonics vs Input Frequency (1kHz to 1MHz) SNR, SINAD vs Input Frequency (1kHz to 1MHz) -60 4 232412 G03 THD, HARMONICS LEVEL (dBFS) 32k Point FFT, fSMPL = 2Msps, fIN = 500kHz SNR = 78.5dB THD = -87.8dB -20 SINAD = 78.2dB SFDR = 95.9dB -40 0 2 CODE 232412 G02 SNR, SINAD LEVEL (dBFS) AMPLITUDE (dBFS) 0 0 -10 -8 -6 -4 -2 4096 -40 -60 -80 -100 -120 1 1.5 2 2.5 3 3.5 VREFOUT(V) 4 4.5 5 232412 G08 -140 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 1 232412 G09 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Typical Performance Characteristics = 4.096V, fSMPL = 2Msps, unless otherwise noted. CMRR vs Input Frequency 120 Step Response (Large Signal Settling) Crosstalk vs Input Frequency -105 VCM = 4VP-P 4096 -107 -109 104 96 -111 -113 -115 -117 -119 2048 1024 -121 88 4.096V RANGE IN+ = 2MHz SQUARE WAVE IN- = 0V 3072 OUTPUT CODE (LSB) CROSSTALK (dB) 112 CMRR (dB) TA = 25C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 0 -123 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 1 -125 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 232412 G10 232412 G11 Step Response (Fine Settling) 400 4.096V RANGE IN+ = 2MHz SQUARE WAVE IN- = 0V 25 0 -25 REF Output vs Temperature 1.00 REFBUFEN = 0V (EXT REF BUF OVERDRIVING REF BUF) 0.50 300 VREFOUT1,2,3,4 = 4.096V 200 100 VREFOUT1,2,3,4 = 2.048V -50 -20 -10 0 10 20 30 40 50 60 70 80 90 SETTLING TIME (ns) 0 0 0.5 1 1.5 SAMPLE FREQUENCY (Msps) 232412 G13 -0.50 -1.00 -2.00 -2.50 2 -3.00 -55 -35 -15 OVDD CURRENT CMOS (mA) SUPPLY CURRENT (mA) 5 30 VDD = 5V 25 VDD = 3.3V 20 OVDD Current vs SCK Frequency, CLOAD = 10pF FULL SCALE SINUSOIDAL INPUT 32 LVDS 30 28 4 26 CMOS(2.5V) 24 3 22 20 2 CMOS(1.8V) 18 16 1 LOW POWER LVDS -0.250 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 232412 G16 15 0 0.4 0.8 1.2 1.6 SAMPLE FREQUENCY (Msps) 2 232412 G17 0 0 22 44 66 88 SCK FREQUENCY (MHz) OVDD CURRENT LVDS (mA) -0.125 5 25 45 65 85 105 125 TEMPERATURE (C) 232412 G15 35 0.250 0 VDD = 5V -1.50 Supply Current vs Sample Frequency 0.125 VDD = 3.3V 0 232412 G14 Offset Error vs Temperature LSB 232412 G12 External Reference Supply Current vs Sample Frequency SUPPLY CURRENT (A) DEVIATION FROM FINAL VALUE (LSB) 50 -1024 -20 -10 0 10 20 30 40 50 60 70 80 90 SETTLING TIME (ns) 1 REF OUTPUT ERROR (mV) 80 14 12 110 232412 G18 232412fa For more information www.linear.com/LTC2324-12 9 LTC2324-12 Pin Functions Pins that are the same for all digital I/O Modes AIN4+, AIN4- (Pins 2, 1): Analog Differential Input Pins. Full-scale range (AIN4+ - AIN4-) is REFOUT4 voltage. These pins can be driven from VDD to GND. GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground. These pins and exposed pad (Pin 53) must be tied directly to a solid ground plane. AIN3+, AIN3- (Pins 5, 4): Analog Differential Input Pins. Full-scale range (AIN3+ - AIN3-) is REFOUT3 voltage. These pins can be driven from VDD to GND. REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to 5V. REF (Pin 8): Common 4.096V reference output. Decouple to GND with a 1F low ESR ceramic capacitor. May be overdriven with a single external reference to establish a common reference for ADC cores 1 through 4. REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to 5V. AIN2+, AIN2- (Pins 11, 10): Analog Differential Input Pins. Full-scale range (AIN2+ - AIN2-) is REFOUT2 voltage. These pins can be driven from VDD to GND. AIN1+, AIN1- (Pins 14, 13): Analog Differential Input Pins. Full-scale range (AIN1+ - AIN1-) is REFOUT1 voltage. These pins can be driven from VDD to GND. VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to GND with a 10F ceramic capacitor and a 0.1F ceramic capacitor close to the part. The VDD pins should be shorted together and driven from the same supply. 10 REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to 5V. SDR/DDR (Pin 23): Double Data Rate Input. Controls the frequency of SCK and CLKOUT. Tie to GND for the falling edge of SCK to shift each serial data output (Single Data Rate, SDR). Tie to OVDD to shift serial data output on each edge of SCK (Double Data Rate, DDR). CLKOUT will be a delayed version of SCK for both pin states. CNV (Pin 24): Convert Input. This pin, when high, defines the acquisition phase. When this pin is driven low, the conversion phase is initiated and output data is clocked out. This input must be driven at OVDD levels with a low jitter pulse. This pin is unaffected by the CMOS/LVDS pin. CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin to enable CMOS mode, tie to OVDD to enable LVDS mode. Float this pin to enable low power LVDS mode. OVDD (Pins 31, 37): I/O Interface Digital Power. The range of OVDD is 1.71V to 2.63V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or 2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38) with 0.1F capacitors. REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie to VDD when using the internal reference. Tie to ground to disable the internal REFOUT1-4 buffers for use with external voltage references. This pin has a 500k internal pull-up to VDD. REFOUT4 (Pin 45): Reference Buffer 4 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the pin with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to 5V. Exposed Pad (Pin 53): Ground. Solder this pad to ground. 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Pin Functions CMOS data output option (CMOS/LVDS = low) SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel 1. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDO1 in SDR mode, 13 SCK edges in DDR mode. SDO2 (Pin 29): CMOS Serial Data Output for ADC Channel 2. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDO2 in SDR mode, 13 SCK edges in DDR mode. SDO3 (Pin 35): CMOS Serial Data Output for ADC Channel 3. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDO3 in SDR mode, 13 SCK edges in DDR mode. SDO4 (Pin 39): CMOS Serial Data Output for ADC Channel 4. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDO4 in SDR mode, 13 SCK edges in DDR mode. CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch the SDO output at the receiver (FPGA). The logic level is determined by OVDD. This pin echoes the input at SCK with a small delay. CLKOUTEN (Pin 34): CLKOUT can be disabled by tying Pin 34 to OVDD for a small power savings. If CLKOUT is used, ground this pin. SCK (Pin 41): Serial Data Clock Input. The falling edge of this clock shifts the conversion result MSB first onto the SDO pins in SDR mode (DDR = LOW). In DDR mode (SDR/DDR = HIGH) each edge of this clock shifts the conversion result MSB first onto the SDO pins. The logic level is determined by OVDD. DNC (Pins 28, 30, 36, 40, 42): In CMOS mode, do not connect this pin. LVDS data output option (CMOS/LVDS = high or FLOAT) SDOA+, SDOA- (Pins 27, 28): LVDS Serial Data Output for ADC Channel 1. The conversion result is shifted CH1 MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDOA in SDR mode, 13 SCK edges in DDR mode. Terminate with a 100 resistor at the receiver (FPGA). SDOB+, SDOB- (Pins 29, 30): LVDS Serial Data Output for ADC Channel 2. The conversion result is shifted CH2 MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDOB in SDR mode, 13 SCK edges in DDR mode. Terminate with a 100 resistor at the receiver (FPGA). CLKOUT+, CLKOUT- (Pins 33, 34): Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch the SDO output at the receiver. These pins echo the input at SCK with a small delay. These pins must be differentially terminated by an external 100 resistor at the receiver (FPGA). SDOC+, SDOC- (Pins 35, 36): LVDS Serial Data Output for ADC channel 3. The conversion result is shifted CH3 MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDOA in SDR mode, 13 SCK edges in DDR mode. Terminate with a 100 resistor at the receiver (FPGA). SDOD+, SDOD- (Pins 39, 40): LVDS Serial Data Output for ADC Channel 4. The conversion result is shifted CH4 MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR mode. 13 SCK edges are required for 13-bit conversion data to be read from SDOA in SDR mode, 13 SCK edges in DDR mode. Terminate with a 100 resistor at the receiver (FPGA). SCK+, SCK- (Pins 41, 42): Serial Data Clock Input. The falling edge of this clock shifts the conversion result MSB first onto the SDO pins in SDR mode (SDR/DDR = LOW). In DDR mode (SDR/DDR = HIGH) each edge of this clock shifts the conversion result MSB first onto the SDO pins. These pins must be differentially terminated by an external 100 resistor at the receiver (ADC). 232412fa For more information www.linear.com/LTC2324-12 11 LTC2324-12 Functional Block Diagram CMOS IO Mode VDD (15, 21, 44, 52) 24 CNV 14 13 AIN1+ SDO1 + S/H - AIN1- 12-BIT+SIGN SAR ADC REF 11 10 AIN2+ 42 SCK NC NC REFOUT1 SDO2 12-BIT+SIGN SAR ADC REF 41 CMOS I/O x1 + S/H - AIN2- GND (3, 7, 12, 18, 26, 32, 38, 46, 49, 53) CMOS I/O NC REFOUT2 x1 OUTPUT CLOCK DRIVER CMOS RECEIVERS CLKOUT CLKOUTEN 27 28 22 29 30 9 33 34 SDR/DDR 23 5 4 AIN3+ SDO3 + S/H - AIN3- 12-BIT+SIGN SAR ADC REF 2 1 AIN4+ SDO4 12-BIT+SIGN SAR ADC REF 8 REF 250A NC REFOUT3 x1 + S/H - AIN4- CMOS I/O x1.7 x3.4 CMOS I/O x1 1.2V INT REF NC REFOUT4 35 36 6 39 40 45 OVDD (31, 37) REFBUFEN 43 CMOS/LVDS 25 232412 BDa 12 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Functional Block Diagram LVDS IO Mode VDD (15, 21, 44, 52) 24 CNV 14 13 AIN1+ + S/H - AIN1- 12-BIT+SIGN SAR ADC REF 11 10 AIN2+ 41 42 SCK+ SCK- SDOA+ SDOA- REFOUT1 12-BIT+SIGN SAR ADC REF LVDS I/O x1 + S/H - AIN2- GND (3, 7, 12, 18, 26, 32, 38, 46, 49, 53) LVDS I/O SDOB+ SDOB- REFOUT2 x1 OUTPUT CLOCK DRIVER LVDS RECEIVERS CLKOUT+ CLKOUT- 27 28 22 29 30 9 33 34 SDR/DDR 23 5 4 AIN3+ + S/H - AIN3- 12-BIT+SIGN SAR ADC REF 2 1 AIN4+ 12-BIT+SIGN SAR ADC REF 8 REF 250A x1.7 x3.4 SDOC+ SDOC- REFOUT3 x1 + S/H - AIN4- LVDS I/O LVDS I/O x1 1.2V INT REF SDOD+ SDOD- REFOUT4 35 36 6 39 40 45 OVDD (31, 37) REFBUFEN 43 CMOS/LVDS 25 232412 BDb 232412fa For more information www.linear.com/LTC2324-12 13 LTC2324-12 Timing Diagram SDR Mode, CMOS (Reading 1 Channel per SDO) SAMPLE N CNV SAMPLE N+1 CONVERT ACQUIRE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK CLKOUT SDO1 Hi-Z Hi-Z Hi-Z DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 D12 CHANNEL 1 CONVERSION N SDO4 Hi-Z DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 Hi-Z CHANNEL 2 CONVERSION N D3 D2 D1 D0 0 0 0 D12 CHANNEL 4 CONVERSION N Hi-Z CHANNEL 1 CONVERSION N 232412 TD01 DDR Mode, CMOS (Reading 1 Channel per SDO) CMOS DDR Mode SAMPLE N CNV CONVERT SAMPLE N+1 ACQUIRE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK CLKOUT SDO1 Hi-Z Hi-Z Hi-Z DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 CHANNEL 1 CONVERSION N SDO4 Hi-Z DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D12 Hi-Z CHANNEL 2 CONVERSION N D2 D1 CHANNEL 4 CONVERSION N D0 0 0 0 D12 Hi-Z CHANNEL 1 CONVERSION N 232412 TD02 14 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Timing Diagram SDR Mode, LVDS (Reading 1 Channel per SDO Pair) SAMPLE N CNV SAMPLE N+1 CONVERT ACQUIRE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SCK CLKOUT SDOA DONT CARE D12 D11 D10 D9 CHANNEL 1 CONVERSION N SDOD DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D12 CHANNEL 2 CONVERSION N D2 D1 D0 0 0 0 CHANNEL 4 CONVERSION N D12 CHANNEL 1 CONVERSION N 232412 TD03 DDR Mode, LVDS (Reading 1 Channel per SDO Pair) SAMPLE N CNV SAMPLE N+1 ACQUIRE CONVERT 1 2 3 4 5 6 7 8 9 D12 D11 D10 D9 D8 D7 D6 D5 D4 10 11 12 13 14 15 16 SCK CLKOUT SDOA DONT CARE D3 D2 D1 D0 0 0 0 CHANNEL 1 CONVERSION N SDOD DONT CARE D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D12 CHANNEL 2 CONVERSION N D2 D1 CHANNEL 4 CONVERSION N D0 0 0 0 D12 CHANNEL 1 CONVERSION N 232412 TD04 232412fa For more information www.linear.com/LTC2324-12 15 LTC2324-12 Applications Information OVERVIEW The LTC2324-12 is a low noise, high speed 13-bit successive approximation register (SAR) ADC with differential inputs and a wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2324-12 has a 4VP-P or 8VP-P differential input range, making it ideal for applications which require a wide dynamic range. The LTC2324-12 achieves 0.5LSB INL typical, no missing codes at 12 bits and 78dB SNR. The LTC2324-12 has an onboard reference buffer and low drift (20ppm/C max) 4.096V temperature-compensated reference. The LTC2324-12 also has a high speed SPIcompatible serial interface that supports CMOS or LVDS. The fast 2Msps per channel throughput with no-cycle latency makes the LTC2324-12 ideally suited for a wide variety of high speed applications. The LTC2324-12 dissipates only 40mW per channel. Nap and sleep modes are also provided to reduce the power consumption of the LTC2324-12 during inactive periods for further power savings. CONVERTER OPERATION The LTC2324-12 operates in two phases. During the acquisition phase, the sample capacitor is connected to the analog input pins AIN+ and AIN - to sample the differential analog input voltage, as shown in Figure 3. A falling edge on the CNV pin initiates a conversion. During the conversion phase, the 13-bit CDAC is sequenced through a successive approximation algorithm effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g., VREFOUT/2, VREFOUT/4 ... VREFOUT/32768) using a differential comparator. At the end of conversion, a CDAC output approximates the sampled analog input. The ADC control logic then prepares the 12-bit digital output code for serial transfer. TRANSFER FUNCTION The LTC2324-12 digitizes the full-scale voltage of 2 x REFOUT1,2,3,4 into 213 levels, resulting in an LSB size of 1mV with REF = 4.096V. The ideal transfer function is shown in Figure 2. The output data is in 2's complement format. Analog Input The differential inputs of the LTC2324-12 provide great flexibility to convert a wide variety of analog signals with no configuration required. The LTC2324-12 digitizes the difference voltage between the AIN+ and AIN - pins while supporting a wide common mode input range. The analog input signals can have an arbitrary relationship to each other, provided that they remain between VDD and GND. The LTC2324-12 can also digitize more limited classes of analog input signals such as pseudo-differential unipolar/ bipolar and fully differential with no configuration required. The analog inputs of the LTC2324-12 can be modeled by the equivalent circuit shown in Figure 3. The backto-back diodes at the inputs form clamps that provide ESD protection. In the acquisition phase, 10pF (CIN) from the sampling capacitor in series with approximately OUTPUT CODE (TWO'S COMPLEMENT) VDD 0 1111 1111 1111 0 1111 1111 1110 RON 15 AIN+ CIN 10pF 0 0000 0000 0001 0 0000 0000 0000 BIAS VOLTAGE VDD 1 1111 1111 1111 1LSB = 2 * REFOUT 8192 1 0000 0000 0001 1 0000 0000 0000 -REFOUT -1 0 1 LSB LSB INPUT VOLTAGE (V) REFOUT - 1LSB 232412 F02 AIN- RON 15 CIN 10pF 232412 F03 Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2324-12 Figure 2. LTC2324-12 Transfer Function 16 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information 15 (RON) from the on-resistance of the sampling switch is connected to the input. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC sampler. The inputs of the ADC core draw a small current spike while charging the CIN capacitors during acquisition. mode input range relaxes the accuracy requirements of any signal conditioning circuits prior to the analog inputs. Pseudo-Differential Bipolar Input Range The pseudo-differential bipolar configuration represents driving one of the analog inputs at a fixed voltage, typically VREF /2, and applying a signal to the other AIN pin. In this case the analog input swings symmetrically around the fixed input yielding bipolar two's complement output codes with an ADC span of half of full-scale. This configuration is illustrated in Figure 4, and the corresponding transfer function in Figure 5. The fixed analog input pin need not be set at VREF /2, but at some point within the VDD rails allowing the alternate input to swing symmetrically around this voltage. If the input signal (AIN+ - AIN -) swings beyond REFOUT1,2,3,4/2, valid codes will be generated by the ADC and must be clamped by the user, if necessary. Single-Ended Signals Single-ended signals can be directly digitized by the LTC2324-12. These signals should be sensed pseudodifferentially for improved common mode rejection. By connecting the reference signal (e.g., ground sense) of the main analog signal to the other AIN pin, any noise or disturbance common to the two signals will be rejected by the high CMRR of the ADC. The LTC2324-12 flexibility handles both pseudo-differential unipolar and bipolar signals, with no configuration required. The wide common VREF 0V LT1819 VREF + - 0V LTC2324-12 25 AIN1+ REFOUT1 VREF REF 220pF 10k VREF /2 10k 1F + - 25 VREF /2 AIN1- SDO1 CLKOUT SCK ONLY CHANNEL 1 SHOWN FOR CLARITY 10F 1F TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) 232412 F04 Figure 4. Pseudo-Differential Bipolar Application Circuit ADC CODE (2's COMPLEMENT) 4095 2047 -VREF -VREF /2 -2048 -4096 0 VREF /2 VREF AIN (AIN+ - AIN-) DOTTED REGIONS AVAILABLE 232412 F05 Figure 5. Pseudo-Differential Bipolar Transfer Function 232412fa For more information www.linear.com/LTC2324-12 17 LTC2324-12 Applications Information Pseudo-Differential Unipolar Input Range The pseudo-differential unipolar configuration represents driving one of the analog inputs at ground and applying a signal to the other AIN pin. In this case, the analog input swings between ground and VREF yielding unipolar two's complement output codes with an ADC span of half of full-scale. This configuration is illustrated in Figure 6, and the corresponding transfer function in Figure 7. If the input signal (AIN+ - AIN-) swings negative, valid codes will be generated by the ADC and must be clamped by the user, if necessary. A possible variant of this mode would be to tie AIN+ to ground and drive AIN- between ground and VREF yielding a code span illustrated by the dotted line in Figure 7. VREF 0V LT1818 VREF + - 0V 25 AIN1+ REFOUT1 REF - AIN1 SDO1 CLKOUT SCK 10F 1F TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) 232412 F06 Figure 6. Pseudo-Differential Unipolar Application Circuit ADC CODE (2's COMPLEMENT) 4095 2047 -2048 -4096 0 VREF /2 VREF AIN (AIN+ - AIN-) 200 VREF /2 LT1819 + - VREF + - VREF 0V 0V 232412 F08 Figure 8. Single-Ended to Differential Driver Fully-Differential Inputs To achieve the best distortion performance of the LTC232412, we recommend driving a fully-differential signal through LT1819 amplifiers configured as two unity-gain buffers, as shown in Figure 9. This circuit achieves the full data sheet THD specification of -88dB at input frequencies up to 500kHz. A fully-differential input signal can span the maximum full-scale of the ADC, up to REFOUT1,2,3,4. The common mode input voltage can span the entire supply range up to VDD, limited by the input signal swing. The fully-differential configuration is illustrated in Figure 10, with the corresponding transfer function illustrated in Figure 11. DOTTED REGIONS AVAILABLE BUT UNUSED 232412 F07 Figure 7. Pseudo-Differential Unipolar Transfer Function Single-Ended-to-Differential Conversion While single-ended signals can be directly digitized as previously discussed, single-ended to differential conversion circuits may also be used when higher dynamic range is desired. By producing a differential signal at the inputs of the LTC2324-12, the signal swing presented to the ADC is maximized, thus increasing the achievable SNR. 18 0V 200 25 -VREF /2 VREF LTC2324-12 220pF -VREF The LT(R)1819 high speed dual operational amplifier is recommended for performing single-ended-to-differential conversions, as shown in Figure 8. In this case, the first amplifier is configured as a unity-gain buffer and the single-ended input signal directly drives the high impedance input of this amplifier. VREF 0V VREF 0V LT1819 + - VREF + - VREF 0V 0V 232412 F09 Figure 9. LT1819 Buffering a Fully-Differential Signal Source 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information VREF 0V LT1819 VREF + - 0V LTC2324-12 25 AIN1+ REFOUT1 REF 220pF VREF 0V 10F 1F VREF + - 0V 25 AIN1- SDO1 CLKOUT SCK TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) ONLY CHANNEL 1 SHOWN FOR CLARITY 232412 F10 Figure 10. Fully-Differential Application Circuit ADC CODE (2's COMPLEMENT) 4095 2047 -VREF -VREF /2 0 VREF /2 VREF AIN (AINn + - AINn -) -2048 232412 F11 -4096 Figure 11. Fully-Differential Transfer Function INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2324-12 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike when during acquisition. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2324-12. The amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC inputs, which draw a small current spike during acquisition. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. The simple 1-pole RC lowpass filter shown in Figure 12 is sufficient for many applications. 232412fa For more information www.linear.com/LTC2324-12 19 LTC2324-12 Applications Information SINGLE-ENDED INPUT SIGNAL ADC REFERENCE IN+ 50 IN- 3.3nF BW = 1MHz Internal Reference LTC2324 SINGLE-ENDED TO DIFFERENTIAL DRIVER 232412 F12 Figure 12. Input Signal Chain The sampling switch on-resistance (RON) and the sample capacitor (CIN) form a second lowpass filter that limits the input bandwidth to the ADC core to 110MHz. A buffer amplifier with a low noise density must be selected to minimize the degradation of the SNR over this bandwidth. High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. The LTC2324-12 has an on-chip, low noise, low drift (20ppm/C max), temperature compensated bandgap reference. It is internally buffered and is available at REF (Pin 8). The reference buffer gains the internal reference voltage to 4.096V for supply voltages VDD = 5V and to 2.048V for VDD = 3.3V. The REF pin also drives the four internal reference buffers with a current limited output (250A) so it may be easily overdriven with an external reference in the range of 1.25V to 5V. Bypass REF to GND with a 1F (X5R, 0805 size) ceramic capacitor to compensate the reference buffer and minimize noise. The 1F capacitor should be as close as possible to the LTC2324-12 package to minimize wiring inductance. The REFBUFEN pin does not affect the internal REF buffer. The voltage on the REF pin must be externally buffered if used for external circuitry. Table 1. Reference Configurations and Ranges REFERENCE CONFIGURATION Internal Reference with Internal Buffers Common External Reference with Internal Buffer (REF Pin Externally Overdriven) External Reference with REF Buffers Disabled 20 VDD REFBUFEN REF PIN REFOUT1,2,3,4 PIN DIFFERENTIAL INPUT RANGE 5V 5V 4.096V 4.096V 4.096V 3.3V 3.3V 2.048V 2.048V 2.048V 5V 5V 1.25V to 5V 1.25V to 3.3V 1.25V to 5V 3.3V 3.3V 1.25V to 5V 1.25V to 3.3V 1.25V to 3.3V 5V 0V 4.096V 1.25V to 5V 1.25V to 5V 3.3V 0V 2.048V 1.25V to 3.3V 1.25V to 3.3V 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information External Reference The internal REFOUT1,2,3,4 buffers can also be overdriven from 1.25V to 5V with an external reference at REFOUT1,2,3,4 as shown in Figure 13(c). To do so, REFBUFEN must be grounded to disable the REF buffers. A 55k internal resistance loads the REFOUT1,2,3,4 pins when the REF buffers are disabled. To maximize the input signal swing and corresponding SNR, the LTC6655-5 is VDD 3.3V TO 5V REF LTC2324-12 REFOUT1 10F LTC6655-4.096 REFBUFEN VIN SHDN REF VOUT_F VOUT_S 10F LTC2324-12 10F 0.1F REFOUT1 10F REFOUT2 10F VDD +5V 5V TO 13.2V REFBUFEN 1F recommended when overdriving REFOUT. The LTC6655-5 offers the same small size, accuracy, drift and extended temperature range as the LTC6655-4.096. By using a 5V reference, a higher SNR can be achieved. We recommend bypassing the LTC6655-5 with a 10F ceramic capacitor (X5R, 0805 size) close to each of the REFOUT1,2,3,4 pins. If the REF pin voltage is used as a REFOUT reference when REFBUFEN is connected to GND, it should be buffered externally. REFOUT2 10F REFOUT3 REFOUT3 10F REFOUT4 10F GND 10F 232412 F13a REFOUT4 GND 232412 F13b (13a) LTC2324-12 Internal Reference Circuit (13b) LTC2324-12 with a Shared External Reference Circuit +5V VDD REFBUFEN REF 1F 5V TO 13.2V LTC6655-4.096 VIN VOUT_F SHDN VOUT_S REFOUT1 10F 0.1F 5V TO 13.2V LTC2324-12 LTC6655-2.048 VIN VOUT_F SHDN VOUT_S REFOUT2 10F 0.1F 5V TO 13.2V LTC6655-2.5 VIN VOUT_F SHDN VOUT_S REFOUT3 10F 0.1F 5V TO 13.2V LTC6655-3 VIN VOUT_F SHDN VOUT_S REFOUT4 10F 0.1F GND 232412 F13c (13c) LTC2324-12 with Different External Reference Voltages Figure 13. Reference Connections 232412fa For more information www.linear.com/LTC2324-12 21 LTC2324-12 Applications Information Internal Reference Buffer Transient Response 4096 CNV IDLE PERIOD 232412 F14 2048 1024 0 -1024 -20 -10 0 10 20 30 40 50 60 70 80 90 SETTLING TIME (ns) 232412 F15 Figure 15. Transient Response of the LTC2324-12 Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 16 shows that the LTC2324-12 achieves a typical SNR of 78dB at a 2MHz sampling rate with a 500kHz input. 0 Fast Fourier transform (FFT) techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. The LTC2324-12 provides guaranteed tested limits for both AC distortion and noise measurements. The typical large signal transient pulse response of the ADC is illustrated in Figure 15. AMPLITUDE (dBFS) Figure 14. CNV Waveform Showing Burst Sampling DYNAMIC PERFORMANCE 4.096V RANGE IN+ = 2MHz SQUARE WAVE IN- = 0V 3072 OUTPUT CODE (LSB) The REFOUT1,2,3,4 pins of the LTC2324-12 draw charge (QCONV) from the external bypass capacitors during each conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge with a DC current equivalent to IREF = QCONV/tCYC. Thus, the DC current draw of IREFOUT1,2,3,4 depends on the sampling rate and output code. In applications where a burst of samples is taken after idling for long periods, as shown in Figure 14 , IREFBUF quickly goes from approximately ~75A to a maximum of 500A for REFOUT = 5V at 2Msps. This step in DC current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at REFOUT will affect the accuracy of the output code. If an external reference is used to overdrive REFOUT1,2,3,4, the fast settling LTC6655 reference is recommended. SNR = 78.5dB THD = -87.8dB -20 SINAD = 78.2dB SFDR = 95.9dB -40 -60 -80 -100 -120 -140 0 0.2 0.4 0.6 FREQUENCY (MHz) 0.8 1 232412 F16 Figure 16. 32k Point FFT of the LTC2324-12 Signal-to-Noise and Distortion Ratio (SINAD) Total Harmonic Distortion (THD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is bandlimited to frequencies from above DC and below half the sampling frequency. Figure 16 shows that the LTC2324-12 achieves a typical SINAD of 78dB at a 2MHz sampling rate with a 500kHz input. Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL /2). THD is expressed as: 22 THD=20log V22 + V32 + V42 + ... +VN 2 V1 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. POWER CONSIDERATIONS The LTC2324-12 requires two power supplies: the 3.3V to 5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2324-12 to communicate with any digital logic operating between 1.8V and 2.5V. When using LVDS I/O, the OVDD supply must be set to 2.5V. Power Supply Sequencing The LTC2324-12 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC232412 has a power-on-reset (POR) circuit that will reset the LTC2324-12 at initial power-up or whenever the power supply voltage drops below 2V. Once the supply voltage re-enters the nominal supply voltage range, the POR will reinitialize the ADC. No conversions should be initiated until 10ms after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. 35 TIMING AND CONTROL CNV Timing The LTC2324-12 sampling and conversion is controlled by CNV. A rising edge on CNV will start sampling and the falling edge starts the conversion and readout process. The conversion process is timed by the SCK input clock. For optimum performance, CNV should be driven by a clean low jitter signal. The Typical Application at the back of the data sheet illustrates a recommended implementation to reduce the relatively large jitter from an FPGA CNV pulse source. Note the low jitter input clock times the falling edge of the CNV signal. The rising edge jitter of CNV is much less critical to performance. The typical pulse width of the CNV signal is 30ns with < 1.5ns rise and fall times at a 2Msps conversion rate. SCK Serial Data Clock Input In SDR mode (SDR/DDR Pin 23 = GND), the falling edge of this clock shifts the conversion result MSB first onto the SDO pins. A 110MHz external clock must be applied at the SCK pin to achieve 2Msps throughput using all four SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD), each input edge of SCK shifts the conversion result MSB first onto the SDO pins. A 55MHz external clock must be applied at the SCK pin to achieve 2Msps throughput using all four SDO1 through SDO4 outputs. SUPPLY CURRENT (mA) CLKOUT Serial Data Clock Output 30 The CLKOUT output provides a skew-matched clock to latch the SDO output at the receiver. The timing skew of the CLKOUT and SDO outputs are matched. For high throughput applications, using CLKOUT instead of SCK to capture the SDO output eases timing requirements at the receiver. For low throughput speed applications, CLKOUT can be disabled by tying Pin 34 to OVDD. VDD = 5V 25 VDD = 3.3V 20 15 0 0.4 0.8 1.2 1.6 SAMPLE FREQUENCY (Msps) 2 232412 F17 Figure 17. Power Supply Current of the LTC2324-12 vs Sampling Rate Nap/Sleep Modes Nap mode is a method to save power without sacrificing power-up delays for subsequent conversions. Sleep mode has substantial power savings, but a power-up delay is incurred to allow the reference and power systems to become valid. To enter nap mode on the LTC2324-12, the SCK signal must be held high or low and a series of 232412fa For more information www.linear.com/LTC2324-12 23 LTC2324-12 Applications Information two CNV pulses must be applied. This is the case for both CMOS and LVDS modes. The second rising edge of CNV initiates the nap state. The nap state will persist until either a single rising edge of SCK is applied, or further CNV pulses are applied. The SCK rising edge will put the LTC2324-12 back into the operational (full-power) state. When in nap mode, two additional pulses will put the LTC2324-12 in sleep mode. When configured for CMOS I/O operation, a single rising edge of SCK can return the LTC2324-12 into operational mode. A 10ms delay is necessary after exiting sleep mode to allow the reference buffer to recharge the CNV 1 external filter capacitor. In LVDS mode, exit sleep mode by supplying a fifth CNV pulse. The fifth pulse will return the LTC2324-12 to operational mode, and further SCK pulses will keep the part from re-entering nap and sleep modes. The fifth SCK pulse also works in CMOS mode as a method to exit sleep. In the absence of SCK pulses, repetitive CNV pulses will cycle the LTC2324-12 between operational, nap and sleep modes indefinitely. Refer to the timing diagrams in Figure 18, Figure 19, Figure 20 and Figure 21 for more detailed timing information about sleep and nap modes. 2 FULL POWER MODE NAP MODE SCK HOLD STATIC HIGH OR LOW WAKE ON 1ST SCK EDGE SDO1 - 4 Z Z 232412 F18 Figure 19. CMOS and LVDS Mode NAP and WAKE Using SCK REFOUT1 - 4 REFOUT RECOVERY 4.096V 4.096V tWAKE CNV 1 2 3 4 NAP MODE SCK SLEEP MODE FULL POWER MODE HOLD STATIC HIGH OR LOW WAKE ON 1ST SCK EDGE SDO1 - 4 Z Z Z Z 232412 F19 Figure 18. CMOS Mode SLEEP and WAKE Using SCK REFOUT1 - 4 REFOUT RECOVERY 4.096V 4.096V tWAKE CNV 1 2 3 4 NAP MODE SCK SDO1 - 4 WAKE ON 5TH CNV EDGE 5 SLEEP MODE FULL POWER MODE HOLD STATIC HIGH OR LOW Z Z Z Z Z 232412 F20 Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV 24 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information SDR MODE TIMING DDR MODE TIMING tCYC tCNVH tCYC tCONV tREADOUT tCNVH tDSCKCNVH CNV 1 2 3 tREADOUT tDSCKCNVH tSCKH tSCK SCK tCONV CNV tSCKH tSCK 14 15 SCK 16 1 2 3 1 2 3 14 15 CLKOUT 16 1 tDSCKCLKOUT SDO HI-Z D12 D11 D10 X X X D12 2 3 14 16 15 tDSCKCLKOUT tDCNVSDOZ tHSDO tDCNVSDOV 15 tSCKL tSCKL CLKOUT 14 tDCNVSDOV HI-Z SDO HI-Z Figure 21. LTC2324-12 Timing Diagram DIGITAL INTERFACE The LTC2324-12 features a serial digital interface that is simple and straightforward to use. The flexible OVDD supply allows the LTC2324-12 to communicate with any digital logic operating between 1.8V and 2.5V. In addition to a standard CMOS SPI interface, the LTC2324-12 provides an optional LVDS SPI interface to support low noise digital design. The CMOS /LVDS pin is used to select the digital interface mode. The SCK input clock shifts the conversion result MSB first on the SDO pins. CLKOUT provides a skew-matched clock to latch the SDO output at the receiver. The timing skew of the CLKOUT and SDO outputs are matched. For high throughput applications, using CLKOUT instead of SCK to capture the SDO output eases timing requirements at the receiver. In CMOS mode, use the SDO1 - SDO4, and CLKOUT pins as outputs. Use the SCK pin as an input. In LVDS mode, use the SDOA+/ SDOA- through SDOD+/SDOD- and CLKOUT+/CLKOUT- pins as differential outputs. These pins must be differentially terminated by an external 100 resistor at the receiver (FPGA). The SCK+/SCK- pins are differential inputs and must be terminated differentially by an external 100 resistor at the receiver(ADC). SDR/DDR Modes The LTC2324-12 has an SDR (single data rate) and DDR (double data rate) mode for reading conversion data from the SDO pins. In both modes, CLKOUT is a delayed version of SCK. In SDR mode, each negative edge of SCK shifts the conversion data out the SDO pins. In DDR mode, tDCNVSDOZ tHSDO D12 D11 D10 X 16 X X D12 HI-Z 232412 F21 each edge of the SCK input shifts the conversion data out. In DDR mode, the required SCK frequency is half of what is required in SDR mode. Tie SDR/DDR to ground to configure for SDR mode and to OVDD for DDR mode. The CLKOUT signal is a delayed version of the SCK input and is phase aligned with the SDO data. In SDR mode, the SDO transitions on the falling edge of CLKOUT as illustrated in Figure 21. We recommend using the rising edge of CLKOUT to latch the SDO data into the FPGA register in SDR mode. In DDR mode, the SDO transitions on each input edge of SCK. We recommend using the CLKOUT rising and falling edges to latch the SDO data into the FPGA registers in DDR mode. Since the CLKOUT and SDO data are phase aligned, we recommend digitally delaying the SDO data in the FPGA to provide adequate setup and hold timing margins in DDR mode. Multiple Data Lanes The LTC2324-12 has up to four SDO data lanes in CMOS mode and four SDO lanes in LVDS mode. In CMOS mode, the number of possible data lanes range from four (SDO1, SDO2, SDO3 and SDO4), two (SDO1 and SDO3) and one (SDO1). Generally, the more data lanes used, the lower the required SCK frequency. When using less than four lanes in CMOS mode, there is a limit on the maximum possible conversion frequency (see Table 2). Each SDO pin will hold the MSB of the conversion data. In DDR mode you can use a SCK frequency half of SDR mode. See Table 2 for examples of various possibilities and the resulting SCK frequency required. 232412fa For more information www.linear.com/LTC2324-12 25 LTC2324-12 Applications Information LTC2324-12 2.5V SCK+ SCK- 2.5V CMOS/LVDS FPGA OR DSP OVDD LTC2324-12 + - 100 2.5V SCK+ SCK- SDOD+ SDOD- 100 + - SDOD+ SDOD- SDOC+ SDOC- 100 + - SDOC+ SDOC- CLKOUT+ CLKOUT - 100 + - SDOB+ SDOB- 100 + - SDOB+ SDOB- SDOA+ SDOA- 100 + - SDOA+ SDOA- CNV 2.5V CMOS/LVDS CLKOUT+ CLKOUT - RETIMING FLIP-FLOP FPGA OR DSP OVDD CNV + - 100 100 + - 100 + - RETIMING FLIP-FLOP 232412 F22 Figure 22. LTC2324-12 Using the LVDS Interface 232412 F23 Figure 23. LTC2324-12 Using the LVDS Interface with One Lane Table 2. Conversion Frequency for Various I/O Modes I/O MODE CMOS LVDS SDR/ DDR PIN SDO1 - 4 LANES GND (SDR) GND (CMOS) OVDD (DDR) OVDD (DDR) SDO1, SDO3 55 55 32 GND (SDR) SDO1 110 110 64 1.0 300 300 16 2.0 OVDD (LVDS) SDOA - D LANES SCK FREQ (MHz) CLKOUT FREQ (MHz) SCK CYCLES SDO1 - SDO4 110 110 16 SDO1 - SDO4 55 55 8 CONVERSION FREQUENCY (Msps/CH) CMOS/ LVDS PIN GND (SDR) SDOA - SDOD OVDD (DDR) SDOA - SDOD 150 150 8 OVDD (DDR) SDOA, SDOC 150 150 16 GND (SDR) SDOA 300 300 64 OVDD 2.0 1.8V to 2.5V 2.5V 2.0 1.5 2.0 2.0 2.0 Notes: Conversion Period (SDR) = tCNV_MIN + tCONV_MAX + (64/(Lanes * fSCK)) Conversion Period (DDR) = tCNV_MIN + tCONV_MAX + (32/(Lanes * fSCK)) Conversion Frequency = 1/Conversion Period SCK Cycles (SDR) = 64/Lanes SCK Cycles (DDR) = 32/Lanes 26 232412fa For more information www.linear.com/LTC2324-12 LTC2324-12 Applications Information CMOS In CMOS mode, the number of possible data lanes range from four (SDO1, SDO2, SDO3 and SDO4), two (SDO1 and SDO3) and one (SDO1). As suggested in the CMOS Timing Diagrams, each SDO lane outputs the conversion results for all analog input channels in a sequential circular manner. For example, the first conversion result on SDO1 corresponds to analog input channel 1, followed by the conversion results for channels 2 through 4. The data output on SDO1 then wraps back to channel 1 and this pattern repeats indefinitely. Other SDO lanes follow a similar circular pattern except the first conversion result presented on each lane corresponds to its associated analog input channel. Applications that cannot accommodate the full four lanes of serial data may employ fewer lanes without reconfiguring the LTC2324-12. For example, capturing the first two conversion results (32 SCK cycles total in SDR mode and 32 SCK edges in DDR mode) from SDO1 and SDO3 provides data for analog input channels 1 and 2, 3 and 4, respectively, using two output lanes. Similarly, capturing the first four conversion results (64 SCK cycles total in SDR mode and 64 SCK edges in DDR mode) from SDO1 provides data for analog input channels 1 to 4, using one output lane. Generally, the more data lanes used, the lower the required SCK frequency. When using less than four lanes in CMOS mode, there is a limit on the maximum possible conversion frequency. See Table 2 for examples of various possibilities and the resulting SCK frequency required. LVDS In LVDS mode, the number of possible data lane pairs range from four (SDOA - SDOD), two (SDOA and SDOC) and one (SDOA). As suggested in the LVDS Timing Diagrams, each SDO lane pair outputs the conversion results for all analog input channels in a sequential circular manner. For example, the first conversion result on SDOA corresponds to analog input channel 1, followed by the conversion results for channels 2 through 4. The data output on SDOA then wraps back to channel 1 and this pattern repeats indefinitely. Other SDO lanes follow a similar circular pat- tern except the first conversion result presented on each lane corresponds to its associated analog input channel pairs (SDOA: analog input 1, SDOB: analog input 2, SDOC: analog input 3 and SDOD: analog input 4). Applications that cannot accommodate the full four lanes of serial data may employ fewer lanes without reconfiguring the LTC2324-12. For example, capturing the first two conversion results (32 SCK cycles total in SDR mode and 32 SCK edges in DDR mode) from SDOA and SDOC provides data for analog input channels 1 through 4, respectively, using two output lanes. If only one lane can be accommodated, capturing the first four conversion results (64 SCK cycles total in SDR mode and 64 SCK edges in DDR mode) from SDOA provides data for all analog input channels. Generally, the more data lanes used, the lower the required SCK frequency. When using less than four lanes in LVDS mode, there is a limit on the maximum possible conversion frequency. See Table 2 for examples of various possibilities and the resulting SCK frequency required. BOARD LAYOUT To obtain the best performance from the LTC2324-12, a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals adjacent to analog signals or underneath the ADC. Supply bypass capacitors should be placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. A single solid ground plane is recommended for this purpose. When possible, screen the analog input traces using ground. Recommended Layout For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer to DC2395A, the evaluation kit for the LTC2324-12. 232412fa For more information www.linear.com/LTC2324-12 27 LTC2324-12 Package Description Please refer to http://www.linear.com/product/LTC2324-12#packaging for the most recent package drawings. UKG Package 52-Lead Plastic QFN (7mm x 8mm) (Reference LTC DWG # 05-08-1729 Rev O) 7.50 0.05 6.10 0.05 5.50 REF (2 SIDES) 0.70 0.05 6.45 0.05 6.50 REF 7.10 0.05 8.50 0.05 (2 SIDES) 5.41 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (2 SIDES) 0.75 0.05 R = 0.115 TYP 0.00 - 0.05 5.50 REF (2 SIDES) 51 52 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45C CHAMFER 8.00 0.10 (2 SIDES) 6.50 REF (2 SIDES) 6.45 0.10 5.41 0.10 R = 0.10 TYP TOP VIEW 0.200 REF 0.00 - 0.05 0.75 0.05 (UKG52) QFN REV O 0306 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD SIDE VIEW NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 28 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE For more information www.linear.com/LTC2324-12 232412fa LTC2324-12 Revision History REV DATE DESCRIPTION A 07/17 Corrected DNL typical value PAGE NUMBER 3 232412fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2324-12 29 LTC2324-12 Typical Application Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop VCC 0.1F 50 1k NC7SZ04P5X MASTER_CLOCK VCC 1k D PRE NL17SZ74US8 Q CLR CONV CONV ENABLE CNV LTC2324-12 SCK CLKOUT GND CMOS/LVDS GND SDR/DDR CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) SDO1 - 4 10 10 NC7SVU04P5X (x 5) 232412 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS ADCs LTC2311-16/LTC2311-14/ 16-/14-/12-Bit, 5Msps Differential Input ADC LTC2311-12 3.3V Supply, 1-Channel 40mW, 20ppm/C Internal Reference, Flexible Inputs, 16-Lead MSOP Package LTC2320-16/LTC2320-14/ 16-/14-/12-Bit, Octal, 1.5Msps/Channel LTC2320-12 Simultaneous Sampling ADC 3.3V/5V Supply, 20mW/Channel, 20ppm/C Internal Reference, Flexible Inputs, 7mm x 8mm QFN-52 Package LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, Dual 2Msps, Simultaneous LTC2321-12 Sampling ADC 3.3V/5V Supply, 40mW/Channel, 20ppm/C Max Internal Reference, Flexible Inputs, 4mm x 5mm QFN-28 Package LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, LTC2367-16/LTC2364-16 Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm x 3mm DFN-16 Packages LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, LTC2377-16/LTC2376-16 Low Power ADC 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm x 3mm DFN-16 Packages DACs LTC2632 Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal Reference 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, Rail-to-Rail Output, 8-Pin ThinSOTTM Package LTC2602/LTC2612/ LTC2622 Dual 16-/14-/12-Bit SPI VOUT DACs with External Reference 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package LTC6655 Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package LT1818/LT1819 400MHz, 2500V/s, 9mA Single/Dual Operational Amplifiers -85dBc Distortion at 5MHz, 6nV/Hz Input Noise Voltage, 9mA Supply Current, Unity-Gain Stable LT1806 325MHz, Single, Rail-to-Rail Input and Output, Low -80dBc Distortion at 5MHz, 3.5nV/Hz Input Noise Voltage, Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable LT6200 165MHz, Rail-to-Rail Input and Output, 0.95nV/Hz Low Noise, Low Distortion, Unity-Gain Stable Low Noise, Op Amp Family References Amplifiers 30 232412fa LT 0717 REV A * PRINTED IN USA For more information www.linear.com/LTC2324-12 www.linear.com/LTC2324-12 (c) LINEAR TECHNOLOGY CORPORATION 2017