FW21154BE - Intel - Datasheet.Live

21154 PCI-to-PCI Bridge Datasheet

Pr oduct Features

■Complies fully with the PCI L o cal Bu s

Specification, Revision 2.1

■Complies fully with the PCI Po w er

Management Specificat ion, Revision 1.01

■Supports 64-bit extension signals on the

primar y and s ec ondary int erfaces

■Implements d elayed tr ansa ct ions for all P CI

configu ration, I/O, and memory read

co mm an ds–up to thr ee transaction s

si mu lta n eo u sly in ea ch di r ect i on

■ Allows 152 byt es of buffering (data and

address ) for upstream pos ted m emory write

commands and 88 bytes of buffering for

downstream posted memory write

command s—up to nine upstream and five

downstream poste d write trans actions

simultaneously

■Allows 152 bytes of read data buf ferin g

upstream and 152 bytes of read data

buffering downstream

■Provi des concurrent primary and secondary

bus operation to isolate traffic

■Provides ten secondary clock outputs:

—Low skew, permitting direct drive of

option slots

—Indi vidual clock disables, ca pable of

automatic configuration during reset

■Provides arbitration support for nine

secondary bus device s:

—A programmable 2-level arbiter

—Hardware disable control, permitting use

of an external arbi ter

1. For the 21154–AB and la ter revis ions only. The 21154–A A does not implement this feature.

■Provides a 4-pin general-purpose I/O

interface, access ible through device-

spe cific configurati on space

■Provides enhanc ed address decoding:

—A 32-bit I/O addre ss range

—A 32-bit memory-mapped I/O addres s

r ange

—A 64-b it prefetchabl e mem ory address

range

—I SA-aware mode for legac y support in

the first 64KB of I/O address range

— VGA address ing and VGA palette

snooping support

■I ncludes live insertion support

■Supports PCI tra nsaction fo rwarding f or the

f ollowing commands:

—All I/O and memory commands

—Type 1 to Type 1 configuration

commands

—Type 1 to Type 0 configuration

com mands (downstrea m onl y)

—Al l Type 1 to s pecia l cycle confi gura tion

commands

■I ncludes downstrea m lo ck s upport

■Sup ports bot h 5-V and 3.3-V signaling

environments

■Available in both 33 MHz and 66 Mhz

versions

■Provides an IEEE standard 1149.1 JTAG

interface

Order N um be r: 27 81 08-00 2

J uly 1999

Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 21154 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

 Datasheet iii
 
PCI-to-PCI Bridge
Contents
0 Introduction.........................................................................................................................1
1 Architecture...........................................................................................................3
2 Data Pa th.... ............ ....... ............ ....... ............ ....... ............ ....... ....... ............ ....... ....5
2.1 Posted  Write Que ue.................................................................................6
2.2 Delayed Transaction Queue................................................ ................... ..6
2.3 Read Data Queue ....................................................................................6
0 Signal Pins .........................................................................................................................7
1 Primary PCI Bus Interface Signals..................................................... ...................8
2  Primary PCI Bus Interface 64-Bit Extension Signals..........................................11
3 Secondary  PCI Bus Interface Signals ............................................................ .....12
4 Secondary  PCI Bus Interface 64-Bit Extensio n Signals................................. .....14
5 Secondary  Bus Arbitra tion Signals. ...................................... ...............................15
6 General-Purpose I/O Interface Signals ...............................................................15
7 Clock Signals.......................................................................................................16
8 Rese t Si g nals ... ....... ............ ....... ............ ....... ............ ....... ....... ............ ....... .........16
9 Miscellaneous Signals.... ............ ....... ............ ....... ........................ ....... ............ ....17
10 JTAG Signal s ........................................................... ...........................................18
0 Pin Assignment................................................................................................................19
1 Numeric Pi n Assignment.....................................................................................20
2 Pins Listed in Alphabetic Order.......................................... .............. ...................25
0 PCI Bus Operation ...........................................................................................................31
1 Types of T ransactio ns.........................................................................................31
2 Addr e ss Ph a se........ ............ ....... ............ ....... ............ ....... ............ ....... ....... .........32
2.1 Single Address Phase............................................................................32
2.2 Dual Ad d re ss Ph ase................ ....... ........... ........ ........... ....... ............ .......32
3 Device Select (DEVSEL#) Generation................................................................33
4 Data Ph ase.............. ....... ............ ....... ............ ....... ............ ....... ............ ....... .........33
5 Write Transactions ..............................................................................................33
5.1 Posted  Write Transactions .....................................................................34
5.2 Memory Write and Invalidate Trans act ions. ...........................................35
5.3 Delayed Write Transactions...................................................................36
5.4 Write Transaction Addres s Bound aries................... ...............................38
5.5 Buffering Multiple W rite Transactions.....................................................38
5.6 Fast Back-to-Ba ck Write Transactions...................................................39
6 Read Tra nsaction s..............................................................................................40
6.1 Prefetchable Read Transactions...... ......... ................... ................... .......40
6.2 Nonprefetchable Read Transactions................................... ...................40
6.3 Read Prefetch Addres s Bounda ries.......................................................41
6.4 Delayed Read Requests .................. ....... ....... ....... ....... ..... ....... ....... .......41
6.5 Delaye d Read Co mpletion with  Target...................................................42
6.6 Delayed Read Completi on on Initiator Bu s ............................................42
7 Configuration Tran sa ction............ ........ ........... ....... ............ ....... ........................ ..46
7.1 Type 0 Access to the 21154... ................................................................46
7.2 Type 1 to  Type 0 Transl ation..................................................................47

P CI-to-PCI Bridge
 
iv  Datasheet
7.3 Type 1 to Type 1 Forwarding.................................................................48
7.4 Special Cycles........................................................................................49
8 64-Bit Op erati on..................................................................................................50
8.1 64-Bit and 32-Bit Trans actions  Initiated by the 21154............................50
8.2 Address Phase of 64-Bit Transactions...................................................50
8.3 Data  Phase of 64-Bit Transactions ........................................................51
8.4 64-Bit Transactions Received by the  21154...........................................51
8.5 64-Bit Extension Support During Reset..................................................52
9 Transaction Flow  Through ..................................................................................52
10 Transaction Termination .....................................................................................53
10 .1 Master T ermination Initiated by the 21154.............................................54
10.2 Master Abo rt Received by the 21154. ...................................... ..............54
10 .3 Target Termination Received by the  21154...........................................55
10.3.1Delayed Write Target Termination Response.... ....... .......... .. ....56
1 0.3.2Posted Write Target Termination Resp onse.............................56
10.3.3Delayed Read Target Term ination Response............. ..............57
10.4 Target Term ination Initiated by the 21154 .............................................59
1 0.4.1Target Retry ..............................................................................59
10.4.2Target Disconnect...................... ................................. ..............60
1 0.4.3Target Abort..............................................................................60
0 Address Decoding............................................................................................................61
1 Address Ranges............................................ ......................................................61
2 I/O Address Decoding.........................................................................................61
2.1 I/O Base and Limit Address Registers...................................................62
2 .2 ISA Mo d e . ............ ....... ............ ....... ............ ....... ............ ....... ............ ......63
3 Memory Address Decoding.................................................................................64
3.1 Memory-Mapped I/O B ase and Lim it Address Registe rs.......................65
3.2 Prefetc hable Mem ory Base and Limit Address Registers. .....................66
3.3 Prefetc hable Mem ory 64-Bit Addressing  Registers................................67
4 VGA Support....... ......... ................... ................... ................... .............. ................68
4 .1 VGA Mode............... ....... ............ ....... ........... ........ ....................... ....... ....68
4.2 VGA Snoop Mode ........................................ ................... ................... ....69
0 Transaction Ordering .......................................................................................................71
1 Transactions Gov erned by Ordering  Rules.................................... .....................71
2 General Ordering Guidelines .................................... ................... ................... ....72
3 Orde r i n g Rules......... ....... ............ ....... ............ ....... ............ ....... ........... ........ ........72
4 Dat a Synch r o n i za tion......................... ....... ............ ....... ............ ....... ............ ....... .73
0 Error Handling..................................................... ................................. ............................75
1 Address Parity Errors..........................................................................................75
2 Dat a Parity Errors......... ........ ........... ........ ........... ....... ............ ....... ............ ....... ....76
2.1 Configuration Write Transactions to 21154  Configuration Spa ce ..........76
2.2 Read Transactions. ................................................................................76
2.3 Delayed Write Transactions...................................................................77
2.4 Posted Write Transactions.....................................................................79
3 Dat a Parity Error Reporting Summary ........ ....... ............ ....... ....... ............ ....... ....80
4 System Error (SERR#) Reporting.......................................................................85

 Datasheet v
 
PCI-to-PCI Bridge
0 Exc lusive Access............. ....... ........ ........... ........ ........... ....... ............ ....... ............ ....... .......87
1 Concurrent Locks................................................................................................87
2 Acquiring Exclusive Access Across the 21154................................. ...................87
3 Ending  Exclusive Access ....................................................................................88
0 PCI Bus Arbitration...........................................................................................................91
1 Primary PCI Bus Arbitration ................................................................................91
2 Secondary  PCI Bus Arbitra tion .................................................... ........................91
2.1 Secondary Bus Arbitration Using the Internal Arbiter.............................91
2.2 Secondary Bus Arbitration Using an External Arbiter...................... .......93
2.3 Bus Par king.......... ........... ........ ........... ....... ............ ....... ............ ....... .......93
0 General-Purpose I/O Interface.........................................................................................95
1 gpio Control Registers.........................................................................................95
2 Secondary Clock Control.. ...................................................................................96
3 Live Insertion.......................................................................................................98
0 Clocks...............................................................................................................................99
1 Primary and Secondary Clock Inputs..................................................................99
2 Secondary Clock Outp uts ....................................................................................99
2.1 Disabl ing Unused Sec ondary Clock Outputs .......................................100
0 66- Mhz Ope r a ti o n. ........... ....... ............ ....... ............ ....... ............ ....... ............ ....... ............101
0 PCI Power Managem ent.......... ......................................................... .............................103
0 Reset..............................................................................................................................105
1 Primary Interface Reset.....................................................................................1 05
2 Secondary Interface Reset................................................................................105
3 Chi p Rese t........ ............ ....... ............ ....... ............ ....... ............ ....... ............ ....... ..106
0 Configuration  Space Registers.......................................................................................107
1 PCI-to-PCI Bridge Standard Configuration Registers .......... .............................108
1.1 V endor ID Register— Offset 00h . ..........................................................109
1.2 Device ID Register—Offset 02h...........................................................109
1.3 Prim ary Comm and Register—O ffset 04h. ............................................109
1.4 Primary Status Register—Offset 06h...................................................111
1.5 Revision ID Re giste r—Offse t 08h ........................................................112
1.6 Programming Interface Register—Offset 0 9h ......................................1 13
1.7 S ubclass  Code Register—Offset 0Ah ................................... ...............1 13
1.8 Base C lass Code Register—Offset 0Bh...............................................113
1.9 Cache Line Size Register—Offset 0Ch................................................113
1.10 Primary Latency Timer Registe r—Offse t 0Dh......................................114
1.11 Header Type Register—Offset 0Eh........... ..... ....... ....... ..... ....... ....... .....114
1.12 Primary Bus Number Register—Offset 18h .........................................1 14
1.13 S econdary Bu s Number Regist er—O ffset 19h. ....................................115
1.14 Subordinate Bus Number Register—Offset 1Ah................. ..... ....... .....115
1.15 Sec ondary Late ncy Timer Register—Of fset 1Bh .................................115
1.16 I/O Base Address Register—Offset 1Ch..............................................116
1.17 I/O Limit Ad dress Register—Offset 1Dh...............................................116
1.18 Sec ondary Status  Register—Offset 1Eh..............................................117

P CI-to-PCI Bridge
 
vi  Datasheet
1.19 Mem ory Base Address Re giste r—Offse t 20h ......................................118
1 .20 Memory Limit Address Register— Offset 22h.......................................118
1.21 Prefetc hable Memory Base Address Register—Offset 24h.................119
1.22 Prefetc hable Memory Limit Address Register—O ffset  26h..................119
1.23 Prefetchable M em ory Base Address Upper 32 Bits Register—
Offset 28h.... ............ ....... ............ ....... ........... ........ ........... ....... ............ ..120
1.24 Prefetchable M em ory Limit Address Upper 32 Bits Register—
Offset 2Ch.......... ....... ............ ....... ........................ ....... ........... ........ ......120
1.25 I/O Bas e Address Upper 16 Bits Register—Offset 30h..... ...................121
1.26 I/O Limit Address Upper 16 Bits Registe r—O ffset 32h ........................121
1.27 Subsystem Vendor ID Register—Offset 34h................... ................... ..121
1 .28 ECP Pointer Register—Offse t 34h.......................................................122
1 .29 Subsystem ID Register—Offse t 36h ....................................................122
1 .30 Interrupt Pin Register—Offset 3Dh.......................................................122
1.31 Bridge Control Register—Off set 3Eh ...................................................123
1.32 Capabi lity ID Reg ister—Offset DCh. ....................................................125
1 .33 Next Item Ptr Register—Offset DDh.....................................................126
1.34 Po w er Manag ement Capab ilit ies R egist er—Offset DE h............... .......126
1.35 Power Manag eme nt Control and Status Register—Offse t E0h ...........127
1 .36 PPB Support Extensions Registers—Offset E2h.................................127
1 .37 Data  Register — Offset E3h.................................................................128
2 Device - Sp e cific Confi g ura tion Regist ers. ....... ........... ........ ....................... ....... ..128
2 .1 Chip Control Register—Offset 40h.......................................................128
2.2 Diagno stic Control Register—Offset 41h .............................................130
2 .3 Arbiter Control Register—Offset 42h....................................................130
2 .4 p_serr_l Event Disable Register—Offset 64h.......................................131
2 .5 gpio Output Data Register—Offset 65h ...............................................132
2 .6 gpio Output Enable Control Register—Offset 66h ...............................133
2 .7 gpio Input Data Register—Offset 67h ..................................................133
2.8 Secondary  Clock Control Register—Offset  68h...................................133
2 .9 p_serr_l Status Register—Offset 6Ah..................................................135
3 Configuration Register Values After Reset .......................................................136
0 JTAG Test Port ..............................................................................................................139
1 Overview ...........................................................................................................139
2 JTAG Signal Pins..............................................................................................139
3 Test Access Port Controller ..............................................................................139
4 Instr u ction Regist e r.... ....... ............ ....... ............ ....... ............ ....... ....... ............ ....140
5 Bypass Register................................................................................................140
6 Boundary-Scan Regist er........................................... ................... ................... ..140
6.1 Boundary-Scan Register Cells....... ....... ....... .......... .. ....... ....... .......... ....141
6.2 21154 B ounda ry-Scan Order .... ................................. ..........................141
7 Initialization .......................................................................................................147
0 Ele ctrical Spe cificatio n s ........ ............ ....... ............ ....... ........... ........ ........... ....... ..............149
1 PCI Electrical Specification Conforma nce.........................................................149
2 Absolu te  Maximum Ratings . ........... ........ ........... ....... ............ ....... ............ ....... ..14 9
3 DC Specification s......... ............ ....... ............ ....... ............ ....... ............ ....... .........150
4 AC Timing Specifi cations..................................................................................150
4 .1 Clock Timing Specifications.................................................................150

 Datasheet vii
 
PCI-to-PCI Bridge
4.2 P CI Signal Timing Spec ifications . . ................................. ......................1 52
4.3 Reset Timing Specificati ons.................................................................154
4.4 gpio Timing Specifications....................................................................154
4.5 JTAG Timi ng Specifications.................................................................1 55
0 Mechanical Specifications................................................... ................... ................... .....157
Figures 1 21154 on the System Board....... .............. .............. ................... ................... .........2
21154 with Option Cards..... ....... .. ............ ..... ....... ....... ....... ....... ....... .......... .. ....... ..3
21154 Block Diagram............ ..... ....... ....... ....... ....... .......... ....... .. ....... .......... ....... ....4
21154 Downstream Data Path............... ....... ....... ....... ....... ....... ....... ..... ....... ....... ..5
21154 PBGA Cavity Down View .........................................................................19
Flow-Through Posted Memory Write Transaction...............................................35
Downstream Delayed Write Transaction.............................................................37
Fast Back-to-Ba ck Transactions on the Target Bus............................................39
Nonprefetchable Delayed Read Transaction ................... ....... .. ....... .......... .. .......43
Prefetchabl e Delayed Read Transac tion . ............................................................44
Flow-Through Prefet chable Read Tran saction.. ..................................................45
Configuration Transactio n Address Formats.......................................................46
Delayed W rite Transaction Termi nated with Master Abort..................................55
Delayed Re ad Transacti on Terminated with Target Abort..................................58
I/O Tr ansaction Forwarding Using Base and Limit Addresses....... .. .......... ....... ..62
I/O  Tra nsaction  Forwarding in ISA Mode............................................................64
Memo ry Transaction Forwarding Using Base and Limit Registers .....................66
Secondary Arbiter Exampl e ........................................... ......................................92
Examp le of gpio Clock Mask Impleme ntation  on the System Board...................97
Clock Mask and Load Shift Timing.................... ................................. .................98
p_clk and s_clk Relative Timing......................................................... .................99
21154 Configuration Space Map..................... ....... .......... ....... .. ....... .......... .. .....108
PCI Clock Signal AC Parameter Measurem ents...............................................151
PCI Signal Timing Me asureme nt Conditi ons.....................................................1 52
304-Poin t 2-Layer PBGA Pac kage. ............................................. ......................157
Tables 1 21154 Function Blocks.................................... ................... .............. ................... ..4
S ignal  Pin Functional Groups.. ..............................................................................7
Signal Type Abbr eviations............ ................... ................... .............. ................... ..7
P rimary PCI Bus Interface Signals........................................................................8
P rimary PCI Bus Interface 64-Bit Extension Signals...........................................11
S econdary  PCI Bu s Interface Signals. ................................................................12
S econdary  PCI Bu s Interface 64-Bit Extensio n Signals......................................14
S econdary  PCI Bu s Arbitration Signals. ............................................. .................15
General-Purpose I/O Interface Signals ...............................................................15
Clock Signals .......................................................................................................16
Re se t Signals ... ....... ....... ............ ....... ............ ....... ............ ....... ............ ....... .........16
Mi sce llaneous Signals.... ............ ....... ............ ....... ........................ ....... ............ ....17
JTAG Signal s ........................................................... ...........................................18
21154 PBGA Pin List....................................... ................... .............. ...................20
21154 PBGA Pin List....................................... ................... .............. ...................25

P CI-to-PCI Bridge
 
viii  Datasheet
21154 PCI Transa ctions. ...................................... ...............................................31
W rite Transac tion Forwar d i ng..... ............ ....... ........... ........ ........... ....... ............ ....33
Write Transaction Disconnect Address Boundaries.............. .............. ................38
Read Transaction Pr efetching. ............................................................................40
Read Prefetch Address Boundarie s.. ..................................................................41
Device Number to IDSEL s_ad Pin Mapping .......... .. ............ ..... ....... ....... ....... ....48
21154 Response to Delayed Write Target Termination......................................56
21154 Response to Posted Write Target Termination........................................57
21154 Response to Delayed Read Targe t Termination.................................... ..57
Su mmary o f Transaction Ordering......................................................................72
Se tting th e Prim ary Interface Detected Parity Error Bit.......................................80
Se tting th e Secondary Interface Detected Parity Error Bit..................................81
Se tting th e Prim ary Interface Data Parity D etected Bi t .......................................82
Se tting the Secondary Interface Data Parity Detecte d Bit ..................................82
Assertion of p_perr_l...........................................................................................83
Assertion of s_perr_l...........................................................................................84
Assertion of p_serr_l  for Data Parity Errors ........................................................85
gpio Opera tion .....................................................................................................96
gpio Serial Data F ormat......................................................................................96
Power Management Transitions ............... .. ....... ....... .......... .. ....... ....... ..... ....... ..103
Configuration Register Values After Reset .......................................................136
JTAG Pins.........................................................................................................139
JTAG Instruction Register.................................................................................140
Boundary Scan Order ..................... ................... ................... .............. ..............141
Abs olu te  Ma ximum Ratings ... ....... ............ ....... ............ ....... ............ ....... ...........149
Functional Operating Range .... ................... .............. ................... ................... ..149
DC Pa r a mete r s ........ ....... ............ ....... ....................... ........ ........... ....... ............ ..15 0
33 MHz PCI Clock Signal AC  Parameters........................................................151
66 MHz PCI Clock Signal AC  Parameters........................................................152
33 MHz PCI Signal Timing. . ..............................................................................152
66 MHz PCI Signal Timing. . ..............................................................................153
Reset Timing Specifications..............................................................................154
33 MHz gpio Timing Specifications...................................................................154
66 MHz gpio Timing Specifications...................................................................155
JTAG Timing  Specifications..............................................................................155
304-Point 2- Layer PBGA Package Dimensions...... ....... ....... ..... ....... .. .......... ....158

Datasheet 1

1.0 Introduction

The 21154 is a second-generation PCI-to-PCI bridge and is full y com pliant wi th PCI Local Bus

Specification, Revision 2.1. The 21154 has a 64-bit primary bus interfa ce and a 64-bit secondary

interface. The 64-bit interfaces interoperate transparently with either 64-bit or 32-bit devices. T he

21154 provides full support for delayed t r ans act ions, which enables the buffering of memory read,

I/O, and configura tion tr ansactions. The 21154 has separate posted write, read data, an d dela yed

transaction queue s with the most buffering capability of all Intel’s 2115 x PCI-to-PCI bri dge

products. In addition, the 21154 supports buffering of simultaneous multi ple posted write and

delayed transactions in bot h directions. Among the featur es provided by the 21154 are: a

programmable 2-level secondary bus arbiter, an IEEE sta ndard 1149.1 JTAG interface, live

insertion support, a 4-pin general-purpose I/O interface, individual secondary clock disables, and

enhan ced ad dress de coding. The 21154 has suf fi cient clock and arbi tra tion pi ns to s upport nine PCI

bus master devices dire ctly on its secondary interface.

The 21154 allows the two P CI buses to operate concurrent ly. This means t hat a master and a target

on the sam e PCI bus can c ommunicate while the other PCI bus is busy. Thi s t r affic isol ation may

increase system performance in applications such as multimedia.

Figure 1 illustrates the use of two 211 54 PCI-to-PCI bridges on a system board. Each 21154 t hat is

added to the board creates a ne w PCI bus tha t provides support for the addi tional PCI slots or

devices

21154 P CI-to-PCI Bridge

2 Data sh eet

Optio n car d desig ners can us e the 21 154 to i mplem ent multi ple -devic e PCI option c ards. Without a

PCI-to-PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus

Specification loa d ing rules limit PCI option cards to a si ngle connection per PCI signal in th e

option card connector. However, th e 21154 overcomes this restriction by providing, on the option

card, an independent PCI bus to which up to nine devices can be attached.

Figure 2 shows how the 21154 enables the design of a multicomponent option ca rd.

Figure 1. 21154 on the System Board

LJ-05428.AI4

CPU

Core

Logic Graphics

21154

ISA or

EISA

Bridge

ISA or EISA

Option Slots

PCI

Option Slots

LANSCSI ISA or EISA Bus

Support

Chip

Diskette

Keyboard

Serial

Parallel

TOY Clock

Audio

21154

PCI

Option Slots

64-Bit PCI Bus

64-Bit

PCI Bus

21154 PCI-to-PCI Bridge

Datasheet 3

1.1 Architecture

The 21154 internal architecture consists of the foll owing maj or functions:

•PCI interface control logic for the primary and secondary PCI interfaces

•Data pa th and data path control logic

•Conf iguration re giste r and configuration control logic

•Secondary bus arbi ter

Figure 3 shows the majo r functiona l blocks of the 21 154.

Figure 2. 21154 with Op tion Cards

LJ-05429.AI4

64-Bit PCI Bus

21154

LAN

Chip

LAN

Chip

LAN

Chip

LAN

Chip

Note:

P – Primary Interface

S – Secondary Interface

21154 P CI-to-PCI Bridge

4 Data sh eet

Table 1 describes the major functional blocks of the 21154.

Figure 3. 21154 Block Diagram

Secondary

Arbiter

Secondary

Arbiter

Primary

Request

and Grant

Primary

and

Secondary

Control

Primary-

to-

Secondary

Data Path

Secondary-

to-

Primary

Data Path

Primary Data Primary Control Primary Data

Secondary Data Secondary Control Secondary Data

LJ-04633.AI4

85%

Configuration

Registers

Clocks and

Reset

Tab le 1. 21154 Function Blocks (Sheet 1 of 2)

Function Block Description

Pri m ary and Second ary Control

PCI interface control logic. This block contains state machines and control

logic for the primary t arget inter face, the prim ary master interface, the

seco ndar y targe t int erface , and the se conda ry m aste r interfac e. This bloc k

also contains logic that interfaces to the data path and the c onfiguration

block.

Primary-to-Secondary Data Path

Data path for data r eceived on the primary interface and driven on the

secondar y interface. This b lock is used for write transactions in itiat ed on

the primary PCI bus and for returning read data for read transactions

initiated on the secondary PCI bus. This block contains logic to store and,

for posted write t ransactions, to increment t he addr ess of the c urrent

trans action. T his block also per forms bus command and configuration

address format translations.

21154 PCI-to-PCI Bridge

Datasheet 5

1.2 Data Path

The data pat h cons ist s of a primary-to-secondary data path for transactions and da ta flowing in t he

downst ream dire ction and a secon dary-to-p rimary data path for tra nsactio ns and dat a flowi ng i n the

upstream direction.

Both data paths have the following queues:

•Posted write queue

•Delayed transac tion queue

•Read data queue

To prevent deadlocks a nd to maintain data coherency, a set of ordering rules is imposed on the

for warding of posted and delayed transactions across the 21154. The queue structure, along with

the order in whic h the trans actions in the queues are initiated and co mpleted, supports these

ordering requ irements. Section 6.0 describes the 21154 ordering rules in detail.

See Section 4.0 for a de tailed description of 21154 PCI bus oper ation. Figure 4 shows the 21154

data path for the downstream direction, and t he following sections descri be the dat a pa th queues.

Secondary-to-Primary Data Path

Data path for data received on the secondary interface and driven on the

primary interface. This block is u s ed for write transactio ns i nitia ted on the

sec ondary PC I bus an d for returning read data for read transactions

initiated on the primary PCI bus. This block contains logic to store and, for

posted write transactions, to increment the address of the current

transaction. This block also performs bus command and configuration

address f ormat translatio ns

Configuration Registers Conf igur ation sp ace reg ister s and cor respo nding control logic. These

registers are accessib le from the primary interface only.

Secondary Bus Arbiter Control Logic for sec ondary bus arbitration. This block receives s_req_ l<8:0> , as

well as th e 21154 sec ondary bus request, and drives on e of the

s_gnt_l<8:0> lines or the 21154 secondary bus gra nt.

Table 1. 21154 Function Blocks (Sheet 2 of 2)

Function Bloc k D es cription

Figure 4. 21154 Downstream Data Path

LJ-04634.AI4

s_ad

Delayed

Transaction

Queue Address

Control

Delayed Read Data Queue

Posted Write Data Queue

21154 P CI-to-PCI Bridge

6 Data sh eet

1.2.1 Posted Write Queue

The posted write queue conta ins the address and data of mem ory write t r ansactions targeted for the

opposite inte rface. The posted write transaction ca n consist of an arbitrary number of data phases,

sub ject to th e amount of space in the queue and disc onnect boundarie s. The post ed write queue can

conta in multiple posted write tra nsactions. The number of posted write transactions that can be

queue d at one ti me is dependen t upon th eir burs t size. The pos ted writ e queue co nsists of 152 bytes

in the upstream direction and 88 bytes in the downstrea m direction.

1.2.2 Delayed Transaction Qu eue

For a delaye d write request trans ac tion, the delay ed tra nsacti on queue co ntains the address, bus

com mand, 1 Dword of write data, byte enable bits, and parity. When the delayed write transa ction

is completed on the target bus, the write completion s tatus is added to the corresponding entry.

For a delaye d read request transaction, the del aye d transaction queue contains the address an d bus

command, and for nonprefetchable read transact ions, the byte enable bits. Wh en the delayed rea d

transaction is completed on the target bus, the read completion status corres ponding to that

tr ansact ion is a dded to the delayed request entr y. Read data is placed in the rea d data queue.

The delayed tra nsac tion que ue can ho ld up t o three tr ansa ctions (a ny combi nation of rea d and write

transactions).

1.2.3 Read Data Queue

The read data queue contains read data transferred from the target during a de layed read

completion. Read data travels in the opposite direction of the trans action. The pr imary-to-

se condary read data queue contains read data correspondi ng to a delayed read transaction residing

in t he secondar y-to -prima ry de layed trans acti on queue . T he se condary -to- primar y read dat a que ue

cont ains read dat a correspo ndin g to a dela yed rea d trans acti on in the pri mary-t o-se condary de layed

transaction que ue. The amount of read data pe r transaction depends on the amount of spac e in the

queue and disconnect boundaries.

Rea d da ta for up to t hre e t ran sa ct ion s, s ubj ec t t o th e bu rst siz e o f the r ead tr ans ac tio ns and av ail abl e

queue space, ca n be stored. The read data queue for the 21154 consis ts of 152 bytes pointing

upstream and 152 bytes pointing downstre am .

Datasheet 7

2.0 Signal Pins

This chapter provides detaile d des criptions of the 21154 signal pins, groupe d by function.

Table 2 describes the signal pin functional groups, and the followi ng se ctions descri be the signals

in ea ch group.

Table 3 defi nes the si gnal type abbreviat ions used in the s ignal tables :

Table 2. Signal Pin Functional Groups

Function Description

Primary PCI bus interface signal

pins All PCI pins required by th e

PCI-to-PCI Bridge Architecture

Specification.

Primary PCI bus interfa ce

64-bit extension signal pins All 64-bit extension s ignal pins defi ned by the

PCI Loca l B us

Specification.

Secondary PCI bus interface signal

pins All PCI pins required by th e

PCI-to-PCI Bridge Architecture

Specification.

Secondary PCI bus interface

64-bit extension signal pins All 64-bit extension s ignal pins defi ned by the

PCI Loca l B us

Specification.

Sec o nd ar y PCI bus arbiter sign al

pins Nine r equest/grant pairs of pins for the secondary PCI bus and

arbiter enable control pin.

General-purpose I/O interface Four general-purpose pins.

Cloc k signal pins Two clock inputs (one for each PCI interface). Ten clock

outputs (for nine external secondary PCI bus devices and also

for the 21154).

Reset signal pins A primary interface reset input and a secondary interface res et

output.

M iscellaneous signal pins A n input -only pin used to di sable secondary clock outputs.

Two input voltage signaling level pins.

Three pins contr olling 66 MHz operation.

JTAG signal pins All JTAG pins requi red by IEEE standa rd 1149. 1.

Table 3. Signal T ype Abbreviations

Signal Type Description

I Standard input only.

O Standard o utput only.

TS Tristate bidirectional .

STS Sustained tristate. Active low signal must be pulled high for

one cycle when deasserting.

OD St an da r d op en dr ain .

21154 P CI-to-PCI Bridge

8 Datasheet

Note: The _l si gnal name suffix indicates that the signal is asser ted when it is at a low vo ltage level and

corre sponds to the "#" suffix in the PCI Local Bus Specification. If th is suff ix is not present, the

signal is asserte d when it is at a hi gh voltage level.

2.1 Primary PCI Bus Interface Signals

Table 4 describe s the primary PCI bus interface signals.

Tab le 4. Primary PCI Bus Interface Signals (Sheet 1 of 3 )

Signa l N am e Ty pe De sc ript ion

p_ad<31:0> TS

Primary PCI interface address/d ata. These signals are a multiplexed

address and data bu s. During the address phase or phases of a

transaction, the initiator drives a physical address on p_ad<31:0>.

Dur ing the data phases o f a transact ion, t he initiator drives write data,

or the target drives read data, on p_ad<31:0>. When the primary PCI

bus is idl e, th e 21154 dr iv es p _ad to a v alid lo gi c le vel whe n p_ gnt_ l i s

asserted.

p_cbe_l<3:0> TS

Primary PCI interface command/byte e nables. These signal s are a

multiplexed command field and byte enable field. During the address

phase or ph ases of a transaction, the initiator drives the transacti on

ty pe on p_cbe_l<3:0>. When there are two address phases , the fi rst

address phase carries the dual address command and the second

address phase carries the transaction ty pe. For both read and wr ite

transactions, the initiator drives byte enables on p_cbe_l<3:0> during

the data phases. When the primary PCI bus is idle, the 21154 drives

p_cbe_l to a valid logic level when p_gnt_l is asserted.

p_par TS

Primary PCI interface parity. Signal p_par carries the ev en parity of

the 36 bits of p_ad<31:0> and p_cbe_l<3:0> for both a ddress and

data phases. Signal p_par is driven by the same agent th at has driven

the address ( for a ddress parity) or the data (for data par ity). Signal

p_par contains valid parity one cycle after the address is valid

(indicated by assertion of p_frame_l), or one cycle after data is valid

(indicated by assertion of p_irdy_l for write transactions and p_trdy_l

for read transactions). Signal p_par is driven by the device dr iving

read or write data one cycle after p_ad is driven. Signal p_par is

tristated one cycle after the p_ad lines are tristated. Devices receiving

data sample p_par as an input to c heck for possib le parity errors.

When the primary PCI bus is idle, t he 2115 4 drives p_par to a valid

logic level when p_gnt_l is asserted (one cycle after the p_ad bus is

parked).

p_frame_l STS

Prima ry PCI interfac e FRAME#. Signal p_frame_ l is driven by the

initiat or of a transac tion to indicate the beginning and duration of an

ac cess on the primary PCI bus. Signal p_fr ame_l assertion (falling

edge) indicates the beginning of a PCI transaction. While p_frame_l

remains as serted, data trans fers can contin ue. The deasser tion o f

p_frame_l indicates the final data phase requested by the initiator.

When the p rimary PCI bus is idle, p_frame_l is d riven to a dea sserted

state for one cycl e and the n is sustained by an external pull-up

resistor.

21154 PCI-to-PCI Bridge

Datasheet 9

p_irdy_l STS

Primary PCI interface IRDY#. Signal p_irdy_l is driven by the initiator

of a transaction to indicate the initiator’s ability to complete the current

data phase on the primary PCI bus. During a write transaction,

assertion of p_irdy_l indicates that valid write data is being driven on

the p_ad bus. During a read t ransaction , assertion of p_ir dy_l

indicates that the initiator is able to accept read data for the current

data phase. Once asserted during a given data phase, p_irdy_l is not

deasserted until the data phase completes. When the primary bus is

idle, p_irdy_l is driven to a deasserted state for one cycle and then is

sustained by an external pull-up resistor.

p_trdy_l STS

Primary PCI interface TRDY#. Signal p_trdy_l is driven by the target of

a transaction to indicate the target’s ability to complete the current

data phase on the primary PCI bus. During a write transaction,

as sert ion of p_trdy_ l indicates that th e target is able to accept wri te

dat a f or t h e cur ren t da ta p ha se . Duri ng a rea d t ran sa ct ion, a ss ert io n of

p_trdy_l indicates that the target is driving valid read data on the p_ad

bus. Once asserted during a given data ph ase, p_t rdy_l is not

deasserted until the data phase completes. When the primary bus is

idle, p_trdy_l is driven to a deasserted state for one cycle and then is

sustained by an external pull-up resistor.

p_devsel_l STS

Primary PCI interface DEVSEL#. Signal p_devsel_l is asserted by the

target, indicating that the device is accepting the transaction. As a

target, the 21154 performs positiv e decoding on the add ress of a

transaction initiated on the primary bus to determine whether to assert

p_devsel_l. As an initiator of a transaction on the primary bus, the

21154 looks for the assertion of p_devsel_l within five cyc les of

p_fram e_l assertion; otherwise, the 21154 terminates the transaction

with a master abort. When the primary bus is idle, p_devsel_l is

driven to a deasserted state for one cycle and then is sustained by an

external pull -up resistor.

p_stop_l STS

Primary PCI inte rface STOP# . Signal p_stop_l is dr iven by the target

of the current transaction, indicating that the target is requesting the

initiator to stop th e current transaction on the primary bus.

Whe n p_ stop _l i s a sser te d in co nj un ctio n wit h p_ trd y_ l a nd p _d evs el _l

assertion, a disconnect with data transfer is being signaled.

When p_stop_l and p_devsel_l are asserted, but p_trdy _l is

deasserted, a t arget disconnec t without data tr ansfe r is bein g

signaled. When this occurs on the first data phase, that is, no data is

transferred during the transaction, this is referred to as a target retry.

When p_stop_l is asserted and p_devsel_l is deasserted, the target is

signaling a target abort.

When the primary bus is idle, p_stop_l is driven to a deasserted state

for one cycle and then is sustained by an external pull-up resistor.

p_lock_l I

Primary PCI interface LOCK#. Signal p_lock _l is deasserted during

the first address phase of a transaction and is asserted one clock

c ycle later by an initiator attempting to perform an atomic operation

that may take more than one PCI transaction to complete. The 21154

samples p_lock_l as a target and can propagate the lock across to the

s econdary bus. The 21154 does not drive p_lock_l as a n initiator; that

is , t he 21154 does n ot p ropa ga t e loc k ed t r ans ac tion s u ps tre am. W he n

releas ed by an init iator, p_lock_l is drive n to a deasserted state for

one cycle and then is sustained by an external pull-up resistor.

p_idsel I

Primary PCI interface IDSEL#. Signal p_ids el is used as th e chip

select line for Type 0 configuration accesses to 21154 configuration

s pac e. W he n p_id sel i s a ss er ted du rin g t h e a dd ress ph as e o f a Typ e 0

configuration transaction, the 21154 responds to the transaction by

as serting p_devs el_l.

Table 4. Prim ary PCI Bus Interface Signals (Sheet 2 of 3)

Signal Name Type Description

21154 P CI-to-PCI Bridge

10 Datasheet

p_perr_l STS

Primary PCI interface PERR#. Signal p_perr_l is asserted when a

data pa ri ty er r or i s de te cte d fo r data re ce iv ed on t he p rima r y in ter f ac e.

The timing of p_perr_l corresponds t o p_par driven one cycle e arlie r

and p_ad and p_cbe_l driven two cycles earlier. Signal p_perr_l is

as serted by the target during write tra nsactions, and by the init iator

during read transactions. When the primary bus is idle, p_perr_l is

driven to a deasserted state for one cycle and then is sustained by an

external pull-up resistor.

p_serr_l OD

Primary PCI interface SERR#. Signal p_serr_l can be driven low by

any device o n the primary bus to indicate a system error condit ion.

The 21154 can assert p_serr_l for the following reas ons:

Add ress parit y error

Posted write data parity er ror on target bus

Secondary bus s_serr_l assertion

Mas ter abort during po sted write transaction

Targ et abort during posted write t ransac tion

Posted w rite tr ansact ion discarded

Delayed write request discarded

Delayed read request discarded

Delayed tr ansact ion mast er timeout

Signal p_serr_l is pulled up through an external resistor.

p_req_l TS

Primary PCI bus REQ#. Signal p_req_l is asserted by the 21154 to

indi ca te t o th e p rima r y bus a r bi ter tha t it wa nts t o s t art a tr an sa ctio n o n

the pri mary b us. Wh en th e 21154 receives a target retry or dis c onnect

in response to initiating a transaction, the 21154 deasserts p_r eq_l f or

at least t wo PCI cl ock cycles before asserting it again.

p_gnt_l I

Primary PCI bus GNT#. When asserted, p_gnt_l indicates to the

211 54 that a cce ss to t he pri ma r y bus i s gr an ted . Th e 2 1154 ca n star t a

transaction on the primary bus when the bus is idle and p_gnt_l is

as serted. When the 21154 has not requested use of the bus and

p_gn t_ l i s as ser ted , th e 211 54 mu st dr i ve p _ad , p_c be _l , a nd p_p ar to

valid logic levels.

Tab le 4. Primary PCI Bus Interface Signals (Sheet 3 of 3 )

Signa l N am e Ty pe De sc ript ion

21154 PCI-to-PCI Bridge

Datasheet 11

2.2 Primary PCI Bus Interface 64-Bit Extension Signals

Table 5 describes the primary PC I bus interfac e 64-bit e xtension signals.

Table 5. Prim ary PCI Bus Interface 64-Bit Extension Signals

Signal Name Type Description

p_ad<63:32> TS

Primary PCI inte rface address/d ata upper 32 bit s . This multiplex ed

address and data bus provides an additional 32 bits to t he primary

interface. During the address phase or phases of a transaction, when

the dual address command is used and p_req64_l is asserted, the

initiator drives the uppe r 32 bits of a 64-bit address; otherwise, these

bits are undefined, and the initiator drives a valid logic level onto the

pins. During the data phases of a transaction, the initiator drives the

upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of

64-bit read data, when p_req64_l and p_ack64_l are both asserted.

When not driven, signals p_ad<63:32> are pulled up to a valid logic

level through external resistors.

p_cbe_l<7:4> TS

Primary PCI interface command/by te enables upper 4 bits. These

signals are a multiplexed command field and byte enable field. During

the address phase or phases of a tr ansaction , when the dual address

c ommand is used and p_req64 _l is asserted, the initiat or drives the

transaction type on p_cbe_l<7:4>; otherwise, these bits are undefined,

and the initiator drives a valid logic level onto the pins. For both read

and write transactions, the initiator drives byte enables for the

p_ad<63:32> data bits on p_cbe_l<7:4> during the data phases when

p_req6 4_l and p_ack64_l are both asserted. When not driven, signal s

p_cbe_l<7:4> are pu lled up to a valid logic level through ex terna l

resistors.

p_par64 TS

Primary PCI inte rface upper 3 2 bits parity. Signal p_par64 carries the

even parity of the 36 bits of p_ad<63:32> and p_cbe_l<7:4> for both

address and data phases. Signal p_par6 4 is driven by t he initiator and

is valid one cycle after the first address phase when a dual address

c ommand is used and p_req64 _l is asserted. Si gnal p_par64 is also

valid one clock cycle after the second address phase of a dual address

transaction when p_req64_l is asserted. Signal p_par6 4_l is valid on e

cycle after valid data is driven (indicated by assertion of p_irdy_l for

write data and p_trdy_l for read data) when both p_req64_l and

p_ack64_l are asserted for that data phase. Signal p_par64 is driven by

the device driving read or write dat a one cycle after the p_ad lines ar e

driven. Signal p_par64 is tristated one cycle after the p_ad lines are

tristated. Devices receive data sample p_par64 as an input to check for

possible parity errors during 64-bit transactions. When not driven,

p_par6 4 is pulled up to a v alid logic level thr ough external res istor s.

p_req64_l STS

Primary PCI interface request 64-bit transfer. Signal p_req64_l is

as s ert ed by th e i ni ti ato r to in di ca t e tha t t h e ini t ia to r is r equ est in g a 64-b it

data transfer. Signal p_req 64_l has the same timing as p_frame_l.

When p_req64_l is asserted low during reset, a 64-bit data path is

s uppo r te d on t he bo ard . Wh en p_ re q6 4_l i s h i gh duri ng r es et ( in di ca tin g

that a 64 -bit data pat h is not supported on the board), t he 21154 driv es

p_ad<63:32>, p_cbe_l<7:4>, and p_par64 to valid logic levels. When

deasserting, p_req64_l is driven to a deasserted state for one cycle and

then sustained by an external pull-up resistor.

p_ack64_l STS

Primary PCI interface acknowledge 64-bit transfer. Signal p_ack64_l is

as sert ed by the ta rget only when p_req6 4_l is asserted by the initiator ,

to indicate the target’s ability to transfer data using 64 bits. Signal

p_ack64_l has the same timing as p_devsel_l. When deasserting,

p_ack64_l is driven to a deasserted state for one cycle and then is

sustained by an external pull-up resistor.

21154 P CI-to-PCI Bridge

12 Datasheet

2.3 Secondary PCI Bus Interface Signals

Table 6 describe s the seconda ry PCI bus interface signals.

Tab le 6. Secondary PCI Bus Interface Signals (Sheet 1 of 2)

Signa l N ame Type Descriptio n

s_ad<31:0> TS

Secondary PCI interface address/data. These signal s are a

multipl exed address and data bus. During the address ph ase or

phases of a transaction, the initiator drives a physical address on

s_ad<31:0>. During the data phases of a transaction, the initiator

drives write data, or the target drives read data, on s_ad<31:0>.

When the secondary PCI bus is idle, the 21154 drives s_ad to a valid

logic level when its secondary bus grant is asserted.

s_cbe_l<3:0> TS

Secondary PCI interface command/byte enables. These signals are a

multiplex ed c ommand field and byte enabl e field. During the addres s

phase or phases of a transaction, the initiator drives the transaction

type on s_cbe_l<3:0>. When there are two address phases, the first

address phase carries the dual address command and the second

address phase carries the transaction type. For both read and write

transactions, the initi ator drives byte ena bles on s_cbe_l<3:0> during

the data phases. When the secondary PCI bus is idle, the 21154

drives s_cbe_l to a valid logic level when its secondary bus grant is

asserted.

s_par TS

Secondary PCI interface parity. Signal s_par carries the even parity of

the 3 6 bi ts of s_a d< 31 :0> an d s_c be _l<3 : 0> for b oth ad dr ess an d dat a

phases. Signal s _par is driven by t he same agent that has driven th e

address ( for address parity) or the data (for data parity). Signal s_ par

c ontain s valid parity one cycle after the address is valid ( indicated by

assertion of s_frame_l), or one cycle after data is valid (indicated by

assertion of s_irdy_l for write transactio ns and s_trdy_l for r ead

tr an sact io ns ). S i gnal s_p ar i s d r iv en by t h e d evi ce dr i vi ng r ead or w ri t e

data one c ycle after s_a d is dri v en. Signal s_par is tristated one cycle

after the s_ad lines are tristated. Devices receive data sample s_par

as an input to check for possible parity errors. When the secondary

PCI bus is idle, the 21 154 drives s_par to a valid logic level when its

s econdary b us grant i s asserted (one cycle after the s_ad bus is

parked).

s_frame_l STS

Secondary PCI interfac e FRAM E#. Signal s_frame_l is driven by t he

in itiator of a transacti on to indicat e the beginnin g and duration of an

access on the secondar y PCI bus. S ignal s_fram e_l assertion (falling

edge) indicates the beginning of a PCI transactio n. While s_frame_l

remains asserted, data transfers can continue. The deassertion of

s _frame_l indicates the fi nal data phase reques ted by the initi ator.

When the secondary PCI bus is idle, s_frame_l is driven to a

deasserted state for one cycle and then is sustained by an external

pull-up resistor.

s_irdy_l STS

Secondary PCI interfac e IRDY#. Signal s_irdy_l i s driven by the

initiator of a transaction to indicate the initiator’s ability to complete the

current data phase on the secondary PCI bus. During a write

transaction, assertion of s_irdy_l indicates that valid write data is

being driven on the s_ad bus. During a read transaction, assertion of

s_irdy_l indicates that the initiator is able to accept read data for the

current data phase. Once asserted during a given data phase,

s_irdy_l is not deasserted until the data phase completes. When the

s econdar y b us i s idle, s_irdy_l is driven t o a deasserted s tate for one

c ycle and t hen is su staine d by an external pull-up resistor.

21154 PCI-to-PCI Bridge

Datasheet 13

s_trdy_l STS

Secondary PCI interface TRDY#. Signal s_trdy_l is driven by the

target of a transaction to indicate the target’s ability to complete the

current data phase on the secondary PCI bus. During a write

transaction, assertion of s_trdy_l indicates that the target is able to

ac cept write data for the current data phase. During a read

transaction, as sertion of s_trdy_l indicates that the target is driving

valid read data o n the s_ad bus. Once asser ted du ring a given data

phase, s_trdy_l is not deassert ed until the data phase completes.

When the se condary bus is idle, s_trdy_l is dr iven to a deasserted

state for one cycle and then is sustained by an external pull-up

resistor.

s_devsel_l STS

Secondary PCI interface DEVSEL#. Signal s_devsel_l is asserted by

the target, i ndicating that t he device is accepting the transaction. As a

target, the 21154 performs positive decoding on the address of a

transaction initiated on t he secondary bus in order to determine

whether to assert s_devsel_l. As an initiator of a transaction on the

secondar y bus, the 21154 looks for the assertion of s _devsel_l within

five cycles of s_frame_l assertion; otherwise, the 21 154 terminates the

transaction with a master abort. When the secondar y bus is idle,

s_devsel_l is driven to a deasserted state for one cycle and then is

sustained by an external pull-up resistor.

s_stop_l STS

Secondary PCI interface STOP#. Signal s_stop_l is driven by the

target of the current transaction, indicating that the target is requesting

the initiator to stop the current transaction on the secondary bus.

When s_stop_l is asserted in conjunction with s_trdy_l and s_devsel_l

as sertion, a dis c onnect with data transfer is being signaled.

When s_stop_l and s_devsel_l are asserted, but s_trdy_l is

deassert ed, a target dis c onnect without data trans fer is being

signaled. W hen this occurs on the first data phase, that is, no data is

transferred during the transaction, this is referred to as a target retry.

When s_stop_l is asserted and s_devsel_l is deasserted, the target is

signaling a target abort.

When the se condary bus is idle, s_stop_l is drive n to a deasserted

state for one cycle and then is sustained by an external pull-up

resistor.

s_lock_l STS

Secondary PCI interface LOCK#. Signal s_lock_l is deasserted during

the first address phase of a transaction and is asserted one clock

cycle later by the 21154 when it is propagating a locked transaction

downstream. The 21154 does not propagate locked transactions

upstream. The 21154 continues to assert s_lock_l until th e address

phase of the next locked transaction, or until the lock is released.

When the lock is released, s_lock_l is driven to a deasserted state for

one cycle and then is sustained by an external pull-up resis tor.

s_perr_l STS

Secondary PCI interface PERR#. Signal s_perr_l is asserted when a

data parity error is detected for data received on the secondary

interface. The timing of s_perr_l correspond s to s_par driven one

cy cle earlier and s_ad dr iven two c y cles earlier. Signal s_perr_l is

as serted by the target during write transac tions, and by the ini tiato r

during read transactions. Wh en the secondary bus is idle, s_perr_l is

driven to a deasserted state for one cycle and then is sustained by an

external pull-up resistor.

s_serr_l I

Secondary PCI interface SERR#. Signal s_serr_l can be driven low by

any device exc ept the 21154 on the secondary bus to indicate a

system error condition. The 21154 samples s_serr_l as an input and

conditionally forwards it to the primary bus on p_serr_l. The 21 154

does not drive s_serr_l. Signal s_serr_l is pulled up through an

external resistor.

Table 6. Secondary PCI Bus Interface S ignals (Shee t 2 of 2)

Signal Name Type Description

21154 P CI-to-PCI Bridge

14 Datasheet

2.4 Secondary PCI Bus Interface 64-Bit Extension Signals

Table 7 describes the seconda ry PCI bus interface 64-bit extension signals.

Tab le 7. Secondary PCI Bus Interface 64-Bit Extension Signals

Signal Name Type Description

s_ad<63:32> TS

Secondary PCI interfac e addre ss/dat a upper 32 bits. This m ultiplexed

address and data bus prov ides an additional 32 bits to the s econdar y

interface. During the address phase or phases of a tr ansaction, when

the Dual Address command is used and s_req64_l is asserted, the

in itiator driv es the uppe r 32 bits of a 64- bit address; otherw ise these bits

are undefined and the initiator drives a v alid logic level onto these p ins.

During the data phases of a transaction, the initiator drives the upper 32

bi ts of 64-bit write data, or the target dr ives the upper 3 2 bits of 64-bit

read data, when s_req64_l and s_ack64_l are both asserted. When not

driven, s_ad<63:32> are pulled up to a valid logic level through external

resistors.

s_cbe_l<7:4> TS

Secondary PCI interface command/byte enables upper 4 bits. These

signals are a multiplexed command field and byte enable field. During

the address phase or phases of a t ransa ction , when the dual address

command is used and s_req64_l is asserted, the initiator will drive the

transaction type on s_cbe_l<7:4>; otherwise these bits are undefined

and the initiator drives a valid logic level onto the pins. For both reads

and write transactions, the initiator will drive byte enables for the

s _ad<63:32> data bits o n s_cbe_l<7:4> during the data phases when

s_req64_l and s_ack64_l are both asserted. When not driven,

s_cbe_l<7:4> is pulled up to a valid logic level through external resistors.

s_par64 TS

Seconda ry PCI interfac e upper 32-bits parity. Signal s_ par64 carries t he

even parity of the 36 bits of s_ad<63:32> and s_cbe_l<7:4> for both

address and dat a phases. Signal s_par64 is driven by the initi ator and is

valid on e cy cl e aft er the first add res s phas e when a dua l ad dr e s s

c ommand is used and s_ req64_l is asser ted. Signal s_par64 is also

valid on e clo c k cy c le after the sec o nd addres s phas e of a du al ad dr e s s

transaction when s_req64_l is asserted. Si gnal s_par64_l is valid o ne

cycle after valid data is driven (indicated by s_irdy_l assertion for write

data and s_trdy_l assertion for read data) and both s_req64_l and

s _ack64_l are asserted for that data phase. Signal s_par64 is driven by

the device driving read or write data one cycle after the s_ad lines are

driven. Signal s_par64 is tristated one cycle after the s_ad lines are

tristated. Devices receive data sample s_par64 as an input in order to

check for possible parity errors during 64-bit transactions. When not

driven, s_par64 is pulled up to a valid logic level through external

resistors.

s_req64_l STS

Secondary PCI interface request 64-bit transfer. Signal s_req64_l is

asserted by the initiator to indicate that the initiator is requesting a 64-bit

data transfer. Signal s_req64_l has the same timing as s_frame_l. The

21154 asserts s_req64_l low during reset, indicating that a 64-bit PCI

bus is s uppor t ed on th e b oa rd. Wh en d ea ss ert in g, s_ r eq 64_ l is d r iv en to

a deasserted state for one cycle and then sustained by an external pull-

up resistor .

s_ack64_l STS

Seconda ry PCI interface acknowledge 64-bit trans fer. Si gnal s_ack64_l

is asserted by the target only when s_req64_l is asserted by the initiator,

to indicate the target’s ability to transfer data using 64 bits. Signal

s _ack64_l has the same timing as s_devsel_l. When deasserting,

s _ack64_l is driven to a deasser ted state for one cycl e and th en

s ustained by an external pull-up resistor.

21154 PCI-to-PCI Bridge

Datasheet 15

2.5 Secondary Bus Arbitration Signals

Table 8 describes the secondary bus arbitration signa ls.

2.6 General-Purpose I/O Interface Signals

Table 9 describes the general-purpose I/O interface signals.

Table 8. Secondary PCI Bus Arbitrati on Signals

Signal Name Type Description

s_req_l<8:0> I

Secondary PCI interface REQ#s. The 21154 accepts nine request inputs,

s _req_l<8:0> , into its secondary bus arbiter. The 21154 request input to the

arbiter is an internal signal. Each reques t input ca n be programmed to be

in either a high priority rotating group or a low priority rotating group. An

asserted level on an s_req_l pin indicates that the corresponding master

wants to initiate a transaction on the secondary PCI bus. If the internal

arbiter is disabled (s_cfn_l tied high), s_req_l<0> is reconfigured to be an

ex ter n al sec on da ry gr a nt in pu t f or t he 2115 4. I n t hi s case , a n as sert e d le ve l

on s_req_l<0> indicates that the 21154 can start a transaction on the

s econdar y PCI bus if the bus is idle.

s_gnt_l<8:0> TS

Secondary PCI i nterface GNT#s. The 21154 secondary bus arbite r can

assert one of nine secondary bus grant outputs, s_gnt_l<8:0>, to indicate

that an initiator can start a transaction on the secondary bus if the bus is

idle. The 21154’s se condary bus grant is an internal signal. A

programmable 2- level r otating priority algorithm is used. If the internal

arbiter, s_cfn_l, i s disabled (tied high), s_gnt_l<0> is reconfigured to be an

external secondary bus request output for the 21154. The 21154 asserts

this signal whenev er it wa nts to start a transaction on the secondary bus.

s_cfn_l I

Secondary PCI central function enable. When tied low, s_cfn_l enables the

21154 secondary bus arbiter. When tied high, s_cfn_l disables the internal

arbiter. An ex ternal s econdary bus arbiter must then be used. Si gnal

s_req_l<0> is reconfigured to be the 21154 secondary bus grant input, and

s _gnt_l<0> is reconfigured to be the 21154 secondary b us request output,

when an external arbiter is used. Secondary bus parking is done when

s _req_l<0> is asserted, the secondary bus is idle, and the 21154 does not

want to init iate a transactio n.

Table 9. General-Purpose I/O Interface Signals

Signal Name Type Description

gpio<3:0> TS

General-pu rpose I/O data. Th ese four general-purpos e signals are

programmable as either input-only or bidirectional s ignals by wr iting the

gpio output enable control re gister in configuration space. T he value on

these signals is reflecte d in a gpio input dat a confi guration register when

read. Levels to be driven on gpio pins configured as bidirectional are

derived from the valu e written in the gpio output data configuration

During t he first 23 clock cycles (46 cycles when s_clk operates at 66 MHz)

while p_rst_l is deasserted and s_rst_l is asserted, the gpio signals are

used to control an external shift register that can shift in a serial clock

disable mask into the msk_in input. The gpio pins should not be driven by

software during these 23 clock cycles. The mask can then be read and

modified in the secondary cloc k control register in configuration space.

21154 P CI-to-PCI Bridge

16 Datasheet

2.7 Clo ck Si gn al s

Table 10 des cribes the clock signa ls.

2.8 R es et Si gn al s

Table 11 describes the reset signals.

Table 10. Clock Signals

Signa l N ame Typ e Descri ptio n

p_clk I

Primary interface PCI CLK. Provides timing for all transactions on the

primary PCI bus. All primary PCI inputs are sampled on the rising edge of

p_clk, and all prim ary PCI outputs are driven from the rising edge of p_clk.

Frequencies sup ported by the 2 1154 range from 0 MHz to 33 MHz, or

0 MHz to 66 MHz for a 66 MHz capable 21154.

s_clk I

Secondary interface PCI CLK. Provides timing for all transactions on the

secondary PCI bus. All secondary PCI inputs are sampled on the rising

edge of s_ clk, and all secondary PCI o utputs are driven from the rising

edge of s_clk. Frequencies supported by the 21 154 range from 0 MHz to 33

MHz, or 0 MHz to 66 MHz for a 66 MHz capable 21154 .

s_clk_o<9:0> O

Secondary interface PCI CLK outputs. Signals s_clk_o<9:0> are 10 clock

outputs generated from the primary interface clock input, p_clk. These

clocks operate at the same frequency of p_clk, or at half the frequency

when the primary bus frequ ency is 66 MHz and the secondary bus

frequency is 33 MH z.

When these clocks are us ed, one of the cloc k outputs must be fed back to

the secondary clock inpu t, s_clk. Unused clock outputs can be disabled

eit h er by u si ng t he seri al di sabl e mas k me cha ni sm (usi ng the gp io pin s an d

msk_in), or by writing the secondary clock disable bits in configuration

s p ace; otherwise, ter m inate them elec trically.

Tab le 11. Reset Signal s (Sheet 1 of 2)

Signa l N am e Type Descr ipt ion

bpcce1I

Bus/power clock control management pin. When signal bpcce is tied high

and the 21154 is placed in the D3hot power state, the 21154 places the

secondary bus in the B2 power state. The 21154 disables the secondary

clocks and driv es them to 0. When tied low, placin g the 21154 in the D3hot

power state has no effect on the secondary bus clocks.

p_rst_l I

Prima ry PCI bus RST#. Signal p_rst_l forc es the 21154 to a known state.

All register state is cleared, and all primary PCI bus outputs are tristated.

The 21154 samples p_req64_l during p_rst_l assertion to determine

whether the 64-bit extension is supported on the board. Signal p_rst_l is

as ynchronous to p_ clk.

21154 PCI-to-PCI Bridge

Datasheet 17

2.9 Misce llaneous Signals

Table 12 describe s the miscellaneous signals.

s_rst_l O

Se con da ry P CI bus RS T# . Si gn al s_ rst _l is dri ven by th e 2 1154 and act s a s

the PCI r eset for the second ary bus. The 21154 asserts s_rst_l when any

of the fol lowing conditions is met:

• Signal p_rst_l is asserted.

• The secondary reset bit in the bridge control register in configuration

space is set.

• The chip reset bit in the diagnostic control register in configuration

space is set.

When the 21154 asserts s _rst_l, it tristates all secondary control s ignals

and d riv e s ze r os on s_ ad , s_ cbe_ l, s_ par, an d s_ pa r 64 . The 2 115 4 also

as sert s s_req6 4_l dur ing re set, indicating that a 64-bit bus is s upported on

the secondary interfac e. Signal s _rst_l remains asserted until p_rst_l is

deasserted, the gpio serial clock mask has been shifted in, and the

s econdary reset b it is clear. Assertion of s_rst_ l by i tself does not clear

primary PCI interface.

1. For 21154–AB and later revisions only.

Table 11. Reset Signals (Sheet 2 of 2)

Signal Name Type Description

Table 12. Miscellaneous Signals (Sheet 1 of 2)

Signal Name Type Description

msk_in I

Secondary clock disable serial input. This input-only signal is used by the

hardwar e mechanism to disable secondary clock outputs. The s erial s tream

is re ce ived b y ms k_ in , s t art in g wh en p_ rs t is det e cted de ass er ted an d s _rst _ l

is detected asserted. This serial data is used for selectively disabling

secondary clock outputs and is shifted into the secondary clock control

configuration register. This input can be tied low to enable all secondary

c lock out puts, or tied high to drive al l s econdary clock outputs high .

p_vio I

Primary interface I/O voltage. This signal must be tied to either 3.3 V or 5 V,

corresponding to the signaling environment of the primary PCI bus as

des c ri bed i n th e

PC I Lo ca l Bus Sp eci f ic atio n

Re vi sion 2. 1

. Wh en an y d ev ice

on the primary PC I bus uses 5-V signaling levels, tie p_vio to 5 V. Signal

p_vio is tied to 3.3 V only when all the devices on the primary bus use 3.3-V

signaling levels.

s_vio I

Secondary interface I/O voltage. This signal must be tied to either 3.3 V or 5

V, corresponding to the signaling environment of the secondary PCI bus as

described in the

PCI Local Bus Specification, Revision 2.1

. When any device

on the secondary PCI bus uses 5-V signaling levels, tie s_vio to 5 V. Signal

s _vio is tied to 3.3 V only when all the devices on the secondary bus use 3.3-

V signaling levels.

21154 P CI-to-PCI Bridge

18 Datasheet

2.10 JTAG Signals

Table 13 describes the JTAG signals.

config66 I

Configure 66 MHz operation. This input only pin is used to spec ify if the

21 154 is capable of running at 66 MHz. If the pin is tied high, then the device

can be run at 66 MHz. If the pin is tied low, then the 21154 can only function

under the 33 MHz PCI specif ication.

p_m66ena I

Prima ry interface 66 M Hz enable. This input-only signal pin is used to

designat e the primary i nterface bus sp eed. Th is signal sho uld be pulled low

for 33 MHz operation on the primary bus. In this case , the s_m66ena pi n will

be driven low, forcing the secondary interface to also ru n at 33 MHz. For 66

MHz operation on the primar y bus, this signal shou ld be pulled high.

s_m66ena I/OD

Secondary interface 66 MHz enable. This signal pin is used to designate the

secondary interface bus speed. If the primary bus is operating at 33 MHz (i.e.

if p_m66ena is low), then the s_m66ena pin will be driven low by the 211 54

forcing the seco ndary bus to operate at 33 MHz. If the prima ry bus is

operating at 66 MHz, then the s_m 66ena pi n is an input and should be

ex ternally pulled high for the secon dary bu s to operate at 66 MHz or low for

the second ary bus to operate at 33 MHz.

Tab le 12. Miscella neous S ignals (Sheet 2 of 2)

Signa l N am e Type Desc r ipt ion

Table 13. JTAG Signals

Signa l N ame Typ e Descri ptio n

tdi I

J TAG serial data in. Signa l tdi is the serial in put th rough which JTA G

instructions and test data enter the JTAG interface. The new data on tdi is

s ample d o n t he risi ng ed ge of tc k. An un te r mi nate d t di pro du ces th e sa me

result as if tdi were driven high.

tdo O J TAG serial data out. Signal tdo is the s e rial o utput t hrough which t est

instructions and data from the test logic leave the 21154.

tms I J TAG test mode select. Signal tms cau s es stat e transitions in the test

access port (TAP) controller. An undriven tms has the same result as if it

were drive n high.

tck I JTAG boundary-scan clock. Signal tck is the clock controlling the JTAG

logic.

trst_l I

JT AG T AP reset. When asserted low , the T AP controller is asynchronously

forced to enter a reset state, which in turn asynchronously initializes other

test logic. An unterminated trst_l produces the same result as if it were

driven high. The TAP controller must be reset before the chip can function

in normal operating mode.

Datasheet 19

3.0 Pin Assign men t

This chapter describes the 21154 pin assignm ent and lists the pins according to location and in

alphabetic order.

Figure 5 shows the 21154 304-point bal l grid array, represent ing the pins in vertical rows la beled

alphabetical ly, and horizontal rows labeled numerically. Table 14 and Table 15 use this location to

identify pin assi gnments.

Figure 5. 21154 PBGA Cavi ty Down View

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20

21154

21 22 23

LJ-05554.AI4

Pin 1 Corner

Top View

(Pin Down)

21154 P CI-to-PCI Bridge

20 Datasheet

3.1 Numeric Pin Assignment

Table 14 lists th e 21 154 pi ns in orde r of locat ion , showin g the locati on co de, name, and signal type

of ea ch pin .

Figure 5 prov ides t he map for ide ntifying the pin locat ion codes, listed in alpha betic o r der in the

PB G A L oc at io n co lumn in Table 14.

The following table defines the signal type abbreviations used in the Type column in Table 14.

Signa l Ty pe De sc ript ion

I Standard input only.

O S tan da rd outp ut on ly.

PPower.

TS Tristate bidirectional.

STS Sustained tristate. Active low signal must be pulled high for one cycle when

deasserting.

OD Stan da r d op en drain.

Tab le 14. 21154 PBGA Pin List (Sheet 1 of 6)

PB GA

Locati on Pi n Name Type PBGA

Location Pin Name Type

A1 vss P A2 vdd P

A3 s_ad<30> TS A4 s_ad<27> TS

A5 vss P A6 s_ad<23> TS

A7 s_ad<22> TS A8 s_ad<19> TS

A9 s_ad<16> TS A10 s_trdy_l STS

A11 s_lock_l STS A12 vss P

A13 s_ad<13> TS A14 s_m66ena OD

A15 s_cbe_l<0> TS A16 vss P

A17 s_ad<2> TS A18 s_ad<0> TS

A19 s_cbe_l<7> TS A20 s_cbe_l<5> TS

A21 s_ad<62> TS A22 vdd P

A23 vss P —— —

B1 vdd P B2 vss P

B3 s_ad<29> TS B4 s_ad<26> TS

B5 s_ad<24> TS B6 vddvdd P

B7 s_ad<20> TS B8 s_ad<18> TS

B9 s_frame_l STS B10 s_devsel_l STS

B11 s_serr_l I B12 s_par TS

B13 s_ad<14> TS B14 s_ad<10> TS

B15 s_ad<8> TS B16 s_ad<6> TS

21154 PCI-to-PCI Bridge

Datasheet 21

B17 s_ad<4> TS B18 s_ad<1> TS

B19 s_req64_l STS B20 vdd P

B21 vss P B22 vss P

B23 vdd P —— —

C1 s_req_l<1> I C2 s_req_l<2> I

C3 s_ad<31> TS C4 s_ad<28> TS

C5 s_ad<25> TS C6 s_cbe_l<3> TS

C7 vss P C8 s_ad<17> TS

C9 s_irdy_l STS C10 s_stop_l STS

C11 s_perr STS C12 s_cbe_l<1> TS

C13 s_ad<15> TS C14 s_ad<11> TS

C15 s_ad<9> TS C16 s_ad<7> TS

C17 s_ad<5> TS C18 s_ack64_l STS

C19 s_cbe_l<6> TS C20 s_ad<63> TS

C21 s_ad<60> TS C22 s_ad<58> TS

C23 s_ad<59> TS — — —

D1 s_req_l<5> I D2 s_req_l<6> I

D3 s_req_l<3> I D4 s_req_l<0> I

D5 vdd P D6 vdd P

D7 s_ad<21> TS D8 vss P

D9 s_cbe_l<2> TS D10 vdd P

D11 vdd P D12 vss P

D13 s_ad<12> TS D14 vdd P

D15 vdd P D16 vss P

D17 s_ad<3> TS D18 vdd P

D19 s_cbe_l<4> TS D20 s_ad<61> TS

D21 s_ad<57> TS D22 s_ad<55> TS

D23 vss P — — —

E1 s_req_l<8> I E2 s_gnt_l<0> TS

E3 s_req_l<7> I E4 s_req_l<4> I

— — — E20 s_ad<56> TS

E21 s_ad<54> TS E22 vdd P

E23 s_ad<53> TS — — —

F1 s_gnt_l<2> TS F2 s_gnt_l<3> TS

F3 s_gnt_l<1> TS F4 vss P

—— —F20vss P

F21 s_ad<52> TS F22 s_ad<50> TS

Table 14. 21154 PBGA P in List (S h eet 2 of 6)

PBGA

Locati on Pin Name Type PBGA

Location Pin Name Type

21154 P CI-to-PCI Bridge

22 Datasheet

F23 s_ad<51> TS —— —

G1 s_gnt_l<4> TS G2 s_gnt_l<6> TS

G3 s_gnt_l<7> TS G4 s_gnt_l<5> TS

— G20 s_ad<49> TS

G21 s_ad<47> TS G22 s_ad<48> TS

G23 vss P — — —

H1 s_gnt_l<8> TS H2 s_rst_l O

H3 vss P H4 vdd P

—— —H20vdd P

H21 s_ad<44> TS H22 s_ad<45> TS

H23 s_ad<46> TS — — —

J1 vdd P J2 vss P

J3 vdd P J4 s_clk I

— — — J20 s_ad<42> TS

J21 vdd P J22 s_ad<41> TS

J23 s_ad<43> TS — — —

K1 s_cfn_l I K2 gpio<3> TS

K3 gpio<2> TS K4 vss P

— — — K20 vss P

K21 s_ad<38> TS K22 s_ad<39> TS

K23 s_ad<40> TS — — —

L1 gpio<0> TS L2 s_clk_o<0> O

L3 s_clk_o<1> O L4 gpio<1> TS

— — — L20 vss P

L21 s_ad<36> TS L22 s_ad<35> TS

L23 s_ad<37> TS — — —

M1 s_clk_o<3> O M2 s_clk_o<4> O

M3 s_clk_o<2> O M4 vdd P

—— —M20vdd P

M21 s_ad<32> TS M22 s_ad<34> TS

M23 s_ad<33> TS — — —

N1 s_clk_o<6> O N2 vss P

N3 s_clk_o<5> O N4 vdd P

—— —N20tck I

N21 s_par64 TS N22 s_vio I

N23 trst_l I — — —

P1 s_clk_o<9> O P2 s_clk_o<8> O

Tab le 14. 21154 PBGA Pin List (Sheet 3 of 6)

PB GA

Locati on Pi n Name Type PBGA

Location Pin Name Type

21154 PCI-to-PCI Bridge

Datasheet 23

P3 s_clk_o<7> O P4 vss P

—— —P20vss P

P21 tms I P22 tdo O

P23 tdi I — — —

R1 vdd P R2 p_gnt_l I

R3 p_rst_l I R4 bpcce1I

—— —R20p_vio I

R21 msk_in I R22 config66 I

R23 vdd P — — —

T1 vdd P T2 vss P

T3 p_clk I T4 vdd P

—— —T20vdd P

T21 p_par64 TS T22 p_ad<32> TS

T23 p_ad<33> TS — — —

U1 p_ad<29> TS U2 p_ad<31> TS

U3 p_req_l TS U4 p_ad<30> TS

— — — U20 p_ad<35> TS

U21 vss P U22 p_ad<34> TS

U23 p_ad<36> TS — — —

V1 p_ad<27> TS V2 p_ad<28> TS

V3 p_ad<26> TS V4 vss P

—— —V20vss P

V21 p_ad<39> TS V22 p_ad<37> TS

V23 p_ad<38> TS — — —

W1 p_ad<24> TS W2 p_ad<25> TS

W3 vdd P W4 p_ad<23> TS

— — — W20 p_ad<44> TS

W21 p_ad<42> TS W22 p_ad<40> TS

W23 p_ad<41> TS — — —

Y1 p_idsel I Y2 p_cbe_l<3> TS

Y3 p_ad<22> TS Y4 p_ad<19> TS

Y5 p_ad<16> TS Y6 vdd P

Y7 p_serr_l OD Y8 vss P

Y9 vss P Y10 vdd P

Y11 p_ad<8> TS Y12 vss P

Y13 p_ad<1> TS Y14 vdd P

Y15 p_cbe_l<5> TS Y16 vss P

Table 14. 21154 PBGA P in List (S h eet 4 of 6)

PBGA

Locati on Pin Name Type PBGA

Location Pin Name Type

21154 P CI-to-PCI Bridge

24 Datasheet

Y17 p_ad<59> TS Y18 vdd P

Y19 p_ad<52> TS Y20 p_ad<47> TS

Y21 p_ad<45> TS Y22 vdd P

Y23 p_ad<43> TS —— —

AA1 p_ad<21> TS AA2 vss P

AA3 p_ad<20> TS AA4 p_ad<17> TS

AA5 p_frame_l STS AA6 p_devsel_l STS

AA7 p_cbe_l<1> TS AA8 p_ad<14> TS

AA9 p_ad<11> TS AA10 p_ad<9> TS

AA11 p_ad<6> TS AA12 p_ad<5> TS

AA13 p_ad<2> TS AA14 p_ad<0> TS

AA15 p_cbe_l<7> TS AA16 p_ad<63> TS

AA17 p_ad<61> TS AA18 p_ad<56> TS

AA19 p_ad<54> TS AA20 p_ad<51> TS

AA21 p_ad<48> TS AA22 vss P

AA23 p_ad<46> TS — — —

AB1 vdd P AB2 vss P

AB3 p_ad<18> TS AB4 p_cbe_l<2> TS

AB5 p_trdy_l STS AB6 p_lock_l I

AB7 p_par TS AB8 p_ad<15> TS

AB9 p_ad<12> TS AB10 p_m66ena I

AB11 p_ad<7> TS AB12 p_ad<4> TS

AB13 p_ad<3> TS AB14 p_ack64_l STS

AB15 p_cbe_l<6> TS AB16 p_ad<62> TS

AB17 p_ad<60> TS AB18 p_ad<58> TS

AB19 vdd P AB20 p_ad<53> TS

AB21 p_ad<50> TS AB22 vss P

AB23 vdd P — — —

AC1 vss P AC2 vdd P

AC3 vdd P AC4 vss P

AC5 p_irdy_l STS AC6 p_stop_l STS

AC7 p_perr_l STS AC8 vdd P

AC9 p_ad<13> TS AC10 p_ad<10> TS

AC11 p_cbe_l<0> TS AC12 vdd P

AC13 vss P AC14 p_req64_l STS

AC15 p_cbe_l<4> TS AC16 vdd P

AC17 vss P AC18 p_ad<57> TS

Tab le 14. 21154 PBGA Pin List (Sheet 5 of 6)

PB GA

Locati on Pi n Name Type PBGA

Location Pin Name Type

21154 PCI-to-PCI Bridge

Datasheet 25

3.2 Pins Listed in Alphabetic Order

Table 15 lis ts the 2 1 1 54 pins in alphabe ti c order, showi ng the nam e, lo catio n code , and signa l t ype

of each pin.

Figure 5 provides the map for identifying the pin loca tion codes.

The following table defines the signal type abbreviations used in the Type column in Tabl e 15.

AC19 p_ad<55> TS AC20 vss P

AC21 p_ad<49> TS AC22 vdd P

AC23 vss P —— —

1. Pertains to the 21154–AB and later revisions only. For the 21154–AA, this pin is vss.

Table 14. 21154 PBGA P in List (S h eet 6 of 6)

PBGA

Locati on Pin Name Type PBGA

Location Pin Name Type

Signal Type Description

I Standard input only.

O Standard output only.

PPower.

TS Trista te bi di rec ti on al.

STS Sustained tr istate. Act ive low signal must be pulled high for on e cycle when

deasserting.

OD S tandard open drain.

Table 15. 21154 PBGA P in List (S h eet 1 of 5)

Pin Name PBGA

Location Type Pin Name PBGA

Location Type

bpcce1R4 I p_ad<4> AB12 TS

config66 R22 I p_ad<5> AA12 TS

gpio<0> L1 TS p_ad<6> AA11 TS

gpio<1> L4 TS p_ad<7> AB11 TS

gpio<2> K3 TS p_ad<8> Y11 TS

gpio<3> K2 TS p_ad<9> AA10 TS

msk_in R21 I p_ad<10> AC10 TS

p_ack64_l AB14 STS p_ad<11> AA9 TS

p_ad<0> AA14 TS p_ad<12> AB9 TS

p_ad<1> Y13 TS p_ad<13> AC9 TS

p_ad<2> AA13 TS p_ad<14> AA8 TS

p_ad<3> AB13 TS p_ad<15> AB8 TS

21154 P CI-to-PCI Bridge

26 Datasheet

p_ad<16> Y5 TS p_ad<53> AB20 TS

p_ad<17> AA4 TS p_ad<54> AA19 TS

p_ad<18> AB3 TS p_ad<55> AC19 TS

p_ad<19> Y4 TS p_ad<56> AA18 TS

p_ad<20> AA3 TS p_ad<57> AC18 TS

p_ad<21> AA1 TS p_ad<58> AB18 TS

p_ad<22> Y3 TS p_ad<59> Y17 TS

p_ad<23> W4 TS p_ad<60> AB17 TS

p_ad<24> W1 TS p_ad<61> AA17 TS

p_ad<25> W2 TS p_ad<62> AB16 TS

p_ad<26> V3 TS p_ad<63> AA16 TS

p_ad<27> V1 TS p_cbe_l<0> AC11 TS

p_ad<28> V2 TS p_cbe_l<1> AA7 TS

p_ad<29> U1 TS p_cbe_l<2> AB4 TS

p_ad<30> U4 TS p_cbe_l<3> Y2 TS

p_ad<31> U2 TS p_cbe_l<4> AC15 TS

p_ad<32> T22 TS p_cbe_l<5> Y15 TS

p_ad<33> T23 TS p_cbe_l<6> AB15 TS

p_ad<34> U22 TS p_cbe_l<7> AA15 TS

p_ad<35> U20 TS p_clk T3 I

p_ad<36> U23 TS p_devsel_l AA6 STS

p_ad<37> V22 TS p_frame_l AA5 STS

p_ad<38> V23 TS p_gnt_l R2 I

p_ad<39> V21 TS p_idsel Y1 I

p_ad<40> W22 TS p_irdy_l AC5 STS

p_ad<41> W23 TS p_lock_l AB6 STS

p_ad<42> W21 TS p_m66ena AB10 I

p_ad<43> Y23 TS p_par AB7 TS

p_ad<44> W20 TS p_par64 T21 TS

p_ad<45> Y21 TS p_perr_l AC7 STS

p_ad<46> AA23 TS p_req_l U3 TS

p_ad<47> Y20 TS p_req64_l AC14 STS

p_ad<48> AA21 TS p_rst_l R3 I

p_ad<49> AC21 TS p_serr_l Y7 OD

p_ad<50> AB21 TS p_stop_l AC6 STS

p_ad<51> AA20 TS p_trdy_l AB5 STS

p_ad<52> Y19 TS p_vio R20 I

Tab le 15. 21154 PBGA Pin List (Sheet 2 of 5)

Pin Name PBGA

Location Type Pin Name PBGA

Location Type

21154 PCI-to-PCI Bridge

Datasheet 27

s_ack64_l C18 STS s_ad<36> L21 TS

s_ad<0> A18 TS s_ad<37> L23 TS

s_ad<1> B18 TS s_ad<38> K21 TS

s_ad<2> A17 TS s_ad<39> K22 TS

s_ad<3> D17 TS s_ad<40> K23 TS

s_ad<4> B17 TS s_ad<41> J22 TS

s_ad<5> C17 TS s_ad<42> J20 TS

s_ad<6> B16 TS s_ad<43> J23 TS

s_ad<7> C16 TS s_ad<44> H21 TS

s_ad<8> B15 TS s_ad<45> H22 TS

s_ad<9> C15 TS s_ad<46> H23 TS

s_ad<10> B14 TS s_ad<47> G21 TS

s_ad<11> C14 TS s_ad<48> G22 TS

s_ad<12> D13 TS s_ad<49> G20 TS

s_ad<13> A13 TS s_ad<50> F22 TS

s_ad<14> B13 TS s_ad<51> F23 TS

s_ad<15> C13 TS s_ad<52> F21 TS

s_ad<16> A9 TS s_ad<53> E23 TS

s_ad<17> C8 TS s_ad<54> E21 TS

s_ad<18> B8 TS s_ad<55> D22 TS

s_ad<19> A8 TS s_ad<56> E20 TS

s_ad<20> B7 TS s_ad<57> D21 TS

s_ad<21> D7 TS s_ad<58> C22 TS

s_ad<22> A7 TS s_ad<59> C23 TS

s_ad<23> A6 TS s_ad<60> C21 TS

s_ad<24> B5 TS s_ad<61> D20 TS

s_ad<25> C5 TS s_ad<62> A21 TS

s_ad<26> B4 TS s_ad<63> C20 TS

s_ad<27> A4 TS s_cbe_l<0> A15 TS

s_ad<28> C4 TS s_cbe_l<1> C12 TS

s_ad<29> B3 TS s_cbe_l<2> D9 TS

s_ad<30> A3 TS s_cbe_l<3> C6 TS

s_ad<31> C3 TS s_cbe_l<4> D19 TS

s_ad<32> M21 TS s_cbe_l<5> A20 TS

s_ad<33> M23 TS s_cbe_l<6> C19 TS

s_ad<34> M22 TS s_cbe_l<7> A19 TS

s_ad<35> L22 TS s_cfn_l K1 I

Table 15. 21154 PBGA P in List (S h eet 3 of 5)

Pin Name PBGA

Location Type Pin Name PBGA

Location Type

21154 P CI-to-PCI Bridge

28 Datasheet

s_clk J4 I s_req64_l B19 STS

s_clk_o<0> L2 O s_rst_l H2 O

s_clk_o<1> L3 O s_serr_l B11 I

s_clk_o<2> M3 O s_stop_l C10 STS

s_clk_o<3> M1 O s_trdy_l A10 STS

s_clk_o<4> M2 O s_vio N22 I

s_clk_o<5> N3 O tck N20 I

s_clk_o<6> N1 O tdi P23 I

s_clk_o<7> P3 O tdo P22 O

s_clk_o<8> P2 O tms P21 I

s_clk_o<9> P1 O trst_l N23 I

s_devsel_l B10 STS vdd A2 P

s_frame_l B9 STS vdd A22 P

s_gnt_l<0> E2 TS vdd B1 P

s_gnt_l<1> F3 TS vdd B6 P

s_gnt_l<2> F1 TS vdd B20 P

s_gnt_l<3> F2 TS vdd B23 P

s_gnt_l<4> G1 TS vdd D5 P

s_gnt_l<5> G4 TS vdd D6 P

s_gnt_l<6> G2 TS vdd D10 P

s_gnt_l<7> G3 TS vdd D11 P

s_gnt_l<8> H1 TS vdd D14 P

s_irdy_l C9 STS vdd D15 P

s_lock_l A11 STS vdd D18 P

s_m66ena A14 OD vdd E22 P

s_par B12 TS vdd H4 P

s_par64 N21 TS vdd H20 P

s_perr_l C11 STS vdd J1 P

s_req_l<0> D4 I vdd J3 P

s_req_l<1> C1 I vdd J21 P

s_req_l<2> C2 I vdd M4 P

s_req_l<3> D3 I vdd M20 P

s_req_l<4> E4 I vdd N4 P

s_req_l<5> D1 I vdd R1 P

s_req_l<6> D2 I vdd R23 P

s_req_l<7> E3 I vdd T1 P

s_req_l<8> E1 I vdd T4 P

Tab le 15. 21154 PBGA Pin List (Sheet 4 of 5)

Pin Name PBGA

Location Type Pin Name PBGA

Location Type

21154 PCI-to-PCI Bridge

Datasheet 29

vdd T20 P vss F4 P

vdd W3 P vss F20 P

vdd Y6 P vss G23 P

vdd Y10 P vss H3 P

vdd Y14 P vss J2 P

vdd Y18 P vss K4 P

vdd Y22 P vss K20 P

vdd AB1 P vss L20 P

vdd AB19 P vss N2 P

vdd AB23 P vss P4 P

vdd AC2 P vss P20 P

vdd AC3 P vss T2 P

vdd AC8 P vss U21 P

vdd AC12 P vss V4 P

vdd AC16 P vss V20 P

vdd AC22 P vss Y8 P

vss A1Pvss Y9P

vss A5 P vss Y12 P

vss A12 P vss Y16 P

vss A16 P vss AA2 P

vss A23 P vss AA22 P

vss B2 P vss AB2 P

vss B21 P vss AB22 P

vss B22 P vss AC1 P

vss C7 P vss AC4 P

vss D8 P vss AC13 P

vss D12 P vss AC17 P

vss D16 P vss AC20 P

vss D23 P vss AC23 P

1. Pertains to the 21154–AB and later revisions only. For the 21154–AA, this pin is vss.

Table 15. 21154 PBGA P in List (S h eet 5 of 5)

Pin Name PBGA

Location Type Pin Name PBGA

Location Type

Datasheet 31

4.0 PCI Bus Operation

This chapter pre sents detailed inform ation about PCI trans actions , transaction forwardi ng across

the 21154, and transaction termination. S ection 4.1 through Section 4.7 describe 32-bit tr ans action

operation. Section 4.8 descri bes specia l considerations for 64-bi t transaction operat ion.

4.1 Types of Transactions

This section provides a sum m ary of PCI transactions performed by the 21154. Table 16 list s the

command code and na me of each PCI transaction. The Master and Targe t columns indica te 21154

support for each transaction when the 21154 initiat es transactions as a master, on the primary bus

and on the secondary bus , and when t he 21154 respo nds to tra ns actions as a target, on the primary

bus and on the secondary bus .

As indicated in Table 16, the f ollowing PCI commands are not s upported by the 21154:

•The 21 154 ne ve r initia tes a PCI transact io n with a reserv ed comman d code and, as a t ar get, the

21154 ignore s re served command codes.

•The 21154 never initiates an interrupt acknowle dge transacti on and, as a ta rget, th e 21154

ignores in terrupt acknowle dge transactions . Interrupt acknowledge transactions are expected

to reside e n tirely on the primar y PCI bus closest to the host bri dge.

•The 21154 does not respond to spec ial cycle transactions. The 21154 cannot guarantee

delivery of a special cyc le trans action to downstream buses beca use of the broadcast na ture of

th e specia l cy cle command and th e in ability to con tr o l t h e transaction as a tar g et. To gen erate

Table 16. 21154 PCI Transactions

Type of Transaction 21 154 Initiates As Master

Primary Secondary 21 154 Responds As Target

Primary Secondary

0000 Interrupt acknowledge No No No No

0001 Special cycle Yes Y es No No

0010 I/O read Yes Yes Yes Yes

0011 I/O write Yes Yes Yes Yes

0100 Reserved No No No No

0101 Reserved No No No No

0110 Memory read Yes Yes Yes Yes

0111 Memory write Yes Yes Yes Yes

1000 Reserved No No No No

1001 Reserved No No No No

1010 Configuration read No Yes Y es No

1011 Configuration write Type 1 Yes Yes Type 1

1100 Memory read multiple Yes Yes Yes Yes

1101 Dual address cycle Yes Yes Yes Yes

1110 Memory read lin e Yes Yes Ye s Yes

1111 Memory write and invalidate Yes Yes Yes Yes

21154 P CI-to-PCI Bridge

32 Datasheet

spe cial cycle transact ions on other PCI bus es , either upstr ea m or downstream, a Type 1

configuration command m ust be used.

•The 21154 does not generate Type 0 configuration transactions on the primary interface, nor

does it respond to Type 0 con figuration transacti ons on the secondary PCI interface. The PCI-

to-PCI Bridge Ar chitecture Specification does not support configurat ion from the secondary

bus.

4.2 Address Phase

The standard PCI transaction consists of one or two address phases, followed by one or more data

phas es. An address phase alwa ys las ts one PCI cloc k cyc le. The first address phase is designated

by a n a ss er ti ng ( f alli ng) edg e on th e FR A M E# s ign al.

The numbe r of address phas es depends on whether t he address is 32 bits or 64 bits.

4.2.1 Single Address Phase

A 32-bit address uses a single address phas e. This address is driven on AD<31: 0>, and the bus

com ma nd is driven on C/BE#<3:0>.

The 21154 supports the linear increment address mode only, which is indic ated when the low 2

address bits are equal to 0. If eithe r of the low 2 address bits is nonzero, the 21154 automatically

d isconnects the tr ansaction af ter the fir st data tr ansfe r.

4.2.2 Dual Address Phase

Dual address transactions are PCI transactions that contain two address phases specifying a 64-bit

address.

The firs t address phase is denoted by the a s se rting edge of FRAME#.

The second address phase always follows on the next cloc k cycle.

For a 32-bit interface , the first address phase contains the dua l address comma nd code on the C/

BE#<3:0> lines, and the low 32 a ddress bits on the AD<31:0> lin es. The second addre ss phase

cons ists of the specific memory transaction command code on the C/BE#< 3:0> lines, and the high

32 address bits on the AD<3 1:0> lines. In this way, 64-bit address ing can be supported o n 32-bit

PCI buses.

The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in

t h e prefetchabl e memory r ang e o n ly. Se e Section 5.3.3 for a discussion of prefetchable address

spa ce. The 21154 suppor ts dual addre s s tra nsacti ons in both the upstream and the downstr eam

direction. The 21154 supports a programm able 64-bi t address range in prefetchable memory for

downs tream f orwarding of dua l addres s tran saction s. Dual address tr ansa ctions fal li ng outsi de the

pr efetchable address range are forwarded upstrea m, but not downs tream. Prefetchi ng and posting

are perfo rme d in a manner cons iste nt wi th the g uide li nes gi ven in th is s pecif ica ti on for e ach ty pe of

memory transaction in prefetchable memory sp ace.

The 21154 responds only to dual address t r ansactions tha t us e the foll owing tr ansaction comman d

codes:

•Memory write

21154 PCI-to-PCI Bridge

Datasheet 33

•Memory write and invalidate

•Memory read

•Memory read line

•Memory read multiple

Use of other transaction codes may result in a master abort.

Any me m ory transactions address ing the first 4GB space should use a single address phase; th at is,

the high 32 bits of a dua l address transaction should never be 0.

4.3 Device Select (DEVSEL#) Generation

The 21154 always perform s positive address decoding when acce pting transacti ons on either the

primar y or secondar y buses. The 21154 never subtractivel y decodes. Medium DEVSEL# timing is

used on both interfaces.

4.4 Data Phase

The addres s phase or phas es of a PCI transaction are followed by one or more data phas es . A data

phas e is completed when IRDY# and either TRDY# or STOP# ar e a sserted. A transfer of data

occurs only when both IRDY# and TRDY# are as serted during the s am e PCI cl ock cycl e. The las t

data phase of a transa ction is indi cated when FRAME# is deass erted and both TRDY# and IRDY#

are asserted, or when IRDY# and STOP# are asserted. See Section 4.10 for further discussion of

tr ansaction termination.

Depending on the command type, the 21154 can su pport mul tiple data phase PCI transacti ons. For

a detaile d description of how the 21154 imposes disconnect boundaries, see Section 4.5.4 for a

description of write address boundaries and Section 4.6.3 for a description of read address

boundaries.

4.5 Write Transactions

W rite transactions are treated as either poste d wr ite or delaye d wr ite trans actions.

Table 17 shows the m ethod of forwarding used for each type of write operation.

Table 17. Write T r ansaction Forwarding

Type of Transaction Type of Forwarding

Memory write Posted

Memory write and invalidate Posted

I/O write Delayed

Type 1 configuration write Delayed

21154 P CI-to-PCI Bridge

34 Datasheet

4.5.1 Posted Write Transactions

Posted write forwarding is use d for memor y write and for mem ory write and invalidate

transactions.

When the 21154 determines that a memory write transaction is to be forwarded across the bridge,

the 21154 as serts DE VSEL# with medium ti ming and TRDY# in the same cycle, provided that

enough buffer space is av ailable in the posted data queue for the ad dres s and at leas t 8 Dwor ds of

data. This enables the 21154 to accept write da ta without obtaining access to the target bus. The

21154 ca n acce p t 1 Dw o r d o f wr it e dat a ev ery P C I clo ck c y cl e; th at is, n o ta rg et wa i t sta te s ar e

inserted. This write data is stored in internal posted write buffers and is subseque ntly delivered to

the target.

The 21154 continues to accept write da ta until one of the following events occurs:

•The initiator terminates the tra nsaction by deasserting FRAME# and IRDY#.

•An internal write address boundary is reached, such as a cache line boundary or an aligned

4KB boundary, depending on the transaction type.

•The posted write data buffer fills up.

When one of the last two events occurs , the 21154 returns a tar get disconnect to the requesting

in itiator on this d ata phase to terminate the transaction.

Once the post ed write d ata moves to t he he ad of the posted d ata que ue, the 211 54 ass erts its re quest

on the tar get bus. This can occur while the 21154 is s till receiving data on the initiator bus. When

the grant for the target bus is re ce ived and the target bus is detected in the idle condition, the 21154

asserts FRAME# and dr ives the st or ed write address out on the tar get bu s. On the following cycl e,

th e 21154 drives the f ir st Dword of write data and continues to transfer write data until all write

data corresponding to that transaction is de livered, or until a target termi nation is received. As long

as write data exis ts in the queue, the 21154 can drive 1 Dword of write data each PCI clock cycle;

tha t is, no mas ter wa it sta tes ar e ins erte d. I f write da ta is fl owing thr ough t he 21154 and t he in itia tor

stal ls, the 21154 may have to insert wait states on the target bus if the queue empties.

Figure 6 shows a memory write transact ion in flow-through mode, where data is being remove d

f rom buffers on the target interfa ce while more data is being transferred int o the buffers on the

master interface.

21154 PCI-to-PCI Bridge

Datasheet 35

The 21154 ends the tra nsaction on the target bus when one of the followi ng conditions is met:

•Al l posted w r it e d ata ha s be en de li v e r e d to th e targ et .

•The target retu rns a target disconnect or target retry (the 21154 starts another transaction to

deliver the r es t of the write data).

•The target retu rns a target abort (the 21154 discard s re maining write data).

•The master latenc y timer expires, and the 21154 no longer has the target bus grant (the 21154

st ar t s an oth er tr a nsacti on to deli v e r remain i n g w r ite d at a ) .

Section 4.10.3. 2 provides det ailed information about how the 21 154 responds to target termination

dur ing posted write transactions.

4.5.2 Memory Write and Invalidate Transactions

Poste d write forwar ding is used for memory write and invalidate transactions.

Memory write and invalidate transactions guarant ee transf er of ent ire cache lines. If the write

buf fer fills befor e an entire cache lin e is transf erre d, the 21154 disconnect s the trans action and

converts it to a memory write transact ion.

Figure 6. Flow-Th rough Posted Memo ry Write Tran saction

86%

LJ-04843.AI4

p_frame_l

p_cbe_l

p_ad

p_irdy_l

p_devsel_l

p_trdy_l

p_stop_l

s_frame_l

s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

s_clk

Cycle CY0

< 15ns >

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14 CY15 CY16 CY17

Addr Data Data Data Data Data Data Data Data

7 Byte Enables

Byte Enables

Addr

Data Data

DataData

Data Data Data Data Data Data Data Data

21154 P CI-to-PCI Bridge

36 Datasheet

The 21154 disconnects memory write and invalidate commands at aligned cache line boundaries.

The cache line size value in the 21154 cache line size register gives the number of Dwords in a

cac he line . For the 21 154 to gene rate memory write and inva li date tra nsacti ons , this c ache li ne size

value mus t be writt en to a value t hat is a no nzero po wer of 2 and les s than or equal to 16 (that is, 1,

2, 4, 8 , or 16 D wo r ds).

I f the cache line size does not m eet the memory write and invalidate conditions, tha t is, the val ue is

0, or is not a power of 2, or is greater tha n 16 Dwords, the 21154 treats the memory write and

invalidate command as a memory write command. In this case, when the 21154 forwards the

me mory write and invalidate transacti on to the tar get bus, it converts the c ommand code to a

memory write code and does not obs erve cache li ne boundaries.

I f the value in the cac he line siz e register does meet the memory write and invalidate conditions,

tha t is, th e value is a nonzer o power of 2 less tha n or equal to 16 Dwords , the 21154 return s a tar get

dis connect to the i nitiator either on a cache line boundary or when the posted write buf f er fills. For

a cache line size of 16 Dwords, the 21154 disconnects a memory write and invalidate transaction

on every cache line boundary. When the cache line size is 1, 2, 4, or 8 Dwords, the 21154 accepts

another cac he line if at least 8 Dwords of empty space remains in the poste d write bu ffer. If less

than 8 Dwords of empty space remains , the 21154 disconnects on that cache line boundary.

When the memory write and invalida te transaction is disconnected b efore a cache line boundary is

reached, typica lly because the posted write buffer fills, the transaction is conve rted to a memory

wr it e tr ansac tio n.

4.5.3 Delayed Write Transactions

Delayed write forwarding is used for I/O write transacti ons and for Type 1 con f iguration writ e

t ran sactions.

A del aye d wr i te tra nsact io n gu ar ant e es th at th e ac tu al ta rg et re s p on se is re tu r n ed back to th e

in itiator without holding the initiating bus in wait states. A delaye d wr ite transac tion is limited to a

sing le D w ord da ta transf e r.

When a write transaction is first detected on the initiator bus, and the 21154 forwards it as a

dela yed transaction, the 21154 claims the access by asserting DE VSEL# and returns a ta rget retry

to the initiator. During the addre ss phase, the 21154 samples the bus command, add r es s , and

addre ss parity one cycl e late r. After IRDY# is assert ed, the 21154 also sample s the fi rst data

Dword, byte enable bits, and data parity. This inform ation is placed into the delayed transaction

qu eue. The transaction is queued onl y if no other existing delaye d tr ansactions have th e sam e

address and command, and if th e delayed tra ns action queue is not full. When the delayed write

tr ansact ion move s to the head of the delayed tra nsacti on queue and all ordering constraints with

p o sted data are satisf ied (see Section 6.0), the 21154 initiates the t r ansaction on the target bus. The

2 1154 tr ansfers the wri te data to the tar get.

I f the 21154 r eceiv es a ta rg et ret ry in respo nse to the writ e tr ansact ion on t he t arge t b us, i t conti nues

to repeat the write transac tion until the data transfer is completed, or until an error condition is

encountered.

I f the 21154 is una ble to del iver write data aft er 224 at te m p t s, th e 2 115 4 ce ases fu r t h er write

attempts and returns a target abort to the initiator. The delayed tr ansaction is re move d f r o m the

delayed t r ansactio n queue. The 21154 also asserts p_serr_l if the primar y SERR# enable bit is se t

in the command register. See S ection 7.4 for information on the as sertion of p_serr_l.

21154 PCI-to-PCI Bridge

Datasheet 37

When t h e in itiator repeats th e same write transacti o n (sam e command, address, by te enabl e bits,

and data), and the completed delayed transaction is at the head of the queue, th e 21154 claims the

access by as se r ting DEVSEL# and returns TRDY# to the initiator, to indicate that the write da ta

was trans ferred . If the initiator requests mult iple Dwords, the 21154 al s o as serts STOP # in

conju nct ion with TRDY# to sig nal a tar ge t dis connec t. Not e t hat onl y th ose by tes o f writ e data wit h

valid byte ena ble bits are compared. If any of the byte enable bits are turned off (driven hi gh), the

corresponding byte of write data is not compared.

If the initia tor repeats the write transaction before the d ata has been transferred to the ta rget, the

21154 return s a target retry to the initiator. The 21154 continues to return a t arget retry to the

initiator unt il write data is delivered to the target, or until an error condition is encountered. When

the write transa ction is repeated, the 21154 does not make a new ent r y into the delayed transaction

queue. Section 4.10.3.1 provides detailed information about how the 21154 responds to target

term ination during delayed write trans ac tions.

Figure 7 shows a delayed write transaction forwarded downstream across the 21154.

Figure 7. Downstream D elayed Write Transaction

LJ-04844.AI4

p_frame_l

p_cbe_l

p_ad

p_irdy_l

p_devsel_l

p_trdy_l

p_stop_l

s_frame_l

s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

Cycle CY0

< 15ns >

s_clk

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14

Addr Addr

Addr

Data Addr Data

Data

3 3 Byte Enables 3 Byte EnablesByte Enables

Byte Enables3

21154 P CI-to-PCI Bridge

38 Datasheet

The 21154 implements a di scard timer that st arts counting when the delayed write com pletion is at

the head of the delayed tra nsacti on queue. The initial value of this timer can be set to one of two

values, selecta ble through both the primary and sec ondary master timeout bits in the bridge control

expires, the 21154 discards the delayed write transac tion from t he de layed transaction queue. The

21 154 also conditionally asserts p_serr_l (see Section 7.4).

4.5.4 Write Transaction Address Boundaries

The 21154 imposes internal a ddress boundaries when accepting write data. The aligned address

boundaries are used to prevent the 21154 from cont inuing a transaction over a device address

bounda ry a nd to provi de an upp er l imit on maxi mum late ncy. T he 21 15 4 returns a ta rg et dis conne ct

to the initiator when it reach es the ali gned addre s s boundaries under the conditions shown in

Table 18.

4.5.5 Buffering Multiple Write Transactions

The 21154 continues to accept posted memory write transactions as long as spac e for at least 8

Dwor ds of data in the post ed write da ta buffer remains. If the posted wr ite data buffer fills before

the initiator termi nates the write trans action, the 21 154 returns a target dis connec t to the initiator.

Delayed write trans actions ar e pos ted as long as at leas t one open ent ry in the 211 54 delayed

tr ansaction queue exists. There f ore, several pos ted and delayed write transactions can exist in data

b u ffers at the s ame time.

See Section 6.0 for information about how multiple posted and dela yed write tr ans act ions are

ordered.

Tab le 18. Write Tran saction Discon nect Address Boundari es

Type of Transaction Condition Aligned Address Boundary

Delayed write All Disconnects after one data transfer

Posted memory write Memory write

disconnect cont rol

bit = 01

1. The memory write disconnect control bit is located in the chip control register at offset 40h in configuration space.

4KB aligned ad dress bo undary

Posted memory write Memory write

disconnect cont rol

bit = 11Disconnect s at cach e line boundary

Posted memory write and

invalidate C ache line size ≠

1, 2, 4, 8, 16 4KB aligned address boundary

Posted memory write and

invalidate C ache line size =

1, 2, 4, 8

th cache line boun dary, where a cache

line boundary is reached and less than 8

free Dwords of posted wri te buf fer space

remains

Posted memory write and

invalidate Cache line size = 16 16-Dword aligned address boundary

21154 PCI-to-PCI Bridge

Datasheet 39

4.5.6 Fast Back-to-Back Write Transactions

The 21154 can recognize and pos t fast back-to- bac k write transactions. When the 21154 cannot

acc ept the second transaction bec ause of buffer space lim itations, it returns a target retry to the

initiator.

When the 21154 has posted multiple write transactio ns, it can initiate fa st back-to-back write

tr ansactions if the fast back-to-back enable bit is set in the command register for upstream write

tr ans act ions, and in the bridge control register for downstr ea m write transactions. The 21154 does

not perform write combining or merging.

Figure 8 shows how multiple memory write transactions can be posted and then initiated as fas t

back-to-back transactions on the target bus.

Figure 8. Fast Back-to-Back Transacti ons on the Tar get Bus

86%

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s_cbe_l

s_ad

s_irdy_l

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s_trdy_l

s_stop_l

p_clk

s_clk

Cycle CY0

< 15ns >

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14 CY15 CY16 CY17

Addr1 Addr2

Byte Enables 17 7 Byte Enables 2

Addr1

Data

Data Addr2 Data

Data

Data Data Data Data

Byte Enables 17 7 Byte Enables 2

21154 P CI-to-PCI Bridge

40 Datasheet

4.6 Read Transactions

Delayed read forw arding is used for all read transactions cros sing the 21154.

Delayed read transactions are treated as either prefetchable or nonprefetchable.

Table 19 shows the read behavi or, prefetchable or nonprefet chable, for each type of read operation.

See Section 5.3 for de tailed information about prefetchable and nonprefetc hable address spaces.

4.6.1 Prefetchable Read Transactions

A prefetchable read transaction is a read transaction where the 21154 performs spec ulati ve Dword

r eads , t ran sferr ing da ta from t he targ et bef or e it is reque st ed f rom the i nit ia tor. Th is beha vior allo ws

a prefetchable read tr ans action to cons ist of multiple data transfers . Howeve r, byt e enabl e bits

can not be forwarde d for all data phases as is done for the single data phase of the nonpre fetchable

read transaction. For prefetchable read transactions, the 21154 forc es all byte enable bits to be

turned on for all data phases.

Pre fetch able be havior is used for me mory read lin e and memory read multi ple t rans actio ns, as well

as fo r mem o r y read transactio n s that fall into p r efetch able memor y space.

The amo unt of data th at is prefetched dep ends on the type of transaction. The amount of

pr efetching may also be affected by the amount of free buffer spac e availab le in t he 21154, and by

any rea d address boundaries encountered.

Pre fetch ing sho uld n ot be us ed for t hose r ead tra nsac tions that have s ide ef fect s in t he targ et device,

that is, control and s tatus registers, FIFOs, and so on. The target de vice’s base addr ess regi ster or

regi sters indicat e if a memory address regi o n is pr ef etchable.

4.6.2 Nonprefetch able Read Transactions

A nonprefetchable read trans act ion is a read transacti on where the 21154 reque sts 1, and only 1,

Dwor d fr om th e target and disconnects the initiator afte r delivery of the first Dword of rea d data.

Unlike prefetchable read t r ansactions, the 21154 forwards the r ead byt e en able inf ormation for the

data phase .

Nonprefetchable behavior is used for I/O and configuration read transactions, as well as for

me mory read transactions that fall into nonprefe tchable memory space.

Tab le 19. Read Transaction Prefetching

Type of Transaction Read Behavior

I/O read Prefetching never done

Co nf igura t io n rea d Pr e fet ch ing ne ve r don e

Memory read Do wnstream: Pr efetching used if address in prefetcha ble space

Upstream: Prefetching used if prefetch disable is off (default)

Memory read line Prefetching always used

Memory read multiple Prefetching always used

21154 PCI-to-PCI Bridge

Datasheet 41

If extra read transactions could have side effects, for example, when accessing a FIFO, use

non pr efetchable read t r ansactions to those location s. Accor dingly, if it is important to retain the

value of the byte en able bit s during the dat a phase, use nonprefetchabl e rea d transactions . If thes e

lo cations are mapped in memory sp ace, use t he mem o r y r ead comm and a n d map the t arget in to

nonprefetchable (memory-mappe d I/O) me mo ry space to utilize no nprefetching behavior.

4.6.3 Read Prefetch Address Boundaries

The 21154 imposes inte rnal read addre ss boundaries on rea d prefetching. When a read tr ansaction

reac hes one of these al igned add ress bounda rie s, the 21 15 4 stops pre fetc hing data , unles s the tar get

sign als a target disconnect before the read prefetch bou ndary is reached. When the 21154 finishes

transferring this read data to the initiator, it returns a target disconnect with the last data trans fer,

unless the initiator completes the trans action before all prefetched read data is delivered. Any

leftover prefe tched data is di scarded.

Prefetchable read tra nsactions in flow-through mode prefetch to the nearest aligned 4KB a ddress

boundary, or until the initiator deasserts FRAME#. Section 4.6.6 describes flow-through mode

dur ing read operations.

Table 20 shows t he read pref etch a ddress bo unda ries for rea d tr ansact ions dur ing no n-flow-thro ugh

mode.

4.6. 4 Delayed Read Re que sts

The 21154 treat s a ll read trans act ions as delaye d read trans ac tions, which means that the rea d

request from the initiator is post ed into a delayed tr ans act ion queue. Read data from the target is

placed in the read dat a queue di rec ted toward t he initiator bus int erfa ce and is transferred to the

initiator when the initiator repeats the read transaction.

When the 21154 accept s a dela yed read reque st , it first samples the re ad ad dress, read bus

comman d, and address parity. When IRDY# is asser ted, the 21154 then samp les the byte enable

bits for the firs t data phase. This information is entered into the delayed transact ion queue. The

Table 20. Read Prefetch Address Boundaries

Type of T ransaction Address Space Cache Line Size Pr efetch Aligned Ad dress

Boundary

Configuration read — — 1 Dword (no prefetch)

I/O read — — 1 Dword (no prefetch)

Memory read Nonprefetchable — 1 Dword (no prefetch)

Memory read Prefetchable CLS ≠ 1, 2, 4, 8 16-Dword aligned

addres s boundar y

Memory read Prefetchable CLS = 1, 2, 4, 8 Cache line ad dress

boundary

Memory read line — CLS ≠ 1, 2, 4, 8 16-D word aligne d

addres s boundar y

M emory read line — CLS = 1, 2, 4, 8 Cache li ne boundary

Memory read multiple — CLS ≠ 1, 2, 4, 8 Q ue ue full

Memory read multiple — CLS = 1, 2, 4, 8 Second cache line

boundary

21154 P CI-to-PCI Bridge

42 Datasheet

21154 terminat es the transact ion by signaling a target r etry to the initiator. Upon reception of the

target retry, the initiator is required to continue to repeat the same read trans action until at lea st one

dat a trans fer is compl eted, or until a t arge t resp onse other tha n a targ et retry (t ar get abor t, or maste r

abor t) is rece ived.

4.6.5 Delayed Read Completion with Target

When the delaye d read request reaches the head of the delayed transaction queue , and al l

pr eviously queue d p oste d write tran saction s have be en delivere d, the 21154 arbitra te s for the tar get

bus and initiates the read transaction, using the exact read address and read command captured

f rom the init ia tor du ring the init ial de layed read req uest. If the re ad transa ct ion is a nonprefe tcha ble

read, the 21154 drives the captured byte enable bits during the next cycle. If the transaction is a

pr efetchable read tr ans action, it drives all byte enable bits to 0 for all data phases . If the 21154

r eceiv es a targ et re try in res ponse to th e read tran sactio n on the ta r get bus, it c onti nues to repeat the

r ead transaction until at le as t one dat a transfer is completed, or until an error condition is

encountered. If th e transaction is terminated via normal master termination or target disconnect

after at least one data transfer has been completed, the 21154 does not initiat e any further atte mpts

to read more data.

I f the 21154 is una ble to obta in read data from the target afte r 224 a tt emp ts, th e 21154 cease s

f u r ther read attempts a nd retur n s a tar get abort to the initiator. The dela yed tr ansaction i s removed

f r om th e del ayed transaction queue. The 21154 also asserts p_ serr_l if the primary SERR# enable

bit is se t in th e comm a nd r eg iste r. See Section 7.4 for information on the asse rtion of p_serr_l.

Once the 21154 receives DEVSEL# and TRDY# from the tar get, i t transfe rs the data read to the

opposite direc tion read data queue, pointing toward the opposite interfac e, before te rmi nating the

t r ansaction. For ex ample, read d ata in response to a downstream re ad transaction initiated on the

pr imary bus is placed in the upstream read data queu e. The 21154 ca n accept 1 Dword of r ead data

each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred

during a delayed read transaction depends on the conditions give n in Table 20 (ass um ing no

disconnect is received from the target).

4.6.6 Delayed Read Completion on Initiator Bus

When the tr ans action has been com pleted on the target bus, and the delayed re ad data is at the head

of the read data queue, and all orde ring c onstraints with post ed write transactions have been

satisfied, the 21154 transfers the data to the init iator when the initiator r epeats the transaction. For

memory read transacti ons, t he 21 1 54 aliases the memory read, memory read line , and memory re ad

mul tip le bus commands whe n matc hi ng the bus comma nd of t he trans act ion to th e bus comma nd in

the delayed transaction queue. The 21154 returns a target disconn ect along with the transfer of the

las t Dword of r ead dat a to t he in iti ator. If the ini tiato r ter mi nat es the tra nsac tio n befo re al l re ad data

has been transferred, the re ma ining read data left in data buffers is discar ded.

21154 PCI-to-PCI Bridge

Datasheet 43

Figure 9 shows a nonprefetchable delayed read transaction.

Figure 9. Nonprefetchable Delayed Read Transaction

LJ-04846.AI4

p_frame_l

p_cbe_l

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p_irdy_l

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s_cbe_l

s_ad

s_irdy_l

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s_trdy_l

s_stop_l

p_clk

s_clk

Cycle CY0

< 15ns >

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14

Addr Addr Data

Addr

2 2

Data

Byte Enables 2 Byte EnablesByte Enables

Byte Enables2

21154 P CI-to-PCI Bridge

44 Datasheet

Figure 10 shows a prefetchable delayed read transaction.

When the master repe ats the transac tion a nd starts tra nsferring prefetchable read data from 21154

data buffers while the read transaction on the target bus is still in progress and before a read

boundary is reached on the tar get bus, the read tra ns action st arts op erati ng in flow-through mode.

Bec ause dat a is flowing t hroug h the data buf fers from the ta r get to the ini tiat or , l ong re ad bursts can

th en be sustained. In this case, the read tr ansaction is allowed to continue until th e initiat o r

terminates the transactio n, or until an aligned 4KB addre ss bounda ry is reached, or until the buf fer

f ills , whiche ver comes fi rst. Whe n the buf fe r empti es, the 21154 refle cts t he stall ed condi ti on to the

initiator by deass erting TRDY# until more re ad dat a is avail able; otherwise, the 21154 does not

insert any target wait states. When the initiator terminates the transaction, the deassertion of

FRAME# on the initia tor b u s is forw ar ded to the ta rget bus. Any rema ining read data is discarded.

Figure 10. Prefetchable Dela yed Read Transa ction

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_devsel_l

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s_ad

s_irdy_l

_devsel_l

s_trdy_l

s_stop_l

p_clk

Cycle CY0

< 15ns >

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14 CY15 CY16 CY17 CY18 CY19 CY20 CY21

s_clk

Addr Addr Addr

Byte Enables Byte Enables6 66 Byte Enables

Addr

Data

21154 PCI-to-PCI Bridge

Datasheet 45

Figure 11 shows a flow-through prefetchable read transactio n.

The 21154 impl ements a dis ca r d tim er that start s counting when the dela yed re ad completion is at

the hea d of the delayed transact ion queue, and the read da ta is at the head of the read data queue.

The ini tial value of this timer can be set to one of two values , select able through both the primary

and secondary master ti me out value bits in the bridge control register. If th e initiator does not

repeat the read tr ansact ion before the discard timer expire s , the 21154 discards the re ad transacti on

and the read data from it s queues. The 21154 also condi tionally asser ts p_serr_ l (se e Secti on 7.4).

The 21154 has th e ca pability to post multiple delayed read reque st s, up to a maxi mum of three in

each d irection. I f an initiator star ts a read transactio n th at match es the address a n d r ead comm and

of a rea d transaction that i s alr eady queued, the c urrent read command is not posted as it is already

contained in the delayed trans ac tion queue.

See Section 6.0 for a discus s ion of how delayed read transactions are ordere d when cro ssing the

21154.

Figure 11. Flow-Through Prefetchable Read Transaction

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s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

s_clk

Cycle CY0

<15ns>

CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14 CY15 CY16 CY17 CY18 CY19

Addr Addr

Byte Enables6 6 Byte Enables

Addr

Data

Data Data Data Data Data Data Data

21154 P CI-to-PCI Bridge

46 Datasheet

4.7 Configuration Transaction

Configuration transactions are used to initialize a PCI sys tem. Every PCI device has a

confi gura tion s pace that is access ed by con figu ration c ommands . All 21154 re gisters are ac cessi ble

in configuration s pace only.

I n addition to accepting configuration transactions for initi alization of its own configura tion space,

the 21154 al so forwards configuration transactions for device initialization in hierarchical PCI

systems, as wel l as for special cycl e generat ion .

To su pport hierarchical PCI bus systems, two types of configuration tr ansacti ons are specified:

Type 0 and Type 1.

Type 0 configuration transactions are issued when the intended ta rget res ides on the same PCI bus

as the initiator . A Type 0 configurat ion transact ion is identified by the configuration command and

the lowest 2 bits of the addres s set to 00b.

Type 1 configuration transactions are issued when the intended t arget resides on another PCI bus,

or when a speci al cycle is to be generated on another PCI bus. A Type 1 configuration com mand is

identified b y the configuration command and the lowest 2 address bits se t to 01b.

Figure 12 shows the address formats for Type 0 and Type 1 configuration transactions.

The registe r numbe r is fou nd in both Type 0 a nd Type 1 for mats an d gives th e Dword addres s of t he

configuration regi ster to be acce ssed. The function numb er is also included in both Type 0 and

Type 1 formats and indicat es which function of a multifunction devic e is to be a ccessed. For

single-functi on devices, this value is not decoded. Type 1 confi guration trans act ion addresses also

include a 5-bit field des ignati ng the device numbe r that identifies the device on t he ta rget PCI bus

that is to be accessed. In add ition, the bus numbe r in Type 1 transactions specifi es the PCI bus to

wh ich th e tr ansaction is tar geted.

4.7.1 Type 0 Access to the 21154

The 21154 configuration space is accesse d by a Type 0 configuration transaction on the primary

interface. The 21154 configuration space c annot be acce ssed from the secondary bus. The 21154

r es ponds to a Type 0 config uration transact ion by as serting p_devsel_l when the following

conditions are met during the address phase:

•The bus command is a configuration read or configuration write trans action.

Figure 12. Configuration Tran sacti on Address Formats

LJ-04638.A14

31 24 23 16

Device Number Func. No. Register No. 0 1Bus Number

Func. No. Register No. 0 0Reserved

Reserved

Type 1

15 11 10 08 07 02 01 00

Type 0

11 10 08 07 02 01 00

21154 PCI-to-PCI Bridge

Datasheet 47

•Low 2 address bits p_ad<1:0> must be 00b.

•Signa l p_idse l must be asserted .

The function code is ignored because the 21154 is a single -function device .

The 21154 limits al l configuration ac ce sses to a single Dword data transfer and returns a tar get

disconnect with the firs t data transfer if additional da ta phases are requ es ted. Because read

tr ansact ions to 21 1 54 configu rat ion spa ce do not have side ef fect s, all by tes i n the requ este d Dword

are returned, regardless of the value of the byte enable bits.

Type 0 configurat ion write and read transactions do not use 21154 data buffers; that is, these

tr ans act ions are completed im mediately, rega rdless of the state of the data buffers.

The 21154 ignores all Type 0 transactions initiated on the secondary interface.

4.7.2 Type 1 to Type 0 Translation

Type 1 con f iguration transactions are use d specifi cally for device configuration in a hie r archical

PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1

configuration com mand. Type 1 confi guration commands are used when the configuration acc es s

is intended for a PCI devic e tha t resides on a PCI bus other than the one where the Type 1

tr ansaction is genera ted.

The 21154 pe rforms a Ty pe 1 to Typ e 0 translation when the Type 1 transaction is generated on the

primar y bus and is intended for a device attached direc tly to the secondary bus . The 21154 must

convert the configurat ion c ommand to a Type 0 format s o that the secondary bus device can

res pond to it. Type 1 t o Type 0 transla tions a re performed onl y in the downst ream direc tion; tha t is,

the 21154 generates a Type 0 transacti on only on the secondary bus , a nd never on the primary bus.

The 21 154 re sponds to a Type 1 co nfigurat ion t ransa ction a nd trans lates it into a Type 0 transa ction

on the secondary b us when the following conditions ar e met during the a ddress pha se:

•The low 2 addr ess bits on p_ad<1:0> are 01b.

•The bus num ber in address field p_ad<23:1 6> is equal to the va lue in the second ary bus

number register in 21154 configuration space .

•The bus comm and on p_cbe_l< 3:0> is a configuration read or confi guration write transaction.

When the 21154 translates the Type 1 tra nsaction to a Type 0 tran saction on the secondary

in terface, it performs the following tra n slations to the a ddr ess:

•Sets the low 2 address bits on s_ad<1:0> to 00b

•Decode s the de vic e number an d dri ves t he bit pa ttern spec ified i n Tabl e 21 o n s_ad<31: 16> for

the purpose of as serting the device ’s IDS EL signal

•Se ts s_ ad< 15 : 11> to 0

•Leaves unchang ed the function number and register number fiel ds

The 21154 asse rts a unique address line base d on the de vice number . These address li nes may be

use d as secondary bus IDSEL signals. The mapping of the address lines depends on the device

number in the Type 1 address bits p_ad<15:11>.

21154 P CI-to-PCI Bridge

48 Datasheet

Table 21 pres ents the mapping that the 21154 use s .

The 21154 can assert up to 16 unique address lines to be used as IDSEL si gnals f or up to 16

devices on the secondary bus, for device numbers ra nging from 0 through 15. Because of electrical

loa ding con straint s of the PCI bu s, more than 16 I DSEL signals should not be necess ary. Howeve r ,

if device numb ers grea ter than 15 ar e desire d, s om e ext ernal method of generating IDSEL lines

must be used, and no upper a ddress bits are then as serted. The configuration transaction is still

tr anslated and pas sed from the prim ary bus to the seconda ry bus. If no IDSEL pin is ass erted to a

secondary device, the transaction ends in a m aster abort.

The 21154 forwards Type 1 to Type 0 configurati on read or wri te tran sactions as delayed

tr ansact ions. Type 1 to T yp e 0 configurat io n re ad or wr ite tran saction s are limit ed to a single 32-bi t

data transfer.

4.7.3 Type 1 to Type 1 Forwarding

Type 1 to Type 1 trans acti on forwarding provides a hierarchi cal configuration mechani sm when

two or more levels of PCI-to-P CI bridges are used.

When the 21154 detects a Type 1 configuration transaction intended for a PCI bus downstream

f r om th e s ec ondary bus , the 21154 forwards the tra nsacti on unchanged to the sec ondary bus .

Ultimately, this tran sac tion i s translated to a Type 0 co nf iguration command o r to a special cycle

trans action by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwa rding occurs

when the following conditions are met dur ing the address phase:

Tab le 21. Device Numbe r to IDSEL s_ad Pin Mapping

Device Number p_ad<15:11> Secondary IDSEL s_ad<31:16> s_ad Bit

0h 00000 0000 0000 0000 0001 16

1h 00001 0000 0000 0000 0010 17

2h 00010 0000 0000 0000 0100 18

3h 00011 0000 0000 0000 1000 19

4h 00100 0000 0000 0001 0000 20

5h 00101 0000 0000 0010 0000 21

6h 00110 0000 0000 0100 0000 22

7h 001 11 0000 0000 1000 0000 23

8h 01000 0000 0001 0000 0000 24

9h 01001 0000 0010 0000 0000 25

Ah 01010 0000 0100 0000 0000 26

Bh 01011 0000 1000 0000 0000 27

Ch 01100 0001 0000 0000 0000 28

Dh 01101 0010 0000 0000 0000 29

Eh 01110 0100 0000 0000 0000 30

Fh 01111 1000 0000 0000 0000 31

10h–1Eh 10000—11110 0000 0000 0000 0000 —

1Fh 11111 Generate special cycle (p_ad<7:2> = 00h) 0000

0000 0000 0000 ( p_ad<7:2> ≠ 00h) —

21154 PCI-to-PCI Bridge

Datasheet 49

•The lo w 2 ad dress b its are equal to 01b .

•The bus num ber fa lls in the range defined by the lower limit (excl usive) in the secondary bus

number regis ter and the upper limit (inclusive) in the subordinate bus number register.

•The bus comm and is a configur ation read or write trans action.

The 21154 also supports Type 1 to Type 1 forwarding of configuration wri te transactions upstream

to support upstream special c ycle generation. A Type 1 configuration command is forwarded

upstream when the fol lowing conditions are met:

•The lo w 2 ad dress b its are equal to 01b .

•The bus num ber falls outside the range defined by the lower limit (inclusi ve) in the secondary

bus number register and the upper limit (inclusive) in the subordinate bus numbe r register.

•The device number in address bits AD<15:11> is equal to 11111b.

•The function number in address bits AD<10:8> is equal to 111b.

•The b u s command is a conf ig urat io n write transact io n .

The 21154 forwards Type 1 to Type 1 configuration write transactions as de layed transactions.

Type 1 to Type 1 configuration write tra nsacti ons are limited to a single data transf er.

4.7.4 Special Cycles

The Type 1 conf iguration mech anism is use d to generate special cycle t r ans actions in hiera r chica l

PCI systems. Special c ycle trans actions are ignored by a PCI-to-PCI bridge acting a s a target and

are not forwarde d ac ross the bridge. Speci al cycle transacti ons can be generate d fr om Ty pe 1

configura tion write transactions in either the upstream or the downs tream direct ion.

The 21154 initiates a special c ycle on the target bus when a Type 1 configuration wri te trans action

is de tecte d on the initiating bus and the following conditions a r e met during the a ddress phase:

•The low 2 addr ess bits on AD<1:0>are equa l to 01b.

•The device number in address bits AD<15:11> is equal to 11111b.

•The function number in address bits AD<10:8> is equal to 111b.

•The register num ber in addre ss bits AD<7:2> is equal to 000000b.

•The bus num ber is equal t o the value in the secon dary bus number register in configuration

spa ce for downstream forwarding or equal to the value in the primary bus num ber register in

configuration space for upstream forwa rding.

•The bus comm and on C/BE# is a configuration write command.

When t h e 2 1154 in itiates t h e transaction o n the target in terface, t h e b u s command i s changed f rom

configuration write to special cycle. The address and data are forwa r ded uncha nged. Devices that

use specia l cycles ignore the address and de code only the bus command. The data pha se contains

the speci al cy cl e m essag e . Th e tr ans ac ti o n is for w ar d ed as a de lay ed tran s a ct i on , bu t in th is ca se

th e target res po ns e is not f orw ar ded ba ck (b ecaus e sp ecial cyc le s res ul t in a mast er a bor t ). Onc e t he

transaction is c ompleted on the target bus, through detection of the m aster abort condition, the

21 154 re sponds wi th TRDY# to the next at tempt of the configur ati on trans acti on from the initi ato r .

If more th an one data tra nsfer is requested, t he 21154 responds with a target disconnect operation

during the first data phase.

21154 P CI-to-PCI Bridge

50 Datasheet

4.8 64-Bit Operation

The 21154 provides 64-bit extens ion support on the prima ry and seconda ry interfaces. Both 64-bit

and 32-bit operation are suppor ted on both interfaces .

This section describes how to use the 64-bit extensions . It describes the conditions under which a

tr ansact ion can be treated as a 64-bit transaction and inclu des information about how the

transaction is forwarded.

4.8.1 64-Bit and 32-Bit Transactions Initiated by the 21154

The 21154 requests a 64-bit transaction on the prim ary or secondary bus 64-bit PCI extension by

as serting p_re q64_l on the primary bus or s_req64_l on the seco ndary bus respectively, during the

address phase.

The 21154 asserts an d deassert s RE Q6 4# duri ng the same cycle s in which it asserts and deasse rts

FRAME#, respectively.

Under c ertain circumstances, the 21154 does not use the 64-bit extension when initia ting

tr ansact ions and t herefore does not assert REQ64#.

The 21154 do es not as sert REQ64# when initiating a t r ans action, and the tra nsaction is therefor e

initiated as a 32-bit wide trans act ion, when a ny of the following is true:

•Si gnal p_req64_l was not assert ed by the primary bus central function during reset (64-bit

extension not supported on primary PCI bus), for upstream transactions only.

•The 21154 is initiating an I/O transaction.

•The 21154 is initiating a configuration transaction.

•The 21154 is initiating a nonprefetchable memory read transaction.

•The 21154 is initiating a special cycle transaction.

•The address is not quadword aligned (AD<2> = 1).

•A 1- or 2-Dword memory writ e transaction is being performed.

•The 21154 is resumin g a memory write trans acti on after a ta rget discon nect, and ACK64# was

n o t asser ted b y the target in the pr ev ious tran saction—does n o t appl y when the previous targ et

t ermination was a target retry.

•A singl e Dword re ad tra nsaction is being performed.

•The address is near the top of a cache line (AD<3> = 1)—applies to prefetchabl e read

t ran sactions.

4.8.2 Address Phase of 64-Bit Transactions

When a t ransa ction using th e primar y bus 64- bit extensi on is a s ingle addr ess cycle (SAC)—that is,

the address falls below the 4GB boundary, and the upper 32 bit s of the address a r e ass umed to be

zero— AD<63:32> a nd C/BE#<7:4> are not define d but are drive n to valid logic level during the

address phase.

21154 PCI-to-PCI Bridge

Datasheet 51

When the transaction is a dual addres s c ycle (DAC)—that is, the address fal ls above the 4GB

boundary, and the upper 32 bits of the address are nonzero—signals AD<63: 32> contai n the upper

32 bits of the addre ss for both addre ss phases. Signals C/B E#< 7:4> con tain the memory bus

comman d during both add ress phases. A 64-bit ta rg et then ha s the oppor tunity to decode the entire

64- bit addre ss and bus comman d after the first ad dress phase. A 32-bit t arget needs both address

phas es to dec ode the full address and bus command.

4.8.3 Data Phase of 64-Bit Transactions

During memory write transactions, when the 21154 has driven REQ64# to indicate it is initiating a

64- bit trans fer, during the data phase the 21154 drives the following :

•The low 32 bits of data on AD<31:0>

•The low four byte e nable bits on C/BE#<3:0>

•The hig h 32 bits of dat a on AD<63 :32>

•The high four byte enable bits on C/BE#<7:4 >

When the 21154 dete cts ACK64# asse rted by the target at the same ti me that it de tect s DEVSEL#

asserted, every da ta phase then consists of 64 bits an d eight byte enable bits.

For write transactions, when the 21154 does not detect ACK64# asserted at the same time that it

detects DEVSEL# asserted, the 21154 redirect s the write data that it has on the AD<63:32> bus to

AD<31:0> during the sec ond data phase. S imilarl y, t he upper fou r byte enable bits are redi recte d to

C/BE#<3: 0> during the seco nd data phase . All data phase s then cons ist of 32 bits.

For 64 -bit mem ory wri te tra nsactio ns tha t e nd at a n odd Dword bound ary, the 21154 d rive s the byt e

enable bi ts to 1 during the la st data pha se. Sig nals AD<63:32> are then unpredictable but are

dr iv en to a va lid lo gi c lev el.

For read transactions, when the 21154 has asserted REQ64#, it dr ives 8 bits of byte enables on C/

BE#< 7:0>. Because the only read transa ctions that use the 64-bit extension are prefetchable

mem o ry read tran sact io n s, the b y te enable bits are always zero. There f o re, no special redir ection is

needed based on the target’s assertion or lack of assertion of ACK64#. W hen the target asserts

ACK64# at the sa me tim e that it assert s DEVSEL#, all read data transfers then consist of 64 bit s

and the targe t dri ves PAR64, wh ich cove rs AD<63: 32> and C/B E#<7:4>. When the ta rg et does not

asse rt ACK64# when it ass erts DEVSEL #, all data phases then consist of 32 bits .

4.8.4 64-Bit Transactions Received by the 21154

When the 21154 is the target of a transac tion and the 21154 detects REQ64# assert ed during a

memory tra nsaction to be forwarde d across the bridge, the 21154 either a sserts ACK64# at the

same time that it asserts DEVSEL# to in dicate it s a b ility to perform 64-bit da ta transfers or, under

cert ain ci rcumsta nces, the 21154 does n ot use th e 64-bit exten sion a s a t arge t and the refo re does not

asse rt ACK64#.

The 21154 does not as sert ACK64# when any of the following is tr ue:

•Sig n al REQ64# was not a sserted by the initiator.

•The 21154 is responding to a nonprefetchable memory rea d transaction.

•The 21154 is responding to an I/O transaction.

•The 21154 is responding to a configuration tra nsacti on.

21154 P CI-to-PCI Bridge

52 Datasheet

•Only 1 Dword of data was read from the target.

When the 21154 is the target of a 64-bit memory write transaction, it is able to accept 64 bits of

data duri ng eac h data phase.

When th e 21 154 i s the ta r get of a 64-bit pre fe tchabl e memory r ead tra nsacti on, it sup plies 64 bits of

r ead da ta during each data pha se and drives PAR64 corr esponding to AD<63:3 2> and C/

BE#<7:4>, for each data phase. If an odd number of Dwords was read from the target and the

21154 has asserted ACK64# when returning read data to the initiator, the 21154 disconnects before

the last odd Dword is ret urned. The 21154 may have read an odd number of Dwords because of

eithe r a target disconnect or a master latency timer expiration during 32-bit da ta transfers on the

opposite interface.

4.8.5 64-Bit Extension Support During Reset

When the 21154 supports a 64-bit interface on its primar y bus, it samp les p_req64_l while p_rst_ l

is asserted to determine whe ther the PCI 64-bi t extension signals are connected on the board. If

p_req64_l is high, the 64-bit extension signals are not connec ted and t he 21154 then always drives

the 64-bit extension outputs to have valid logic levels on the inputs. The 21154 treats all

transactions on the primary interface as 32-bit transactions. If p_re q64_l is low, the 64-bit signa ls

are connected to pul l-up res is tors on the board and th e 21154 does not perform any input biasing.

I n t his cas e, the 21154 can tr eat memory wr ite and pref etch able memory rea d trans acti ons as 64-bit

tr ansact ions on the primary interface, as disc ussed previousl y.

The 21154 always asserts s_req64_l low during s_rst_l assertion to indicate tha t the 64-bit

exte nsion is supported on the secondary bus. Individual pull-up resistors must always be supplie d

for s_ad<63:32>, s_cbe_l<7:4>, and s_par64

4.9 Transaction Flow Through

Transa ction flow occurs when data is removed fr om a 21154 read or write buffer a t the same tim e

th at data for tha t tr ansaction is still being written to the bu f fer.

Fo r wr it es, fl o w - th ro ugh oc cu r s w h en th e 21154 is abl e to ar b it r at e fo r th e target bus , ini t iate th e

transaction and receive a TRDY# from the target, while still receiving data from that same

tr ansact ion on the initiator bus. Writes that were previously posted in that same direction must be

delivered before flow-through can oc cur.

For reads, flow-through occ urs when the initiator repeats the delayed tra nsaction during a timing

window when some read dat a is in the buffer, but the transaction is sti ll ongoing on the target bus.

For read flow-through to occur, there can be no other reads or writes previ ously posted in the same

direction.

The 21154 allows flow-through only when a queue empty condition cannot occur during the

middle of a trans action (in the absence of wait state s). Therefore, a transaction can flow-through

only when the bus bandwidth for data comin g into the 21154 is the sa me or gr ea ter than the bus

bandwidth for data deli vered by the 21154.

For example, when the 21154 accepts a memory writ e transaction as a 32-bit transaction but the

21154 initiates it as a 64-bit transaction, the entire write transactio n must be posted in the 21154

write buffers before th e 21154 can initiate the trans act ion. Otherwise, if the transaction were to be

ini tiat ed on the ta rg et bu s w h ile w r it e da ta wa s sti ll bein g accep t ed by th e 2 115 4 o n th e in itia to r

bus, writ e dat a could be removed from the pos ted write buffer at a rate greater than write dat a is

21154 PCI-to-PCI Bridge

Datasheet 53

posted, even in the absence of master wait states on the initiator bus. It would then be poss ible for

the pos ted write buffer to empty during the write tran sa ction. As a re sult, ad ditional wait states

would be i ntrod uced on the targ et bus. To avoid intr oduc ing addit ion al wa it st ates, a ll t he data must

be pos ted and the write trans action completed on the initiator bus be fore the transaction can be

initiated on the target bus.

Similarly, when read data is accepted from the target using 32-bit trans fers, but is supplied to the

initiator using 64-bit tr ans f ers, the 21154 continues to return ta rget retr y to the initiator until all

read data is buffered and the transaction on the target bus has been terminated.

The previous examples apply when both interfa ces are operating at the same fr equency. However,

bus fre quency as wel l as bandwidth must be considered when calculating whet her flow-through

can oc cur. Thus, a write tra nsacti on initiated on a 32-bi t, 66 MHz bus and directed to a 64-bit, 33

MHz bus can still flow-throu gh the 21154, because the bandwi dths of the t wo buses are the same.

4.10 Transaction Termination

This section des cr ibes how the 21154 r eturns transaction ter mination conditions back to the

in itiator.

The initia tor can terminate transactions with one of the following types of termination:

•Normal term inat ion—occ urs when the ini tia tor deass erts FR AME# at the beginn ing of the last

data phase, and deas serts IRDY# at the end of the last data phase in conjunct ion with either

TRDY# or STO P# assertion from the target.

•Master abort—occurs when no target response is detected. When the initiator does not detect

a DEV SEL# f rom the tar ge t with in fiv e cl o ck cy cles aft er asser t in g FRA M E#, th e in i ti at o r

terminates the transaction with a master abort. If FRAME# is still asserted, the initiator

deasserts FRAME# on the next cycle, and then deas sert s IRDY# on th e following cycle.

IRD Y# must be asserted in the sam e cycle in which FRAM E # dea sse rts. If FRAME# is

alre ady deass erted, IRDY# can be deass erted on th e next clock cycle foll owing detect ion of

the m aster abort condition.

The targe t can te rminate transactions with one of the following types of termination:

•Normal termination—TRDY# and DE VSEL# asserted in conjunction with FRAME #

deasserted and IRDY# asserted.

•Target retry—STOP# and DEVSEL# as s erted without TR DY# during the firs t data phas e. No

data transfers occur during the transaction. This transaction m ust be repeated.

•Target dis connect with dat a tra nsfer —ST OP # and DEVSEL# asserted with TRDY#. Signals

that this is the last data transfer of the transaction.

•Target dis connect without data transfer—STOP# and DEVSEL# asse rted without TR DY#

after previous dat a tra nsfer s have been made. Indic ates that no more data tra ns f ers wil l be

made during this transact ion.

•Targe t abort—STOP# a sserted witho ut DEVSEL# an d without TRDY#. Indicates that the

target w ill never be able to complete this transaction. DEVSEL# must be asserted for at least

one cyc le during the transacti on before the target abort is signale d.

21154 P CI-to-PCI Bridge

54 Datasheet

4.10.1 Master Termination Initiated by the 21154

The 21154, as an in itiator, uses normal term ination if DEVSEL# is returned by the target within

f ive clock cyc les of the 21154’s assertion of FRAME# on the target bus. As an initiat or, the 21154

terminate s a transaction when the following conditions are met:

•Dur ing a delayed write trans act ion, a single Dword is delive red.

•During a nonpref etchable read t r ansaction, a s i n g le Dword is transferred from the target.

•Dur ing a prefetchable read transac tion, a p refetch bounda ry is reached.

•For a posted write transaction, all write data for the transaction is tra nsferred from 21154 data

b u ffers to the target.

•For a bu rs t tr ansfe r , wi th t he e xcept ion of m emory wri te and invali da te tr ans actio ns , the m ast er

latency timer expires and the 21154’s bus grant is deasserted.

•The target terminates the transaction with a retry, disconnect, or target abort.

If the 21154 is delivering post ed write data when it terminates the transac tion because the master

latency timer expires, it ini tiates another transact ion to deliver the remaining write data. The

address of the transaction is updated t o refle ct the address of the current Dword to be delive red.

I f the 21154 is pre f etchi ng rea d data when it terminates the transaction because th e mas ter latency

tim er expires , it does not repeat the transactio n to obtain more data.

4.10.2 Master Abort Received by the 21154

I f the 21154 initiates a trans act ion on the tar get bus and does not detect DEVSEL# returned by the

target within five clock cycl es of the 21154’s assertion of FRAME#, the 21154 terminates the

tr ansact ion with a mas ter abort. The 21154 sets the rec eived master abor t bit in the status regis ter

corresponding to the target bus.

For delayed read and write transactions, when the master abort mode bit in the bridge control

r egi st er is 0, the 21154 ret urns TRDY# on t he initi ator bus and, for read transac tions, returns FFFF

FFFFh as data.

When the master abort mode bit is 1, the 21154 returns target abort on the initiator bus. The 21154

als o set s the signaled target abort bit in the register corresponding to the initiator bus.

Figure 13 shows a delayed write transaction that is terminated with a master a bort.

21154 PCI-to-PCI Bridge

Datasheet 55

When a maste r abort is received in response to a posted write trans action, the 21154 discards the

posted writ e data and makes no more at tempts to deli ver the da ta. Th e 21154 sets the received

maste r ab ort bit in the stat us regi ster when t he master abort i s rece ived on t he pr imary bu s, or it sets

th e received mast er abort bit i n th e secondar y status register when the ma ster abo r t is received o n

the s econdary interface. When a master ab ort is detec ted in respon se to a pos ted write transac tion

and the master abort bit is set, the 2115 4 al so asserts p_se rr_l if ena bled by t he SERR# en able bi t in

the comm and register and if not disa bled by the de vice-specific p_serr_l disable bit for maste r

abort during posted write tra nsactions (that is, master abor t mode = 1; SERR# ena ble bit = 1; and

p_se rr_l disable bit for mast er aborts = 0).

Note: When the 21154 perform s a Type 1 to speci al c ycle translation, a master abort is the expected

ter mination for the s pecial cy cle on the target bus. I n t his case, the master abort received bit is not

set , and the Type 1 configu r ation transacti on is disc onnected after the first data phase.

4.10.3 Target Termination Received by the 21154

When the 21154 initiates a transaction on the target bus and the target responds with DEVSEL#,

the target can e nd the trans action with one of the following types of termination:

•Normal terminat ion (upon dea ssertion of FRAME#)

•Target retry

Figure 13. Delayed Write Transaction Ter m inated with Master Abo rt

91%

LJ-04849.AI4

p_frame_l

p_cbe_l

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p_stop_l

s_frame_l

s_cbe_l

s_ad

s_irdy_l

s_devsel_l

s_trdy_l

s_stop_l

p_clk

s_clk

Cycle CY0

< 15ns > CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14 CY15 CY16

Addr Addr

Addr

Data Addr Data

Data

3 3 Byte Enables 3 Byte Enables

Byte Enables

Byte Enables3

21154 P CI-to-PCI Bridge

56 Datasheet

•Target disconnect

•Target abort

The 21 154 handle s these t ermin ations in di f ferent wa ys, de pending on the t ype of t ran saction bein g

performed.

4.10.3.1 Delayed Write Target Terminat ion Response

Whe n the 21154 initiates a de layed write transaction, the type of ta rget termination re ceived from

the targ et can be pa s s e d b ack to th e ini ti ato r. Ta ble 22 shows the 21154 response to each type of

target termination that occurs during a delayed write transaction.

The 21154 repeats a delayed write transact ion until one of the following conditions is met:

•The 21154 completes at least one data tra nsfer.

•The 21154 receives a mas ter abort.

•The 2 1154 recei v es a ta rg et abor t .

•The 21154 make s 224 write attempts resulting in a response of target retry.

After the 21154 makes 224 attempts of the sa me delaye d write transaction on the target bus, the

21154 asserts p_serr_l if the prim ary SERR# enable bit is set in the command register and the

implementation-specific p_serr_l disable bit for thi s co ndition is not set in the p_serr_l even t

disa ble register. T he 21154 stops initiating transactions in response to that delayed write

tr ansact ion. T he del ayed wri te re quest is di sca rded. Up on a su bsequ ent writ e tr ansact ion at te mpt by

the initiat or, th e 21154 returns a target abort. See Section 7.4 for a desc ription of system error

conditions.

4.10.3.2 Posted Write Target Te rmination Response

When the 21154 init ia tes a poste d write tr ansa ction, the tar get termi nation can not be pa ssed bac k to

the in iti ato r. Ta ble 23 shows the 21154 respons e to ea ch type of target termination that occurs

during a posted write transaction.

Table 22. 21154 Response to Delayed Write Target Termination

Target Termination 21 154 Response

Normal Return disconnect to initiator with first data transfer only if multiple data

phases requested.

Target retry Return target retry to initiator. Continue write attempts to target.

Target disconnect Return disconnect to initiator with first data transfer only if multiple data

phases requested.

Target abort Return target abort to initiator.

Set re ceived tar get abort bit in target interface status register.

Set signaled target abort bit in initiator interface status register.

21154 PCI-to-PCI Bridge

Datasheet 57

Note that when a target ret r y or target dis connect is returned and posted write data associated with

that tra nsactio n remai ns in t he write buf fers, the 21154 init ia tes anoth er wri te tra nsactio n to a ttem pt

to deliver the rest of the write data. In the case of a target retry, the exact same address will be

driven as for the initial write transaction attempt. If a target disconnect is received, the address that

is driven on a subsequent write transac tion attempt is updated to reflect the addres s of the c urrent

Dword. I f the initial write tran saction is a memory wr ite and invalidate tra n saction, a nd a partial

delivery of write data to the target is performed befo re a target disconnec t is rec eived, the 21154

uses the memory write command to deliver the rest of the write data because less than a cache line

will be transferred i n the subsequent write transaction attempt.

After the 21154 makes 224 write transaction attempts and f ails to deliver all the posted write data

assoc iate d wit h th at tra nsac tion, the 21 154 a sse rts p_ serr_l if the primar y SERR # enabl e bi t is set i n

the command re gister and the device-specific p_ser r_l disable bit for this condition is not s et in th e

p_se rr_l even t disab le register. The write dat a is discarde d. See S ection 7.4 for a discussion of

system error conditions.

4.10.3.3 Delayed Read Target Termination Re sponse

When the 21154 initiates a delay ed read transaction, the abnorm al target responses can be p as s ed

back to the initiat or. Other target responses depend on how much dat a the initiator requests. Table

24 shows the 21154 response to ea ch type of target termination that occurs during a delayed re ad

transaction.

Figure 14 sho w s a de lay ed re ad tr ans a c ti o n th at is ter min at ed wi t h a target a bor t.

Table 23. 21154 Response to Posted Write Tar get Termina tion

Target Termination 21154 Response

Normal No additional action.

Target retry Repeat write transaction to target.

Target disconnect Initiate writ e transactio n to del iver remaining posted write data.

Target abort Set received targe t abor t bit in the targ et interface status register. Assert

p_serr_l if enabled, and set the signaled system error bit in the primary

s tatus register.

Table 24. 21154 Response to Delayed Read Target Ter m ination

Target Termination 21154 Response

Normal If p refetchable, target disconnec t only if initiato r requests mor e data t han

read from target. I f nonprefet chable, target disconnect on first da ta phase.

Target retry Reinitiate read transaction to target.

Target disconnect If initiator requests more data than read from target, return target

disconnect to initiator.

Target abort Return target abort to initiator.

Set received target abort bit in the target interface status register.

Set signaled target abort bit in the initiator interface st atus r egister.

21154 P CI-to-PCI Bridge

58 Datasheet

Figure 14. Delayed Read Tran saction Terminated with Target Abort

LJ-04850.AI4

p_frame_l

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CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8 CY10

CY9 CY11 CY12CY13 CY14

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2 2 Byte Enables 2 Byte EnablesByte Enables

Byte Enables2

21154 PCI-to-PCI Bridge

Datasheet 59

The 21154 repeats a delayed read transaction until one of th e following conditions is met:

•The 21154 compl etes at least one da ta transfer.

•The 21154 receives a master abort.

•The 21154 receives a target abort.

•The 21154 makes 224 read attempt s resu lting in a resp onse of target retry.

After the 21154 makes 224 attempts of the same delayed read transaction on the target bus, the

21154 asserts p_serr_l if the primary SERR# en able bit is set in the command register and th e

implementat ion-specifi c p_serr_l disable bit for this condition is not set in the p_se rr_l eve nt

disabl e re gist er. The 2 1 154 s tops i nitia ti ng tr ansacti ons i n respo nse t o that d elaye d read t ransa ction .

The de layed read reque st is disc arded. Upon a subsequent read t r ans action attempt by the in itiator,

the 21154 returns a target abort. See Se ction 7.4 for a description of system error conditions.

4.10.4 Target Termination Initiated by the 21154

The 21 15 4 ca n return a tar get retry, tar get di sconn ect, or tar get abort to an i nitia tor fo r reasons oth er

than detection of tha t condition at the target int erface.

4.10.4.1 Target Re try

The 21154 returns a target retry t o the initiator when it c annot acce pt write data or ret urn rea d data

as a result of internal conditions. The 21154 returns a target retry to an ini tiator when any of the

following condit ions is met:

•For delayed write trans ac tions:

— The transac tion is being entere d into the delayed transact ion queue.

— The transac tion has already been entered into the dela yed tran sa ction queue, but target

resp ons e has not yet been re ce ived.

— Tar get response has bee n received but has not progressed to the head of the return queue.

— The dela yed transacti on queue is full, and the transaction cannot be queued.

— A tra n sactio n wi th the same address and command ha s been queued.

— A locked sequen ce is being propaga ted acros s the 21 154, and t he write tra nsacti on is not a

locked transaction.

•For delayed read transac tions:

— The transac tion is being entere d into the delayed transact ion queue.

— The read request has already been que ued, but read data is not yet available .

— Data has been read from the t arget, but it is not yet at t he hea d of the read data queue, or a

posted write transaction precedes it.

— The dela yed transacti on queue is full, and the transaction cannot be queued.

— A delayed read request with the same addre ss and bus command has already been queued.

— A locked sequence is being propa gated across t he 21154, and the read transaction is not a

locked transaction.

— The 21154 is current ly discarding previously prefetched rea d data.

•For posted write transac tions:

21154 P CI-to-PCI Bridge

60 Datasheet

— The poste d write data buf fer does not h ave enough spa ce for add ress and at lea st 8 Dword s

of w r ite d a t a .

— A lo cked seque nce is bein g propagat ed across the 21 15 4, and the write transa ct ion is not a

l o cked transaction .

When a t arget r etry is returned to the initiator of a delayed tra nsactio n, the initiator m u st repe at th e

tr an sact ion wi th the s ame addr ess and bus c ommand as well a s th e dat a if t his is a write tra nsac ti on,

withi n the time frame speci fie d by t he master timeout va lue ; otherwi se, the tra nsacti on is dis carde d

f rom the 21154 buffers.

4.10.4.2 Ta rget Disconnect

The 21154 ret urns a target disco nnect to an initi ator when one of the following conditions is met:

•The 21154 hits an internal address boundary

•The 21154 cannot accept any more write data

•The 21154 has no more rea d data to deliver

See Section 4. 5.4 for a description of write addres s boundaries, a nd Section 4.6.3 for a description

of rea d address bounda ries.

4.10.4.3 Ta rget Abort

The 21154 returns a target abort to an initiator when on e of the following conditions is met:

•The 21154 is re tur ning a target abort from th e intended target.

•The 21 154 is unable to ob tain de la yed read data from the ta r get or to de li ver del ayed writ e da ta

to the target after 224 attempts.

Whe n th e 21 154 r etur ns a target ab or t to the i nit ia tor, it se ts t he si gna led tar g et abo r t bit i n th e s tatu s

r egister correspondin g to the init iator interface.

Datasheet 61

5.0 Address Decoding

The 21154 uses thr ee a ddress ranges that co ntrol I/O and memory transaction forwarding. These

address ranges are defined by ba s e and li mit address registers i n the 21154 configuration space.

This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.

5.1 Address Ranges

The 21154 uses the following address ranges that deter mi ne which I/O and memory tra ns actions

are forwa r ded from the prim ary PCI bus to th e s ec ondary PCI bus, and from the secondary bus to

th e pr imary bus:

•One 32-bit I/O address range

•One 32-bit memory-mapped I/O (nonprefet chable memory)

•One 64-bit prefetchable memory address range

Transactions falling within these ranges are forwarded downstream from the primary PCI bus to

the s econdary PCI bus. Transactions falli ng outsi de these ra nges ar e forwa r ded upstr eam from the

secondary PCI bus t o the prim ary P CI bus .

The 21154 uses a flat address space; that is, it does not perform a ny address transl ations. The

address space has no “gaps”—addresses that a r e not marked for downstr ea m forwar ding are

always forwarded upstre am.

5.2 I/O Address Decoding

The 21154 uses the following mechanisms that are defined in the 21154 configurati on spa ce to

specify the I/ O address space for downstream and upstream forwarding:

•I/O base and limit address registers

•The ISA en ab l e b it

•The VGA mode bit

•The VGA snoop bit

This section provides inf ormation on the I/O address registers and IS A m ode. Section 5.4 provi des

information on the VGA modes.

To enab le downst ream forwarding of I/O transactions, th e I/O enable bit must be set in the

comman d register in 21154 c onfiguration s pace . If the I/O enable bit is not set, all I/O transactions

initiated on the primary bus are ig nored. To enable upstream forwar ding of I/O trans act ions , the

master enable bit must be set in the command register. If the master enable bit is not set, the 21154

ig nor es all I/ O a nd me mory transactions initiated on the se condary b u s. Setting the master enable

bit also allows upstre am forwarding of memory tra nsactions.

Caution: If any 21 154 configuration sta te affecting I/O transaction forwarding is changed by a configuration

write ope ration on the primary bus at the same time that I/O transactions are ongo ing on the

secondary bus, the 21154 response to the seco ndary bus I/O transactions is not predictable.

21154 P CI-to-PCI Bridge

62 D atashee t

Configure the I/O base and limit a ddress registers, ISA enabl e bit, VGA mod e bit, and VGA sn oop

bit before setting the I/O enable and master enable bits, and change them subsequently only when

the primary and secondary PCI buses are idl e.

5.2.1 I/O Base and Limit Address Registers

The 21154 implements one set of I/O base and limit address re gisters in configurat ion space that

defi ne an I/O addr ess range for downstr eam forwardi ng. The 21 154 supp orts 32-b it I/O addre ssing,

which al lows I/O addre sses downstr eam of t he 21 1 54 to be mapped a nywhere in a 4GB I/O a ddre ss

space.

I /O transactions wit h address es that fall i ns ide the range defined by the I/O base and l im it regi sters

are forwarde d downs tream from the pri mar y P CI bus to the sec ondary PCI bus. I/O transactions

with address es th at fa ll outs ide this range are forwarde d upstream from the secondary PCI bus to

the primary PCI bus.

The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/

O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and

no I/O transactions are forwarded downstream.

Figure 15 illustrate s tran saction forwarding within and outside the I/O addre ss range.

The 21154 I/O range has a minimum granula rity of 4KB and is aligned on a 4KB boundary. The

maximum I/O range is 4GB in size.

The I/O base register c onsists of an 8-bit field at configuration address 1Ch, and a 16-bit field at

address 30h. The top 4 bits of the 8-bit fie ld define bits <15:12> of the I/O base address. The

bott om 4 bits read on ly as 1h to indic ate th at the 2 1 154 su pport s 32-bit I/O addre ssing. Bits < 11 :0>

of the base address are as sumed to be 0, which naturally alig ns the base address to a 4KB boundary .

The 16 bits contained in the I/O base upper 16 bits register a t configuration offset 30h define

AD<31:16> of the I/O base addres s. All 16 bits are re ad/write. After primary bus res et or chip

r eset, the value of th e I/O base address is initializ ed to 0000 0000h.

Figure 15. I/O Transac tio n Forward ing Usi ng Base and Limi t Address es

LJ-04636.AI4

I/O Limit

Primary

Interface Secondary

Interface

4KB

Multiple

I/O Base

I/O Address Space

21154 PCI-to-PCI Bridge

Datasheet 63

The I/O lim it register consists of an 8-bit fie ld a t configuration offset 1Dh and a 16-bit field at

of fset 32h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O limit address. The bottom

4 bits read only as 1h to indicate that 32-bit I/O addres sing is supported. Bits <11:0> of the limit

address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O

address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration of fs et

32h define AD<31:16> of the I/O limit address. All 16 bits are read/write. After prim ary bus reset

or chip reset, t he va lue of the I/ O limit a ddress is reset to 0000 0FFFh.

Note: The initi al states of the I/O base and I/O limit address registe r s define an I/O range of 0000 0000h

to 0000 0FFFh, which is the bot tom 4KB of I/O s pace . Write the se registers with their appropri ate

values be f or e setting either the I/O enable bit or the ma ster enable bit in the command register in

configuration spa ce .

5.2.2 ISA Mode

The 21154 supports ISA mode by providing an ISA enab le bit in the brid ge control r egister in

configurat ion space. ISA mode modifies the respons e of the 21154 inside t he I/O address r ange in

order to s upport mapping of I/O space in the presence of a n I SA bus in the system . This bit only

affects the resp onse of the 21154 whe n the transaction falls inside the address range defi ned by the

I/O base and limit address registers, and only when this address also fal ls insi de the first 64KB of I/

O space (address bit s <31:16> are 0000h).

When the ISA enable bit is set, the 21154 does not forwa r d downstr eam any I/O transactions

addressing the top 768 byte s of each aligned 1KB bloc k. Only thos e tra nsactions addressing the

bottom 256 bytes of an al igned 1KB block insid e the base and limit I/O address range are

for warded downstream. Transactions above the 64KB I/O address boundary are forwa r ded as

defined by the addre ss range defined by the I/O bas e and limit regi sters.

Accordingly, if the ISA enable bit is set, the 21154 forwards upstream thos e I/O transact ions

addressing the top 768 byte s of each aligned 1KB bloc k within the first 64KB of I/O space. The

maste r ena ble bit in the command configuration regi ster must also be set to e nable upstream

for warding. All other I/O transactions i nitiated on the secondary bus are forwarded upst rea m only

if they fall outside the I/O address range.

When the ISA enable bit is set, devices downstream of the 21154 can hav e I/O space mapped into

the firs t 256 bytes of each 1KB chunk be low the 64KB bounda ry, or anywhere in I/O space a bove

the 64KB boundary.

21154 P CI-to-PCI Bridge

64 D atashee t

Figure 16 illustrates I /O fo r warding when the ISA enable bit is set.

5.3 Memory Address Decoding

The 21154 has three mechanisms for de fining memory addre ss ranges for forwardi ng of memory

transactions:

•Memory-mapped I/O base and limit address registers

•Pre fetch able memory bas e and li mi t address regis ters

•VGA mode

Th is se ct ion de sc rib es the fi rs t tw o m ech an i s ms . Se ction 5.4.1 desc ribes VGA mode.

To enable downstream forwarding of memory transac tions, the memory ena ble bit must be set in

the command re gister in 21154 c onfigura tion space. To enable upstream forwarding of memory

t r ansactions, the master en able bit must be set in th e comma n d reg ister. Setting the master ena ble

bit also all ows upstream forwarding of I/O transacti ons .

Caution: If any 21154 conf iguration sta te affecti ng me mory transaction forwarding is changed by a

configuration write oper ation on the prim ary bus at the same tim e tha t m em ory transactions are

ongoing on the s ec ondary bus, the 2115 4 response to the s econdary bus memory transactions is not

Figu re 16. I /O Tr ansactio n Forwarding in ISA Mo de

LJ-04637.AI5

5000h - FFFFh

4C00h - 4CFFh

4800h - 48FFh

4400h - 44FFh

0000h - 3FFFh

I/O Address Space

Note:

In this example:

I/O Base Address = 0000 4000h

I/O Limit Address = 0000 4FFFh

ISA Enable = 1

4000h - 40FFh

Primary

Interface Secondary

Interface

4D00h - 4FFFh

4900h - 4BFFh

4500h - 47FFh

4100h - 43FFh

21154 PCI-to-PCI Bridge

Datasheet 65

predictable. Configure the memory-mapped I/O base and lim it addre ss registe rs, pref etch able

memory base and limit address registers, and VGA mode bit before setting the mem ory enable an d

maste r enable bits, and change them subseq uently onl y when the primary and secondary PCI buses

are idle.

5.3.1 Memory-Mapped I/O Base and Limit Address Register s

Memory-mapped I/O is also referred to as nonprefetchable memory. Memory addresses that

cannot aut o m atically be pre f etche d but that can conditionall y prefetch based on comma nd type

should be mappe d into this space. Read transactions to nonprefe tchable space may exhibit side

effects; th is space may have non-m emory-like behavior. The 21154 pref etch es in this space onl y if

the mem ory read li ne or memory read multi ple commands are used; transact ion s using the memory

read command a re li mited to a single data transfer.

The memory-mapped I/O bas e address and memory-mapped I/O limit add r ess regis ters define an

address range that the 21154 uses to determi ne when to forward memory commands. The 21154

for wards a memo ry transaction f rom the primary to the secondary i nterfac e if the transaction

address falls within the me mory -mapped I/O address range. The 21154 ignores me mory

transactions initiated on the secondary interface that fall into this address range. Any transactions

that fall outsi de this address range a re ignore d on the prim ar y interfa ce and are forward ed upst ream

from the s econdary interfac e (provided that they do not fall into the prefetchable memory range or

are not forwarded downstre am by the VGA mechani sm).

The memory-mapped I/O range supports 32-bit add r essing only. The PCI-to-PCI Bridge

Ar chite cture Spe ci fication do es not pr ovide for 64-bit addr essing in the memory-mapped I/ O space.

The memory-mapped I/O address range has a granul arity an d ali gnment of 1MB. The maximum

memory-mapped I/O addres s range is 4GB.

The memory-mapped I/O address range is defined by a 16-bit me mory -mapped I/O base address

regis ter at configuration offset 20h and by a 16-bi t memo ry-mapped I/O limit addr ess regi st er at

of fs et 22h. The top 12 bits of each of these registers correspond to bits <31:20> of the me mor y

address. The low 4 bits ar e hardwired to 0. The low 20 bits of the memory-mapped I/O base

address are ass umed to be 0 0000h, whic h results in a natural alignme nt to a 1MB boundar y. The

low 20 bits of the memory-mappe d I/O limi t address are assumed to be F FFFFh, which results in

an alignment to the top of a 1MB block.

Note: T he initi al st ate of the memory- mapped I/O bas e address reg iste r is 0000 0000h . The initia l sta te of

th e memo ry-m ap ped I/O limit address reg ister is 000F FFFFh. Note that the ini t ial sta tes of these

registers de fine a memory-mapped I/O range at the bottom 1MB block of memory. Write these

registers with their appropriate values before setting either the memory enable bit or the master

enable bit in the com mand register in configuration spac e.

To turn off the memory-m apped I/O address range, write the memory-mapped I/O base address

regis ter with a v alue greater than that of the memory-mapped I/ O limit address register.

21154 P CI-to-PCI Bridge

66 D atashee t

Fi gure 17 shows how tra nsacti ons are f orward ed using b oth the memo ry-mapped I/O ra nge and the

prefetchable memory range.

5.3.2 Prefetchable Memory Base and Limit Address Registers

Loca tio n s accessed in the pr e f et ch ab l e m e m o ry ad d r ess ra nge must ha v e tru e m e m o r y -li ke

behavior and must not exhibit side effect s when rea d. This means that extra reads to a prefetchable

memory location must have no side effects. The 21154 prefetches for all types of memory read

com mands in this address spac e.

The prefetchable memory base address and prefetchable memory limit address registers define an

address range that the 21154 uses to determine when to forwar d memory commands . T he 21154

forward s a memor y tran saction fr o m th e p r imary to the secondary i n terfa ce if the transact io n

address falls within the prefetchable memory address range. The 21154 ignores m emory

tr ansact ions initiated on the s ec ondary interface that fall into this address range. The 21154 does

not res pond to any transact ions that fall outs ide this add res s range on the primary interface and

f orwards those transactions up st ream from the seco ndary inte rface (provided that they do not fall

into the memory-mapped I/ O range or are not forwarded by the VGA mechani sm).

The pr efetchabl e mem ory range supports 64-bit addre ssing and provid es additional regi sters to

defi ne the upper 32 bit s of the memory address rang e, the prefetcha ble memory base addre ss upper

32 bits register, and the prefetcha ble memory limit addres s upper 32 bits regis ter. For addre ss

com parison, a single a ddress cycle (32-bit add res s ) prefetchabl e memory tr ansacti on is treat ed like

a 64-bi t addr ess tran saction where t he upper 32 bit s of the addres s are equa l to 0. This uppe r 32-bit

value of 0 is compared to the prefe tchable memory bas e add r es s upper 32 bits r egister and the

Figu re 17 . M em ory Tr ansact io n Fo rwa rding U sing Bas e and Li m i t Registers

LJ-04639.AI4

Prefetchable Memory Limit

Prefetchable Memory Base

Primary

Interface

Note:DAC – Dual Address Cycle

SAC – Single Address Cycle

DAC

SAC

DAC

SAC

4GB

SAC

Secondary

Interface

1MB

Multiple

Memory Address Space

Memory-Mapped I/O Limit

Memory-Mapped I/O Base

SAC

SAC1MB

Multiple

21154 PCI-to-PCI Bridge

Datasheet 67

prefetc hable m emory limit address upper 32 bits regis ter. The prefet chable memory base address

upper 32 bits register must be 0 in order to pass any single address cycle tra nsactions downstream .

Section 5.3 .3 further describe s 64-bit addre ssing support.

The prefetchable memory address range has a granularity and alignment of 1MB. The maximum

memory ad dres s range is 4GB when 32-bit addressing is us ed, and 264 bytes when 64-bit

addressing is used.

The prefetchable memory address range is define d by a 16-bit prefetchable memory base address

regis ter at configuration of fset 24h and by a 16-bit prefet chable memory limit address register at

of fset 28h. The top 12 bi ts of each of these registers correspond to bits <31:20> of the memory

address. The low 4 bits ar e ha rdwired to 1h, indica ting 64-bit address suppo rt. The low 20 bits of

the prefetcha ble memory ba se address are assu med to be 0 0000h, whic h results i n a nat ural

alignm ent to a 1MB boundary. The low 20 bits of the prefetchable memory lim it address are

assumed to b e F FFFFh, which results in an alig nment to the top of a 1MB block.

Note: T he init ial s tate o f the pref etcha ble memo ry base addr ess registe r is 0000 00 00h. The ini tial state of

the prefetchable memor y limit address register is 000F FFFFh. Note that the initial states of these

regis ters define a prefe tchabl e m emory range at the bottom 1MB block of memory. Write the se

registers with their appropriate values before setting either the memory enable bit or the master

enable bit in the com mand register in configuration spac e.

To turn off the prefetch able mem o r y addres s range, write the p r efet ch able me mory base addre ss

re gist er with a value gr eate r than th at of the pref etc hab le mem ory lim it addre s s regis ter. Th e ent ire

bas e val ue m ust be greater tha n the entire limit value, meaning that the upp er 32 bits must be

cons idered. Therefore, to disable the address range, the upper 32 bits register s can both be set to

th e same value, whil e the lower base reg ister is set gr eater tha n the lower limit register; otherwise,

the upper 32-bit bas e must be greater than the upper 32-b it limit.

5.3.3 Prefetchable Memory 64-Bit Addressing Registers

The 21154 supports 64-bit memory address decoding for forwarding of dual address memory

tr ans actions. The dua l address cycle is used to supp ort 64-bit addre ssing. The f irs t address phase

of a dual ad dress transaction contai ns the low 32 addre ss bits, and the second add r es s phase

contains the high 32 address bits . During a dua l address cycle transaction, the u pper 32 bits must

never be 0—use the s ingle ad dress cycle commands f or transactions a ddressing the first 4GB of

memory space.

The 21154 impl ements the prefetcha ble memor y bas e address uppe r 32 bits regis ter and the

prefetch able memory lim it addre ss upper 32 bits register to define a prefetchable memor y address

range greater than 4GB. The prefe tchable address space can the n be de fined in three different

ways:

•Residing e ntirely in the first 4GB of memory

•Res iding ent irely above th e firs t 4GB of memory

•Crossing the first 4GB memory boundary

If the prefetchable memory space on the secondary interface resides ent irely in the first 4GB of

memory, both upper 32 bits registers must be set to 0. The 21154 ignores all dual address cycle

tr ansactions initiated on the pr imary in terface and f or w ards all dual address transacti ons initiated

on the secondary inte rface ups tream.

21154 P CI-to-PCI Bridge

68 D atashee t

I f the sec ondary interface prefetcha ble memory space re s ides entirely above the f irs t 4GB of

me mory, b oth the prefetcha ble memor y bas e ad dres s upper 32 bits register and the prefetchable

me mory lim it address upper 32 bits register must be initialized to nonzero va lues. The 21154

ignores all single addre s s memory transac tions initia ted on the primary interface and forward s al l

single addre s s memory transacti ons initiated on the secondary interface ups tream (unless they fall

within the memory-mapped I/O or VGA memory range). A dual address memory transaction is

f orwarded downst rea m from the primary interfa ce if it fa ll s within the address ran ge define d by the

pr efetchable memory base addr es s , prefetcha ble memor y bas e ad dres s upper 32 bits , prefe tchab le

me mory lim it address, and prefetchable memor y lim it addre ss upper 32 bits re gis ters. If the dual

addr ess trans action initiat ed on the secondary i n terface fall s outs ide this addres s rang e, it is

f orwarded upstream to the primary interface. The 21 154 does not resp ond to a dua l address

tr ansact ion initiated on the primary int erfa ce tha t falls outside this addres s ra nge, or to a dual

address transaction initiated on the secondary interface that falls within the address range.

I f the second ary in terfac e prefe tchabl e memory space s traddl es the firs t 4GB addre ss bou ndary, the

p refe tchable me mory b ase addres s upper 32 bi ts register is set t o 0 , whil e the prefetchable memory

lim it addre ss upper 32 bits re gister is initialized to a nonzer o value. Sing le a ddress cycle memory

t ran sactions are com p ared to t h e p refetchabl e memory base address re g ister on ly. A transaction

initiated on the primary interfac e is forwarded downstream if t he address is great er than or equal to

the base add r ess. A tra ns action initiated on the sec ondary interface is forwar ded upstream if the

ad d ress is le ss than the base ad d r ess. Dual address t r ansactions a re comp ared t o th e p refetchable

memory lim it address and the prefetcha ble memory limit addres s upper 32 bits registers. If the

addr es s of the dual add res s tra nsac ti on is le ss t han or equ al t o the limi t, the tra ns actio n is forwa rded

d ownstream from the primary inter f ace and is ignored on the se condary interface. If the address of

the dual ad dres s transaction is greate r than this limit, the tra nsaction is ignored on the prim ary

interface and is forwar ded ups tream from the secondary interface.

The pr efetc hable memory base address upper 32 bits register is locat ed at configurati on Dword

of fset 28h, and the prefet chable memory limit address upper 32 bits re gister is locat ed at

configuration Dword offset 2Ch. Bot h r egisters are reset to 0. See Fig ure 17 for an illus tration of

h o w transact io ns are f o rwa rded usi n g b o th the memo r y -mapp ed I/O range an d th e prefetchable

memory range.

5.4 VGA Support

The 21154 provides two modes for VGA support:

•VGA mode, supporting VGA-compatible a ddressi ng

•VGA snoop mode, sup porting VGA palette forwa rding

5.4.1 VGA Mode

When a VGA-com patible device exists downstr eam from the 21154, set the VGA mode bit in the

br idge control register in configu r ation space to enable VGA m ode. When the 21154 is operating

in VGA mode, it forwards downstream those transactions addressing t he VGA frame buffe r

memory a nd VGA I/O registers, regardless of the values of the 21154 base and limit addres s

registers. The 21154 ignores transactions initiated on the secondary interface addre ssing these

locations.

The VGA frame buffe r consists of the following memor y address range:

000A 0000h-000B FFFFh

21154 PCI-to-PCI Bridge

Datasheet 69

Read trans actions to frame buffer m emory are tr eated as nonprefetchabl e. The 21154 re quests only

a si ng l e d at a tr an s f e r fro m th e ta rg et , an d re ad by t e en ab le bi t s ar e fo r w a rd e d to th e targ e t bu s.

The VGA I/O addresses consist of the following I/O addresses:

•3B0h–3BBh

•3C0h–3DFh

These I/O a ddresses are alia sed every 1KB th roughout the first 64KB of I/O space . This means

that address bits <15:10> are not decoded an d can be any value, while addres s bits <31:16> must

be all 0s.

VGA BIOS addresses starting at C0000h are not decode d in VGA mode.

5.4.2 VGA Snoop Mode

The 21154 provides VGA snoop mod e, allowing for VGA palett e write transactions to be

for warded downstream. This mod e is used when a graphics device downstream from t he 21154

needs to snoop or respond to VGA palette write transacti ons. To enabl e the mode , set the VGA

snoop bit in the command register in co nfiguration space .

Note that t he 2115 4 claims VGA palette write transactions by ass erting DEVSEL# in VGA snoop

mode .

When the VGA snoop bit is set , the 21154 forwards downstream tr ansactions with the following I/

O addresses:

•3C6h

•3C8h

•3C9h

Note that these addresses are also forwarded as part of the VGA compatibility mode previousl y

des cribed. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal

to 0, which means that these addresses a re aliased every 1KB throughout the first 64KB of I/O

space.

Note: If both the VGA mode bit and the VGA snoop bit are set, the 21154 beha ves in the same way as if

only the VGA mode bit were set.

Datasheet 71

6.0 Transaction Ordering

To maint ai n data cohere ncy and c onsist ency, the 211 54 co mplies with the orde ring rules s et f orth in

the PCI Local Bus Specification, Revis ion 2.1, for transact ions crossing the bridge.

This chapter describes the ordering rules that control transaction forwarding acro ss the 21154. For

a more deta iled discuss ion of transaction ordering, s ee Appendix E of the PCI Local Bus

Specification, Revision 2.1.

6.1 Transactions Governed by Ordering Rules

Ordering relationships are established for the following cla sses of transa ctions cro ssing the 21154:

•Pos ted write transactions, comprised of memor y wr ite and memory wr ite and invalidat e

transactions

Posted write transactions complete at the source before they complete at the destination; that

is, data is wr itten into intermediate da ta bu ffers before it reaches the tar g et.

•Delayed write reques t trans act ions, compris ed of I/O write and co nfiguration write

transactions

Delayed write requests are termin ated by target retry on t he initiator bus and are queued i n the

dela yed tra nsac tion queu e. A del ayed writ e tr ansact ion must c omple te on the ta rget bus befo re

it completes on the initiator bus.

•Delayed write compl etion transactions, also comprised of I/O write and confi guration write

transactions

Delayed write compl etion transactions have been completed on the target bus , and the target

resp onse is queued in the 21154 buffers. A delayed write completion transaction proceeds in

the direction opposite that of the original delayed write request; that is, a delayed writ e

completion transac tion proceeds from the targe t bus to the initiator bus.

• Delayed read request transactions, comprised of all m emory read, I/O re ad, and configuration

read transactions

Delayed read requests ar e terminated by target ret r y on the initiator bus and a r e queued in the

delaye d transaction queue.

•Delay ed re ad completion transactions, comprised of all memory read, I/O read, and

configuration read transactions

Delayed read co mpletion tr an sactions h av e been completed on t h e target bus, an d the read

data ha s been queued in the 21154 read data buffers. A del ayed read completion transaction

proceeds in the direct ion opposite tha t of the original delayed read reque st; that is, a delayed

read completion transaction p roc eeds fr o m the targ et bus to t h e initiator bus.

The 21154 does not com bine or merge write transac tions:

•The 21154 does not com bine separate write tra nsactions into a si ngle write transactio n—this

optimization is best imp lemen ted in the originating master.

•The 21154 does not merge bytes on separate masked writ e tra nsactions to the same Dword

address—this optimiz ation is also bes t im plemented in the originating master.

•The 21154 does not collapse sequential write tran sa ctions to the same addres s into a single

write transact io n —the PCI Local Bus Specific ation does not permit this com bining of

transactions.

21154 P CI-to-PCI Bridge

72 Datasheet

6.2 General Ordering Guidelines

Independent transactions on the primary and secondary buses have a re lationship only when those

tr ansactions cros s the 21154.

The following genera l ordering guidelines govern transactions cross ing the 21154:

•The or dering rel ationship of a transaction with respect to other transactions is determined

when the transaction completes, that is, when a transaction ends with a termination other than

target retry.

•Reque sts terminate d with tar get retry can be ac cepted and completed in any order with respect

to other transactions that have been terminated with target retry. If the or der of co mpl etion of

delayed requests is importa nt, the initiator should not s tart a second delayed tra nsaction until

the first one has been comp leted . If more than one delaye d transaction is initiated, the initiator

should repeat all the delaye d transaction requests, using some fa irness algorithm. Repe ating a

delayed transaction can not be contingent on completion of another delayed transaction;

otherwise, a deadlock can occur.

•Write tra nsactions f lowing in one direction have no ordering requirements with respect to

write tran sa ctions flowing in the other di rec tion. The 21154 can accept posted write

t r ansactions on both inter f aces at the same ti me, as well as initiate posted wri te transact io ns on

b o th interfaces at the s ame time.

•The acc eptan ce of a po st ed m emory write transaction as a ta rget can never be cont ingent on

the completion of a nonlocked, nonposted transaction as a maste r. This is true of the 21154

and mu st also be true of other bus agents; otherwise, a deadlo ck can occur.

•The 21154 accept s posted write tr ansactions, rega rdless of the state of co mpl etion of an y

delayed transactions being forwarded across the 21154.

6.3 Ordering Rules

Table 25 shows the ordering rel ationshi ps of all the transactions and refers by num ber to the

or dering rules that follow.

Note: The supers cript acco mpanyi ng some of t he tabl e entr ie s refers to any ap pli cable orde ring rule li sted

in this section. Many entries are not governed by these ordering rules; therefore , the

Tab le 25. Summ ary of Tran saction Order ing

↓ Pass→Posted

Write

De la yed

Read

Request

Delayed

Write

Request

Delayed

Read

Completion

Delayed

Write

Completion

Posted write No1Yes5Yes5Yes5Yes5

Delayed read request No2No No Yes Yes

De la yed wr it e re qu e st No 4No No Yes Yes

De la yed read co m pl etion No 3Yes Yes No No

Delayed write completion Yes Yes Yes No No

21154 PCI-to-PCI Bridge

Datasheet 73

implementat ion can ch oos e whether or not the tran sa ctions pass each other. The entries without

supe rscripts reflect the 21 154’s implementat ion choices.

The fol lowing ordering rules des cribe t he transaction relationships. Each ordering rule is fol lowed

by an explanation, and the ordering rules are refe rred to by number in Table 25. Th es e orde ring

rules apply to posted write transac tions, delayed write and rea d requests, and delaye d write and

read completion transactions crossing the 21154 in the same direction. Note that delayed

comp letion transactions cross the 21154 in the directi on opposite that of the corresponding delayed

reque st s .

1. Posted write transac tions must co mplete on the target bus in the or der in which they wer e

received on the in itiator bus.

The subs equent posted write transaction can be setting a flag that covers the data in the firs t

post ed write tr ansa ction; if the s econd t ransact ion were to compl ete be fore the firs t t ransact ion,

a devic e c hecking the flag could subseq uently consume stal e dat a.

2. A delayed read request traveling in the same direction as a previously queued posted writ e

tr ans act ion must push the posted write data ahead of it. The post ed write transacti on must

comp lete o n the target bus before the delayed read request ca n be at temp ted on the target bus.

The r ead transaction can b e to the same loc ation as the wr ite data, so if the read transaction

wer e to pass the write tr ansaction, it wou ld return stale data.

3. A delay ed read compl etion must “pull ” ahea d of previousl y queu ed post ed write data tra veling

in the s ame direction. In this case, the re ad data is traveli ng in the same direction as the write

data, and the in itiator of the read tr ansaction is on the same si de of the 21154 as the target of

the write transaction. The posted write transaction must complete to the target before the read

data is returned to the initiator.

The read transaction ca n be to a sta tus register of the initiator of the posted write data a nd

therefore should not complete until the write transaction is complete.

4. Delay ed write reques ts cannot pass previous ly queued poste d write data.

As in the case of posted memory write transacti ons, the del aye d write transaction can be

set ting a flag that cove rs the data in the posted write trans act ion; if the dela yed write request

were to co mplete before the earlier posted write transac tion, a d evice chec king the flag could

subsequently consume stale data.

5. Poste d write transactions mus t be given opportunities to pas s delayed read and write reque sts

and completions.

Otherwise, de adlocks may occur when bridges that support dela yed transactions are us ed in

the sam e system with bri dges that do not support del ayed tra nsac tions . A fairne ss algori thm is

use d to arbitrate between the posted write que ue and the dela yed transact ion queue.

6.4 Data Synchronization

Data synchronization refers to the relationship between in terrupt signaling and dat a delivery. The

PCI Local Bus Spe cification, Re vision 2.1, p r ovides the fo llowing alterna tive metho ds for

sync hronizing data and interrupts.

•The device signaling the inte rrupt performs a read of the data just written (software).

•The device driver performs a read opera tion to any register in the interrupting device before

acc essing da ta writt en by the device (software).

•System hardware guarantees that write buffers are flushed before interrupts are forwarded.

21154 P CI-to-PCI Bridge

74 Datasheet

The 21 154 doe s not have a hardware mechani sm to guarant ee dat a synchron iz ation fo r poste d wri te

t ran sactions. Therefore, all posted write transact io n s mus t be followed by a read o p eration, eith er

f r om th e device to the location just written (or som e other locat ion along the same path), or fr om

the device driver to one of the device registers.

Datasheet 75

7.0 Error Handling

The 21154 checks, forwards, and generates parity on both the prim ary and secondary interfa ces.

To maintain transpa rency, the 21154 al ways tri es to forward the existing parity cond ition on one

bus to the other bus, along wit h address a nd data. The 21154 always attempts to be transparent

when reporting errors, but this i s not always possi ble, given the prese nce of posted data and

delaye d transactions.

To supp ort error reporting on the PCI bus, the 21154 implements the following:

•PERR# and SERR# s ignals on both the prima ry and s ec ondary interfaces

•Primary status and s econdary status registers

•The device-speci fic p_s err_l event disable register

•The device-spe cific p _s err_l status register

This chapter provides detaile d information abou t how the 21154 handles errors. It also des cribes

error status reporting and e rror ope ration disabling.

7.1 Address Parity Er rors

The 21154 checks address parit y for all transact ions on bot h buses, for all address and all bus

commands.

When the 21154 dete cts an address parity error on the primary interface , the following events

occur:

•If the pari ty error response bit is set in the command register , the 21154 does not claim the

tr ansaction with p _devsel_ l; this may allow the transaction to terminate in a master abor t.

If the pari ty error response bit is not set, the 21154 proceeds normally and accepts the

tr ansaction if it is directed to or ac ross the 21154.

•The 21154 sets th e det ected parity error bit in t he status register.

•The 21154 asse rts p_serr_ l and sets the s ignaled system error bit in the status register, if both

of the following conditions are met:

— The SERR # enable bit is set in the command register.

— The parity error re sponse bit is se t in the command reg is ter.

When the 21154 dete cts an addre ss parity error on the seco ndary interface , the following events

occur:

•If the parit y error respons e bit is set in the bri dge contr ol regis ter , the 21 154 does not cl aim the

tr ansaction with s_devsel_l; this may al low the transac tion to termi nate in a master abort.

If the pari ty error response bit is not set, the 21154 proceeds normally and accepts the

tr ansaction if it is directed to or ac ross the 21154.

•The 21154 sets the det ec ted parity error bit in the secondary s tatus register.

•The 21154 asse rts p_serr_ l and sets the s ignaled system error bit in the status register, if both

of the following conditions are met:

— The SERR # enable bit is set in the command register.

21154 P CI-to-PCI Bridge

76 Datasheet

— The parity error re sponse bit is se t in the bridge control regis ter.

7.2 Data Parity Errors

When forwarding transactions, the 21154 attempt s to pa ss the data pa rity condition from one

interface to the other unchanged, whenever poss ible, to allow the mast er and tar get devices to

handle the error condition.

The following sections describe, for each type of tra nsacti on, the sequence of events that oc curs

when a pa rity error is detected and the way in which the pari ty condition is forwarded across the

21154.

7.2.1 Configuration Write Transactions to 21154 Configurat ion Space

When th e 21 154 d et ects a d ata pa rit y error duri ng a Type 0 c onfi guratio n writ e transa ct ion to 21154

configuration spac e, the following events occur:

•I f the pa rity error re sponse bi t is set in the command regis ter , the 21154 asserts p_trdy_l and

writes the da ta to the configuration register. The 21154 also asserts p_perr_l.

I f the pa rity error re sponse bi t is not set, the 21154 does not assert p_perr_l.

•The 21154 sets the de tected parit y error bit in the status register, regar dless of the state of the

parity error response bit.

7.2.2 Read Transactions

When the 21154 detec ts a parity error during a read tra nsaction, the ta rget drives data and data

parity, and the initiator c hecks parity and conditionally asserts PERR#.

For downstream transactions, when the 21 154 detects a rea d data parity error on t he second ary bus,

the following events occur:

•The 21154 asserts s_perr_l two cycles following the data tr ans fer, if the seco ndary interface

parity error response bit is set in the bridge control register.

•The 21154 sets the detected parity error bit in the secondary status register.

•The 21154 sets the data parity dete cted bit in the secondary status register, if the seconda ry

interface parity error r esponse bi t is se t in the bridge control registe r.

•The 21154 forwards the bad parity with the dat a back to the ini tiator on the primary bus .

I f the da ta with the bad parity is prefetched and is not read by the initiator on the pr imary bus,

the data is discarded and the data with ba d parity is not re turned to the initiat or.

•The 21154 completes the transaction normally.

For upstream transactions , when the 21154 detects a rea d data pari ty error on the primary bus, the

following events occ ur:

•The 21154 asserts p_perr_l two cycles following the data transfer, if the primary interface

parity error response bit is set in the command regis ter.

•The 21154 sets the detected parity error bit in the primary status register.

21154 PCI-to-PCI Bridge

Datasheet 77

•The 21154 sets th e data parit y detect ed bit in the primary stat us regis ter , if the primary

interfac e pa rity error response bit is se t in the command register.

•The 21154 forwards the bad parity with the data back to the initiator on the seconda ry bus.

If the data with the bad parity is prefetched and is not read by the initiator on the seconda ry

bus, the da ta is dis carded and the da ta with ba d parity is not return ed to the ini tiator.

•The 21154 completes the transaction norma lly .

The 21154 returns to the initiator the data and parity that was received from the tar get. When the

in itiator detects a parity erro r on this read data and is enabled to re por t it, the initiat or a sserts

PERR# two c ycles after t he data tra nsfer oc cur s. It is as sumed th at t he init ia tor take s respons ib ility

for handling a parity error condition; therefore, when the 21154 detects PERR # asserted while

returning read data to the initiator, the 21154 does not take any further action and completes the

tr ans action norma lly.

7.2. 3 Delayed Wr ite Tra nsac tions

When the 21154 detects a data parity e rror during a delayed write transaction, the initiator drives

data and data parity, and the tar get che cks parity and c onditiona lly as se rts PERR#.

For delayed writ e transactions, a parity error can occur at the following times:

•During the original delayed write request transaction

•When t h e in itiator repeats th e d elayed w rit e r equest tran saction

•When the 21154 completes the delayed write trans action to the target

When a delayed write tr ansaction is normally queue d, the ad dress, command, address parity, data,

byte enabl e bit s, and data parity ar e all capture d and a t arge t retry is retur ned to the init iator. When

the 21154 detec ts a parity error on the wr ite data for the ini tial delayed writ e request tr ansact ion,

th e f ollowing events occur:

•If the parity error response bit corre sponding to the initiator bus is set, the 21154 as serts

TRDY# to the initiator and the transaction is not queued. If multiple data phase s a re

requested, S TOP# is also asserted to ca use a target dis connect. Two cycles after the data

tran sfer, the 21154 also asserts PER R #.

If the pari ty error response bit is not set, the 21154 returns a target retr y and que ues the

tr ansaction as usual. Signal PERR# is no t asserted. In this case, th e initiator repeats the

transaction.

•The 21154 sets th e detected parity error bit in the status register corr es ponding to the initiator

bus, regardless of the state of the parity error response bit.

Note: If pa rity che cking is turned of f and da ta parity errors have occurred for queued or subse quent

delayed write tr ansactions on the initiator bus, it is possible tha t the initiator’s reattempts of the

write transact ion may not match the original queued delayed wri te information contained in the

dela yed tra nsac tion que ue. In thi s case , a maste r t imeout co ndit ion ma y occur, pos sibl y result ing i n

a system error (p_serr_l assertion).

For downstream transactions, when the 21154 is deli vering dat a to the target on the secondary bus

and s_perr_l is asserted by the targ et, the following event s occur:

•The 21154 sets the second ar y interfac e data pari ty detected bit in the seco n d ary status register,

if the secondary parity error response bit is set in the bridge control regist er.

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78 Datasheet

•The 21154 captures the parity error condition to forward it back t o the initiator on the primary

bus.

Si mi larly, for upstream transa ctions, when the 211 54 is deliveri ng data to the target on the prim ary

bus and p_perr_l is asserted b y the tar get, t he following events occur:

•The 21154 sets the primary interface data parity de tected bit in the status register, if the

pr imary parity error response bit is se t in the comm and regist er.

•The 21154 captures the pa rity error condition to forward it ba ck to the initiator on the

secondary bus.

A delayed write transaction is complete d on the initiator bus when t he initiator repeats t he wr ite

tr ansact ion with the same address, comm and, data, and byt e en able bit s as the delayed writ e

command that is a t the head of the posted data queue. Note that the parity bit is not compare d

when determi ning whethe r the transact ion matches those in the delayed transaction queues.

Two cases must be cons idered:

•When pa rity e rror is detected on the initiator bus on a subsequent reattempt of the transaction

and was not detected on the target bus

•When parity error is forwarded back from the target bus

For downstream delayed writ e transactions, when the parity error is detected on the initiator bus

and the 21154 has write stat us to return, the following eve nts occur:

•The 21154 first asserts p_trdy_l and then asserts p_perr_l two cycles la ter, if the primary

interface parity error r esponse bi t is se t in the co mmand register.

•The 21154 sets the primary interface parity error detected bit in the status re gister.

•Bec ause there was not an exact dat a and byte enabl e match, th e writ e status is not returned and

th e transa ction remains in the queue.

Similarly, f o r upstream de layed write trans actions, when th e parity error is detected on the initiator

bus and the 21154 has write sta tus to return, the following events occur:

•The 21154 first asserts s_trdy_l and then asserts s_perr_l two cycles later, if the secondary

interface parity error r esponse bi t is se t in the bridge control registe r.

•The 21154 sets the secondary interfa ce parity error detected bit in the secondary status regis ter.

•Bec ause there was not an exact dat a and byte enabl e match, th e writ e status is not returned and

th e transa ction remains in the queue.

For downstre am trans acti ons, in the c ase where the parity erro r is be ing pass ed back from the targ et

bus and the parity erro r condition was not ori ginally detected on the in itiator bus, th e following

events occur:

•The 21154 asserts p_perr_l two cycles after the data transfer, if both of the following are true:

— The primary interface parity error res ponse bit is set in the command register.

— The secondary interface parit y error resp onse bit is set in the bridge control regi ster.

•The 21154 completes the transaction normally.

For upstream transactions , in the case where th e pari ty error is being passed back from the

target bus and the parity error condition was not originally detect ed on the initiator bus, the

following events occ ur:

•The 21154 asserts s_perr_l two cycles after the dat a tra nsfer, if both of the following are true:

21154 PCI-to-PCI Bridge

Datasheet 79

— The primary interface pari ty error response bit is set in the command r egister.

— The secondary interfa ce parity er ror res ponse bit is set in the bridge cont rol register.

•The 21154 completes the transaction norma lly .

7.2.4 Posted Write Transactions

During downstream posted write transactions, when the 21154, responding as a target, detects a

data parity error on the initi at or (primary) bus , the following events occ ur:

•The 21154 asse rts p_perr_l two cycles after the data tra ns f er, if the prim ary interface parity

error response bit is set in the command regi s ter.

•The 21154 sets th e prim ary interface parity error det ected bit in the sta tus register.

•The 21154 capt ures and forwards the bad parity condition to the secondary bus.

•The 21154 completes the transaction norma lly .

Similarly, during upstre am posted write transactions, when the 21154, responding as a target ,

detects a data parity error on the in itiator (secondary) bus, the following eve nts occur:

•The 21154 asse rts s_perr_l two cycle s after the da ta transfer, if the sec ondary interface parity

error response bit is set in the bridge cont rol register.

•The 21154 sets the secondary interface pa rity error detec ted bit in the secondary status register.

•The 21154 capt ures and forwards the bad parity condition to the prim ary bus.

•The 21154 completes the transaction norma lly .

During downstream write transactions, when a data parity error is reported on the target

(se condary) bus by the target’s assertion of s_ perr_l, the followi ng eve nts occur:

•The 21154 sets th e dat a parity detected bit in the seco ndary status regis ter , if the seco ndary

interfac e pa rity error re sponse bit is set in the bridge control register.

•The 21154 asse rts p_serr_ l and sets the s ignaled system error bit in the status register, if all of

the following conditions are met:

— The SERR # enable bit is set in the command register.

— The device-s peci fic p_s err_l disable bit for pos ted write parity e rrors is not set.

— The secondary interfa ce parity error response bit is set in the bridge cont rol register.

— The primary interface pari ty error response bit is set in the command r egister.

— The 21154 did not detec t the pari ty error on the primary (initiator) bus; that is, the parity

error was not forwarded from the primary bus .

During upstream write transactions, when a data pa rity error is reported on the t arget (pri mary) bus

by the tar get’ s assert ion of p_perr_l, the following events occ ur:

•The 21154 set s the data parity detect ed bit in the status regist er, if the prim ary interfac e parity

error response bit is set in the command regi s ter.

•The 21154 asse rts p_serr_ l and s ets the signaled system error bit in the stat us regist er, if all of

the following conditions are met:

— The SERR # enable bit is set in the command register.

— The secondary interfa ce parity er ror res ponse bit is set in the bridge cont rol register.

21154 P CI-to-PCI Bridge

80 Datasheet

— The primary interface parity error res ponse bit is set in the command register.

— The 21 154 did not de tect the parity error on the seconda ry (in iti ator) bus ; tha t is, the parity

error wa s not forwarde d from the secondary bus.

The as sertion of p_serr_l is used to signal the pa rity error condition in the cas e where the initiator

does not know that the error occurred. Because the data has already been delivered with no errors,

there is no other way to signal this information back to the initiator.

I f the pa rity error was forwa rded from th e initiati ng bus to the target bus, p_serr_l is not asserted.

7.3 Data Parity Error Reporting Summary

I n the pre vious sections , the 21154’s responses to data parit y errors are presented according to the

type of transaction in progress. This section organizes the 21154’s responses to data parity errors

acc ording to the status bits that the 21154 sets and the s ignals that it as se rts.

Table 26 shows setting the detec ted pari ty error bit in the status register , corresponding to the

pr imary interface. This bit is set when the 21154 dete cts a parity e rror on the primary int erfa ce.

Table 27 shows setting the detec ted pari ty error bit in the secondary status register, corresponding

to the secondary interfac e. This bit is set when the 21154 detects a parit y error on the secondary

interface

Tab le 26. Setting the Primary Interface Detected Parity Erro r Bit

Primary

Detected

Parity Error

Bit

Transaction

Type Direction Bu s Where

Error Was

Detected

Prim ary/Se condar y

Parity Error Response

Bits1

1. x — don’t care.

0 Read Downstream Primary x/x

0 Read Downstream Secondary x/x

1 Read Upstream Primary x/x

0 Read Upstream Secondary x/x

1 Posted write Downstream Primary x/x

0 P o ste d wr it e D o wns tr e a m Se co nd ar y x/ x

0 P o ste d w rite Ups trea m Pr i ma r y x/x

0 Posted write Upstream Secondary x/x

1 Delayed write Downstream Primary x/x

0 Delayed write Downstream Secondary x/x

0 Delayed write Upstream Primary x/x

0 Delaye d write Upstream Sec ondar y x/x

21154 PCI-to-PCI Bridge

Datasheet 81

Table 28 shows setting the data parity detected bit in the status regis ter , correspo nding to the

primar y interface. This bit is set under the fol lowing conditions:

•The 21154 must be a maste r on the primary bus .

•The parity error response bit in the command register, corresponding to the primary interface,

must be set.

•The p_perr_l signal is detec ted as serted or a parity error is detected on the prim ary bus.

Table 27. S etting the Secon dary Interfac e Detected Pari ty Error Bit

Secondary

Detected

Parity

Error Bit

Transaction

Type Direction Bus Where

Error Was

Detected

Primary/Secondary

Parity Error Response

Bits1

1. x — don’t care.

0 Read Downstream Primary x/x

1 Read Downstream Secondary x/x

0 Read Upstream Primary x/x

0 Read Upstream Secondary x/x

0 Posted write Downstream Primary x/x

0 Posted write Downstream Secondary x/x

0 Posted writ e Ups tream Primary x/x

1 Posted writ e Ups tream Secondary x/x

0 Delayed write Downstream Primary x/x

0 Delayed write Downstream Secondary x/x

0 Delayed write Upstream Primary x/x

1 Delayed write Upstream Secondary x/x

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82 Datasheet

Table 29 shows sett ing t he data par ity det ecte d bit in th e sec ondary s tatus re gist er , c orres ponding to

the secondary interface. This bit is set under the following c onditions:

•The 21154 must be a master on the secondary bus .

•The parity error re sponse bit in the bridge control regi ster, corresponding to the secondary

interface, m ust be set.

•The s_perr_l signal is detected as serted or a parity error is detected on the secondary bus.

Tab le 28. Setting the Primary Interface Data Parity Detected Bit

Primary

Data

Parity

Detected

Bit

Transaction

Type Direction Bu s W he r e

Error Was

Detected

Primary/Secondary

Parity Error Response

Bits1

1. x — don’t care.

0 Read Downstream Primary x/x

0 Read Downstream Secondary x/x

1 Read Upstream Primary 1/x

0 Read Upstream Secondary x/x

0 P o ste d write D o wns tr e a m P rim ary x/x

0 Posted write Downstream Secondary x/x

1 P o ste d write U p s trea m P rim ary 1/x

0 P o ste d wr it e U p s tream Sec on da r y x / x

0 Delayed write Downstream Primary x/x

0 Delay ed write Down s tream Secondary x/x

1 Delayed write Upstream Primary 1/x

0 Delayed write Upstream Secondary x/x

Tab le 29. Setting the Secondary Interface Data Pari ty Detected Bit (She et 1 of 2)

Secondary

Data Parity

Detected

Bit

Transaction

Type Direction Bu s W he r e

Error Was

Detected

Primary/Secondary

Parity Error Response

Bits1

0 Read Downstream Primary x/x

1 Read Downstream Secondary x/1

0 Read Upstream Primary x/x

0 Read Upstream Secondary x/x

0 Posted write Down stream Pr imary x/x

1 Posted write Downstream Secondary x/1

0 Posted write U pstream Primary x/x

0 Posted write Upstream Secondary x/x

0 Delayed write Downstream Primary x/x

21154 PCI-to-PCI Bridge

Datasheet 83

Table 30 shows assertion of p_perr_l. T his signal is set under the following c onditions:

•The 21154 is either the target of a write tr ans act ion or the initiator of a read transaction on the

primary bus.

•The parity error response bit in the command register, corresponding to the primary interface,

must be set.

•The 21 154 de te cts a data p arity er ror on the p rimary bus or de tects s_pe rr_l asse rted durin g the

comp letion phase of a downstream delayed write trans act ion on the target (secondary) bus.

Table 31 shows assertion of s_ perr_l. Th is signal is se t under the following conditions:

•The 21154 is either the target of a write tr ans act ion or the initiator of a read transaction on the

secondary bus.

•The parity error response bit in the bridge control register, corresponding to the secondary

interface, must be set.

•The 21154 det ects a data parity error on the secondary bus or detects p_perr_l assert ed durin g

the completion phase of an upstream delayed writ e tra nsaction on the t arget (primary) bus.

1 Delayed write Downstream Secondary x/1

0 Delayed write Upstream Primary x/x

0 Delayed write Upstream Secondary x/x

1. x — don’t care.

Table 29. S etting the Secondary Interface Data Parity Detected Bit (Sh eet 2 of 2)

Secondary

Data Parity

Detected

Bit

Transaction

Type Direction Bus Where

Error Was

Detected

Primary/Secondary

Parity Error Response

Bits1

Table 30. Assertion of p_perr_l

p_perr_l Transaction

Type Direction Bus Where

Error Was

Detected

Primary/Secondary

Parity Error

Re sp ons e B its1

1. x — don’t care.

1 (deass erted) Read Downstream Primary x/x

1 Read Downstream Secondary x/x

0 (asserted) Read Upstream Primary 1/x

1 Read Upstream Secondary x/x

0 Pos te d wr ite D ownst rea m Pri m ary 1 /x

1 Pos te d wr ite D ownst rea m Se c on da ry x /x

1 Posted wr ite U ps tre am Pri m ary x /x

1 Posted wr ite U ps tre am Sec on da r y x/x

0 Delayed write Downstream Primary 1/x

2. The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

Delayed write Downs tream Secondary 1/1

1 Delayed write Upstream Primary x/x

1 Delayed write Upstream Secondary x/x

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84 Datasheet

Table 32 shows as sert ion of p_serr_l. This s ignal is set under the following conditions:

•The 21154 has detec ted p_perr_l asserted on an ups tream posted write tra nsaction or s_perr_l

as serted on a downstream posted writ e transaction.

•The 21154 did not detect the pa rity error as a target of the posted write transaction.

•The parity error res ponse bit on the command register and the parity error response bit on the

br idge cont rol regis ter must both be set.

•The SERR# enable bit must be set in the command register.

Table 31. Assertion of s_perr_l

s_perr_l Transaction

Type Direction Bu s Where

Error Was

Detected

Primary/Secondary

Parity Error

Response Bits1

1. x — don’t care.

1 (deasserted) Read Dow nstream Primary x/x

0 (asserted) Re ad Do wnstream S econdary x/1

1 Read Upstream Primary x/x

1 Read Upstream Secondary x/x

1 Po ste d w rite Dow n s tr ea m Pri mary x/ x

1 Posted write Downstream Secondary x/x

1 Po ste d w rite Ups tr e am Pri ma r y x/ x

0 Posted write Upstream Secondary x/1

1 Delayed write Downstream Primary x/x

1 Delayed write Downstream Secondary x/x

2. The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

Delayed write Ups tream Prim ary 1/1

0 Delayed w rite Upstream Secondary x/1

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Datasheet 85

7.4 System Error (SERR#) Reporting

The 21154 uses the p_serr_l signal to report conditionally a number of system error conditions in

addition to the specia l case parity error co nditions described in Sect ion 7.2.3.

Whenever the as se rtion of p_serr_l is discussed in this document, it is assume d that the following

conditions apply:

•For the 21154 to assert p_ serr_l for any reason, the SERR# enable bit must be se t in the

command regis ter.

•Wheneve r the 21154 asserts p_serr_l, the 21 154 must al so set the si gnaled system error bit in

the status register.

In compliance with t h e PC I-to-PCI Bridge Architec ture Spe cification, the 21154 asserts p_serr_l

when it det ects the secondary S ERR# input, s_serr _l, asse rted and the SERR# forward enabl e bit is

set i n the bridge control regist er. In add ition, the 21 154 a lso sets the rec eived sys tem error bit in the

secondary status register.

The 21154 also conditionally asserts p_ser r_l for any of the followi ng reasons:

•Targ et ab o rt de te cted du ring p oste d w r it e tr a n s ac ti o n

•Mast er abort detected during pos ted write transaction

•Posted write dat a dis carded after 224 attempts to deliver (224 target re tr i es r e c ei ved )

•Par ity error reported on target bus during posted write transaction (see previous secti on)

•Delayed write data discarded after 224 attemp ts to deli v e r (2 24 targ et retries recei ved )

Table 32. Assertion of p_serr_l for Data Parity Errors

p_serr_l Transaction

Type Direction Bus Where

Error Was

Detected

Primary/Secondary

Parity Error

Response Bits1

1. x — don’t care.

1 (deasserted) Read Downstream Primary x/x

1 Read Downstream Secondary x/x

1 Read Upstream Primary x/x

1 Read Upstream Secondary x/x

1 P osted write Downstream Primary x/x

02 (asserted)

2. The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

Posted write Downstream Secondary 1/1

3. The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

Posted write Upstream Primary 1/1

1 P osted write U pstream Secondary x/x

1 Delayed write Downstream Primary x/x

1 Delayed write Downstream Secondary x/x

1 Delayed write Upstream Primary x/x

1 Delayed write Upstream Secondary x/x

21154 P CI-to-PCI Bridge

86 Datasheet

•Delayed read data cannot be transferred from target after 224 atte mp t s (2 24 target retries

received)

•Mas ter timeout on del ayed trans action

The device-s peci fic p_serr_l st atus register reports the reason for the 21154’s assertion of p_serr_l.

Most of these events have additional device-spe cific disable bits in the p_serr_l event disable

r egister th at make it pos sible to mask out p_serr_l a sserti on for specifi c events . The master t imeou t

condi ti on has a S ERR# enabl e bit for t ha t event in the br idge control regis ter and ther efore do es not

have a de vice-specific disable bit.

Datasheet 87

8.0 Exclusive Access

This chapter describes the use of the LOCK# si g nal to i mplemen t ex clusive acc ess to a target for

tr ansactions that cross the 21154.

8.1 Concurrent Locks

The pri mar y and s ec ondary bus lock mechanisms operate concurrently except when a loc ked

tr ans act ion crosses the 21154. A primary master can lock a primary target without a ffecting the

status of the lock on the secondary bus, and vice versa. This means t hat a pri mar y m as ter ca n lock

a pr imary targ e t at the sa me ti m e th a t a seco ndar y ma ster lo ck s a sec o nd a r y ta rg et .

8.2 Acquiring Exclusive Access Across the 21154

For any PCI bus, before acquiring access to the LOCK# signal and starting a seri es of locked

tr ans actions, the initiator must first check that both of the following conditions are met:

•The PCI bus must be idle.

•The LOCK# signal must be deasserted.

The initiator leaves the LOCK# signal deasserted during the address phase (only the firs t address

phase of a dual addr ess tra n saction) an d a sse rts LO CK# one clock cy cle later. Once a data transfer

is completed from the target, the target lock has been achieved.

Locked tra nsac tions can cross the 21 1 54 only in th e downstream direct ion, from t he primar y b us to

the s econdary bus .

When the target resides on another PCI bus, the master must acquire not only the lock on its own

PCI bus but al so the lock on every bus between its bus and th e target’s bus. When the 21154

detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus,

the 21154 sa mples the a ddress, transaction type, byte enable bits, and pa rity, as desc ribed in

Section 4.6.4. It also sam ples the lock signal. Because a target retry is s ignaled to the init iator, the

initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established.

The first locked tr ansacti on must be a rea d transaction. Subsequent locked trans ac tions can be rea d

or writ e transactions. Posted mem o ry write tr an sact io n s that are a part o f t h e l o ck ed tran sacti o n

sequence are stil l po sted. Memory read transact ions that are a p art of the locked tr ansacti o n

sequence are not prefetched.

When the locked de layed read request is queued, the 21154 does not queue any more transactions

until the locked sequence is finished. The 21154 signals a target retry to all transactions initiated

subsequent to the loc ked read transac tion that are intended for targets on the other side of the

21 154. The 2115 4 allows a ny tra nsacti ons que ued befo re the l ocked t ran saction to c omple te befo re

initiating the locked transaction.

When the locked de layed read request transact ion m oves to the head of the delayed transaction

queue, the 21154 initiates the transacti on as a locked read tr ansaction by deass erting s_lock_ l on

the s econdary bus during the first addre ss phas e, and by asserting s_lock_l one c ycle later . If

s_lock_l is already asserted (used by a nother initiat or), the 21154 waits to request access to the

secondary bus until s_lock_l is sampled de as serted when the s ec ondary bus is idle. Note that the

21154 P CI-to-PCI Bridge

88 Datasheet

exis ting lock on the secondary bus could not have crossed the 21154; otherwise, the pending

qu eued lo cked tra nsac tion woul d not have be en qu eued. Whe n the 21154 i s able to c omple te a data

transfer with the locked read transaction, the lock is established on the se condary bu s.

When the initiator repeats the locked read transaction on the primary bus with the same address,

tr an sact ion type, an d byte ena ble b its, the 21 15 4 tra nsf ers the rea d dat a back to the i nit iat or, and the

lock is t hen also es tablished on the primary bus .

For the 21154 to recognize and respond to the initiator , the initiator’ s subsequent attempts of the

r ead trans act ion must use the locked transaction sequence (deassert p_lock_l during addres s phas e,

and assert p_lock_l one cycle la ter). If the LOCK# sequ ence is not used in sub se quent at temp ts, a

ma ster timeout condition may result. When a mas ter timeout condit ion occurs, p_serr_l is

conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded,

and the s_loc k_l signal is deasserted on the seco ndary bus .

Once the intended target has been locked, any subsequent locked tr an sact io n s initiated on the

pr imary bus that are forwa r ded by the 21154 are driv en as locked transactions on the secondary

bus.

When the 21154 rece ives a target abort or a master abort in res ponse to the delayed locked re ad

transaction, a target abort is returned to the initiator, and no locks are established on either the

target or the initi ator bus. The 21154 resumes forwarding unlocked transactions i n both directions.

When the 21154 detects, on the secondary bus, a locke d delayed transaction request intended for a

target on the primary bus, the 21154 queues and forwards the transaction as an unlocked

transaction. The 21154 ignores s_loc k_l for upstream transactions and initiate s all upstream

tr ansact ions as unlocked tra nsacti ons.

8.3 Ending Exclusive Access

After the loc k has been acquired on both the primary and secondary buses, the 21154 must

ma intain the lock on the se condary (target) bus for any subse quent locked transactions until the

initiator relinquishes the lock.

The only time a t arget retry ca uses the lock to be relinquish ed is on the fi rst trans act ion of a locked

se quence. On s ubseq uent tra nsacti ons in t he seq uence, the ta r get ret ry has no e ffec t on t he st atus of

the lock signal.

An es tabl ished ta r get lo ck i s main tai ned unt il the in iti at or reli nqui shes t he lock. The 21154 does not

k n o w wheth er th e current t r an sact io n i s the last o n e in a sequence of locked t r ansac tions until t h e

initiator deasserts the p_lock_l signal at the end of the tr ans action.

Whe n the las t locked transac tion is a delayed transaction, the 21 154 has alr eady complete d the

tr ansact ion on the secondary bus . In this case, as soon as the 21154 detects that the initiator has

r elinquished the p_lock_l signal by sampling it in the deass erted state while p_frame_l is

deasserted, the 21154 deasserts the s_lock_l signal on the secondary bus as soon as possible.

Bec aus e of this behavior, s_lock_l may not be dea s se rted until several cycles after the las t locked

tr ansact ion has been completed on the secondary bus. As soon as the 211 54 has dea sserted

s_lock_l to indicate the end of a sequence of locked transactions, it resu mes forwarding unlocked

t ran sactions.

When the las t locked tra nsaction is a posted write t ransactio n, the 21154 deass erts s_lo ck_l on the

se condary bus at t he end of the tra nsac tio n because the loc k was reli nqui shed at th e e nd of the wri te

transaction on the prim ary bus.

21154 PCI-to-PCI Bridge

Datasheet 89

When the 21154 receives a target abort or a master abort in response t o a loc ked dela yed

tra nsacti o n , th e 2 115 4 r et u rn s a targ et ab or t wh en the in it iato r re p ea ts th e lock ed tr an sact i on . The

initiator must then deass ert p_lock_l at the end of the transaction. The 21154 sets the appropriate

status bits, flaggi ng the abnormal target termination condition (see Section 4.10). Normal

forw arding of unlocked posted and delayed transactions is resumed.

When the 21154 receives a target abort or a master abort in response t o a loc ked post ed write

tr ansact ion, th e 21154 ca nnot pas s ba ck that status to the ini tiat or. T he 21 15 4 assert s p_ser r_l whe n

a target abort or a maste r abort is received during a locked posted write transaction, if the SERR#

enable bit is se t in the command register. Signal p_serr_l is ass erted for the master abort condition

if the master abort mode bit is set in the bridge control register (see Se ction 7.4).

Datasheet 91

9.0 PCI Bus Arbitrat ion

The 21154 must arbitrate for us e of the primary bus when forwarding upstream trans actions , and

for use of the secondary bus when forwa r ding downst ream transa ctions. The arbiter for the

primar y bus res ides external to the 21154, typica lly on the motherboard. For the secondary PCI

bus, the 21154 implem ents an internal arbiter. This arbiter can be disabl ed, and an external arb iter

can be used instead.

This chapter describes prim ary and secondary bus arbitration.

9.1 Primary PCI Bus Arbitration

The 21154 impl ements a reque st output pin, p_req_l, and a grant input pin, p_g nt_l, for primary

PCI bus arbitration. The 21154 asserts p_req_l when forwarding transactions upstream; that is, it

acts as initi ator on the primar y P CI bus . As lon g as at le ast one pending tr ansacti on res ides in the

queues in the ups tream direction, either poste d wr ite data or delayed transacti on requests, the

21154 keeps p_re q_l asser ted. However, if a target retry, target disconnec t, or a tar get abort is

rece ived in response to a transaction initiated by the 21154 on the primary PCI bus, the 21154

deass erts p_req_l for two PCI cl ock c ycles.

When p_gnt_l is asse rted low by the primar y bus arbiter aft er the 21154 has asserted p_req_l, th e

21154 initiat es a transaction on the primary bus during the next PCI clock cycle. When p_gnt_l is

asse rted to the 21154 when p_req_l is not asse rted, t he 21154 parks p_ad, p_c be_l, and p_par by

drivin g the m to valid logi c le vels. When t he primary bus is park ed at the 2 1 154 and t he 21 154 t hen

has a trans action to initiate on the primary bus, the 21154 starts the transaction if p_gnt _l was

asse rted during the previous cycle.

9.2 Secondary PCI Bus Arbitration

The 21154 impl ements an internal secondary PCI bus arbit er. Thi s arbiter supports ni ne exte rnal

maste rs in ad dit ion to the 21 154 . The in ter nal arbi ter can be disa bled, and an exte rnal arb ite r can be

use d instead for secondary bus arbitration.

9.2.1 Secondary Bus Arbitration Using the Internal Arbiter

To use the internal arbiter , the secondary bus arbiter enable pin, s_c f n_l, must be tied low . The

21154 has nine sec ondary bus request input pins, s_req_ l<8:0>, and nine secondary bus output

grant pins, s_gnt_l<8:0>, to support external sec ondary bus masters. The 21154 secondary bus

request and grant signa ls are connected inte rnally to the arbiter and are not brought out to external

pins when s_cfn_l is low.

The se condary arbiter supports a programmable 2-level rotating algorithm. Two groups of masters

are assigned, a high priority group and a low pri ority group. The low priori ty group as a whole

represents one entry in the high priority group; that is, if the high priority group consists of n

mas ters, th en in at least every n +1 transacti ons the highe st priority is assigned to the low priority

group. Pr iority rotates eve nly amon g the low priori ty group. Therefore, members of the high

priority group can be serviced n transac tions out of n + 1, while one member of the low priority

group is serviced once every n +1 tran sactions. Figure 18 shows an example of an internal arbiter

where four master s , including the 21154, are in the high priority group, and s ix mas ters ar e in the

21154 P CI-to-PCI Bridge

92 Datasheet

low priority group. Using this example, if all requests are always asserted, the highe st priority

r otates among the ma sters in the following fashion (high pri ority members are given in ital ics, low

p r ior ity members, in boldface type):

B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, and so

on.

Each bus master, incl uding the 21154, can be config ured to be in either the low priority group or

the high priority group by sett ing the co rres ponding priority bit in the arbiter control regis ter in

device-specific c onfiguration spa ce. Each mas ter has a co rres ponding bit. If the bit is se t to 1, the

ma ster is a ssigned to the high priority group. If the bit is set to 0, the mas ter is assigned to the low

pr iority group. If all the masters are assigned to one group, the algorithm defa ults t o a straight

r o tating prior ity among all the maste r s. After re set, all external masters are as signed to the low

pr iority group, and the 21154 is assigned to the high priori ty group. The 21154 receives highe st

pr iority on the target bus every other transaction, and pri ority rotates evenly among th e othe r

masters.

Priorities are reevaluated every time s_frame_l is asserted, that is, at the start of each new

tr an sact ion on the seco ndar y PC I bus. F rom thi s point unti l the ti me that the ne xt tran sacti on s tarts ,

the arbiter asse rts the grant signal corresponding to the highest pri ority request tha t is as s erted. If

a grant for a particular request is asserted , and a higher priority reque st subseque ntly asserts , the

arbiter deasserts the asserted grant signal and as se rts the grant corresponding to the new hi gher

pr iority re ques t on th e next PCI c lock cycle . When priori ti es are ree valua ted, t he highe st prior ity is

assigned to the next highest prio r ity mas ter relative to the master that initiated the previou s

transaction. The master that initi ated the last transa ction now has th e lowest priority in its group.

I f the 21154 detects that an initiator has failed to a ssert s_frame_l aft er 16 cycl es of both grant

as sertion an d a secondary idle bus condition, the arbite r dea sserts the grant. That master does not

receive any mor e grants until it deasser ts its re q u est for at least one PCI clock cycle.

To prevent bus contention, if the secondary PCI bus is idle, th e arbiter never asserts one grant

signal in the sa me PCI cycle in which it deasserts another. It deassert s one grant, and the n as serts

the next grant, no earlier than one PCI clock cycl e later. If the secondary PCI bus is bus y, that is,

eithe r s_frame_l or s_irdy_l is asserted, the arbiter can deassert one grant and a ssert another grant

d uring the same PCI clock cycle.

Figu re 18. S econda ry Ar bi ter Exam pl e

lpg

Note:

B – 21154

– Bus Master Number

lpg – Low Priority Group

Arbiter Control Register = 10 0000 0111b LJ-05003.AI4

21154 PCI-to-PCI Bridge

Datasheet 93

9.2.2 Secondary Bus Arbitration Using an External Arbiter

The int ernal a rbiter is disabled when the sec ondary bus centra l function control pin, s_cfn_l, is

pulled high. An ex ternal arbiter must then be used.

When s_cfn_l is tied high, the 21154 reconfigures two pins to be external request a nd grant pins.

The s_gnt_l<0> pin is reco nfigured to be the 21154’s external request pin becaus e it is an output.

The s_req_l<0> pi n is reconfigured to be the external gra nt pin because it is an input. When an

exte rnal arbi ter is used, t he 21 154 use s the s _gnt_l< 0> pin to requ est th e seconda ry bus. When t he

reconfigured s_req_l<0> pin is as serted low after the 21154 has asserte d s_gnt_l<0>, the 21154

init iat es a trans action on the second ary bus one c ycle late r. If s_req_l< 0> is assert ed and the 21 154

has not assert ed s_gnt_l<0>, the 21154 parks the s_a d<31:0>, s_cbe_ l<3:0>, and s_par pins by

driving them to valid logic levels.

The unused secondary bus grant outputs, s_gnt_l<8:1>, ar e driven high. Unused secondary bus

request input s, s_req_l<8:1>, should be pulled high.

9.2.3 Bus Parking

Bus pa rking re fers t o driving the AD, C/BE #, and PAR lines t o a known va lue whi le the bus is idle .

In gene ral, the devic e implementing the bus arbiter is re sponsible for parking the bus or assigning

another dev ice to park the bus. A device parks the bus when the bus is idle, its bus grant is

asse rted, and the de vice’s request i s not ass erted . The AD and C/B E# si gnals s houl d be dri ven firs t,

with the PAR signal driven one cycle l ater. The 64-bit extension signals are not park ed, because

those signa ls are connected to e xternal pull-up re sistors.

The 21154 parks the primary bus only when p_gnt_l is asserted, p_req_l is deasserted, and the

primary PCI bus is idle. When p_gnt_l is deasserted, the 21154 tristates the p_ad, p_cbe_l, and

p_par signals on the next PCI c lock cycle. If the 21154 is parking the primary PCI bus and want s

to initiate a transaction on tha t bus , then the 21154 can start the transaction on the next PCI clock

cycle by asserting p_frame_l if p_gnt_l is still assert ed.

If the internal seconda ry bus a rbiter is enabled, the secondary bus is al ways parked at the last

maste r that used the PCI bus. That is , the 21154 keeps the secondary bus gra nt assert ed to a

particul ar m as ter until a new secondary bus requ es t comes along. Aft er reset, the 21154 parks the

seconda ry bus a t its elf unti l tr ansa ctions star t occu rring o n the seco nda ry bus. If the i nte rnal ar biter

is disabled, the 21154 parks the secondary bus only when the reconfigu r ed gra nt signal,

s_re q_l<0>, is assert ed and the se condary bus is idle.

Datasheet 95

10.0 General-Purpose I/ O Interface

The 21154 impl ements a 4-pin genera l-purpose I/O gpio interfac e. During norma l operation, the

gpio interface is cont rolled by device-specific c onfiguration registers. In add ition, the gpio

interface can be used for the following functions :

•During s econdary interfac e reset, the gpio interface can be used to shift in a 16-bit serial

stream that serves as a second ary bus clock disable mask.

•A live insertion bit can be used, along with the gpio<3 > pin, to bring the 21154 grac efully to a

halt through hardware, permitting live insertion of option cards behind the 21154.

10.1 gpio Control Registers

During normal ope ration, the gpio interface is controlled by the following device-specific

configura tion regis ters:

•The gpi o output data registe r

•The gpi o output enable control register

•The gpio input data register

These registers consist of five 8-bit fields:

•W rite-1-to-set output data field

•W rite-1-t o-clear output data field

•W rite-1-t o-set signal output enable cont rol field

•W rite-1-t o-clear signal output enabl e control f ield

•Input dat a field

The bottom 4 bits of the output enable fields control whether each gpio signal is input only or

bidire ction al . Each sig nal is cont roll ed indep endent ly by a bit in e ach outpu t enable control field. If

a 1 is writ ten to the write-1-t o-set fiel d, the corresponding pin is activated as an output. If a 1 is

wri tten to the write - 1 - to-cle ar f ield, the output dr iver is tristated, and the pin is then inpu t only.

Writing zeros to these registers has no effect. The reset stat e for these signals is input only.

The inp ut data fi eld is read only and refle cts the curr ent val ue of the gpio pins. A type 0

configura tion read operation to this address is used to obtain the values of these pins. All pins can

be read at any time, whet her configured as input only or as bidirectional.

The o utpu t da ta field s a lso u se t he wr ite -1- to- set and writ e-1 -to- cle ar method . If a 1 is wri tten t o th e

write-1-to-set fi eld and the pin is ena bled as an output, the corresponding gpio output is driven

high. If a 1 is written to the write-1-to-clear field and the pin is enabled as an output, the

corresponding gpio output is dri ven low . Writing zeros to these registers has no effect . The value

writte n to the output re gister will be dri ven only when the gpio si gnal is configured as bid irectional.

A type 0 configuration write operati on is used to program these f ields. The reset value for the

output is 0.

21154 P CI-to-PCI Bridge

96 Datasheet

10.2 S econdary Clock Con trol

The 21154 uses the gpi o pins and the msk_in signa l to input a 16-bit serial dat a st ream. Th is data

stream is shifted into the secondary clock control register and is used for select ively disabling

secondary clock outputs.

The seri al data stream is shifted in as soon as p_rst_l is detecte d deass erted and the se condary reset

signal , s_rst_l, is detect ed asserted. The deasse rtion of s_rst_l is delaye d until the 21154 c ompletes

shifting in the clock mask data, which takes 23 clock cyc les (46 cycles if operating a t 66 MHz).

After that, the gpio pins can be used as general pu rpose I/O pins.

An external shift register should be used to load an d shi f t the dat a. The gpio pins are us ed for s hift

r egist er control and serial dat a input. Table 33 shows the ope ration of the gpio pins.

The data is input through the dedicated input signal, msk_in.

The shi ft register circui try is not neces sar y for correct operation of the 21154. The shi f t registe r s

can be eli mi nated, and msk_in can be t ied low to enabl e all secondary clock outputs or tie d high to

force all secondary clock outputs high.

Table 34 shows the format of the serial stream.

Table 33. gpio Operation

gpio Pin Operation

gpio< 0> Shif t re gi st er cl oc k ou tp ut at 33 MH z ma x im um fr eq ue nc y

gpio<1> Not used

gpio<2> Shift Register control:

0—Load

1—Shift

gpio<3> Not used

Table 34. gpio Serial Data Format

Bit Description s_clk_o Output

<1:0> Slot 0 PRSNT#<1:0> or device 0 0

<3:2> Slot 1 PRSNT#<1:0> or device 1 1

<5:4> Slot 2 PRSNT#<1:0> or device 2 2

<7:6> Slot 3 PRSNT#<1:0> or device 3 3

<8> Device 4 4

<9> Device 5 5

<10> D evice 6 6

<11 > Device 7 7

<12> D evice 8 8

<13> 2115 4 s_clk input 9

<14> Reserved Not applicable

<15> Reserved Not applicable

21154 PCI-to-PCI Bridge

Datasheet 97

The fir st eigh t bit s contain the PRSNT#<1 :0> si gnal valu es for four sl ots, and thes e bits contro l the

s_c lk_o<3: 0> output s. If one or both of t he PRSNT #<1:0> signals are 0, th at indi cate s that a card is

pres ent in the slot and there f ore the secondary clock for that slot is not mas ked. If these clocks are

connected to devi ce s a nd not to s lots, one or both of the bits should be tied l ow to enabl e the clock.

The next five bits are the clock mask for device s; each bit enable s or disables the clock for one

device. These bit s control the s_cl k_o<8:4> outputs : 0 enables the clock, and 1 disables the clock.

Bit 13 is the clock enable bit for s_clk_o <9>, which is connected to the 21154’s s_clk input.

If desired, the assignment of s_clk_o clock out puts to slots, devices, and the 21154’s s_clk input

can be rearranged from the assignment shown here. Ho weve r, it is important that the se rial da ta

stream format match th e assignment of s_clk_o outputs.

The gpi o pin s erial protocol is designed to work with two 74F166 8-bit shi f t registers.

Figure 19 shows how the serial mask circuitry may be impleme nted for a motherboard with four

slots.

Figure 19. E xample of gpio Clock Mask Implementation on the System Board

21154

msk_in

gpio<0>

gpio<2>

CE#

MR#

LJ-05558.AI4

74F166

Vss

Vcc

Vss

Vcc

prsnt0#<0>

prsnt0#<1>

prsnt1#<0>

prsnt1#<1>

prsnt2#<0>

prsnt2#<1>

prsnt3#<0>

prsnt3#<1>

CE#

MR#

74F166

21154 P CI-to-PCI Bridge

98 Datasheet

The eight lea st significant bits are connected t o the PRSNT # pins for the sl ots. The next five bits

are tied high to disable the ir respective secondary clocks because those cloc ks are not connect ed to

anything. The nex t bit is ti ed low because that secondary clock output is connected to the 21154

s_c lk input.

When the secondary reset s ignal, s_rst_l, is detec ted asserted an d the primary reset signal, p_rst_l,

is detected deasserted, the 21154 drives gpio<2> low for one cycle to load the cl ock mas k inputs

into the shift register. On the next cycle, the 21154 drives gpio<2> high to perform a shift

o perati on. This shi fts the clock mask into msk_i n; the mos t signi fican t bit is shift ed in firs t , and the

least signi f icant bit is s hif ted in last.

Figure 20 shows a timing diagram for the load and for the beginning of the shift operation.

After the shift operation is complete, the 21154 trist ates the gpio signals an d ca n deassert s _rs t_l if

the seconda ry res et bit is clear. Th e 21154 then ignores ms k_in. Control of the gpio signa l now

r eve rts to the 21154 gpio control registers. Th e cl ock disabl e mask can be modi fied subsequently

through a configuration write command to the secondary clock control register in device-specif ic

configuration spac e.

10.3 Live Insertion

The gpio<3> pi n can be used, along with a live in se rtion mo de bit, t o disable transacti on

f orwarding.

To enable live inse rtion mode, t he live inse rtion mode bit in the chip control r egister must be set to

1, and the output enable control for gpio<3> must be set to inpu t only in the gpi o output enable

control registe r. When live ins ertion mode is enabled, whenev er gpio<3> is drive n to a value of 1,

the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This

means that, as a target, the 21154 no longer accepts any I/O or memory transactions, on either

in terface. When read, the register bits st ill refl ect the valu e or iginally written by a c onf iguration

wr it e co m man d ; wh en gpi o<3 > is dea ss e rt ed, th e in te r n al ena b le bi ts r et u rn to th ei r or ig i n al va lu e

( as th ey ap p ear when r ead f rom the com mand regi ster ) . When th i s mode is ena bl ed, as a m ast er, the

21154 completes any posted write or delayed re quest transactions that have alre ady been queued.

Delayed completion transa ctions ar e not re turned to th e ma ster in this mode because the 21154 is

not res ponding to any I/O or memory tra nsactions du ring this time.

Note that the 21154 continues to accept confi guration transa ctions in live ins ertion mode.

Once live insertion mode brings the 21154 to a ha lt and que ued transactions are c omplete d, the

se condary reset bit in t he bridge control regis ter can be used t o assert s_rst_l , if des ired, to r eset and

tr is tate secondary bus devices, and to e nable an y live inser tion hardware.

Figure 20. Clock Mask and Load Sh ift Ti min g

LJ-04645.AI4

gpio<0>

gpio<2>

msk_in Bit 15 Bit 14 Bit 13 Bit 12 Bit 11

Datasheet 99

11.0 Clocks

This chapter provides informa tion about the 21154 clocks.

11.1 Prim ary and Secondary Cl ock Inputs

The 21154 impl ements a separate clock input for each PCI interfac e. The pri mar y interface is

sync hronized to the primary cloc k input, p_clk, and the s ec ondary interface is synchronized to the

secondary cl ock input, s_clk.

The 21154 operates at a maximum frequency of 33 MHz, or 66 MHz if the 21154 is 66 MHz

capable. s_clk operates either at the same frequency or at half the frequency as p_clk.

The pri mar y and s ec ondary clock inputs must al ways ma intain a synchronous relat ions hip to ea ch

other; that is, thei r edge relati onships to each other are well defined. T he maximum skew between

s_c lk ris ing edges is 7 ns, as is the max im um skew between p_clk and s_clk falling edges. The

mini mum sk ew between p_clk and s _clk edges is 0 ns. The secondary clock edge must neve r

precede the primar y clock edge. Figure 21 illustrates the tim ing relationship between the primary

and the secondary clock inputs.

11.2 Se condary Clock Outputs

The 21154 has five secondary clock outputs, s_clk_o<9:0>, that can be used as clock inputs for up

to nine external secondary bus devices and for the 21154 secondary clock input.

The s_clk_o outputs are de rived from p_clk. The s_clk_o edge s are delayed from p_clk edges by a

mini mum of 0 ns and a maxim um of 5 ns. The maximum skew between s _clk_o ed ges is 500 ps.

Therefore, to meet the p_clk and s_clk requirements stated in Section 11.1, no more than 2 ns of

delay is allowe d for secondary clock etch returning to the device secondary clock inputs.

Figure 21. p_clk and s_clk Relative Timing

p_clk

s_clk

tskew

LJ-04646.AI4

tskew

21154 P CI-to-PCI Bridge

100 Datasheet

The rules for using secondary c locks are:

•Eac h seconda ry clock output is limite d to one load.

•One of the secondary clock outputs must be used for the 21154 s_clk input.

•I ntel recommends usin g an equivalent amou nt of etch on the b oard for al l secondary clocks , to

min imize skew betw ee n them, and a maxi mum delay of the etch of 2 ns.

•I ntel recommends term inating or disa bling unused secondary cloc k outputs t o reduce power

dissipati on and noise in the system .

11.2.1 Disabling U nused Secondary Clock Outputs

When secondary clock out puts ar e not used, both gpio<3:0> and msk_in can be use d to clock in a

se rial m ask th at sele ct ively t rista te s seco ndar y clock ou tput s. Secti on 10.2 de scri bes how t he 21 154

use s the gpi o pins and the msk_in s ignal to input th is dat a st ream.

After the serial mask ha s be en shifted into the 21154, the value of the mask is rea dable and

modifiable in the secondary clock disable mask register. When the mask is modified by a

configuration write oper ation to t his register, the new clock ma s k disables the appropriate

secondary clo ck outputs within a few cycles. Th is feature allows sof twar e t o d isable or enabl e

secondary clock outputs based on the presence of option cards, and so on.

The 21154 delays deasserting the secondary reset signal, s_rst_l, until the serial clock m ask has

been completely shifted in and the secondary cl ocks have been disable d or e nabled, according to

the mask. The delay between p_rs t_l deassert ion and s_ rst _l deassertion is approximately 23

cycles (46 cycles if s_cl k is operating at 66 MHz).

21154 PCI-to-PCI Bridge

Datasheet 101

12.0 66-Mhz Operation

Some ver sions of the 21154 support 66 MHz operat ion.

Sig nal confi g66 must be tied high on the board to enable 66 MHz operation and to set the 66 MHz

Capable bit in the Status register and Secondary Status register in configuration s pace . If the 21154

vers ion is not 66MHz c apabl e, then config66 should be tied low. Signal s p_m66en a and s_m66ena

should never be pulled high unless config66 is also high.

Signals p_m66ena and s _m66ena indicate whether the primary and sec ondary interfaces,

respectively, are operating at 66 MHz1. This inf ormati on is needed to control the f r equency of the

secondary bus. Note that the PCI Local Bu s Spe cification, Revision 2.1 restricts clock fre quency

changes above 33 MHz to duri ng PC I r eset only.

The 66Mhz capable 21154 supports the followi ng primary and s ec ondary bus frequenc y

combinations:

•66 MHz primary bus, 66 MHz secondary bus

•66 MHz primary bus, 33 MHz secondary bus

•33 MHz primary bus, 33 MHz secondary bus

The 21154 does not support 33 MHz primary/66 MHz seco ndary bus operati on, where the

secondary bus is operating at twice the freque ncy of the primary bus . If config66 is high and

p_m66e na is low (66 MHz ca pable, primary bus at 33MHz), then the 21154 pulls down s_m66ena

to indicate that the secondary bus is operating at 33 MHz .

The 21154 generates the clock signals (s_c lk_o<9:0>) for the secondary bus devices and its own

secondary interface. The 21154 divides the primary bus clock p_clk by two to generate the

secondary bus clock outputs wheneve r the prim ary bus is operating at 66 MHz and the secondary

bus is operating at 33 MHz. The bridge detect s this condi tion when p_m66ena is high and

s_m 66ena is low.

1. In general , 66-MHz operation means operation ran ging from 33 MHz up t o 66 MH z.

Datasheet 103

13.0 PCI Power M anagement

The 211541 i ncorporates functionality that meets the re quirements of the PCI Power Manageme nt

Specification, Revision 1.0. These features include:

•PCI power man age me nt registers using th e enhanced capa bilities port ( ECP) address

mechanism

•Suppo rt for D0, D3hot, and D3cold power management states

•Suppo rt for D0, D1, D2, D3hot, and D3cold power m anagement states for devices behind the

bridge

•Suppo rt of the B2 secondary bus power stat e when in the D3hot powe r ma nagement state

Table 35 shows the sta tes and rela ted actions that the 21154 performs during power management

transitions. (No other transactions are permitted.)

PME# sig nals are routed from downs tream devices around PCI-to-PCI bridges. PME# signals do

not pass through PCI-to-PCI bridges.

1. The 21154 - A A does not incl ude th es e features.

Table 35. Power Management T ransitions

Current State Next State Action

D0 D3cold Pow er has been removed from t he 21154. A p ower-

up reset must be performed to bring the 21154 to D0.

D0 D3hot If enabled to do so by the bpcce pin, the 21154 will

disable t he s econdary clocks and drive them low.

D0 D2 Unimplemented power state. The 21154 will ignore

the write to the power state bits (power state remains

at D0).

D0 D1 Unimplemented power state. The 21154 will ignore

the write to the power state bits (power state remains

at D0).

D3hot D0

The 21154 enables seconda ry cloc k output s and

performs an internal chip reset. Signal s_rst_l will not

be assert ed. All registers will be r etur ned to t he reset

val ues an d bu ffer s will be clea re d.

D3hot D3cold Powe r has been removed from the 21154. A power-

up reset m ust be performed to bring the 21154 to D0.

D3cold D0 Power-up reset. The 21154 performs the standard

power-up reset functions as described in

Se c tio n 11.0 .

Datasheet 105

14.0 Reset

This chapter des cribes the p r imary interfa ce, secon dary interfac e, and chip reset me chani sm s.

14.1 Primary Interface Reset

The 21154 has one reset input, p_rst _l. When p_rst_l is as s erted, the following events occur:

•The 21154 imme diately tristates all primary a nd secondary PCI interface signals.

•The 21154 performs a chip reset.

•Regis ters that have default values are reset. Section 15.3 list s the values of all co nfiguration

space registers after reset.

•The 21154 samples p_req64_l to determine whether the 64-bit extension is enabled on the

primary bus (see Sec tion 4.8.5).

The p_rst_l ass erting and deasserting edges can be async hronous t o p_clk and s_clk.

14.2 Secondary Interface Reset

The 21154 is responsibl e for driving the secondary bus reset s ignal, s_rst_l. The 21154 assert s

s_rst_ l when any of th e f ollowing conditions is me t:

•Si gn al p _r st_ l is as ser ted .

Sig nal s_rst_l remains a sserted as long a s p_rst_l is asse rted and does not deassert until p_rst_l

is de as s erted a nd the secondary cloc k se rial disable mask has been shifted in (23 or 46 clock

cycl es after p_rst_l deassertion).

•The secondary reset bit in the bridge control register is set.

Signal s_rst_l remains asserted until a configuration write operation clears the seco ndary reset

bit and the sec ondary cl ock s erial mask ha s been shifted in.

•The ch ip res et bit in the diagnostic control regis ter is set.

Signal s_rs t_l remains asserted until a configuration write operation clears the seco ndary reset

bit and the sec ondary cl ock s erial mask has been shifted in.

When s_rst_l is asserted , all s econd ary PCI interface control sig nals, includi ng the secondary gr ant

output s, a re im mediate ly trist ated . Signa ls s _ad<3 1:0>, s_cbe_l <3: 0>, and s _par a re dri ven low f or

the duration of s_rst_l assertion. Signal s _req64_l is asserted low indica ting 64-bit extension

support on the s econ dary interf ac e. All post ed write and del aye d transaction data buffers are reset;

therefore, an y transact ions resi ding in 21154 buf fers at the time of s ec ondary reset a re disca r ded.

When s_rst_l is asserted by mea ns of the secondary res et bit, the 21154 remains acc es sible during

secondary interface reset and continues to respond to accesses to its configuration space from the

primary interface.

21154 P CI-to-PCI Bridge

106 Datasheet

14.3 Chip Reset

The chip rese t bi t in the diagnos t ic cont rol regi ste r can be u sed to res et th e 21 154 a nd t he secon dary

bus.

When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. In

addition, s_rst_l is asserted, and the secondary reset bit is autom atically s et. Signal s_rst_l remains

as serted unt il a configuration write operati on clears the secondary reset bit and the serial clock

mask has been shifted in.

As soon as chip reset completes, within 20 PCI clock cycles after compl etion of the configura tion

write oper ation tha t sets th e chip reset bit, the chip re set bit au tomatically cl ears and the chip is

ready for configuration.

During chip reset, the 21154 is inaccessible.

Datasheet 107

15.0 Confi guration Space Registers

This ch apt er provid es a d etail ed descr ipt ion o f the 21154 c onfigurat io n space re gist ers. The chapt er

is divided into three sect ions: Sec tion 15.1 describes the standard 21154 PCI-to-PCI bridge

configura tion regis ters, Sect ion 15.2 describes the 21154 device -specific confi guration regist ers ,

and Section 15.3 describes the configuration register values after reset.

The 21154 configuration space uses the PCI-to-PCI bridge standard format specif ied in the PCI-to-

PCI Br idge Ar c hi tec tu r e Speci fi cat ion. The hea der type at confi guratio n addre ss 0Eh reads as 01h,

indica ting that this device uses the PCI-to-PCI bridge format.

The 21154 al so contains device-specific registers, starting at addres s 40h. Use of t hes e regist ers is

not required for st andard PCI-to-P CI bridge implementations.

The configuratio n sp ace regi sters can b e accessed only from the primary PCI b u s. To access a

Type 0 add ress phase , p_ad<7: 2> indic ates the Dword offse t of the regi ster. During th e data phase ,

p_cbe_l<3:0> selects the bytes in the Dword that is being ac cessed.

Caution: Software change s the configuration re gister value s that affect 21154 behavior only during

initialization. Change these values subse quently only whe n both the primary and secondary PCI

buse s are idle, and the data buffers are empt y; otherwise, the be havior of the 2 1154 is

unpredictable.

21154 P CI-to-PCI Bridge

108 Datasheet

Figure 22 shows a summary of configurat ion spac e:

15.1 PCI-to-PCI Bridge Standard Configuration Registers

This section provides a detai led description of the PCI-to -PCI bridge standard configuration

re gist e rs .

Each field has a separate description.

Fi elds that have the s ame configuration Dword address are se lect able by turning on (driving low)

the appropriate byte enable bits on p_cbe_l during the dat a phase. To select all fie lds of a

configuration address , drive all byte enable bits low.

All reserved fi elds and reg is ters are re ad only and always return 0.

Figure 22. 21154 Configuration Space Map

31 16 15 00

Device ID Vendor ID 00h

Primary Status Primary Command 04h

Class Code Revision ID 08h

Reserved Header Type Pr imary Latency Timer Cache Line Size 0Ch

Reserved 10h

Reserved 14h

Secondary Latency

Timer Subordinate Bus

Number Se condary Bus

Number Primary Bus Number 18h

Secondary Status I/O Limit Address I/O Base Address 1Ch

Memory Limit Address Memory Base Address 20h

Prefetchable Memory Limit Address Prefetchable Memory Base Address 24h

Prefetchable Memory Base Address Upper 32 Bits 28h

Prefetchable Memory Limit Address Upper 32 Bits 2Ch

I/O Limit Address Upper 16 Bits I/O Base Address Upper 16 Bits 30h

Reserved* ECP Pointer* 34h

Reserved 38h

Bridge Control Interrupt Pin Reserved 3Ch

Arbiter Control Diagnos tic Control Chi p Control 40h

Reserved 44h-60h

gpio Input Data gpio Output Enable

Control gpio Output Data p_serr_l Event

Disable 64h

Reserved p_serr_l Status Secondary C lock Control 68h

Reserved 6Ch-DBh

Power Management Capabilities** Next Item Ptr** Capability ID** DCh

Data** PPB Support

Extensions** Power Management CSR** E0h

Reserved E4h-FFh

* For the 211 54-AA, these r egisters are R/W Subsystem ID and Subsys tem V endor ID.

** These ar e reserved for the 21154-AA.

21154 PCI-to-PCI Bridge

Datasheet 109

15.1.1 Vendor ID Register—Offset 00h

This s ection describes the vendor ID register.

Dword address = 00h

Byte enable p_cbe_l<3:0> = xx00b

15.1.2 Device ID Register—Offset 02h

This se ction describes the devi ce ID register .

Dword address = 00h

Byte enable p_cbe_l<3:0> = 00xxb

15.1.3 Primary Command Register—Offset 04h

This se ction describes the primary command regi ste r.

These bits affect the behavior of the 21154 prim ary interfac e, except where noted. Some of the bits

are re peated in the bridge control register, to act on the secondary interface.

This register must be initialized by configuration software.

Dword address = 04h

Byte enable p_cbe_l<3:0> = xx00b

Dwor d Bit Name R /W De sc r ipti on

15:0 Vendor ID R Identifies Intel as the vendor of this device.

Internally har dwired to be 1011h.

Dword Bit Name R/W Description

31:16 Device ID R Identifies this device as the 21154.

Internally hardwired to be 26h.

21154 P CI-to-PCI Bridge

110 Datasheet

Dword Bit Name R/W Description

0I/O sp ac e

enable R/W

Controls the 21154’s response to I/O transactions on the

pr im a ry interfac e.

When 0: The 21154 does not respond to I/O transactions

initiat ed on the primary bus.

When 1: The 21154 response to I/O transactions initiated

on the secondary bus is enabled.

Reset value: 0.

1Memor y

space enable R/W

Controls the 21154’s response to memory transactions on

the 21154 primary interface.

When 0: The 21154 does not res pond to memory

transactions initiated on the primary bus.

When 1: The 21154 response to memory transactions

initiated on the primary bus is enabled.

Reset value: 0.

2 Master enable R/W

Controls the 21154’s ability to initiate memory and I/O

transactions on the primary bus on behalf of an initiator on

the secondary bus. Forwarding of configuration

t ran sa c t io ns is no t affec ted.

When 0: The 21154 does not respond to I/O o r memor y

transactions on the secondary interface an d does not

initiat e I/O or m emory t ransactions on the primary

interface.

When 1: Th e 21154 i s e nab l ed t o op er ate as a n i ni tia t or on

the primary bus and responds to I/O and memory

transactions initiated on the secondary bus.

Reset value: 0.

3Special cycle

enable RThe 21154 ignores special cycl e transactions, so this bit is

read only and returns 0.

4Memory write

and inva li da te

enable R

The 21154 generates memory write and invalidate

transactions only when operating on behalf of another

mas ter whose memory write and inva lidat e transactio n is

crossing the 21154.

This bit is read only and returns 0.

5VGA snoop

enable R/W

Controls the 21154’s response to VGA-compatible palette

write transact ions. VGA palette write transactio ns

correspond to I/O transactions whose address bits are as

follows:

• p_ad<9:0> are equal to 3C6h , 3C8h, and 3C 9h.

• p_ad<15:10> are not decoded.

• p_ad<31:16> must be 0.

When 0: VGA palette write transactions on the primary

interface ar e ignor ed unless they fall inside the 21154’s I/O

address range.

When 1: VGA palette write transactions on the primary

interface are p ositively de coded and forwarded to the

secondary interface.

Reset value: 0.

21154 PCI-to-PCI Bridge

Datasheet 111

15.1.4 Primary Status Register—Offset 06h

This se ction describes the primary status registe r.

These bits affect the status of the 21154 primary interface. Bits reflecting the status of the

secondary interface are f ound in the sec ondary status regist er. W1TC indicate s that writing 1 to a

bit se ts that bit to 0. Writing 0 has no ef fect.

Dword address = 04h

Byte enable p_cbe_l<3:0> = 00xxb

6Parit y error

response R/W

Controls the 21154’s response when a pa rity err or is

detect ed on the primary interface.

When 0: Th e 21154 does not assert p_perr_l, no r does it

s et the data parity repo rted bit in t he stat us register. The

21154 does not report address parity errors by asserting

p_serr_l.

When 1: The 21154 drives p_perr_l and conditionally sets

the data parity reported bit in the status regist er when a

data parity error is detected (see Section 7.0). The 2115 4

allows p_serr_l assertion when address parity errors are

detect ed on the primary interface.

Reset value: 0.

7Wait cycle

control RReads as 0 to indicate that the 21154 does not perform

address or data stepping.

8SERR#

enable R/W

Controls the enable for p_serr_l on the primary interface.

When 0: Signal p_serr_l cannot be dri ven by the 21154.

When 1: Signal p_serr_l can be driven low by the 21154

under the conditions described in Section 7.4.

Reset value: 0.

9Fast back-to-

back enable R/W

Controls the ability of the 21154 to generate fast back-to-

back transactions on the primary bus.

When 0: The 21154 does n ot generate back-to-back

transactions on the primary bus.

When 1: The 21154 is enabled to generate back-to-back

transactions on the primary bus.

Reset value: 0.

15:10 Reserved R Reserved. Returns 0 when read.

Dword Bit Name R/ W Description

Dwor d Bit N a me R/W De sc ription

19:16 Reserved R Reserved. Returns 0 when read.

20 ECP R

Enhanced capabilities port (ECP) enable. Reads as 1 in

the 21154–AB and later revisions to indicate that the

21154–AB supports an enhanced capabilities list. The

21 154–AA reads as 0 to show that this capability is not

supported.

21154 P CI-to-PCI Bridge

112 Datasheet

15.1.5 Revision ID Register—Offset 08h

This section describes the revision ID register.

Dword = 08h

Byte enable p_cbe_l<3:0> = xxx0b

21 66-MHz

capable R

Indicat es whether the primary interface is 66- MHz

capable.

Reads as 0 when pin config66 is tied low to indicate that

the 21154 is not 66 MHz capable.

Reads as 1 when pin conf ig66 is tied high to indicat e

that the primary bus is 66 MHz capable

22 Reserved R Re s erved . Retur ns 0 when read.

23 Fast back-to-

back capable RRe ads as 1 to indicate tha t the 21154 is able to respon d

to fast back-to -back transactio ns on the primary

interface.

24 Data parity

detected R/W1TC

This bit is set to 1 when all of t he following are tr ue:

• The 21154 is a master on the primary bus.

• Signal p_perr_l is detected asserted, or a parity

error is detected on the primary b us.

• The parity e rro r response bit is set in the command

Reset value: 0.

26:25 DEVSEL#

timing R

Indicates slowes t respo nse to a noncon figur ation

command on the primary interface.

Reads as 01b to indicate that the 21154 responds no

slower than with medium timing.

27 Signaled

target abort R/W1TC

This bit is set to 1 when th e 21154 is acting as a target

on the primary bu s and returns a target abort to the

primary master.

Reset value: 0.

28 Received

target abort R/W1TC

This bit is set to 1 when the 21154 is acting as a master

on the primary bus and rec eives a target abort f rom the

primary target.

Reset value: 0.

29 Received

master abort R/W1TC This bit is se t to 1 w hen the 21154 is acting as a ma ster

on the primary bus and receives a ma ster abort.

30 Signaled

system error R/W1TC This bit is set to 1 when the 21154 has asserted

p_serr_l.

Reset value: 0.

31 Detected

parity error R/W1TC Thi s bi t is se t to 1 when th e 21154 de te ct s an ad dr es s or

data parity error on the primary interface.

Reset value: 0.

Dw ord Bit Name R/W Description

Dword Bit Name R/W Description

7:0 R evision ID R Indicates the rev ision number of thi s device.

21154 PCI-to-PCI Bridge

Datasheet 113

15.1.6 Programming Interface Register—Offset 09h

This s ection describes the program ming interface regis ter.

Dword address = 08h

Byte enable p_cbe_l<3:0> = xx0xb

15.1.7 Subclass Code Register—Offset 0Ah

This se ction describes the su bclass code register.

Dword address = 08h

Byte enable p_cbe_l<3:0> = x0xxb

15.1.8 Base Class Code Register—Offset 0Bh

This section describes the base class code register.

Dword address = 08h

Byte enable p_c be_l<3:0> = 0x xxb

15.1.9 Cache Line Size Regist er—Offset 0Ch

This section describes the cache line size register.

Dword address = 0Ch

Byte enable p_cbe_l<3:0> = xxx0b

Dwor d Bit Nam e R/W De sc ripti o n

15:8 Programming

interface RNo pro gra mming int erface s have be en defi ned f or

PCI-to-PCI bridges.

Reads as 0.

Dword Bit Name R/W Description

23:16 Subclass code R Reads as 04h to indicate that this bridge device

is a PCI-to-PCI bridge.

Dword Bit Name R/W Description

31:24 Base cl ass

code R Reads as 06h to indicate that this device is a bridge device.

Dwor d Bit Na me R/W De sc ripti on

7:0 Cache

line size R/W

Designates the cache line size for the system in units of 32-bit

Dwords. Used for prefetching me mory read transactions and

for terminating memory write and invalidate transactions.

The cache line size should be written as a power of 2. If the

val ue is not a pow er of 2 or is gre at er tha n 16 , the 211 54

behaves as if the cache line size were 0.

Reset value: 0.

21154 P CI-to-PCI Bridge

114 Datasheet

15.1.10 Primary Latency Timer Register—Offset 0Dh

This section describes the primary laten cy timer regi ste r.

Dword address = 0Ch

Byte enable p_cbe_l<3:0> = xx0xb

15.1.11 Header Type Register—Offset 0Eh

This section describes the header type register.

Dword address = 0Ch

Byte enable p_cbe_l<3:0> = x0xxb

15.1.12 Primary Bus Number Register —Offset 18h

This section describes the primary bus number register.

This register must be ini tialized by configuration softwa re.

Dword address = 18h

Byte enable p_cbe_l<3:0> = xxx0b

Dword Bit Name R/W Description

15:8 Master

latency

timer R/W

Master latency timer for the primary interface. Indicates the

number of PCI clock cycles from the assertion of p_frame_l to

the expiration of the timer when the 21154 is acting as a

mast er on the pr i ma ry int e rfa ce . A ll bi ts ar e wr itab le , resu lt in g

in a granularity of one PCI clock cycle.

When 0: The 21154 relinquishes the bus after the first data

transfer when the 21154’s primary bus grant has been

deasserted, with the exception of memory write and invalidate

transactions.

Reset value: 0.

Dword Bit Name R/W Descriptio n

23:16 Header

type R

Defines the layo ut of addresses 10h through 3F h in

configuration space.

Reads as 01h to i ndicate that the register layout conforms to

the standard PCI-to-PCI bridge layout.

Dword Bit Name R/W Description

7:0 Primary bus

number R/W

Indicates the number of the PCI bus to which the primary

interface is connect ed. The 21154 uses this register to

decode Type 1 configuration trans actions on th e

secondar y interface that should either be conv erte d to

special cycle transactions on the primary interface or

passed upstream unaltered.

Reset value: 0.

21154 PCI-to-PCI Bridge

Datasheet 115

15.1.13 Secondary Bus Number Register—Offset 19h

This se ction describes the secondary bus number register.

This register must be initialized by configuration software.

Dword address = 18h

Byte enable p_c be_l<3:0> = x x0xb

15.1.14 Subordinate Bus Number Register—Offset 1Ah

This se ction describes the su bordinate bus number register.

This register must be initialized by configuration software.

Dword address = 18h

Byte enable p_c be_l<3:0> = x 0xxb

15.1.15 Secondary Latency Timer Register—Offset 1Bh

This se ction describes the secondary latency timer register.

Dword address = 18h

Byte enable p_c be_l<3:0> = 0x xxb

Dwor d Bit Na me R /W De sc r ipti on

15:8 Second ary bus

number R/W

Indicates the number of the PCI bus to which the

secondary interface is connected. The 21 154 uses this

T y pe 1 conf ig ura ti on t r ansa ct io ns on t he pr ima ry i nte r face ,

and to determine when to convert them to Type 0 or

special cycle transactions on th e secondary interface.

Reset value: 0.

Dwor d Bit Nam e R/W De sc r ipti on

23:16 S ub ordin ate bu s

number R/W

Ind ica t es the n um be r of t he hi gh es t num be r ed PCI b us

that is behind (or subordinate to) the 21154. Used in

conjunct ion with the secondary bus number to

determi ne when to respon d to T ype 1 configuration

tr ans ac ti ons on th e pr i mar y in te rf ace an d pass t he m to

the secondary interface as a Type 1 co nfiguration

transaction.

Reset value: 0.

21154 P CI-to-PCI Bridge

116 Datasheet

15.1.16 I/O Base Address Register—Offset 1Ch

This section describes the I/O ba se address re gister.

This register must be ini tialized by configuration softwa re.

Dword address = 1Ch

Byte enable p_cbe_l<3:0> = xxx0b

15.1.17 I/O Limit Address Register—Offset 1Dh

This section describes the I/O limit address register.

This register must be ini tialized by configuration softwa re.

Dword address = 1Ch

Byte enable p_cbe_l<3:0> = xx0xb

Dword Bit Name R/W Description

31:24 Secondary

latency t imer R/W

Mas ter latency timer for the secondary interface.

Indicates the number o f PCI clock cycles from the

assertion of s_frame_l to the expiration of the timer

when the 21154 is acting as a master on the secondary

int er face . All b it s are w rit ab le , r es ul tin g i n a g ran ul ari ty o f

one PCI clock cycle.

When 0: The 21 154 ends the transaction after the first

data transfer when the 21 154’s secondary bus grant has

been deasserted, with the exception of memory write

and invalidate transactions.

Reset value: 0.

Dword Bit Name R/W Description

3:0 32-bit

indicator RThe l ow 4 bits of this register read as 1h to indica te that

the 21154 supports 32-bit I/O address decoding.

7:4 I/O bas e

address

<15:12> R/W

Defines the bottom address of an addres s range us ed by

the 21154 to determine when to forward

I/O tr an sa ctio ns fr o m on e i nte rf ac e to th e o t he r . T he up pe r

4 bits are writable and correspond to address bits

<15: 12 >. Th e low er 12 bit s of the ad dr e ss are assu me d to

be 0. The upper 16 bits corresponding to address bits

<31:16> are defined in the I/O base address upper 16 bi ts

and granu larity.

Reset value: 0.

Dword Bit Name R/W Description

11:8 32-bit

indicator R/W The low 4 bits of this regi ster read as 1h to in dicate that

the 21154 supports 32-bit I/O address decoding.

21154 PCI-to-PCI Bridge

Datasheet 117

15.1.18 Secondar y Status Register—Offset 1Eh

This se ction describes the secondary status re gis ter .

These bits reflect the stat us of the the 21154 seco ndary inter face. W1TC indica tes that writing 1 to

that bit s ets th e bit to 0. Writing 0 has no effect.

Dword address = 1Ch

Byte enable p_cbe_l<3:0> = 00xxb

15:12 I/O limit

address

<15:12> R/W

Defines the top address of an address range used by

the 21154 to determine when to forward I/O transactions

from one interface to the other. The upper 4 bits are

writable and correspond to address bits <15:12>. The

lower 12 bits of the address are assumed to be FFFh.

The upper 16 bits corresponding to address bits

<31:16> are defined in the I/O l imit address upp er 16

bits re gister. The I/O addr ess range adheres to 4KB

alignment and granularity.

Reset value: 0.

Dword Bit Name R/ W Description

Dword Bit Name R/W Description (Sheet 1 of 2)

20:16 Reserved R Reserved. Returns 0 when read.

21 66-MHz capabl e R

Indicates whether the secondary interface is 66-

MHz capable.

Reads as 0 when pin config66 is tied low to indicate

that the 21 154 is not 66 MHz capable.

Reads as 1 when pin config66 is tied high to

indicate that the secondary bus is 66 MHz capable

22 Reserved R Reserved. Returns 0 when read.

23 Fast back-to-

b ac k ca pa bl e RReads as 1 to indicate that the 21 154 is able to

respond to fast back-to- back transactions on the

secon da r y in terfac e.

24 Data parity

detected R/W1TC

This bit is set to 1 when all of the following are true:

• The 21154 is a master on the secondary bus.

• Signal s_perr_l is detected asserted, or a parity

err or is detected on the secondary bus.

• The pa rit y err or r e sp onse bi t is set i n t he b r id ge

control re giste r.

Reset value: 0.

26:25 s_devsel_l

timing R

Indicat es slowest re sponse to a command on the

secondary interface.

Reads as 01b to indicate that the 21154 responds

with medium (or faster) timing.

27 Signaled target

abort R/W1TC

This bit is set to 1 when th e 21154 is acting as a

target on the secondary bus and returns a target

abort to the secondary bus master.

Reset value: 0.

21154 P CI-to-PCI Bridge

118 Datasheet

15.1.19 Memory Base Address Register—Offset 20h

This section describes the me m ory base address register.

This register must be ini tialized by configuration softwa re.

Dword address = 20h

Byte enable p_cbe_l<3:0> = xx00b

15.1.20 Memory Limit Address Register—Offset 22h

This section describes the mem ory lim it address register.

This register must be ini tialized by configuration softwa re.

Dword address = 20h

Byte enable p_cbe_l<3:0> = 00xxb

28 Received target

abort R/W1TC

This bit is set to 1 when the 21154 is acting as a

mas ter on the s econdar y bus and receive s a target

abort f rom the secondary bus target.

Reset value: 0.

29 Received master

abort R/W1TC

This bit is set to 1 when the 21154 is acting as an

initiator on the seco ndary bus and receives a

mas ter abort.

Reset value: 0.

30 Received system

error R/W1TC Th is bit is set to 1 when the 21154 detects the

assertion of s_serr_l on the secondary interface.

Reset value: 0.

31 Detected parity

error R/W1TC

This bit is set to 1 when the 21154 detects an

address or data pa rity erro r on the secondary

interf ace.

Reset value: 0.

Dword Bit Name R/W Description (Sheet 2 of 2)

Dword Bit Name R/W Description

3:0 Reserved R The low 4 bits of this register are read only and

retu rn 0.

15:4 Memory base address

<31:20> R/W

Defines the bottom address of an address range

us ed by t he 211 54 to determine when to forward

mem ory transact ions fr om o ne interface to the

other . The upper 12 bits are writable and

correspond to address bits <31:20>. The lower 20

bits of the address a re assumed to be 0. The

memory address range adheres to 1MB alignment

and granu larity.

Reset value: 0.

21154 PCI-to-PCI Bridge

Datasheet 119

15.1.21 Prefetchable Memory Base Address Register—Offset 24h

This se ction describes the prefe tchable memory bas e address register.

This register must be initialized by configuration software.

Dword address = 24h

Byte enable p_cbe_l<3:0> = xx00b

15.1.22 Prefetchable Memory Limit Address Register—Offset 26h

This section des cr ibes the pr ef etchab le memor y limit address register.

This register must be initialized by configuration software.

Dword address = 24h

Byte enable p_cbe_l<3:0> = 00xxb

Dwor d Bit Name R/W De scription

19:16 Reserved R The low 4 bits of this register are read only and

retu rn 0.

31:20 Memory limit address

<31:20> R/W

Defines the top a ddress of an addres s range used

by the 21154 to det e rmine when to fo rward

memory transactions from one interface to the

other. The upp er 12 bits are writable and

correspond to address bits <31:20>. The lower 20

bits of the address are assumed to be FFFFFh.

T he mem o ry ad dr e ss rang e adhe res to 1M B

alignment and g ranularity.

Reset value: 0.

Dwor d Bit Nam e R/W De sc ript ion

3:0 64-bit indicator R The low 4 bits of this register are read only and

return 1h to indicate that this range supports 64-

bit addre s sing .

15:4 Prefetchable memory

base address

<31:20> R/W

Defines the bottom address of an address range

us ed b y the 21154 to determine when to forward

memory read and write transactions from one

interface to the other. The upper 12 bits ar e

writable and correspond to address bits <31:20>.

The lower 20 bits of the address are assumed to

be 0. The memory base register upper 32 bits

contains the upper half of the base address. The

mem ory address range adheres to 1MB

alignment and granularity.

Re se t va lue: 0.

21154 P CI-to-PCI Bridge

120 Datasheet

15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register—Offset

28h

This section describes the prefetcha ble memory base a ddress upper 32 bits registe r.

This register must be ini tialized by configuration softwa re.

Dword address = 28h

Byte enable p_cbe_l<3:0> = 0000b

15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register—Offset

2Ch

This section describes the prefetcha ble memory limit address upper 32 bits re gis ter.

This register must be ini tialized by configuration softwa re.

Dword address = 2Ch

Byte enable p_ cbe_l<3:0> = 0000b

Dword Bit Name R/W Description

19:16 64-bit indicator R The low 4 bits of this regi ster are read only and

return 1h to indicate that this range supports 64-

bit addressing.

31:20 Prefetchable memory

limi t ad dr e ss <31:2 0> R/W

Defines the top address of an address range

used by the 21154 to determine when to forward

memory read and write transactions from one

inter face to the other. The upper 12 bit s are

wr itable and correspond to address bits <31:20>.

The lower 20 bits of the address are assumed to

be FFFFFh. The memory limit upper 32 bits

addres s. The memory address range ad heres to

1M B alignm ent and granulari ty.

Reset value: 0.

Dword Bit Name R/W Description

31:0

Upper 32

pre fetch able memory

base address

<63:32>

R/W

Defines the upper 32 bits of a 64-bit bottom

address of an address range used by the 21154

to determine when to forward memory read and

wri te transact ions from one interface to the other.

T he mem o r y ad dre ss r an ge adhere s t o 1M B

alignment and granu larity.

Reset value: 0.

21154 PCI-to-PCI Bridge

Datasheet 121

15.1.25 I/O Base Address Upper 16 Bits Register—Offset 30h

This se ction describes the I/O base address upper 16 bits registe r.

Dword address = 30h

Byte enable p_cbe_l<3:0> = xx00b

15.1.26 I/O Limit Address Upper 16 Bits Register—Offset 32h

This se ction describes the I/O limit address upper 16 bits regi st er.

This register must be initialized by configuration software.

Dword address = 32h

Byte enable p_c be_l<3:0> = 00 xxb

15.1.27 Subsystem Vendor ID Register—Offset 34h

This se ction describes the su bsy stem vendor ID register.

Dword address = 34h

Byte enable p_c be_l<3:0> = x x00b

Dwor d Bit Nam e R / W Desc r ipt ion

31:0

Upper 32

prefetchable

m emory limit

address <63:32>

R/W

Defines the upper 3 2 bits of a 64-bit top address of

an address range used by the 21154 to determine

when to forward memory read and write

transactions from one interface to the other . Extra

read transactions should have no side effects. The

mem ory address range adheres to 1MB alig nment

and granu larity.

Reset value: 0.

Dword Bit Name R/W Description

15:0 I/O base address

upper 16 bits

<31:16> R/W

Defines the upper 16 bits of a 32-bit bottom address

of an ad dre ss r ang e u se d b y th e 2 1154 t o det e rmin e

when to forward I/O transactions from one interface

to the other. The I/O address range adheres to 4KB

alignment and granularity.

Reset value: 0.

Dwor d Bit Nam e R/W D escr i ptio n

31:16 I/O limit address

upper 16 bits

<31:16> R/W

Defines the upper 16 bits of a 32-bit top address of

an addre ss rang e used by the 21154 to determ ine

when to forward I/O transactions from one interface

to the other. The I/O address range adheres to 4KB

alignment and granularity.

Reset value: 0.

21154 P CI-to-PCI Bridge

122 Datasheet

15.1.28 ECP Pointer Register—Offset 34h

This section describes the ECP poi nter register.

Dword address = 34h

Byte enable p_cbe_l<3:0> = xx00b

15.1.29 Subsystem ID Register—Offset 36h

This section describes the subsystem ID registe r.

Dword address = 34h

Byte enable p_cbe_l<3:0> = 00xxb

15.1.30 Interrupt Pin Register—Offset 3Dh

This section describes the interrupt pin r egister.

Dword address = 3Ch

Byte enable p_cbe_l<3:0> = xx0xb

Dword Bit Name R/W Description

15:0 Subsystem vendor ID R/W

Provides a mechanism allowing add-in cards to

distinguish their cards from one another. The

21154 prov ides a writable subsystem vendor ID

that can be initialized during POST. This register is

implemented only in the 21154–AA.

Reset to 0.

Dword Bit Name R/W Description

7:0 ECP_PTR R

Enhanced capabilities port (ECP) offset pointer.

Reads as DC h in the 21154–AB and later revisions

to indicate that the first item, which corresponds to

the power management registers, resides at that

configuration offset. This is a R/W register with no

side effects in the 21154–AA.

31:8 Reserved R Reserved. The 21154–AB and later revisions

return to 0 when read. This is a R/W register with

no side ef fect s in the 21154–AA.

Dword Bit Name R/W Descriptio n

31:16 Subsystem ID R/W

Provides a mechanism allowing add-in cards to

distingu ish their cards fr om o ne another. The 21154

provides a writable subsystem ID that can be initialized

during POST. This register is implemented only in the

21154–AA

Re s et to 0.

21154 PCI-to-PCI Bridge

Datasheet 123

15.1.31 Bridge Control Register—Offset 3Eh

This section des cr ibes the br idge control register.

This register must be initialized by configuration software.

Dword address = 3Eh

Byte enable p_cbe_l<3:0> = 00xxb

Dwor d Bit Nam e R/W Descr i ptio n

15:8 Interrupt pin R Reads as 0 to indicate that th e 21154 does not have an

interrupt pin.

Dword Bit Name R/W Description

16 Parity error

response R/W

Controls the 21154’s response when a pa rity err or is de tecte d

on th e se co n dary interfac e.

When 0: Th e 21154 does not assert s_perr_l, no r does it se t

the da ta pa rit y r epor t ed bi t i n t he sec on dary st atus re gi st er. Th e

21154 does not report address parity errors by asserting

p_serr_l.

When 1: Th e 21154 driv es s_perr_l and conditionally s ets the

data parity reported bit in the secondary status register when a

data parity error is detected on the secondary interface (see

Section 7.0.) Also must be set to 1 to allow p_serr_l assertion

when addres s parity errors are detec ted on the secondary

interface.

Reset value: 0.

17 SERR#

forward

enable R/W

Controls whether the 21154 asserts p_serr_l when it detects

s_serr_l asserted.

When 0: Th e 21154 does not driv e p_ser r_l when it detects

s_serr_l asserted.

Whe n 1: The 21154 ass ert s p_ serr _ l whe n s_ serr _ l is d etec t ed

asserted (the primary SERR# driver enable bit must also be

set).

Reset value: 0.

18 ISA en ab le R / W

Modifies the 21154’s response to ISA I/O addresses. Applies

only to those addresses falling within the I/O base and limit

address registers and within the first 64KB of PCI I/O space.

When 0: Th e 21154 forwards all I/O transactions dow nstream

that fall within the I/O base and limit address registers.

When 1: The 21 154 ignores primary bus I/O transactions within

the I/O base and limit address registers and within the first

64KB of PCI I/O space that address the last 768 bytes in each

1KB block. Secondary bus I/O transactions are forwarded

upstream if the address falls within the last 768 bytes in each

1KB block.

Reset value: 0.

21154 P CI-to-PCI Bridge

124 Datasheet

19 VGA en able R/W

Modifies the 21154’s response to VGA-compatible addresses.

When 0: VGA transactions are ignored on the prim ary bus

unless they fall within the I/O base and limit address registers

and the ISA mode is 0.

When 1: The 21154 positively decodes and forwards the

following transactions downstream, regardless of the values of

the I/O base and limit regist ers, ISA mode bit, or VGA snoop bit:

• Memory transactions addressing 000A0000h–000BFFFFh

• I/O transaction addressing:

— p_ad<9:0> = 3B0h–3BBh and 3C0h–3DFh

— p_ad<15: 10> are not decoded.

— p_ad<31:16> = 0000h.

I/O and me mor y spac e enab l e bi ts mus t be set in the co mma nd

The transactions listed here are ignored by the 21154 on the

sec ondary bus.

Reset value: 0.

20 Reserved R Reserved. Returns 0 when read.

21 Mas ter abort

mode R/W

Controls th e 21154’s behavior when a master abort ter m inat ion

occ urs in response to a t ransaction init iated by the 21154 on

either the primary or secondary PCI interf ace.

When 0: The 21154 asserts TRDY# on the initiato r bus for

delayed transactions, and

FFFF FFFFh for read transactions. For posted write

transactions, p_serr_l is not asserted.

When 1: The 21154 returns a target abort on the initiator bus

for delayed transactions. For posted write transactions, the

21 154 asserts p_serr_l if the SERR# enable bit is set in the

com m and register.

Reset value: 0.

22 Secondary

bus reset R/W

Controls s_rst_l on the secondary interf ace.

When 0: The 21154 deasserts s_rst _l.

When 1: The 21154 asserts s_rst_l. When s_rst_l is asserted,

the data buffers and the secondary interface are initialized back

to reset conditions. The primary interface and configuration

registers are not affected by the assertion of s_rst_l.

Reset value: 0.

23 Fast back-to-

back enable

Controls th e ability of the 21154 to generate fa st back-t o-back

transactions on the secondary interface.

When 0: The 21154 does not generate fast back-to- back

transactions on the secondary PCI bus.

When 1: The 21154 is enabled to generate fast back-to-back

transactions on the secondary PCI bus.

Reset value: 0.

Dword Bit Name R/W Description

21154 PCI-to-PCI Bridge

Datasheet 125

15.1.32 Capability ID Register—Offset DCh

This se ction describes the ca pability ID register. (Implemente d in the 211 54–AB and lat er

revisions only. In the 21154–AA, this register is reserved.)

Dword address = DCh

Byte enable p_cbe_l<3:0> = xxx0b

24 Primary

master

timeout R/W

Sets the maximum number of PCI clock cycles that the 21154

waits for an initiator on the primary bus to repeat a delayed

transaction reques t. The counte r starts once the delayed

tr an sact io n c om pl etio n is at t he he ad of t he qu eu e. If t he mas te r

has not repeated the transaction at least once before the

c ounter expires, the 21154 discards the transaction from its

queues.

When 0: Th e primary master timeout value is 215 PCI clock

cycles, or 0.983 ms for a 33-MHz bus.

When 1: Th e value is 210 PCI clock cycles, or 30.7 µs for a 33-

MHz bus.

Reset value: 0.

25 Secondary

master

timeout R/W

Sets the maximum number of PCI clock cycles that the 21154

waits for an initiator on the seco ndary b us to repeat a delayed

transaction request. The counter starts once the delayed

tr an sact io n c om pl etio n is at t he he ad of t he qu eu e. If t he mas te r

has not repeated the transaction at least once before the

c ounter expires, the 21154 discards the transaction from its

queues.

When 0: Th e primary master timeout value is 215 PCI clock

cycles, or 0.983 ms for a 33-MHz bus.

When 1: Th e value is 210 PCI clock cycles, or 30.7 µs for a 33-

MHz bus.

Reset value: 0.

26 Master

timeout

status R/W1TC

This bit is set to 1 when either the primary master timeout

counter or the secondary master timeout counter expires and a

delayed transaction is discarde d from the 21154’s qu eues.

Write 1 to clear.

Reset value: 0.

Master

timeout

SERR#

enable

R/W

Controls assertion of p_serr_l during a master timeout.

When 0: Signal p_serr_l is not asserted as a result of a master

timeout.

When 1: Signal p_serr_l is asserted when either the primary

master timeout counter or the secondary master timeout

c ount er e xpi r es and a de la ye d tr an sact io n i s d is card ed fr om t he

21154’s queues. The SERR# enable bit in the command

Reset value: 0.

31:28 Reserved R Reserved. Returns 0 when read.

Dword Bit Name R/W Description

Dword Bits Name R/ W Description

7:0 CAP_ID R Enh anc ed ca pa bi li tie s I D . Rea ds on ly a s 0 1h to in di ca te

that this is the power management enhanced capability

21154 P CI-to-PCI Bridge

126 Datasheet

15.1.33 Next Item Ptr Register—Offset DDh

This section describes the ne xt item ptr register. (Implemented in the 21154–AB and later

r evisions only. I n the 21154–AA, this register is res erved .)

Dword address = DCh

Byte enable p_cbe_l<3:0> = xx0xb

15.1.34 Power Management Capabilities Register—Offset DEh

This section describes the power mana gement ca pabilities register. (Implemented in the

21154–AB and later revisions only. In the 21154–AA, this register is reserved.)

Dword address = DCh

Byte enable p_cbe_l<3:0> = 00xxb

Dword Bit Name R/W Descriptio n

15:8 NEXT_ITEM R Next item pointer. Reads as 0 to indicate that there is no

oth er ECP regi ster.

Dword Bit Name R/W Description

18:16 PM_VER R Power Management Revision. Re ads as 001 t o indicate

that this device is compliant to Revision 1.0 of the

PCI

Pow er Management Interfac e Specif ication

19 PME#Clock R PME# Clock Re quired. Reads as 0 because this device

does not support the PME# pin.

20 AUX R Auxiliary Power Support. Reads as 0 because this device

does not have PME# support or an auxiliar y p ower source.

21 DSI R Device-Specific Initia lization. Reads as 0 to indicate that

this devi ce does not have device-specific initialization

requirements.

24:22 Reserved R Reserved. Read as 000b.

25 D1 R D1 Power State Support. Reads as 0 to indicate that this

device does not support the D1 power management state.

26 D2 R D2 Power State Support. Reads as 0 to indicate that this

device does not support the D2 power management state.

31:27 PME_SUP R PME# S u ppor t . R eads as 0 t o in dica te t hat th i s d evice do es

not support the PME# pin.

21154 PCI-to-PCI Bridge

Datasheet 127

15.1.35 Power Management Control and Status Register—Offset E0h

This se ction describes the power management control a nd status registe r. (Imple mented in the

21154–AB and later revisions only. In the 21154–AA, this regis ter is reserved .)

Dword address = E0h

Byte enable p_cbe_l = xx00b

15.1.36 PPB Support Extensions Registers—Offset E2h

This se ction describes the PPB support extensions regi sters. (Implemented in the 21154–AB and

later revisions only. In the 21 154–AA, these registers are res erve d.)

Dword address = E0h

Byte enable p_cbe_l<3:0> = x0xxb

Dwor d Bit N a me R/W D e sc ription

1:0 PWR_STATE R/W

Power State. Reflects the current power state of this

device. I f an unimpl emented power state is written to this

re gi st er, the 21154 com pl et es the w rite transa ct ion,

ignores the write data, and do es n ot change the value of

this field. Writing a value of D0 when the previous state

was D3 will cause a chip reset t o occur (wi thout assert ing

s_rst_l).

• 00b: D0

• 01b: D1 (not implemented)

• 10b: D2 (not implemented)

• 11b: D3

Re se t va lue: 00 b

7:2 Reserved R Reserved. Reads as 00000b.

8PME_ENR

PME# Enable. Reads as 0 because the PME# pin is not

implemented.

12:9 DATA_SEL R Data Select. Reads as 0000b because the data register is

not implemented.

14:13 DATA_

SCALE RData Scale. Reads as 00b because the data register is

not implemented.

15 PME_STAT R PME S tatu s . Reads as 0 because the PME# pin is not

implemented.

21154 P CI-to-PCI Bridge

128 Datasheet

15.1.37 Data Register — Offset E3h

This section describes the da ta register.

Dword address = E0h

Byte enable p_cbe_l<3:0> = 0xxx b

15.2 Device-Specific Configuration Registers

This section provides a detai led description of the 21154 device -sp ecific con f iguration registers .

Each field has a separate description.

Fi elds that have the s ame configuration address are se lect able by tu rning on (dr iving low) the

appro pria te byte enable b its on p_c be_l duri ng the data phas e. To s elect al l fields of a confi guratio n

addr ess, drive all byte enable bits low.

All reserved fi elds and registers are re ad only and always return 0.

15.2.1 Chip Control Register—Offset 40h

This section describes the chip control regist er.

Dword address = 40h

Byte enable p_cbe_l<3:0> = xxx0b

Dword Bit Name R/W Description

21:16 Reserved R Reserved. Read only as 000000b.

22 B2_B3 R

B2_B3 Support for D 3 hot. When the BPCC_En (bit 23)

reads as 1, this bit reads as 1 to indicate that the

seco nd ary bu s c lo ck out pu ts wi ll b e st oppe d a nd d riv en low

when this device is placed in D3hot. This bit is not defined

when the BPCC_En bit reads as 0.

23 BPCC_En R

Bus Power/Clock Control En able. When the bpcce pin is

tied high, this bit reads as a 1 to indicate that the bus

power/clock control mechanism is enabled, as described in

B2_B3 (bit 23). When the bpcce pin is tied lo w, this bit

reads as a 0 to indicate that the bus power/clock control

mechanism is disabled (second ary cl ocks are not di sabled

when this device is placed in D3hot).

Dword Bit Name R/W Description

31:24 Data R Data register. This regi ster is not implemen ted and r eads

00h.

21154 PCI-to-PCI Bridge

Datasheet 129

Dwor d Bit Name R /W Desc r ipt ion

0 Reserved R Reserved. Returns 0 when read.

1M emory write

disconnect

control R/W

Controls when the 21154, as a target, disconnects

memory write transactions.

When 0: The 21154 disconnects on queue full or on a

4KB boundary.

When 1: The 21154 disconnects on a cache line

boundary, as well as when th e queue fil ls or on a 4KB

boundary.

Reset value: 0.

3:2 Reserved R Reserved. Returns 0 when read.

4Secondary bus

prefetch disable R/W

Controls the 21154’s ability to prefetch during upstream

mem ory read transactions.

When 0: The 21154 prefetches and does not forward

byte enable bits during memory read transactions.

When 1: Th e 21154 requests only one Dword from th e

target during memory read transactions and forwards

read byte enab le bi ts. The 21154 return s a targe t

disconnect to the requesting master on the first data

trans fer. Memory re ad line and memory read multiple

trans action s are still pr efetchable.

Reset value: 0.

5Live insertion

mode R/W

Enables hardware control of transaction forwarding in

the 21154.

When 0: Pin gpio<3> has no effect on the I/ O, memory,

and master enable bits .

When 1: If the output enable control for gpio<3> is set

to input only in the gpio output en able control re gister,

this bit enables gpio<3> to mask the I/O enable,

mem ory enable, and master enable bits to 0. These

enable bits are masked when gpio< 3> is driven high.

When this occurs, the 21154 stops accepting I/O and

mem ory transactions.

Re se t va lue: 0.

7:6 Reserved R Reserved. Returns 0 when read.

21154 P CI-to-PCI Bridge

130 Datasheet

15.2.2 Diagnostic Control Register—Offset 41h

This section describes the dia gnostic cont rol register.

W1TR indicates that writing 1 in this bit position causes a chi p r es et to occ ur. Wr iting 0 has no

effect.

Dword address = 40h

Byte enable p_cbe_l<3:0> = xx0xb

15.2.3 Arbiter Control Register—Offset 42h

This section describes the arbit er con trol register.

Dword address = 40h

Byte enable p_ cbe_l<3:0> = 00xxb

Dword Bit Name R/W Description

8 Chi p r es et R/ W1T R

Chip and seco ndary bus reset control.

When 1: Causes the 21154 to perform a chip reset.

Data buffers, conf igur ation registers, and bot h the

primary and secondary interfaces are reset to their

initial state. The 21154 clears this bit once chip reset is

c omplete. The 21154 can them be reconfig ured.

Secondary bus reset s_rst_l is asserted and the

secondary reset bit in the bridge control register is set

when this bit is set. The secondary reset bit in the

bridge control register must be cleared in order to

de as se r t s_ r st _l.

10:9 Test mode R/W

Co ntro ls th e te stabil ity of t he 21 15 4’s intern al co unter s.

These bits are used for chip test only. The va lue of

these bits controls which bytes of the counters are

exercised:

• 00b = Normal functionality—all bits are exercised.

• 01b = Byte 1 is exercised.

• 10b = Byte 2 is exercised.

• 11b = Byte 0 is exercised.

Reset value: 00b.

15:11 Reserved R Reserved. Returns 0 when read.

Dword Bit Name R/W Description

25:16 A rbiter control R/W

Each bit controls whether a secondary bus master is

assigned to th e high pr iority arbit er group or the low

priority arbiter group. Bits <24:16> correspond to request

inputs s_req_l<8:0>, respectively. Bit <25> corresponds

to the 21154 as a secondary bus master.

When 0: Indicates that the master belongs to the low

priority group.

When 1: Indicates that the master belongs to the high

priority group.

Reset value: 10 0000 00 00b.

31:26 Reserved R Reserved. Returns 0 when read.

21154 PCI-to-PCI Bridge

Datasheet 131

15.2.4 p_serr_l Event Disable Register—Offset 64h

This se ction describes the p_serr_l event disable registe r.

Dword address = 64h

Byte enable p_cbe_l<3:0> = xxx0b

Dword Bit Name R/W Description (Sheet 1 of 2)

0 Reserved R Reserved. Returns 0 when read.

1Posted write parity

error R/W

Controls the 21154’s ability to assert p_serr_l

when a data parity error is detected on the target

bus during a posted w rite transaction.

W he n 0: Signa l p_se rr _ l is as se rt e d if thi s ev en t

occurs and the SERR# enable bit in the command

When 1: Signal p_serr _l is not asser ted if this

ev ent occurs.

Reset value: 0.

2Pos te d w rit e

nondelivery R/W

Controls the 21154’s ability to assert p_serr_l

when it is unable to deliver posted write data after

224 attempts.

W he n 0: Signa l p_se rr _ l is as se rt e d if thi s ev en t

occurs and the SERR# enable bit in the command

When 1: Signal p_serr _l is not asser ted if this

ev ent occurs.

Reset value: 0.

3Ta rg et ab or t du rin g

posted write R/W

Controls the 21154’s ability to assert p_serr_l

when it receives a target abort when attempting to

deliver posted write data.

W he n 0: Signa l p_se rr _ l is as se rt e d if thi s ev en t

occurs and the SERR# enable bit in the command

When 1: Signal p_serr _l is not asser ted if this

ev ent occurs.

Reset value: 0.

4Master abort on posted

write R/W

Controls the 21154’s ability to assert p_serr_l

when it rec eives a master abort when attemptin g

to deliver posted write data.

W he n 0: Signa l p_se rr _ l is as se rt e d if thi s ev en t

occurs and the SERR# enable bit in the command

When 1: Signal p_serr _l is not asser ted if this

ev ent occurs.

Reset value: 0.

21154 P CI-to-PCI Bridge

132 Datasheet

15.2.5 gp io Output Data Register—Offset 65h

This section describes the gpio output data register.

Dword Address = 64h

Byte enable p_cbe_l<3:0> = xx0xb

5Delayed write

nondelivery R/W

Controls the 21154’s ability to assert p_serr_l

wh en it i s un ab le to d el i ver de la ye d wr i te d at a aft er

224 attempts.

When 0: Signal p_serr_l is asserted if this event

occurs a nd th e SERR# enab le bit in the command

When 1: Signal p_serr_l is not asserted if this

eve nt oc curs .

Reset value: 0.

6Delayed read—no data

from target R/W

Controls the 21154’s ability to assert p_serr_l

when it is unable to transfer any read data from

the target after 224 attempts.

When 0: Signal p_serr_l is asserted if this event

occurs a nd th e SERR# enab le bit in the command

When 1: Signal p_serr_l is not asserted if this

eve nt oc curs .

Reset value: 0.

7 Reserved R Reserv ed. Returns 0 when read.

Dword Bit Name R/W Description (Sh e et 2 of 2)

Dword Bit Name R/W Description

11:8 GPIO output

write-1-to-clear R/W1TC

The gpio<3:0> pin output data write-1-to-clear.

Writing 1 to any of these bits drives the

corresponding bit low on the gpio<3:0> bus if it

is programmed as bidirectional. D ata is driven

on the PCI c lock cycle following completion of

the configuration write to this register. Bit

positions corresponding to gpio pins that are

programmed as input only are not driven.

Writing 0 to these bits has no effect. When

read, reflects the last value written.

Reset value: 0.

15:12 GPIO output write-

1-to-set R/W1TS

The gpio<3:0> pin output data write-1-to-set.

Writing 1 to any of these bits drives the

corresponding bit high on the gpio<3:0> bus if it

is programmed as bidirectional. D ata is driven

on the PCI c lock cycle following completion of

the configuration write to this register. Bit

positions corresponding to gpio pins that are

programmed as input only are not driven.

Writing 0 to these bits has no effect. When

read, reflects the last value written.

Reset value: 0.

21154 PCI-to-PCI Bridge

Datasheet 133

15.2.6 gpio Output Enable Control Register—Offset 66h

This section des cr ibes the gpio output enable control regist er.

Dword Addr ess = 64h

Byte enable p_cbe_l<3:0> = x0xxb

15.2.7 gpio Input Data Register—Offset 67h

This se ction describes the gpio input da ta register.

Dword address = 64h

Byte enable p_cbe_l<3:0> = 0xxxb

15.2.8 Secondary Clock Control Register—Offset 68h

This se ction describes the secondary clock control register.

Dword address = 68h

Byte enable p_cbe_l<3:0> = xx00b

Dwor d Bit Nam e R/W De sc ription

19:16 GPI O output

enable write-1-to-

clear R/W1TC

The gpio<3:0> pin output data write-1-to-

enable. Writin g 1 to an y of t hese bits drive s the

corresponding gpio<3:0> pin as input only; that

is, the output driver is trista ted. Writing 0 to th is

last value written.

Reset value: 0 (all pins are input only).

23:20 GPI O output

enable write-1-to-

set R/W1TS

The gpio<3:0> pin output enable control write-

1-to-set. Writing 1 to any of these bits

configures the corresponding gpio<3:0> pin as

bidirectional, that is, enables the output driver

and drives the value set in the output data

registe r (65h). Writing 0 to th ese bits has no

effect. When read, reflects the last value

written.

Reset value: 0 (all pins are input only).

Dwor d Bit Name R/ W Desc r ipt ion

27:24 Reserved R Reserved. Returns 0 when read.

31:28 GPIO input R This read-only register reads the state of the gpio <3:0>

pins. This state is updated on the PCI clock cycle

following a change in the gpio pins.

21154 P CI-to-PCI Bridge

134 Datasheet

Dw ord Bit Name R/W Description

1:0 Slot 0 clock

disable R/W

If either bit is 0: Signal s_clk_o<0> is enabled.

When both bits are 1: Signal s_cl k_o<0> is disabled and

driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream. These bit s are assigned to correspond to

the PRSNT# pins for slot 0.

3:2 Slot 1 cloc k

disable R/W

If either bit is 0: Signal s_clk_o<1> is enabled.

When both bits are 1: Signal s_cl k_o<1> is disabled and

driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream. These bit s are assigned to correspond to

the PRSNT# pins for slot 1.

5:4 Slot 2 clock

disable R/W

If either bit is 0: Signal s_clk_o<2> is en abled.

When both bits are 1: Signal s_cl k_o<2> is disabled and

driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream. These bit s are assigned to correspond to

the PRSNT# pins for slot 2.

7:6 Slot 3 clock

disable R/W

If either bit is 0: Signal s_clk_o<3> is en abled.

When both bits are 1: Signal s_cl k_o<3> is disabled and

driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream. These bit s are assigned to correspond to

the PRSNT# pins for slot 3.

8Device 1

clock

disable R/W

When 0: Signal s_clk_o <4> is enabled.

When 1: Signal s_clk_o <4> is disabled and driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream.

9Device 2

clock

disable R/W

When 0: Signal s_clk_o <5> is enabled.

When 1: Signal s_clk_o <5> is disabled and driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream.

10 Device 3

clock

disable R/W

When 0: Signal s_clk_o <6> is enabled.

When 1: Signal s_clk_o <6> is disabled and driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream.

11 Device 4

clock

disable R/W

When 0: Signal s_clk_o <7> is enabled.

When 1: Signal s_clk_o <7> is disabled and driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream.

21154 PCI-to-PCI Bridge

Datasheet 135

15.2.9 p_serr_l Status Register—Offset 6Ah

This se ction describes the p_serr_l stat us regi ster.

This status register indicates the reason for the 21154’s assertion of p_serr_l.

Dword address = 68h

Byte enable p_cbe_l<3:0> = x0xxb

12 Device 5

clock

disable R/W

When 0: Signal s_clk_o<8> is enabled.

When 1: Signal s_clk_o<8> is disabled and driven high.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream.

13 The 21154

clock

disable R/W

When 1: Signal s_clk_o<9> is disabled and driven high.

When 0: Signal s_clk_o<9> is enabled.

Upon secondary bus reset, this bit is initialized by shifting in a

serial data stream. This bit is assigned to correspond to the

21154 secondary clock input, s_clk.

15:14 Reserved R Reserved. Returns 1 when read.

Dwor d Bit N a me R/W D e sc ription

Dword Bit Name R/ W Description

0Address parity

error R/W1TC

When 1: Signal p_serr_l was asserted because

an address parity err or was detected on either the

primary or secondary PCI bus.

Reset value: 0.

1Pos te d w rit e

data parity

error R/W1TC

When 1: Si gnal p_serr _l was asserted because a

posted write data parity error was detected on th e

target bus.

Reset value: 0.

2Pos te d w rit e

nondelivery R/W1TC

When 1: Signal p_serr_l was asserted because

the 21154 was unable to deliver posted write data

to the target after 224 at tem p ts .

Reset value: 0.

3Ta rg et ab or t

dur in g po sted

write R/W1TC

When 1: Signal p_serr_l was asserted because

the 21154 received a target abort when delivering

posted write data.

Reset value: 0.

4Master abort

dur in g po sted

write R/W1TC

When 1: Signal p_serr_l was asserted because

the 21154 received a master abort when

attempting to deliver posted write data.

Reset value: 0.

21154 P CI-to-PCI Bridge

136 Datasheet

15.3 Configuration Register Values After Reset

Table 36 lists the value of the 21154 configuration regis ters a fter reset. Reserved registers are not

lis ted and are always read only as 0.

5Delayed write

nondelivery R/W1TC

When 1: Signal p_serr_l was as sert ed because

the 2 1154 wa s un able t o deli ve r del aye d wr ite da ta

after 224 attempts.

Reset value: 0.

6Delayed

re a d—n o da ta

from target R/W1TC

When 1: Signal p_serr_l was as sert ed because

the 21154 was unable to read any data from the

target after 224 attempts.

Reset value: 0.

7Delayed

transaction

mas ter timeout R/W1TC

When 1: Signal p_serr_l was asserted because a

master did not repeat a read or wr ite transaction

before the master timeou t counter expired on the

initiator’s PCI bus.

Reset to 0.

Dword Bit Name R/W Description

Tab le 36. Configuration Register Values After Reset (Sheet 1 of 2)

Byte Address Register Name Reset Value

00—01h Ve ndor ID 1011h

02—03h Device ID 0026h

04—05h Primary command 0000h

06—07h Primary status 0280h–21154-AA only

0290h–33 MHz 21154

02B0h–66 MH z capabl e 21154

08h Revision ID xxh1

09—0Bh Class code 060400h

0Ch Cache line size 00h

0Dh Primary latency timer 00h

0Eh Header typ e 01h

18h Pr imary bus number 00h

19h Secondary bus number 00h

1Ah Subordinate bus numb er 00h

1Bh Secondary latency timer 00h

1Ch I/O base address 01h

1Dh I/O limit addres s 01h

1E— 1Fh Secondary status 0280h–33 MHz 21154

02A0h–66 MH z capabl e 21154

20—21h Memory b ase address 0000h

22—23h Memory lim it address 0000h

24—25h Prefetchable memory base address 0001h

21154 PCI-to-PCI Bridge

Datasheet 137

26—27h Prefetchable memory limit addr ess 0001h

28—2Bh Prefetchable memory base address upper 32 bits 00000000h

2C— 2Fh Prefetchable memory limit address upper 32 bits 00000000h

30—31h I/O base address upper 16 bi ts 0000h

32—33h I/O limit addr ess u pper 16 bits 0000h

34—35h Sub syste m vendor ID–211 54-AA on ly

ECP pointer 0000h

00DCh

36—37h Sub syste m ID– 21154 -AA only

Reserved 0000h

3Dh Interrupt pin 00h

3E—3Fh Bridge co ntrol 0000h

40h Chip control 00h

41h Diagnostic control 00h

42—43h Arbiter control 0200h

64h p_serr_l event disable 00h

65h gpio output data 00h

66h gpio output enable control 00h

67h gpio input data 00h

68—69h Secondary clock co ntrol2

6Ah p_serr_l status 00h

DCh Power management capability ID301h

DDh Next item pointer300h

DEh–DFh Power management capabilities register30001h

E0h–E1h Po wer managem ent control and statu s30000h

E2h PPB support extension s300h (bpcce=0)

C0h (bpcce = 1)

E3h Power management data register300h

1. Dependent on revision of device.

2. The value of this register is dependent upon the serial clock disable shift function that occurs during

secondary bus reset.

3. In the 21154–AA, these registers are reserved.

Table 36. Con figura tion Register Value s After Reset (Sh eet 2 of 2)

Byte Address Register Name Reset Value

Datasheet 139

16.0 JTAG Test Port

This chapter de scribes the 21154’s implementation of a joint test action group (JTAG) test port

according to IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture.

16.1 Overview

The 21154 conta ins a s erial -scan test port that conforms to IEEE st andard 1149.1. The JTAG test

port consis ts of the following:

• A 5-wire test acce ss port

•A test access por t controlle r

•An instruction register

•A bypass reg is ter

•A boundary-s can regis ter

Note: T he JTAG test acce ss port is to be used only while the 21154 is not

operating.

16.2 JTAG Signal Pins

This chapter describes the JTAG pi ns listed in Ta ble 37.

16.3 Test Access Port Controller

The test access port cont roller is a finit e state mach ine that interprets IEEE 1149.1 protocols

rece ived through the tms line.

The state transitions in the controller are caused by th e tms signal o n the r i sing edge of tck. I n each

state , the cont rol ler generat es appr opri ate clock an d control s ignals tha t contro l the operati on of the

tes t fea tures. After entry into a state, test feature operations are initiated on the rising edge of tck.

Table 37. JTAG Pins

Signal Name Type Description

tdi Input Serial bound ary-scan dat a in

tdo Output Serial bound ary-scan dat a

tms Input JTAG test mode select

tck Input Boundary-scan clock

tr st_l Input JTAG test access port re set

21154 P CI-to-PCI Bridge

140 Datasheet

16.4 Instruc tion Register

The 5-bit instruction register selec ts the test modes and fe atures. The instruction register bits are

interpreted a s instructions, as shown in Tabl e 38. The instructions select and control the operation

of the boundary-scan and bypass registers.

Table 38 des cribes the 21154’s instr uctions.

The instruction register is loade d through the tdi pin. The instruction re gister has a s hift-in stage

f rom which the instruction is then load ed in par allel.

16.5 Bypass Register

The bypas s regist er is a 1-bit s hift register that pr ovides a means for effective ly bypassing the

JTAG test logic through a single-bit serial connect ion through the ch ip from tdi to tdo. At board-

leve l testing, this helps reduce overall length of the scan ring.

16.6 Boundary-Scan Register

The boundary-scan re gister is a single-shift register-based path form ed by boundary-scan cells

placed at the chip's signal pins. The regis ter is accesse d through the JTAG port's td i and tdo pins.

Table 38. JTAG Instruction Register

Instruction

Contents

Instruction Name

(Test Mode or

State)

Te st Register

Selected Operation

00000 EXTEST Boundary-scan External test (drives pins from the

boundary-scan register)

00001 SAM PLE B ou nd ar y -s ca n S a mp le s I/O

00010 BSROSC Boundary-scan Ring oscillates the boundary-scan register

00011 BSRDLY Boundary-scan Configures the boundary-scan register for

propagation de lay measurement

00100 CLAMP Bypass Dri v es pins from the boundary -scan

for shifts

00101 HIGHZ Bypass Tristates all output and I/O pins except the

tdo pin

00110–11111 BYPASS Bypass Selects the bypass register for shifts

21154 PCI-to-PCI Bridge

Datasheet 141

16.6.1 Boundary-Scan Register Cells

Each boundary-scan cell operates in conjunction with the current instruction and the current state

in the test access port controller s tate machine. The funct ion of the BSR cells is determined by the

as so ci ated pin s , as f o ll o w s:

•Input-only pins—The boundary-sc an c ell is bas ical ly a 1-bit shift register. The cell supports

sample and shif t f unctions.

•Output-only pins—The boundary-scan cell comprises a 1-bit shift register and an output

multiplexer. The cell supports the sample, shift, and drive output functions.

•Bidirectional pins —The boundary-sca n cel l is identica l to the output-only pin cell, but it

captures test da ta from the incoming data line. The cell supports sample, shift, drive output,

and hold output functions. It is used at all I/ O pins.

16.6.2 21154 Boundary-Scan Order

Table 39 lists the boundary-scan re gister orde r and the group dis able controls. The group disable

control either ena bles or trista tes its c orresponding group of bidirectional drivers. When the value

of a group disable control bit is 0, the output driver is enabled. When the value is 1, the driver is

tristated. There are nine groups of bidirectional drivers, and the refore nine group disable control

bits.

The Group Disable Number column in Table 39 shows which group disable bit controls the

corresponding output driver . Group disable bits do not affect input-only pins, so those pins have a

blank rather tha n a group numbe r in the By Group Dis able col umn. The group disable co ntro l wire

can co ntrol pins on either si de of where the group disable boundary-s ca n register is placed. The

group dis able boundary-scan registers have a boundar y-scan register order numbe r entry , but they

do not have a corresponding pin number or signal name.

Data shifts from tdi into the most significant bit of the boundary-scan register, and from the least

significa nt bit of the boundary-scan register out to tdo.

Table 39. Bou nd ary S can Or der (Sheet 1 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

D4 s_req_l<0> 88 —

C1 s_req_l<1> 89 —

C2 s_req_l<2> 90 —

D3 s_req_l<3> 91 —

E4 s_req_l<4> 92 —

D1 s_req_l<5> 93 —

D2 s_req_l<6> 94 —

E3 s_req_l<7> 95 —

E1 s_req_l<8> 96 —

E2 s_gnt_l<0> 97 5

F3 s_gnt_l<1> 98 5

F1 s_gnt_l<2> 99 5

21154 P CI-to-PCI Bridge

142 Datasheet

F2 s_gnt_l<3> 100 5

— Vss 101 — Group Disable 5

G1 s_gnt_l<4> 102 5

G4 s_gnt_l<5> 103 5

G2 s_gnt_l<6> 104 —

G3 s_gnt_l<7> 105 5

H1 s_gnt_l<8> 106 5

H2 s_rst_l 107 4

J4 s_clk 108 —

K1 s_cfn_l 109 —

K2 gpio<3> 110 4

K3 gpio<2> 111 4

L4 gpio<1> 112 4

L1 gpio<0> 113 4

L2 s_clk_o<0> 114 4

— Vss 115 — Grou p Disable 4

L3 s_clk_o<1> 116 4

M3 s_clk_o<2> 117 4

M1 s_clk_o<3> 118 4

M2 s_clk_o<4> 119 4

N3 s_clk_o<5> 120 4

N1 s_clk_o<6> 121 4

P3 s_clk_o<7> 122 4

P2 s_clk_o<8> 123 4

P1 s_clk_o<9> 124 4

R3 p_rst_l 125 —

R2 p_gnt_l 126 —

T3 p_clk 127 —

T 2 Vs s 1 28 — Gr o up Di sa bl e 3

U3 p_req_l 129 3

U2 p_ad<31> 130 2

U4 p_ad<30> 131 2

U1 p_ad<29> 132 2

V2 p_ad<28> 133 2

V1 p_ad<27> 134 2

V3 p_ad<26> 135 2

W2 p_ad<25> 136 2

Tab le 39. Bounda ry Sca n Order (Shee t 2 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

21154 PCI-to-PCI Bridge

Datasheet 143

W1 p_ad<24> 137 2

Y2 p_cbe_l<3> 138 2

Y1 p_idsel 139 —

W4 p_ad<23> 140 2

Y3 p_ad<22> 141 2

AA1 p_ad<21> 142 2

AA3 p_ad<20> 143 2

Y4 p_ad<19> 144 2

AB3 p_ad<18> 145 2

AA4 p_ad<17> 146 2

Y5 p_ad<16> 147 2

AC4 Vss 148 — Group Disable 2

AB4 p_cbe_l<2> 149 2

AA5 p_frame_l 150 1

AC5 p_irdy_l 151 1

AB5 p_trdy_l 152 1

AA6 p_devsel_l 153 1

AC6 p_stop_l 154 1

AB6 p_lock_l 155 1

— Vss 156 — Group Disable 1

AC7 p_perr_l 157 1

Y7 p_serr_l 158 1

AB7 p_par 159 0

AA7 p_cbe_l<1> 160 0

AB8 p_ad<15> 161 0

AA8 p_ad<14> 162 0

AC9 p_ad<13> 163 0

AB9 p_ad<12> 164 0

AA9 p_ad<11> 165 0

AC10 p_ad<10> 166 0

AB10 p_m66ena 167 0

AA10 p_ad<9> 168 0

Y11 p_ad<8> 169 0

AC11 p_cbe_l<0> 170 0

AB11 p_ad<7> 171 0

AA11 p_ad<6> 172 0

AA12 p_ad<5> 173 0

Table 39. Bou nd ary S can Or der (Sheet 3 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

21154 P CI-to-PCI Bridge

144 Datasheet

AB12 p_ad<4> 174 0

AB13 p_ad<3> 175 0

AA13 p_ad<2> 176 0

Y13 p_ad<1> 177 0

AA14 p_ad<0> 178 0

AB14 p_ack64_l 179 0

AC14 p_req64_l 180 0

AA15 p_cbe_l<7> 181 0

AB15 p_cbe_l<6> 182 0

Y15 p_cbe_l<5> 183 0

AC15 p_cbe_l<4> 184 0

AA16 p_ad<63> 185 0

AB16 p_ad<62> 186 0

AA17 p_ad<61> 187 0

AB17 p_ad<60> 188 0

Y17 p_ad<59> 189 0

AB18 p_ad<58> 190 0

AC18 p_ad<57> 191 0

AA18 p_ad<56> 192 0

AC19 p_ad<55> 193 0

AA19 p_ad<54> 194 0

AB20 p_ad<53> 195 0

Y19 p_ad<52> 196 0

AA20 p_ad<51> 197 0

AB21 p_ad<50> 198 0

AC21 p_ad<49> 199 0

AA21 p_ad<48> 200 0

Y20 p_ad<47> 201 0

AA23 p_ad<46> 202 0

Y21 p_ad<45> 203 0

W20 p_ad<44> 204 0

Y23 p_ad<43> 205 0

W21 p_ad<42> 206 0

W23 p_ad<41> 207 0

W22 p_ad<40> 208 0

V21 p_ad<39> 209 0

V23 p_ad<38> 210 0

Tab le 39. Bounda ry Sca n Order (Shee t 4 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

21154 PCI-to-PCI Bridge

Datasheet 145

V22 p_ad<37> 211 0

U23 p_ad<36> 212 0

U20 p_ad<35> 213 0

U22 p_ad<34> 214 0

U21 Vss 215 — Group Disable 0

T23 p_ad<33> 216 0

T22 p_ad<32> 217 0

T21 p_par64 218 0

R22 config66 219 —

R21 msk_in 220 —

P23 tdi — —

P22 tdo — —

N21 s_par64 0 8

M21 s_ad<32> 1 8

M23 s_ad<33> 2 8

M22 s_ad<34> 3 8

L22 s_ad<35> 4 8

L21 s_ad<36> 5 8

L23 s_ad<37> 6 8

K21 s_ad<38> 7 8

K22 s_ad<39> 8 8

K23 s_ad<40> 9 8

J22 s_ad<41> 10 8

J20 s_ad<42> 11 8

J23 s_ad<43> 12 8

H21 s_ad<44> 13 8

H22 s_ad<45> 14 8

H23 s_ad<46> 15 8

G21 s_ad<47> 16 8

G22 s_ad<48> 17 8

G20 s_ad<49> 18 8

F22 s_ad<50> 19 8

F23 s_ad<51> 20 8

F21 s_ad<52> 21 8

E23 s_ad<53> 22 8

E21 s_ad<54> 23 8

D22 s_ad<55> 24 8

Table 39. Bou nd ary S can Or der (Sheet 5 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

21154 P CI-to-PCI Bridge

146 Datasheet

E20 s_ad<56> 25 8

D21 s_ad<57> 26 8

C22 s_ad<58> 27 8

C23 s_ad<59> 28 8

C21 s_ad<60> 29 8

D20 s_ad<61> 30 8

A21 s_ad<62> 31 8

C20 s_ad<63> 32 8

D19 s_cbe_l<4> 33 8

A20 s_cbe_l<5> 34 8

C19 s_cbe_l<6> 35 8

A19 s_cbe_l<7> 36 8

B19 s_req64_l 37 8

C18 s_ack64_l 38 8

A18 s_ad<0> 39 8

B18 s_ad<1> 40 8

A17 s_ad<2> 41 8

D17 s_ad<3> 42 8

B17 s_ad<4> 43 8

C17 s_ad<5> 44 8

B16 s_ad<6> 45 8

C16 s_ad<7> 46 8

A15 s_cbe_l<0> 47 8

B15 s_ad<8> 48 8

C15 s_ad<9> 49 8

A14 s_m66ena 50 8

B14 s_ad<10> 51 8

C14 s_ad<11> 52 8

D13 s_ad<12> 53 8

A13 s_ad<13> 54 8

B13 s_ad<14> 55 8

C13 s_ad<15> 56 8

C12 s_cbe_l<1> 57 8

A12 Vss 58 — Group Disable 8

B12 s_par 59 8

B11 s_serr_l 60 —

C11 s_perr_l 61 7

Tab le 39. Bounda ry Sca n Order (Shee t 6 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

21154 PCI-to-PCI Bridge

Datasheet 147

16.7 Initialization

The test access port controlle r and the instruction register output latches are initiali zed when the

trst_l input is asserted. The test access port controller enters the test-logic reset state. The

instruction register is reset to hold the bypa ss register instruction. During test-logic reset state, all

JTAG t est logic i s disabl ed, an d the chi p perform s normal fu nction s. The te st ac cess p ort contr oll er

leaves this state only when an appropriate JTAG test operation sequence is sent on the tms and tck

pins.

A11 s_lock_l 62 7

C10 s_stop_l 63 7

B10 s_devsel_l 64 7

A10 s_trdy_l 65 7

C9 s_irdy_l 66 7

— Vss 67 — Group Disable 7

B9 s_frame_l 68 7

D9 s_cbe_l<2> 69 6

A9 s_ad<16> 70 6

C8 s_ad<17> 71 6

B8 s_ad<18> 72 6

A8 s_ad<19> 73 6

B7 s_ad<20> 74 6

D7 s_ad<21> 75 6

A7 s_ad<22> 76 6

A6 s_ad<23> 77 6

C6 s_cbe_l<3> 78 6

B5 s_ad<24> 79 6

C5 s_ad<25> 80 6

B4 s_ad<26> 81 6

A4 s_ad<27> 82 6

C4 s_ad<28> 83 6

B3 s_ad<29> 84 6

A3 s_ad<30> 85 6

— Vss 86 — Group Disable 6

C3 s_ad<31> 87 6

Table 39. Bou nd ary S can Or der (Sheet 7 of 7)

Number Signal Name Boundary-Scan

Order By Group

Disable Group Disable Cell

Datasheet 149

17.0 Electrical Specificat ions

This chapter sp ec ifies t he following el ectrica l behavi or of the 21154:

•PCI electr ical conform an ce

•Absolute maximum ratings

•dc specifications

•ac timi ng specific ations

17.1 PCI Electrical Specification Conformance

The 21154 PCI pins co nform to the basic set of PCI elect r ical spe cifications in the PCI Local Bus

Specification, Revision 2.1. See that document for a complete description of the PCI I/O protoc ol

and pin ac spe cifications.

17.2 Abso lute Ma xim u m Rating s

The 21154 is spec ified to operate at a maxi mum fr equency of 33 MHz, or 66 MHz if 66 MHz

capa ble, at a junction temperature (Tj) not to exceed 125C. Table 40 list s the abso lute ma x imum

ratings for the 21154. Thes e are stress ratings only; stressing the devi ce beyond the abso lute

maximu m ratings may cause pe rmanent dama ge. Operati ng beyond the functional operat ing range

(see Table 41) is not recommended and ext ended ex posure beyond the functi onal operati ng range

may affect reliability.

Table 40. Absolute Maximum Ratings

Parameter Minimum Maximum

J unction temperature,Tj—125°C

Maximum voltage applied to signal

pins — 5.5 V

Sup pl y vo ltag e, V cc — 3.9 V

Maximum Power, PWC — 2.2 W

Storage temperature range, Tsg –55°C125°C

Table 41. Functional Operating Range

Parameter Minimum Maximum

Sup pl y vo ltag e, V cc 3.0 V 3 .6 V

Operating ambient tem perature, Ta0°C70°C

21154 P CI-to-PCI Bridge

150 Datasheet

17.3 DC Specifications

Table 42 defines the dc parameters met by all 21154 signals under normal operating conditions.

1 Guarantees meeting the specification for the 5-V signaling environment.

2 For 3.3-V signaling environment.

3 For 5-V signaling environment.

4 Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.

Note: In Table 42, curre nts into the chip (chip sinking) are denoted as positive (+) current. Currents from

the chip (chip s ourcing) are denoted as negative (–) curre nt.

17.4 AC Timing Specifications

The next sections specify the following:

•Clock timing specifica tions

•PCI signa l timing specifications

•Re set ti m i n g s p ec if ica tio n s

•g pio timing specifi cations

•JTAG timing specifications

17.4.1 Clock Timing Specifications

The ac specific ations consist of input requirements and output responses. The input requirem ents

cons ist of setup and hold times, pulse widths, and high and low time s . Output responses are delays

f rom clock to signa l. The ac spe cif icat ions ar e define d se par ately for each clock domai n with in the

21154.

Table 42. DC Parameters

Symbol Parameter Condition Minimum Maximum Unit

Vcc Supply voltage —3.03.6V

il Low-level input voltage1— –0.5 0.3 Vcc V

Vih High-level input voltage1— 0.5 Vcc Vcc + 0.5 V V

Vol Lo w -le v el outp ut vo lta g e2Iout = 1500 µA — 0.1 Vcc V

Vol5V Low -lev el ou tp ut vo lta g e3Iout = 6 mA — 0.55 V

Voh High-level output voltage2Iout = –500 µA 0.9 Vcc —V

oh5V High-level output voltage3Iout = –2 mA 2.4 — V

Iil Low-level input leakage

current1,4 0 < Vin < Vcc —±10µA

in Input pin capacitance — — 10.0 pF

CIDSEL p_idsel pin capacitance — — 8.0 pF

Cclk p_clk, s_clk pin capaci tance — 5.0 12.0 pF

21154 PCI-to-PCI Bridge

Datasheet 151

Figure 23 shows the ac parameter meas urements for the p_clk an d s_clk s ignals, and Table 43 and

Table 44 specify p_c lk and s_clk para meter values for clock signal ac timing. See also F igure 24

for a further illus tration of signal timing. Unless otherwis e noted, all ac parameters are guarantee d

when tested within the functional opera ting range of Table 41.

1 0.2 Vcc to 0.6 Vcc.

2 Measured with 30-pF lumped load.

Figure 23. P C I Clock Sign al AC Parameter M easu rem en ts

Table 43. 33 M Hz PCI Clock Signal AC Param eters

Symbol Parameter Minimum Maximum Unit

Tcyc p_clk,s_clk cycle time 30 ∞ns

Thigh p_clk, s_clk high time 11 —ns

low p_clk, s_clk low time 11 — ns

p_clk, s_clk slew rate114V/ns

sclk Delay fr om p_clk to s_clk 0 7 ns

Tsclkr p_ cl k r is ing to s_cl k_o ri s in g 0 5 ns

Tsclkf p_clk fallin g to s_clk_o fal ling205ns

dskew s_clk_0 duty cy cle skew from p_cl k

duty cycle2— 0.750 ns

Tskew s_clk_0<x> to s_clk_0<y> — 0.500 ns

p_clk

s_clk

Thigh

Tskew Tskew

Tcyc

Tlow

Thigh

Tcyc

LJ-04738.AI4

Vt1

Vt2

Vt3

Vt2

Vt1

Vt3

Note:V

_ 2.0 V for 5-V clocks; 0.5 V

for 3.3-V clocks

_ 1.5 V for 5-V clocks; 0.4 V

for 3.3-V clocks

_ 0.8 V for 5-V clocks; 0.3 V

for 3.3-V clocks

21154 P CI-to-PCI Bridge

152 Datasheet

17.4.2 PCI Signal Timing Specifications

Figure 24 and Table 45 show the PCI signal timing spe cifications.

Tab le 44. 66 MHz PCI Clock Signal AC Parameters

Symbol Parameter Minimum Maximum Unit

Tcyc p_clk,s_clk cyc le time 15 30 ns

Thigh p_clk, s_clk high time 6 —ns

low p_c lk , s_ cl k lo w ti me 6 — ns

p _c lk , s_ clk sl ew ra te1

1. 0.2 Vcc to 0.6 Vcc.

1.5 4 V/ns

Tsclk De la y f rom p_ cl k t o s_ c lk 0 tb d2

2. To be determ ined.

Tsclkr p_clk rising to s_clk_o risi ng 0 5 ns

Tsclkf p_clk falling to s_clk_o falling3

3. Measured with 30-pF lumped load.

05ns

dskew s_clk_0 duty cycle skew from p_clk

d ut y cycl e —0.750ns

skew s_clk_0<x> to s_clk_0<y> — 0.500 ns

Figure 24. PCI Signal Timing Measu rem en t Conditions

Tab le 45. 33 MHz PCI Signal Tim ing (Sheet 1 of 2)

Symbol Parameter Minimum Maximum Unit

Tval CLK to signal valid delay — bused

signals1,2,3 211 ns

val(ptp) CLK to sign al v alid delay — point-to-

point1,2,3 212 ns

on Float to active delay1,2 2— ns

off Active to float delay1,2 —28 ns

Valid

Tval Tinval

Toff

Ton

Tsu

Output

Input

CLK

LJ-04739.AI4

Vtest

Note:

test

1.5 V for 5-V signals; 0.4 V

for 3.3-V signals

21154 PCI-to-PCI Bridge

Datasheet 153

1 See Figure 24.

2 All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.

3Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad, p_cbe_l, p_par,

p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_lock_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, p_par64,

s_ad, s_cbe_l, s_par, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_lock_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l,

and s_par64.

1 See Figure 24.

2 All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.

3 Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad, p_cbe_l, p_par,

p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_lock_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, p_par64,

s_ad, s_cbe_l, s_par, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_lock_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l,

and s_par64.

Tsu Input setup time to CLK — bused

signals1,2,3 7— ns

su(ptp) Input setup time to CLK—point-to-

point1,2,3 10, 12 — ns

ThInput signal hold time from CLK1,2 0— ns

Table 45. 33 M Hz PCI Signal Timing (Sh eet 2 of 2)

Symbol Parameter Minimum Maximum Unit

Table 46. 66 MHz PCI Signal Timing

Symbol Parameter Minimum Maximum Unit

Tval CLK to signal valid delay — bused

signals1,2,3 26 ns

val(ptp) CLK to signal valid delay — point-to-

point1,2,3 26 ns

on Float to active delay1,2 2— ns

off Active to float delay1,2 —14 ns

su Input setup time to CLK — bused

signals1,2,3 3— ns

su(ptp) Input setup time to CLK—point-to-

point1,2,3 5— ns

hInput signal hold time from CLK1,2 0— ns

21154 P CI-to-PCI Bridge

154 Datasheet

17.4.3 Reset Timing Specifications

Table 47 sho w s th e r es e t ti m i n g spe cifi c at io ns for p_rst_l and s_rs t_l.

17.4.4 gpio Timing Specifications

Table 48 and Table 49 show the gpio timing specifications. See also Figure 24.

Tab le 47. Reset Timing Specific ations

Symbol Parameter Minimum Maximum Unit

Trst p_rst_l active time after power stable 1 —µs

rst—clk p_rst_l active time after p_clk stable 100 —µs

rst—off p_rst_l active-to-output float delay —40ns

srst s_rst_l active after p_rst_l assertion — 40 ns

Tsrst—on s_rst_l active time after s_clk stable 100 —µs

dsrst s_ rst_l deassertion after p_rst_l

deassertion 20 25 Cycles

p_rst_l slew rate1

1. Applies to rising (deasserting) edge only.

50 — mV/ns

Trrsu p_req64_l to p_rst_l setup time 10*Tcyc —ns

rrh p_rst _l to p_req64_l hold time 0 50 ns

Trval s_rst_l rising to s_req64_l rising 2 52 ns

Table 48. 33 MHz gpio Ti ming Specifications

Symbol Parameter Maximum Minimum Unit

Tvgpio s_clk to gpio output valid 2 12 ns

Tgon gpi o flo at-to-a c tiv e dela y 2 — n s

Tgoff gpio active t o float delay — 28 ns

Tgsu gpio-to-s_clk setup time 7 — ns

Tgh gpio hold time after s_clk 0 — ns

Tgcval s_clk-to-gpio<0> shift clock output

valid —13.5ns

gcyc gpio<0> cy cle time 30 ∞ns

Tgsval gpio<0>-to-gpi o<2> shift control

output valid —8 ns

msu msk_in setup time to gpio<0> 15 — ns

Tmh msk _in hold time after gpio<0> 0 — ns

21154 PCI-to-PCI Bridge

Datasheet 155

17.4.5 JTAG Timing Specifications

Table 50 shows the JTAG timing spec ifications.

Table 49. 66 MHz gpio Timing Specificati ons

Symbol Parameter Maximum Minimum Unit

Tvgpio s_clk to gpio output valid 2 12 ns

Tgon gpio float-to-active delay 2 —ns

goff gpio active to float delay — 28 ns

Tgsu gpio - to-s_ cl k setu p t im e 7 — ns

Tgh gpio hold time after s_clk 0 — ns

Tgcval s_clk-to-gpio<0> shift clock output

valid —13.5ns

gcyc gpio<0> cycle time 30 ∞ns

Tgsval gpio<0>-to-gpio<2> shift control

output va lid —8 ns

msu msk_in setup time to gpio<0> 1 5 — ns

Tmh msk_in hold time after gpio<0> 0 — ns

Table 50. JTA G Timing Specifications

Symbol Parameter Maximum Minimum Unit

Tif tck frequency 0 10 MHz

Tjp tck peri od 100 ∞ns

Tjht tck high time 45 — ns

Tjlt tck low time 45 — ns

Tjrt tck rise time1

1. Measured between 0.8 V and 2.0 V.

—10ns

Tjft t ck fall time2

2. Measured between 2.0 V and 0.8 V.

—10ns

Tje tdi, tms setup time to tck rising edge 10 — ns

Tjh tdi, tm s hold time from tck rising

edge 25 — ns

Tjd tdo valid delay f rom tck falling e dge3

3. C1 = 50 pF.

—30ns

Tjfd tdo float delay from tck falling edge — 30 ns

Datasheet 157

18.0 Mechanical Specif ications

The 21154 is containe d in an industry-standard 304-point 2-layer plastic ba ll grid array (PBGA)

packa ge, shown in Figure 25.

Figure 25. 304-Poi nt 2-Layer PBGA P ackag e

21154

Pin 1 Corner

Pin 1 I.D.

Chamfer

4 Places

_ B _

_ A _

E1 E

_ C _

_ Basic Dimension

_ Reference Dimension( )

aaa

Note:

bbb

/ 0.30

Pin 1 Corner

( J )

( I )

30o

b /

LJ-05555.AI4

Top View

Bottom View

/ /

21154 P CI-to-PCI Bridge

158 Datasheet

Table 51 list s th e p a c ka ge di men sion s in m i ll imet er s .

Tab le 51. 304-Point 2-Layer PBG A Packa ge Dimension s

Symbol Dimension Minimum

Value Nominal Value Maximum

Value

e Ball Pitch —1.27 BSC

1. ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines

Basic Dimension (BSC) as: A numerical value used to describe the theoretically exact size, profile, ori-

entation, or loca tion of a feature or datum t arget. It i s the basis fro m whi ch perm issible var iation s are

established by tolerances on other dimensions, in notes, or in feature control frames.

—

A Overall pack age height 2.12 2.33 2.54

A1Package standoff height 0.50 0.60 0 .70

A2Encapsulation thi c kness 1.12 1.17 1.22

b Ball diameter 0.60 0.76 0.90

c Substrate thickness 0.50 0.56 0.62

aaa Coplanarity — — 0.15

bbb Overall package planar ity — — 0.15

D Overall package width 30.80 31.00 31.20

D1Overall encapsulation width — 26.00 26.70

E Overall pack age width 30.80 31.00 31.20

E1Overall encapsulation width — 26.00 26.70

ILocation of first row

(

-direction) — 1.53 reference2

2. The value for this measurement is for reference only.

—

JLocation of first row

(

-direction) — 1.53 reference2—

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