OUT
VDD
CB_EN
_
GND
1
2
4
3
CD
VC2
VC1
VC1_CB
8
7
5
6
bq29200
bq29209
www.ti.com
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries
Check for Samples: bq29200 ,bq29209
1FEATURES • External Cell Balancing Mode Supported
• 2-Series Cell Secondary Protection • High-Accuracy Overvoltage Protection:
• Automatic Cell Imbalance Correction with – ±25 mV with TA= 0°C to 60°C
External Enable Control • Fixed Overvoltage Protection Thresholds:
– ±30 mV Enable, 0 mV Disable Thresholds 4.30 V, 4.35 V
Typical • Small 8L DRB Package
• External Capacitor-Controlled Delay Timer APPLICATIONS
• External Resistor-Controlled Cell Balance • 2nd Level Protection in Li-Ion Battery Packs
Current – Netbook Computers
• Low Power Consumption ICC < 3 µA Typical – Power Tools
(VCELL(ALL) < VPROTECT)– Portable Equipment and Instrumentation
• Internal Cell Balancing Handles Current – Battery Backup Systems
up to 15 mA
DESCRIPTION
The bq2920x device is a secondary overvoltage protection IC for 2-series cell lithium-ion battery packs that
incorporates a high-accuracy precision overvoltage detection circuit and automatic cell imbalance correction.
The voltage of each cell in a 2-series cell battery pack is compared to an internal reference voltage. If either cell
reaches an overvoltage condition, the bq2920x device starts a timer that provides a delay proportional to the
capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from low to high state.
If enabled, the bq2920x performs automatic cell imbalance correction where the two cells are automatically
corrected for voltage imbalance by loading the cell with the higher charge voltage with a small balancing current.
When the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied
if the imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the
CB_EN pin low, and disabled when CB_EN is pulled to VDD or greater than 2.2 V.
If the internal cell balancing current of up to 15 mA is insufficient, the bq2920x may be configured via external
circuitry to support much higher external cell balancing current.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq29200
bq29209
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAPART NUMBER PACKAGE PACKAGE PACKAGE OVP ORDERING INFORMATION
DESIGNATOR MARKING TAPE AND REEL TAPE AND REEL
(LARGE) (SMALL)
–40°C to BQ29200 QFN-8 DRB 200 4.35 V BQ29200DRBR BQ29209DRBT
+110°C BQ29209 209 4.30 V BQ29209DRBR BQ29209DRBT
THERMAL INFORMATION bq2920x
THERMAL METRIC(1) DRB UNITS
8 PINS
qJA Junction-to-ambient thermal resistance(2) 50.5
qJC(top) Junction-to-case(top) thermal resistance (3) 25.1
qJB Junction-to-board thermal resistance (4) 19.3 °C/W
yJT Junction-to-top characterization parameter (5) 0.7
yJB Junction-to-board characterization parameter (6) 18.9
qJC(bottom) Junction-to-case(bottom) thermal resistance (7) 5.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN FUNCTIONS
PIN NAME NO. DESCRIPTION
CB_EN 6 Cell balance enable
CD 4 Connection to external capacitor for programmable delay time
GND 5 Ground pin
OUT 8 Output
VC1 2 Sense voltage input for bottom cell
VC1_CB 3 Cell balance input for bottom cell
VC2 1 Sense voltage input for top cell
VDD 7 Power supply
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Product Folder Link(s): bq29200 bq29209
5V LDO and
POR
CD
OUT
VDD
GND
VC1
VC2
I
CD(CHG)
=
150 nA
0.1 µF
CB_EN
+
+
–
–
Hys.
CB
Logic
CTRL
VC1_CB
CB2_EN
1_CB EN
bq29200
bq29209
www.ti.com
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS
Over-operating free-air temperature range (unless otherwise noted)(1)
VALUE/UNIT
Supply voltage range, VMAX VDD–GND –0.3 V to 16 V
VC2–GND, VC1–GND –0.3 V to 16 V
Input voltage range, VIN VC2–VC1, CD–GND –0.3 V to 8 V
CB_EN–GND –0.3 V to 16 V
Output voltage range, VOUT OUT–GND –0.3 V to 16 V
Continuous total power dissipation, PTOT See package dissipation rating
Storage temperature range, TSTG –65°C to 150°C
Lead temperature (soldering, 10 s), TSOLDER 300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VDD 4 10 V
Input voltage range VC2–VC1, VC1–GND 0 5 V
Delay time capacitance, td(CD) CCD (See Figure 8.) 0.1 µF
Voltage monitor filter resistance RIN (See Figure 8.) 100 1K Ω
Voltage monitor filter capacitance CIN (See Figure 8.) 0.01 0.1 µF
Supply voltage filter resistance RVD (See Figure 8.) 100 1K Ω
Supply voltage filter capacitance CVD (See Figure 8.) 0.1 µF
Cell balance resistance RCB (See Figure 8 and PROTECTION (OUT) TIMING.) 100 4.7K Ω
Operating ambient temperature range, TA–40 110 °C
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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bq29200
bq29209
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Typical values stated where TA= 25°C and VDD = 7.2 V. Min/Max values stated where TA= –40°C to 110°C and VDD = 4 V
to 10 V (unless otherwise noted).
PARAMETER TEST CONDITION MIN NOM MAX UNIT
Overvoltage bq29209 4.30
VPROTECT detection V
bq29200 4.35
voltage
Overvoltage detection
VHYS 200 300 400 mV
hysteresis
Overvoltage detection
VOA TA= 25°C –10 10 mV
accuracy TA= 0°C to 60°C –0.4 0.4
Overvoltage threshold
VOA_DRIFT mV°/C
temperature drift TA= –40°C to 110°C –0.6 0.6
TA= 0°C to 60°C 6.0 9.0 12.0
Note: Does not include external capacitor variation.
Overvoltage delay time
XDELAY s/µF
scale factor TA= –40°C to 110°C 5.5 9.0 13.5
Note: Does not include external capacitor variation.
Overvoltage delay time
XDELAY_CTM (1) scale factor in Customer 0.08 s/µF
Test Mode
Overvoltage detection
ICD(CHG) 150 nA
charging current
Overvoltage detection
ICD(DSG) 60 µA
discharging current
Overvoltage detection
VCD external capacitor 1.2 V
comparator threshold
ICC Supply current (VC2–VC1) = (VC1–GND) = 3.5 V (See Figure 4.) 3.0 6.0 µA
(VC2–VC1) or (VC1–GND) > VPROTECT,6 8.25 9.5 V
VDD = 10 V, IOH = 0
(VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT,1.75 2.5 V
IOH = –100 µA, TA= 0°C to 60°C
VOUT OUT pin drive voltage (VC2–VC1) and (VC1–GND) < VPROTECT ,200 mV
IOL = 100 µA, TA= 25°C
(VC2–VC1) and (VC1–GND) < VPROTECT ,0 10 mV
IOL = 0 µA, TA= 25°C
VC2 = VC1 = VDD = 4 V, IOL = 100 µA 200 mV
OUT = 1.75 V, (VC2–VC1) or (VC1–GND) = VPROTECT, VDD
IOH High-level output current –100 µA
= VPROTECT to 10 V, TA= 0°C to 60°C
OUT = 0.05 V, (VC2–VC1) or (VC1–GND) < VPROTECT, VDD
IOL Low-level output current 30 85 µA
= VPROTECT to 10 V, TA= 0°C to 60°C
High-level short-circuit OUT = 0 V, (VC2–VC1) = (VC1–GND) = VPROTECT
IOH_ZV –8.0 mA
output current VDD = 4 to 10 V
Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V, –0.2 0.2 µA
TA= 0°C to 60°C (See Figure 4.)
IIN Input current at VCx pins Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V, 2.5 µA
TA= 0°C to 60°C (See Figure 4.)
Cell mismatch detection (VC2–VC1) versus (VC1–GND) and vice-versa when cell
VMM_DET_ON 17 30 45 mV
threshold for turning ON balancing is enabled. VC2 = VDD = 7.6 V
Cell mismatch detection Delta between (VC2–VC1) and (VC1–GND) when cell
VMM_DET_OFF –9 0 9 mV
threshold for turning OFF balancing is disabled. VC2 = VDD = 7.6 V
Cell balance enable ON
VCB_EN_ON Active LOW pin at CB_EN 1 V
threshold
Cell balance enable OFF
VCB_EN_OFF Active HIGH at CB_EN 2.2 V
threshold
Cell balance enable ON
ICB_EN CB_EN = GND (See Figure 5.) 0.2 µA
input current
(1) Specified by design. Not 100% tested in production.
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Product Folder Link(s): bq29200 bq29209
VC1
CB1
CB
I
R
=
(VC2 VC1)
CB2 + )
VD
CB
I(R R
-
=
Temperature (°C)
ICD Charge Current (nA)
ICD CHARGE CURRENT
vs
TEMPERATURE
-40 -20 0 20 40 60 80 100
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
G001
Temperature (°C)
ICD Discharge Current (µA)
ICD DISCHARGE CURRENT
vs
TEMPERATURE
40
45
50
55
60
65
70
75
80
-40 -20 0 20 40 60 80 100
G002
bq29200
bq29209
www.ti.com
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
RECOMMENDED CELL BALANCING CONFIGURATIONS
Typical values stated where TA= 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Min/Max values stated where TA= –40°C to
110°C, VDD = 4 V to 10 V, and (VC2–VC1), (VC1–GND) = 3.0 V to 4.2 V. All values assume recommended supply voltage
filter resistance RVD of 100 Ωand 5% accurate or better cell balance resistor RCB.
PARAMETER TEST CONDITION MIN NOM MAX UNIT
RCB = 4700 Ω0.5 0.75 1
RCB = 2200 Ω1 1.5 2
RCB = 910 Ω234
ICB Cell balance input current RCB = 560 Ω3 4.5 6 mA
RCB = 360 Ω3.5 6 8.5
RCB = 240 Ω4 7.5 11
RCB = 120 Ω5 10 15
The cell balancing current may be calculated as follows:
Cell 1 (VC1–GND):
Cell 2 (VC2–VC1):
TYPICAL CHARACTERISTICS
Figure 2. ICD Charge Current Figure 3. ICD Discharge Current
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): bq29200 bq29209
IIN
IIN
ICC
OUT
VDD
CB_EN
GND
1
2
4
3
CD
VC2
VC1
VC1_CB
8
7
5
6
VCELL
VCELL±VCB
ICB
ICB
OUT
VDD
CB_EN
GND
1
2
4
3
CD
VC2
VC1
VC1_CB
8
7
5
6ICB_EN
d
CD
DELAY
t
C
X
=
CD DELAY
d
t C X´=
bq29200
bq29209
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
TEST CONDITIONS
Figure 4. ICC, IIN Measurement
Figure 5. ICB Measurement
PROTECTION (OUT) TIMING
Sizing the external capacitor is based on the desired delay time as follows:
Where tdis the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds
per microFarad. XDELAY is nominally 9.0 s/µF. For example, if a nominal delay of 3 seconds is desired, use a CCD
capacitor that is 3 s / 9.0 s/µF = 0.33 µF.
The delay time is calculated as follows:
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
Cell Voltage > VPROTECT
When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay
begins to count to td. If the input remains above VPROTECT for the duration of td, the bq2920x output changes from
a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V when
IOH = 0 mA.
The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V
typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.
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OUT
Cell Voltage
VPROTECT
LH
td
VC2
-
VC
1,
VC1 GND
-
V
PROTECT
-
HYS
V
bq29200
bq29209
www.ti.com
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
Figure 6. Timing for Overvoltage Sensing
CELL CONNECTION SEQUENCE
NOTE
Before connecting the cells, propagate the overvoltage delay timing capacitor, CCD.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
CELL BALANCE ENABLE CONTROL
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower State of Charge (SOC) levels.
CELL IMBALANCE AUTO-DETECTION (VIA CELL VOLTAGE)
The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The
recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3.0 V and
4.2 V. Below VDD = 6.0 V, it is recommended to pull CB_EN high to disable the cell balancing function.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): bq29200 bq29209
VC2
7.6 V
6 V
100%
79%
8.4 V
111%
VC2
VC1
VC1_CB
CD GND
OUT
VDD
CB_EN
3
4
7
6
5
CVD
8
2
1
CCD
CIN
CIN
RIN
RIN
RVD
CELL2
CELL1
RCB
VC2
VC1
VC1_CB
CD GND
OUT
VDD
CB_EN3
4
7
6
5
CVD
8
2
1
CCD
CIN
CIN
RIN
RIN
RVD
CELL2
CELL1
Q2
RCB_EXT
RCLAMP
Q1
bq29200
bq29209
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
Figure 7. VMM_DET_ON and VMM_DET_OFF Threshold
BATTERY CONNECTION
Figure 8 shows the configuration for the 2-series cell battery connection.
Figure 8. 2-Series Cell Configuration
EXTERNAL CELL BALANCING
Higher cell balancing currents can be supported by means of a simple external network, as shown in Figure 9.
Figure 9. External Cell Balancing Configuration
RCLAMP ensures that both Q1 and Q2 remain off when balancing is disabled, and should be sized above 2 kΩto
prevent excessive internal device current when the balancing network is activated. RCB_EXT determines the value
of the balancing current, and is dependent on the voltage of the balanced cell, as follows:
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Product Folder Link(s): bq29200 bq29209
VCELL
CB_EXT
Ibal R
=
Test Mode Entered
15 V
> 10 ms
VDD
VC2
4 V
4.5 V
VPROTECT
V V
PROTECT – HYST
<<td
(VC2–VC1)
or
(VC1–GND)
OUT
bq29200
bq29209
www.ti.com
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
CUSTOMER TEST MODE
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of
approximately 0.08, thereby reducing the delay time during an overvoltage condition.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into CTM. Also, avoid exceeding Absolute Maximum Voltages for the individual cell
voltages (VC1–GND) and (VC2–VC1). Stressing the pins beyond the rated limits may
cause permanent damage to the device.
To exit CTM, power off the device and then power it back on.
Figure 10. Voltage Test Limits
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): bq29200 bq29209
bq29200
bq29209
SLUSA52A –SEPTEMBER 2010–REVISED NOVEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (June 2010) to Revision A Page
• Changed values in XDELAY and XDELAY_CTM electrical characteristics ..................................................................................... 4
• Changed specifications for VOUT ........................................................................................................................................... 4
• Changed test conditions for VOUT, IOH, and IOL ..................................................................................................................... 4
• Added VMM_DET_ON: VC2 = VDD = 7.6 V ............................................................................................................................... 4
• Changed VMM_DET_OFF: From VDD – VC2 – 7.6 V to VC2 = VDD = 7.6 V ............................................................................ 4
• Changed content in Recommended Cell Balancing Configurations section ........................................................................ 5
• Added ICD Charge Current figure .......................................................................................................................................... 5
• Added ICD Discharge Current figure ...................................................................................................................................... 5
• Changed XDELAY from nominally 8.0 s/µF to nominally 9.0 s/µF ........................................................................................... 6
• Changed Timing for Overvoltage Sensing figure .................................................................................................................. 6
• Added Cell Imbalance Auto-Detection (Via Cell Voltage) section ........................................................................................ 7
• Added External Cell Balancing section ................................................................................................................................. 8
• Changed VDD value in Customer Test Mode from 8.5 V to 9.5 V ....................................................................................... 9
• Changed the Voltage Test Limits figure ............................................................................................................................... 9
10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 6-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ29200DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29200DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29209DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ29209DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ29200DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29200DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29209DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ29209DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29200DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29200DRBT SON DRB 8 250 210.0 185.0 35.0
BQ29209DRBR SON DRB 8 3000 367.0 367.0 35.0
BQ29209DRBT SON DRB 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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