eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2565 REV B 8/10/99
Bus Controller, Remote Terminal and BUS Monitor
Features
Second Source Compatible to the BUS-65600
RTU implements all dual redundant mode codes
Selective mode code illegalization available
16 bit microprocessor compatibility
BC checks status word for correct address and set flags
RTU illegal mode codes externally selectable
16 bit µProcessor compatibility
DMA handshaking for subsystem message transfers
MIL-PRF-38534 compliant circuits available
DESC SMD #5962–88585 Pending
Packaging – Hermetic Metal
78 Pin, 2.1" x 1.87" x .25" Plug-In type package
82 Lead, 2.2" x 1.61" x .18" Flat package
General Description
The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and
Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions
required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's
ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic
IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus
Monitor (BM).
The CT2565 is compatible with most µprocessors. It provides a 16 bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing as well as DMA and control lines are provided internally. Subsystem overhead
associated with message transfers is therefore minimized. Interface control lines are common for
both BC and RT operation.
The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode
codes. In addition, any mode code may (optional) be illegalized through the use of an external
(200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU
operation. Error detection includes: response time-out, inter message gaps, sync, parity,
Manchester, word count and bit count. The CT2565 complies with all the requirements of
MIL-STD-1553.
The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the
full military temperature range of -55°C to +125°C.
CT2565
FOR MIL-STD-1553B
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CIRCUIT TECHNOLOGY
www.aeroflex.com
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
BUSGRNT
BUSREQ
SOM
BUSACK
INCMD
EOM
OE
CS
WR
CHA/CHB
BCSTART
MSGERR
LOOPERR
LWORD
STATERR
STATEN
HSFAIL
NBGRNT
BITEN
NODT
ADRINC
BSCTRCV
TIMEOUT
I/O LOGIC
BUFFERS
BUFENA
I/O0 - I/O16
LMC
WC0-WC4
ILLCMD
T/R
SERREQ
DBACCEPT
SSBUSY
SSERR
SSFLAG
DATA
BUFFERS
REMOTE
TERMINAL
LOGIC
BUS
CONTROLLER
LOGIC
DATA BUS
STATUS INPUTS
MODE CODE CONTROL
CH B
CONTROL
CH A
ENCODE/
DECODE
CH B
ENCODE/
DECODE
TXDATA A
TXINH A
RXDATA A
RXDATA A
TXDATA A
RTADDR PARITY
CHECKER
TXDATA B
TXINH B
RXDATA B
RXDATA B
TXDATA B
RTADDR
RTADDR
RTADR2
RTADR0
RTADR4
RTADR3
RTADR1
RTADRP
CONTROL BUS
Figure 1 – CT2565 Block Diagram
12MHz
MT
RT/BC
TESTOUT
TESTIN
CH A
CONTROL
I/O BUS
ENR/W
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
GENERAL
The CT2565 uses a custom CMOS ASIC for
protocol logic and I/O buffering to provide low
power dissipation in its small package.
The CT2565 performs a continuous on-line
Built-In-Test (BIT); in this test the last transmitted
word of each message transfer is wrapped
around through the active receiver channel and
verified against the captured encoded word. A
user-defined loop test under subsystem control
can also be implemented. Numerous error flags
are provided to the subsystem including
message error, status error, response time out
and loop test error.
An external 12 MHz, TTL clock connected to Pin
39 is required.
Where appropriate, references to signal names
and their associated pin numbers for the 78 pin
DDIP package are made throughout this
document. For flatpack model pin numbers, refer
to Table 10.
BC/RTU/MT Initialization
The CT2565 provides BC, RTU, and MT
operating modes. The operating mode if
dynamically selectable through two static control
inputs as listed in Table 2. It is recommended
that a master RESET signal be issued (80ns min)
prior to mode selection to clear the internal
registers.
MIL-STD-1553 Word Types
Figure 2 illustrates the three MIL-STD-1553 word
types: Command, Data, and Status.
Values at nominal Power Supply Voltages unless otherwise specified
PARAMETER VALUE UNITS
Logic
VIH 2.0 min V
VIL 0.8 max V
VOH 3.7 min V
VOL 0.4 max V
IIH ±100 max µA
IIL -0.4 max mA
IOL *±1.2 max mA
IOH *±0.4 max mA
CIN (f = 1MHz) 20 max pF
COUT (f = 1MHz) 20 max pF
Power Supply
+5VDC
Tolerances ±10 max %
Supply Current 50 typ (70 max) mA
Internal Decoupling 1.5 typ µF
Temperature Range
Operating (Case) 55 to +125 °C
Storage 65 to +150 °C
Physical Characteristics
Size
78 pin DDIP 1.9 x 2.10 x 0.25
(48.30 x 53.34 x 6.35) in
(mm)
82 pin flatpack 1.6 x 2.19 x 0.15
(40.64 x 55.63 x 3.81) in
(mm)
Weight 1.7 (48) oz (g)
* IOL and IOH parameters are indicated for all logic outputs except Data Bus (DB0 – DB15) which are ±5mA for
both parameters.
Table 1 – CT2565 Specifications
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
DMA-Type Handshake
All BC and RT word transfers are preceded by a
request-grant-acknowledge format DMA
handshake procedure. Timing information is
provided in BC, RTU and MT sections.
In MT mode, the 1553 transmission is transferred
along with an identification Word using a single
DMA handshake containing two memory-write
operations. The DMA format requires that the
subsystem provide a bus grant (BUSGRNT pin
45) low within a timeout period. Note that
BUSGRNT should be set to logic "1" before
another bus request (BUSREQ) is issued.
Memory Read/Write
With the single exception of an RT command
word transfer, all subsystem transfers take the
form of a static memory read or write. A low
pulse on both the chip select (CS) and output
enable (OE) or a low pulse on CS and write
enable (WE) (pins 17, 18 and 44 respectively)
indicates data is valid on the parallel data bus for
the duration of the pulse. The rising edge of CS
triggers an address increment (ADRINC pin) low
output pulse used to increment the subsystem
memory address for successive transfers.
BC OPERATION
In the BC mode, the CT2565 initiates all
MIL-STD-1553 data and control message
transfers. Figure 3 details specific message
transfer flow and Table 3 lists subsystem memory
allocation. The subsystem, or host processor,
must provide a CT2565 protocol Control Word
(See Figure 4) and MIL-STD-1553 command and
data words. The CT2565 will transfer the RTU
status response and provide message transfer
validation during an active transfer. All parallel
word transfers occur in the form of a DMA
(request-grant-acknowledge) handshake with
memory read or operation as shown in Figures 5
and 6.
Command Transfer
In the BC mode pulse BCSTART (pin 41) low.
Following the pulse, the CT2565 will initiate a
DMA handshake and memory read for; the
control, word, command word(s) and up to 32
data words. No handshake timeout is enforced in
the BC mode (CT2565) remains idle during
BUSREQ to BUSGRNT), however 1553 protocol
must be maintained.
Note that commands are named from the BC's
point-of-view (for example, a TRANSMIT CMD
indicates the addressed RTU must transmit data).
BIT TIMES 12345678910 11 12 13 14 15 16 17 18 19 20
COMMAND WD 5 5 5 1
SYNC REMOTE TERMINAL T/R SUBADDRESS DATA WORD P
ADDRESS MODE COUNT/MODE CODE
DATA WORD 16 1
SYNC DATA P
STATUS WORD 5 111 3 111111
SYNC REMOTE TERMINAL RESERVED
ADDRESS PARITY
TERMINAL FLAG
DYNAMIC BUS
CONTROL
ACCEPTANCEMESSAGE ERROR
INSTRUMENTATION SUBSYSTEMFLAG
SERVICE REQUEST BUSY
Note: T/R – Transmit/Receive, P – Parity BROADCAST
COMMAND RCVD
Figure 2 – MIL-STD-1553 Word Types
MODE RT/BC
(PIN 1)
MT
(PIN 2)
BC 0 1
RT 1 1
MT 0 0
Table 2 – Operating Modes
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Loop Test
Upon receipt from the subsystem, the last word
to be transmitted within a given message
transfer (command or Data word) is stored in a
CT2565 internal register. As this word is
transmitted to the 1553 bus, it is looped back
through the active receiver channel for auto-BC,
Short Loop verification. A LOOPERR (.5us typ)
low pulse indicates a mismatch between the
stored and looped word. The CT2565 also
initiates a handshake with a memory write to the
subsystem for user-defined, "long loop"
(subsystem, CT2565, subsystem) verification.
Note that both short and long loop testing are
initiated for all transfers (on the last word
transmitted to 1553). Subsystems response to
use Long Loop Test is to compare the loaded
word to what was looped back into memory.
RECEIVE TRANSMIT
Control Word Control Word
Receive Command Transmit Command
Data 1 Looped Command Word
RTU Status
Data 1
Last Data
Looped Data Word
RTU Status Last Data
Table 3 – BC Memory Allocation
15 8 0
NOT USED
BUS CHANNEL A/B
NOT USED
MASK BROADCAST BIT
NOT USED
MODE CODE
BROADCAST
RT-RT
BIT DEFINITION
BUS CHANNEL A/B When logic "1" transmits over 1553 Bus A.
When logic "0" transmits over 1553 Bus B
(See note)
MASK BROADCAST BIT Always set to "0"
MODE CODE Command Word count field signifies mode code type
BROADCAST Multiple RTU’s addressed, no status word expected
RT-RT When set, RTU(b) transmits, RTU(a) receives. Both RTU Status Words
are validated and sent to subsystem.
Note: Messages-transmission (routing) status pin (pin 16, Chan A/B) becomes active after loading the control word and command word
respectively. The signal is cleared by RESET or EOM low.
Figure 4 – BC Control Word
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
DATA WORDS
RX
CMD
LONG LOOP
FROM
RT
STATUS
HANDSHAKE
(DMA)
MEMORY READ
DATA WORD
FROM SSIU
YES
DATA TO 1553
YES
NO
SHORT LOOP
LONG LOOP
INCREMENT MEM ADDR
NO NO
MEMORY READ
INCREMENT MEM ADDR
NO
RT
STATUS
FROM
MORE
DATA
YES
YES
YES
YESNO
MEMORY READ
MEMORY WRITE MEMORY WRITE
MSGERR
TIMEOUT
STATERR
TO SSIU
STATUS WORD
(DMA)
HANDSHAKE
DATA WORD
TO SSIU
END OF MESSAGE PULSE
STOP
CMD WORD TO 1553
FROM SSIU
CONTROL WORD
INCREMENT MEM ADDR
OUTPUT
FROM SSIU
COMMAND WORD
HANDSHAKE
(DMA)
HANDSHAKE
(DMA)
CMD WORD TO 1553
START BC OPERATION
CONTROL & COMMAND WORDS
NO
A
A
TO SSIU
STATUS WORD
MEMORY WRITE
STATERR
SHORT LOOP
MORE
DATA
FROM
STATUS
RT
MSGERR
TIMEOUT
HANDSHAKE
(DMA)
Figure 3 – BC Message Transfer Flow
Notes:
(1) Steps marked with " ___" indicates operation is transparent to user.
(2) Steps marked with " ___" indicates user interaction required.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
RTU Response
The addressed RTU(s) must respond (to
non-broadcast commands) within a timeout
period as shown in Figures 7, 8, and 9. Figures
10 and 11 illustrate the BC Mode Code Timing.
Status and data words received from the 1553
port are transferred to the subsystem via a
handshake and memory write operation for each
(See Message Length Checking).
BC Status/Error Handling
Message transfer errors are indicated using the
TIMEOUT, MSGERR, LOOPERR and STATERR
BC status outputs (pins 4, 30, 46 and 68
respectively). Additional error detection
methods include user evaluation of status, data
and (long) loop words and/or use of the 1553B
dual redundant mode codes. Note that certain
error conditions not reflected in the current
Status Word (SW) can occur; Broadcast CMD
RT-status and post RT status response may be
accessed via the Transmit Status Word mode
command.
Transmit Bit Word. Additional status informa
tion is generated by an RTU (CT2565 for each
transfer in the form of a BIT word). This word
may be accessed by the BC using the
TRANSMIT B-I-T WORD mode command. See
RTU Error Handling and Mode Code sections).
Message Length Checking. The BC stores the
command word, word-count field in an internal
register. By decrementing this register following
each data word transfer (See BC Memory
Read/Write Timing), the BC can detect an
incorrect message length.
For a description of the possible BC error,
indicators occurring during each stage of
message transfer read from left to right in
Table4. For a description of the possible causes
of errors within a transfer, read from right to left.
TRANSFER/CONDITION DESCRIPTION ERROR SIGNAL PIN
CONTROL/COMMAND WORD 1
Handshake Failure
Memory read by BC subsystem.
No response to Bus Request within timeout
period.
BC waits for Grant
(no 1553 timing error) -
LOOPED WORD
Short Loop Failure
Long Loop Failure
Looped back through receiver.
Received Word last xmitted word.
DMA/Write looped word to subsystem.
LOOPERR
User Defined
46
-
RT-RT Status-RT1, data, status-RT2 response
to follow receive, transmit, commands.
(See definitions in
STATUS/DATA WORD
below)
-
STATUS WORD
No Status Received within 15.5µS NODT timeout TIMEOUT
EOM
4
57
RT Address Mismatch Command RTU Address Status Word
RTU Address
STATERR 68
Error Flag(s) Set Status Word Response from RT:
Error Condition
STATERR 68
Broadcast Received bit Set Response to Transmit Status Word mode
command may allow this, all others ERROR.
Broadcast Mask not set
(See BC Control Word)
STATERR
68
DATA WORD
Handshake Failure
Transmit Command
Receive Command
No subsystem response to Bus Request.
Data lost: Word Count fails.
1553 transmission gap.
BC waits for Grant.
MSGERR
Status Word response:
STATERR
30
68
Data Received from RTU
Less than word count
Greater than word count
Transmit Command (RTU response)
More data received than requested.
MSGERR and EOM
MSGERR and EOM
4
30
Data after Status Set
(all extra words)
Transmit Command: data words received
after status to subsystem.
DMA/memory write
(for each) -
FORMAT ERROR -MSGERR 30
Notes:
(1) LOOPERR is a .5µS pulse which occurs near DMA handshake for loop back word.
(2) TIMEOUT is a 40/160nS pulse which occurs 19.5µS ±0.5µS after the mid-bit parity of the last word onto the bus.
(3) STATERR is a 120/166nS pulse which occurs during the status word DMA handshake.
(4) MSGRR is a 40/160nS pulse which occurs approximately 100nS before INCMD goes high. It is triggered by NODT going inactive (i.e.,
low word count).
Table 4 – BC Error Handling
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
HSFAIL (5)
BUSACK (59)
BUSGRNT (45)
BUSREQ (19)
t4
t3
t2
t1
Figure 5 – BC Handshake Timing
SYMBOL DESCRIPTION MIN MAX UNITS
t1 BUSREQ pulse width 867 1667 ns
t2 BUSREQ to BUSGRNT delay 0 800 ns
t3 BUSGRNT pulse width 166 -ns
t4 BUSGRNT to BUSACK delay 50 200 ns
TRI-STATE
MEMORY READ
ADRINC (49)
MEMORY WRITE
DATA VALIDDATA VALID
D0 - D15
t4
t3
t2
t5
t6t10
t9
t8
t9
t7
t1
t5
t6
CS (17)
BUSACK (59)
WR (44)
OE (18)
CYCLE SYMBOL DESCRIPTION MIN MAX UNITS
Read t1 BUSACK to OE delay -25 ns
t2 OE to CS delay -25 ns
t3 Data setup time -250 ns
t4 CS (OE) pulse width 650 680 ns
t5 CS to ADRINC delay -25 ns
t6 ADRINC pulse width 80 166 ns
Write t7 BUSACK to WR delay -378 ns
t8 WR to CS delay -25 ns
t9 CS and WR pulse width 150 175 ns
t10 Data valid setup 100 -ns
Figure 6 – BC Read/Write Timing
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OUTPUTS
EOM (57)
STATERR (68)
LWORD (29)
INCMD (9)
(CS, OE, ADRINC)
D0 - D15
MEM-READ
(REQ, GRNT, ACK)
HANDSHAKE
BC START (41)
1553 BUS
NODT (71)
(CS, WR, ADRINC)
MEM-WRITE
STAT RTAPCMD RTAP
DATA
P
CHA
/CHB LATCHED
200ns
5.5±0.5µs
7.5±0.5µs
44±0.5µs
5.5µs TYP
5.5±0.5µs
7.5±0.5µs
24±0.5µs43.5±0.5µs
10.75±0.75µs
200
500 ns
166
332 ns
120
166 ns
330
700 ns
50
200 ns
2µs
166µs
4µs
LOOP STATCMDCLT STATDATA
Notes for Figures 7-9
T/R and HSFAIL are static at logic "1" in BC mode. All timing is typical unless otherwise noted.
Figure 7 – BC Receive One Word Command Timing
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OUTPUTS
EOM (57)
STATERR (68)
LWORD (29)
INCMD (9)
(CS, OE, ADRINC)
D0 - D15
MEM-READ
(REQ, GRNT, ACK)
HANDSHAKE
BC START (41)
1553 BUS
NODT (71)
(CS, WR, ADRINC)
MEM-WRITE
CMD RTAPSTAT RTAP
DATA
P
CHA
/CHB LATCHED
200ns
(a)
7.5±0.5µs (B) (B)
5±0.5µs
20±0.5µs30±0.5µs
10.75±0.75µs
200
500 ns
40
160 ns
120
166 ns
330
700 ns
50
200 ns
166µs
STATCMDCLT DATA
LOOP
150ns (NOM)
100ns
MESS ERR.
EX: LOW WD COUNT
(a) 5.5±0.5µs
20±0.5µs
Figure 8 – BC Transmit One Word Command Timing
EOM (57)
STATERR (68)
LWORD (29)
INCMD (9)
(CS, OE, ADRINC)
D0 - D15
MEM-READ
(REQ, GRNT, ACK)
HANDSHAKE
BC START (41)
1553 BUS
NODT (71)
(CS, WR, ADRINC)
MEM-WRITE
CMD
RTARXPRTBTXP
7.5±0.5µs
120
166 ns
330
700 ns
2µs
DATA
CMD
CTL STAT
LOOP
STAT
RTBPDATA P
STAT
RTAP
STATCMD
7.5±0.5µs7.5±0.5µs
5.5±0.5µs
150ns (NOM)
5.5±0.5µs
200
500 ns
5±0.5µs
5.5±0.5µs
Figure 9 – BC RT-RT Transfer Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
CMD
RTAP
STAT
RTAPDATA LCMD P
CTL CMD LOOP STAT LCMD
EOM (57)
900ns
5.0±0.5µs
INCMD (9)
LWORD (29)
D0 - D15
1553 BUS
BUSREQ (19)
ADRINC (49)
80/166ns
70/80µs
400/500ns
Figure 10 – BC Mode Code Transmit Last Command (10010) Timing
CMD
RTAP
CTL CMD LOOP STAT
EOM (57)
900ns
INCMD (9)
LWORD (29)
D0 - D15
1553 BUS
BUSREQ (19)
ADRINC (49)
80/166ns
50/80µsec
400/500ns
Figure 11 – BC Mode Code Transmit Status Word (00010) Timing
STAT
RTAP
40/60µsec
Notes:
All timing is typical unless otherwise noted.
RTU Operation
Each RTU is assigned a unique address on the
1553 bus. It processes commands issued by the
BC to its address or through Broadcast
commands.
Upon receipt of a valid command in the RTU
mode, the CT2565 will attempt to (1) transfer
1553 data received to the subsystem, (2) read
data from the subsystem for transmission on the
1553 bus, (3) transmit status information to 1553,
or (4) set status conditions. All data block
transfers are accompanied by a 1553 Status
Word. Figure 12 details a RTU single message
transfer.
RTU Address
RTU Address pins 33-34 and 72-74 and Address
Parity pin (odd parity) should be programmed to
a unique RTU (1553) address. These inputs
have internal pull-ups and will default a high state
if left unconnected. The CT2565 will not respond
if odd parity is compromised (See Error
Handling).
RTU Initialization
Initialize the CT2565 as an RTU per Table 2.
Upon receipt of valid command word from the
serial bus (RTU addressed or broadcast CMD),
the CT2565 will pulse NBGRNT (New Bus Grant)
pin 42 low.
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HANDSHAKE
(DMA)
INCREMENT MEM ADDR
OUTPUT
STOP
RT-RT
STOP
STOP
STOP
STOP
STOP
END OF MESSAGE
PULSED
ILLEGALIZED
CMD
?
MORE
DATA?
SSU
BUSY
RX
CMD
NO
A
YES
DATA FROM 1553
WORD VALIDATION
STATEN PULSED
STATUS TO 1553
STATUS TO 1553
WORD VALIDATION
STATUS TO 1553
HANDSHAKE
(DMA)
HANDSHAKE
(DMA)
DATA TO 1553
STATUS TO 1553
SHORT LOOP
SHORT LOOP
HS FAIL
INCREMENT MEM ADDR
OUTPUT
MORE
DATA?
HS FAIL
STATEN PULSED
YES
YES
YES
YES
YES
DATA
EXPECTED
NO
NO
NO
NO
NO
YES
YES
HS FAIL
SOM PULSED
RT
ADDR
WORD COUNT LATCHED
T/R BIT LATCHED
MODE CODE PULSE
(MODE CODE ONLY)
RT-RT
TXFER
STATEN PULSED
MEMORY READ
DATA WORD
FROM SSIU
MEMORY WRITE
DATA WORD
TO SSIU
NO
A
?
CMD WORD RECEIVED
FROM 1553
COMMAND WORD
Notes:
(1) Steps marked with " ___" indicates operation is transparent to user.
(2) Steps marked with " ___" indicates user interaction required.
DATA WORD(S)
Figure 12 – RTU Single Message Transfer Flow Diagram
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Mode Code Illegalization (Optional)
The word count and TX/RX pins will be latched
800ns (typ) after the falling edge of NBGRNT
(See Figure 13, RTU Command Word Handling).
Table 5 lists the CT2565 pins associated with
mode code illegalization. If the current command
is a mode code, LMC (pin 55) will go high. Mode
codes can be illegalized, using an external PROM
(<200ns access time recommended), by setting
ILLCMD low after the NBGRNT flag. This will set
the message error (status word) and illegal Mode
Code (BIT word) bits followed by transmission of
the status word. Using the method, mode
commands can be "auto-screened" without
interrupting subsystem operation. For a complete
list of mode codes, refer to Table 8.
Table 5 – Mode Code Illegalization
PIN # SYMBOL DESCRIPTION
51 WC0 Word Count LSB
12 WC1 Word Count 1
52 WC2 Word Count 2
13 WC3 Word Count 3
53 WC4 Word Count MSB
15 T/RTX/RX
Note: A word count field of all 0’s indicates 32 data words; all 1’s
= 31 words.
SYM DESCRIPTION MIN TYP MAX UNITS
Illegalize t1 NBGRNT pulse width 151 -181 ns
t2 NBGRNT to LMC delay 500 -667 ns
t3 LMC to WC-T/R latch -200 -ns
t4 LMC to ILLCMD latch - - 333 ns
Legal t5 NBGRNT to INCMD delay -1.0 1.5 µs
t6 BUSACK to SOM delay -166 -ns
t7 SOM pulse width -166 -ns
t8 CMD VALID setup 60 -100 ns
Status Inputs t9 NBGRNT low to status latch - - 3µs
Note: Memory read/write signals CS, OE, and ADRINC remain static at logic "1".
Figure 13 – RTU Command Word Handling/Status Inputs
NBGRNT (42)
STATUS INPUTS
BUSACK (59)
LMC (55)
BUSREQ (19)
DBACCEPT
,
SSFLAG
,
SVCREQ
,
SSER
and
SSBUSY
INPUTS LATCHED
CMD VALID
LATCHED UNTIL NEXT VALID COMMAND WORD RECEIVED
VALID UNTIL NEXT VALID COMMAND WORD RECEIVED
t
1
t
2
t
3
t
5
t
6
t
7
t
8
t
9
t
4
D0 - D15
INCMD (9)
SOM (78)
ILLCMD (48)
WC0-4 T/R (15)
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TRANSFER/CONDITION DESCRIPTION ERROR SIGNAL PIN
COMMAND WORD
Invalid Word Format
Invalid Command (format error) Sync, bit count invalid.
Operation disagreement (e.g. Broadcast and
Transmit bits set)
None; input ignored
MSGERR (also; SW bit)
-
30
Handshake Failure BUSREQ to BUSGRNT timeout HSFAIL, suppress
SOM, continue
5
78
Illegal Mode Command Subsystem set ILLCMD (pin 48). SW message error bit set
RT-RT Transfer
Response Timeout
Address mismatch
(Transmit) Command to Status Word time.
Transmit Command Address Status Word
address.
TIMEOUT (transmitting RT)
(also; MSGERR bit)
MSGERR (Receiving RT)
(also; MSGERR bit)
4
30
DATA WORD
Handshake Failure
Transmit Command
Receive Command
Number Transmitted (2)
BUSREQ to BUSGRNT timeout
(Continue)
(Message terminated)
Low data word-count received.
High data word count
HSFAIL (1)
Continue message transfer
INCMD high, EOM
MSGERR (3) (SW bit)
MSGERR after validation
(no transfer) SW and BIT-
Word also set.
5
9,57
30
30
LOOP WORD
Short Loop
Long Loop
Looped back through receiver.
Received word to last xmitted 1553 word.
(BC only)
LOOPER (also sets Ter-
Flag bit). 46
Notes:
(1) The HSFAIL low output is reset (high) at the start of the next message transfer (NBGRNT low).
(2) The subsystem can use the status input pins (SW) to report incorrect word count type errors.
(3) MSGERR set 7.5µS after last mid parity bit of last data word.
Table 6 – RTU Error Handling
RTU Commands
A command word transfer will be initiated by the
CT2565 after the rising edge of NBGRNT (See
Figure14). In order to allow the command word to be
stored in user-defined memory space (separate from
data), no memory write operation (CS, WR, ADRINC
outputs) will be initiated following the usual DMA-type
handshake; a Start Of Message (pin 78: SOM low)
pulse indicates that the CMD word is currently valid on
the data bus. Note that commands are named from
the BC point-of-view (i.e., a TRANSMIT CMD dictates
that the addressed RTU must transmit data).
Transmit CMD (RT-BC)
If the subsystem is available (pin 47: SSBUSY high):
following transmission of the status word, the CT2565
will initiate a handshake/memory-read respectively for
the total number of (data) words defined by the
Command Word-word count field. Figure 15 shows
the RTU Read/Write Timing. Note that possible data
word transfer and short-loop test errors will be
reflected in the following status word/bit word. A low
on the SSBUSY input will set the corresponding status
word flag, and no data transfer will be requested
(BUSREQ low) following transmission of the status
word.
Receive CMD (BC-RT). A DMA handshake will be
initiated for each word received over the 1553 data bus
(See Figure 16). If successful, the respective
handshake will be followed by a corresponding
memory write. Transfer errors such as handshake
timeout or SS BUSY will not terminate transfer
attempts for the remaining data words, error flagging
or status word transmission.
RTU(b)-RTU(a) (Transmit/Receive). An RT-RT
transfer will appear to both RTU subsystems as a
standard transmit or receive command except: (1)
transmission of the data block will not be continuous
with that of the receive CMD, and, (2) upon detection
of a command-sync field following the receive CMD,
RTU(a) will recognize an RT-RT transfer and store the
transmit CMD-address field for comparison with the
address field of the following (RTU(b) status) word
(See Figures 17 and 18). If a mismatch is detected,
RTU(a) will issue a message error. The transmitting
RTU will respond as in an RT-BC Transmit CMD.
RTU Status/Error Handling
Message transfer errors are indicated using the
TIMEOUT, HSFAIL, MSGERR and LOOPERR
RTU-status outputs (pins 4, 5, 30 and 46 respectively).
Additional error detection mechanisms available
include status input manipulation (below) and
evaluation of the status and BIT words (See BIT
Word).
Table 6 describes error handling mechanisms related
to each stage in a message transfer (reading left to
right) as well as noting errors associated with a
specific CT2565 status output (reading right to left).
Short Loop Test. The last word to be transmitted in a
given message transfer (Status word, BIT word or
Data word) is stored in a CT2565 internal register. As
this word is transmitted to the 1553 bus, it is "looped
back" through the active receiver channel for
auto-RTU, "SHORTLOOP" verification. A LOOPERR
low pulse indicates a mismatch between the stored
and looped words. Note that short loop testing is
initiated for all RTU transfers except a Broadcast
transfer.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
HSFAIL (5)
BUSACK (59)
BUSGRNT (45)
BUSREQ (19)
t3
t2
t1
SYMBOL DESCRIPTION MIN MAX UNITS
t1 BUSREQ pulse width 667 -ns
t2 BUSGRNT delay
CMD WORD
TX DATA WORD
RX DATA
0
0
0
1.5
15.5
2.33
µs
µs
µs
t3 BUSGRNT to BUSACK delay 40 166 ns
Note: HSFAIL will go low following a BUSREQ to BUSGRNT timeout.
Figure 14 – RTU Handshake Timing
Figure 15 – RTU Read/Write Timing
ADRINC (49)
OE (18)
CS (17)
D0 - D15
BUSACK (59)
WR (44)
VALID VALID
t
7
t
4
t
8
t
9
t
10
t
5
t
5
t
6
t
3
t
2
t
1
t
4
MEMORY WRITE MEMORY READ
CYCLE SYMBOL DESCRIPTION MIN TYP MAX UNITS
Read t1 BUSACK to OE delay - - 25 ns
t2 OE to CS delay - - 25 ns
t3 Data setup time - - 250 ns
t4 CS, OE and BUSACK pulse width -500 -ns
t5 CS to ADRINC delay - - 25 ns
t6 ADRINC pulse width 80 -166 ns
Write t7 BUSACK to CS delay - - 225 ns
t8 WR to CS delay - - 25 ns
t9 CS and WR pulse width 150 166 180 ns
t10 Data valid setup prior to leading edge of WR 60 -100 ns
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Figure 16 – RT Receive Command Timing
EOM (57)
NRGRNT (42)
INCMD (9)
D0 - D15
(REQ, GRNT, ACK)
HANDSHAKE
BCSTRCV (75)
1553 BUS
NODT (71)
(CS, WR, ADRINC)
MEM-WRITE
STAT RTAP
CMD
RTARCV P
DATA (16 BITS)
P
3.9µs
10.75±0.75µs
Note: All timing is typical unless otherwise noted.
SOM (78)
STATEN (3)/
BUFFENA (58)
CHA/CHB (16)
WC0-4 T/R (15)
REF
7.5±0.5µs
5.5±0.5µs 4.5±0.5µs
7.5±0.5µs
3.4±0.5µs
0.5µs
1.5µs
3.2±0.5µs
5.5±0.5µs
4µs
400ns
667ns
166ns
CMD DATA STAT
Use of Status Word
The status word may be captured by the
subsystem as it is transmitted to the 1553 port by
pulsing BUFENA (pin 58) low during STATEN (pin
3: 520ns low pulse). Data becomes valid
approximately 50ns after the falling edge of
BUFENA. This corresponds with all
non-broadcast message transfers and the
TRANSMIT STATUS WORD mode command.
Note that the status word may be transmitted prior
to an error condition (See Transmit CMD). These
conditions will be indicated in the "next" status
word and may be monitored if the BC requests the
SW before it is altered (See Mode Commands).
Subsystem Control
The CT2565 allows the subsystem total control
over the status word flags using the inputs
indicated in Table 7.
BIT Word
The BIT Word (Built-In-Test) becomes available in
response to a TRANSMIT BIT WORD mode
command and provides additional status
information (See Figure 19) to that provided by the
status word. The subsystem may capture the BIT
word on the parallel data bus by pulsing BUFENA
(pin 58) low during BITEN (pin 43: approximately
520ns low pulse). Data Becomes valid
approximately 50ns after the falling edge of
BUFENA. Like the status word, the BIT word
cannot be altered by the subsystem.
PIN
#SYMBOL DESCRIPTION
6DBACCEPT RT accepts BC operation
responsibility (See Table 2).
7SSFLAG Transmitted data may be
invalid sets SSFLAG bit.
8SVCREQ Service Request; see
Transmit Vector mode
command.
10 SSER RTU fault exists: sets
TERMINAL FLAG bit.
47 SSBUSY Subsystem cannot service
1553 request at this time.
48 ILLCMD Mode command subsystem
illegalization: Sets MSGERR
bit, doesn’t suppress status
word.
Table 7 – Subsystem Control of RT-Status
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
EOM (57)
NRGRNT (42)
INCMD (9)
D0 - D15
(REQ, GRNT, ACK)
HANDSHAKE
ILLEGALIZE
1553 BUS
NODT (71)
(CS, OE, ADRINC)
MEM-READ
RTATXP
STAT
RTAP
DATA (16 BITS)
P
10.75±0.75µs
SOM (78)
STATEN (3)/
BITEN (43)
CHA/CHB (16)
WC0-4 T/R (15)
1.0±0.2µs
5.5±0.5µs
4.5±0.5µs
7.5±0.5µs
3.4±0.5µs
LMC
ILLCMD
1.5µs
5.5±0.5µs
4µs
165ns
667ns
166ns
CMD STAT DATA
7.5±0.5µs
CMD
500±20ns 500±20ns
Figure 17 – RT Transmit Command Timing
Notes:
(1) All timing is typical unless otherwise noted.
(2) BITEN only occurs when XMIT BIT WD mode code command is received
(Handshake and read/write signals are not generated in this case).
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Figure 18 – RT-RT Transfer Timing
EOM (57)
NRGRNT (42)
INCMD (9)
D0 - D15
(REQ, GRNT, ACK)
HANDSHAKE
ILLEGALIZE
NODT (71)
(CS, WE, ADRINC)
MEM-READ
RTARCV PRTBTXP
STAT
RTBP
DATA
P
10.75±0.75µs
SOM (78)
STATEN (3)/
BITEN (43)
4.5±0.5µs
7.5±0.5µs
3.4±0.5µs
ILLCMD
1.5µs
5.5±0.5µs
400ns
330ns
CMD STATDATA
7.5±0.5µs
500ns
CMD CMD STAT
RTAP
(16) BITS
LMC
TIMEOUT (4)
5.5±0.5µs
450ns
19.5µs
2.3µs
400ns (NO TIMEOUT)
(TIMEOUT ERROR)
RCV
1553 BUS
10.75±0.5µs
7.5±0.5µs
REF
Note: All timing is typical unless otherwise noted.
15 8 7 0
SET TO "0"
SET TO "0"
CHAN B XMITTER TIMEOUT
CHAN A XMITTER TIMEOUT
CHAN B LOOP TEST FAILURE
CHAN A LOOP TEST FAILURE
CHAN B XMITTER SHUTDOWN
CHAN A XMITTER SHUTDOWN
NON-MODE BROADCAST CMD TO XMIT
MESSAGE HIGH WORD COUNT
MESSAGE LOW WORD COUNT
ILLEGAL MODE CODE OR ILLEGAL
BROADCAST WITH MODE CODE
MODE CODE OR T/R ERROR
CHAN A/B LOOP TEST FAILURE
HANDSHAKE FAILURE
CHAN A/B XMITTER TIMEOUT
Notes:
(1) Bits 0-2 and 10-13 are latched and only cleared by a mode reset command or a master RESET.
(2) Bits 3-7 are cleared at the start of each new message and updated at the end of the message. They reflect the present
command word.
(3) Bits 8-9 are set by the mode command for Transmitter Shutdown and are cleared by the mode command for Override
Transmitter Shutdown, Reset RT or a master RESET.
Figure 19 – Bit Word
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
NAME Definition
GAP TIME NODT low time. 2MHz Clock
allows 500ns increments to
128µs (remains static at FF on
overflow).
WORD TRANSFER Logic "1" indicates successful
transfer to subsystem.
WORD TRANSFERRED Indicates successful transfer
(See bit 7)
VALID WORD Reset (1) indicates Manchester
error, Parity error, Low Bit Count
and/or Status sync field.
COMMAND SYNC Logic "1" indicates Command or
Status sync field. Logic"0"
indicates data sync.
CHAN A/BLogic "1" if word received on
1553 bus Channel B.
WORD GAP Set (0) if current word was
received at least 2µs after
receipt of previous word (parity
to mid-sync).
Note: Subsystem should clear entire memory prior to start of MT
operation.
Figure 20 – Identification Word
MT Operation
In the MT mode, the CT2565 captures all valid
transmissions on both channels of the 1553 bus, allowing
the user to monitor bus activity. Each word is transferred to
the subsystem along with an identification for interpretation
of the 1553 data stream.
MT Initialization
Initialize the CT2565 for MT operation per Table 2. The
CT2565 will remain in an idle state until BCSTART (pin 41)
is pulsed low. Figure 21 illustrates MT operation.
Valid words received by the CT2565 are transferred to the
subsystem along with an identification Word by a single
DMA handshake with two memory-write operations shown
in Figure 22, MT Transfer Timing. Since the decoder will
reject words based on sync field errors and/or errors in the
first 2 non-sync bits, these words will not be processed
further (i.e., the subsystem will receive no indication of the
receipt of this word).
YES
NO
YES
ERROR
?
INCREMENT MEM ADDR
INCREMENT MEM ADDR
IDENTIFICATION WORD
MEMORY WRITE
DMA
NODT LOW
SYNC + 2 BITS
DECODER CHECK
ACTIVITY
1553 BUS
START MT OPERATION
(START-UP ONLY)
INITIALIZATION
START
1553 INPUT
MEMORY WRITE
15 8 7 0
GAP TIME
WORD TRANSFER
LOGIC "1"
LOGIC "1"
VALID WORD
COMMAND SYNC
CH A/B
WORD GAP
SET TO "0"
Figure 21 – MT Operation Flow Chart
Notes:
(1) Steps marked with " ___" indicates operation is
transparent to user.
(2) Steps marked with " ___" indicates user interaction
required.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Simultaneous Transmission
Transmissions appearing simultaneously on
alternate 1553-bus channels will be captured by
CT2565 sequentially providing that each
BUSREQ is answered by the subsystem with a
BUSGRNT within the handshake timeout period.
RESET Signal
Pulsing RESET low will suspend MT operation by
(1) INCMD goes high (EOM goes low on the rising
edge) and (2) the CT2565 enters an idle state.
MT operation may be restored by pulsing
BCSTART low (above) or another mode of
operation may be selected (See Table 2).
Handshake Failure
Note that a handshake failure will abort the
current transfer. Monitoring will resume upon
receipt of a valid word on the 1553 bus.
MODE CODES
Nine of the 13 available, dual redundant mode
codes are handled by the CT2565 without user
intervention. Of the four remaining codes,
Dynamic Bus Control and Synchronize (no data)
require subsystem notification. The remaining
two mode codes, Transmit Vector Word and
Synchronize (with data) involve data transfer with
the subsystem. Mode command illegalization and
handling are detailed in the RTU Operation
section and listed in Table 8.
D0 - D15
CS (17)
DATA VALID
WR (44)
BUSACK (59)
BUSGRNT (45)
BUSREQ (19)
ADRINC (49)
t
7
t
5
t
4
t
3
t
2
t
1
t
6
t
6
t
8
t
6
t
8
t
9
t
10
ID-WORD VALID
Figure 22 – MT Transfer Timing
CYCLE SYM DESCRIPTION MIN TYP MAX UNITS
Handshake t1 BUSREQ to BUSGRNT delay 0-800 ns
t2 BUSGRNT pulse width 166 - - ns
t3 BUSGRNT to BUSACK delay ?-?ns
Write Only t4 BUSACK to WR delay 320 330 370 ns
t5 WR to CS time - - 25 ns
t6 WR and CS pulse width 150 166 175 ns
t7 DATA VALID setup - - 50 ns
t8 CS to ADRINC delay - - 25 ns
t9 ARINC pulse width 80 -166 ns
t10 ID WORD VALID setup - - 100 ns
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DYNAMIC BUS CONTROL (00000)
MESSAGE SEQUENCE = DBC * STATUS
The CT2565 responds with status. If the subsystem wants control of the bus, it must set DBACC within 2.5us after NBGRT.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (Bit Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
5.
Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
SYNCHRONIZE WITHOUT DATA WORD (00001)
MESSAGE SEQUENCE = SYNC * STATUS
The CT2565 responds with status. If sent as a broadcast, the broadcast receive bit will be set and status response suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
TRANSMIT STATUS WORD (00010)
MESSAGE SEQUENCE = TRANSMIT STATUS * STATUS
The status and BIT word registers are not altered by this command and contain the resulting status from the previous command.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
5.
Broadcast Address.
No status response. Bits set: message error, broadcast received (S/W), Illegal Mode code, T/R Error (BIT Word).
INITIATE SELF-TEST (00011)
MESSAGE SEQUENCE = SELF TEST * STATUS
The CT2565 responds with a status word. If the command was broadcast, the broadcast received bit is set and status transmission
suppressed. Short-loop test is initiated on the status word transmitted. If the test fails, an RT fail flag is generated.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
5.
Faulty Test.
Bits set: terminal flag (SW), A/B Loop Test Fail, Current 1553 Bus (A or B) Loop Test Fail (BIT Word).
TRANSMITTER SHUTDOWN (00100)
MESSAGE SEQUENCE - SHUTDOWN * STATUS
This command is only used with dual redundant bus systems. The CT2565 responds
with status. At the end of the status transmission, the CT2565 inhibits any further transmission from the dual redundant channel. Once
shutdown, the transmitter can only be re-activated by Override Transmitter Shutdown or RESET RT commands.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
Table 8 – Mode Codes
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
OVERRIDE TRANSMITTER SHUTDOWN (00101)
MESSAGE SEQUENCE - OVERRIDE SHUTDOWN - STATUS
This command is only used with dual redundant bus systems. The CT2565 responds with status. At the end of the status transmission, the
CT2565 re-enables the transmitter of the redundant bus. If the command was broadcast, the broadcast received bit is set and status
transmission is suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
INHIBIT TERMINAL FLAG BIT (00110)
MESSAGE SEQUENCE - INHIBIT TERMINAL FLAG * STATUS
The CT2565 responds with status and inhibits further internal or external setting of the terminal flag bit in the status register. Once the
terminal flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT command. If the command was
broadcast, the broadcast received bit is set and status transmission is suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
OVERRIDE INHIBIT TERMINAL FLAG BIT (00111)
MESSAGE SEQUENCE - OVERRIDE INHIBIT TERMINAL FLAG * STATUS
The RTU responds with status and reactivates the terminal flag bit in the status register. If the command was broadcast, the broadcast
received bit is set and status transmission is suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
RESET REMOTE TERMINAL (01000)
MESSAGE SEQUENCE - RESET REMOTE TERMINAL * STATUS
The CT2565 responds with status and internally resets. Transmitter shutdown, mode commands, and inhibit terminal flag commands will
be reset. If the command was broadcast, the broadcast received bit is set and the status word is suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
RESERVED MODE CODES (01001-01111)
MESSAGE SEQUENCE = RESERVED MODE CODES * STATUS
The CT2565 responds with status. If the command is illegalized through an optional PROM, the message error bit is set and only the status
word is transmitted.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), Illegal Mode Code (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT
Word).
Table 8 – Mode Codes (continued)
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TRANSMIT VECTOR WORD (10000)
MESSAGE SEQUENCE - TRANSMIT VECTOR WORD * STATUS VECTOR WORD
The CT2565 transmits a status word followed by a vector word. The contents of the vector word (from the subsystem) are enabled onto
DBO-DB15 with BUSREQ after the command transfer (same as data word in a normal transmit command).
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW) High Word Count (BIT Word).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error, Low Word Count (BIT Word).
5.
Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
SYNCHRONIZE WITH DATA WORD (10001)
MESSAGE SEQUENCE - SYNCHRONIZE DATA WORD * STATUS
The data word received following the command word is transferred to the subsystem. The status register is then enabled and its contents
transferred onto the data bus and transmitted. If the command was broadcast, the broadcast received bit is set and status transmission is
suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Not Followed by Data Word.
No status response. Bits set: message error (SW), Low Word Count (BIT Word).
3.
Command followed by too many Data Words.
No status response. Bits set: message error (SW), High Word Count (BIT word).
4.
Command T/R bit Set to One.
No status response. Bits set: message error (SW), T/R Error, High Word Count (BIT Word).
5.
Command, T/R bit Set to One and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), High
Word Count, T/R Error (BIT Word).
TRANSMIT LAST COMMAND (10010)
MESSAGE SEQUENCE = TRANSMIT LAST COMMAND * STATUS LAST COMMAND
The status and BIT word registers are not altered by this command. The SW contains the status from the previous command. The data
word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND).
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, (SW), Illegal Mode Code T/R Error (BIT Word).
5.
Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
TRANSMIT BIT WORD (10011)
MESSAGE SEQUENCE - TRANSMIT BIT WORD * STATUS BIT WORD
The CT2565 transmits a status word followed by the BIT word . When activated, BITEN allows the subsystem to latch the BIT word on the
parallel data bus. The BIT word is not altered by this command; however, the next SW will reflect errors in this transmission.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW).
3.
T/R bit Set to Zero.
No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4.
Zero T/R bit and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error, Low Word Count (BIT Word).
5.
Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
Table 8 – Mode Codes (continued)
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
SELECTED TRANSMITTER SHUTDOWN (10100)
MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS
The data word received is transferred to the subsystem and status is transmitted. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed. Intended for use with RTs with more than
one dual redundant channel.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Not Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT
Word).
3.
Command Followed by too many Data Words.
No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code
(BIT Word).
4.
Command T/R bit Set to One.
No status response. Bits set: message error (SW), Illegal Mode Code, High word count (BIT Word).
5.
Command T/R bit Set to One and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal
Mode Code, High Word Count (BIT Word).
OVERRIDE SELECTED TRANSMITTER SHUTDOWN (10101)
MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS
The data word received after the command word is transferred to the subsystem. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed.
ERROR CONDITIONS
1.
Invalid Command.
No response, command ignored.
2.
Command Not Followed by Data Word.
No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code (BIT
Word).
3.
Command Followed by too many Data Words.
No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code
(BIT Word).
4.
Command T/R bit Set to One.
No status response. Bits set: message error (SW), Illegal Mode Code, High Word Count (Bit Word).
5.
Command T/R bit Set to One and Broadcast Address.
No status response. Bits set: message error, broadcast received (SW), Illegal
Mode Code, High Word Count, T/R (BIT Word).
RESERVED MODE CODES
MESSAGE SEQUENCE = RESERVED MODE CODE (T/R = 1) * STATUS
RESERVED MODE CODE (T/R = 0) * STATUS
The CT2565 responds with status. If the command was broadcast, the broadcast received bit is set and status transmission suppressed.
ERROR CONDITIONS (T/R = 1)
1.
Invalid Command.
No response, command ignored.
2.
Command Followed by Data Word.
No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT
Word).
ERROR CONDITIONS (T/R = 0)
1.
Invalid Command.
No response, command ignored.
2.
Command not Followed by Contiguous Data Word.
No status response. Bits set: message error (SW), High word Count, Illegal Mode
Code (BIT Word).
3.
Command Followed by too many Data Words.
No status response. Bits set: message error (SW), High Word Count, Illegal Mode
Code (BIT Word).
Table 8 – Mode Codes (continued)
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 9A – Pin Function Table (78 Pin DDIP)
Pin # Symbol Description
1RT/BC Mode Select input - logic "1" for RT mode, logic “0” for BC mode.
2MT Monitor mode enable. When unit is operating as a BC, a logic “0” will select monitor
mode.
3STATEN Output signal in RT mode that indicates status word is being transferred on the
internal bus.
4TIMEOUT Indicates No Response Timeout has occured during BC and RTU (RT to RT transfer).
5HSFAIL Output in RT mode indicating the DMA transfer did not occur in time to allow proper
operation on the 1553 bus.
6DBACCEPT Input signal used to set DBACCEPT bit in status register for response to a valid mode
command on the 1553 bus.
7SSFLAG Input which controls the SSFLAG bit in the status register.
8SVCREQ Input which controls the service request bit in the status word.
9INCMD Output signal indicating the RT is currently in a message transfer sequence.
10 SSER Input which controls the subsystem error bit in the status register.
11 TESTOUT Factory test point. Do not connect.
12 WC1 WC bit 1 - latched output of command word.
13 WC3 WC bit 3 - latched output of command word.
14 TXINH B Transmitter inhibit output for channel B.
15 T/ROutput indicating T/R bit of current command word in RT mode.
16 CHA/CHB Output indicating current selected channel (0 = Channel A).
17 CS Chip Select output for subsystem memory control.
18 OE Output Enable output for subsystem memory control.
19 BUSREQ Output signal used to initiate transfer to/from subsystem.
20 +5V +5 Volt DC input.
21 DB0 Least significant bit - 16 bit parallel data bus.
22 DB2 Bit 2 of data bus.
23 DB4 Bit 4 of data bus.
24 DB6 Bit 6 of data bus.
25 DB8 Bit 8 of data bus.
26 DB10 Bit 10 of data bus.
27 DB12 Bit 12 of data bus.
28 DB14 Bit 14 of data bus.
29 LWORD Last word output during BC mode indicates last data word of the current message
transfer has been transferred on the parallel bus.
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30 MSGERR Output signal which indicates an error occurred during the current message
sequence.
31 TXDATA A Bipolar serial data output to positive input of bus transceiver.
32 RXDATA A Bipolar serial input from negative output of bus transceiver.
33 RTADP Parity bit input for RT address.
34 RTAD1 Bit 1 of RT address input.
35 RTAD3 Bit 3 of RT address input.
36 RESET System reset input - resets all inputs in module.
37 TXDATA B Bipolar serial data output to negative input bus transceiver.
38 RXDATA B Bipolar serial data input from positive output of bus transceiver.
39 12MHz 12MHz TTL clock input.
40 GROUND Signal ground.
41 BCSTART Cycle enable input Logic "0" initiates bus controller message transfer operation.
42 NBGRNT New bus grant output from RT indicates beginning of message transfer sequence.
43 BITEN Built in Test enable output indicates RT is transferring BlT word on internal 16 bit bus.
44 WR Write enable output for control of subsystem memory.
45 BUSGRNT Bus request input in response to DTREQ. Allows BC/RT to transfer data to
subsystem.
46 LOOPERR Loop error output. Logic "0" indicates failure of loop back transmitted data.
47 SSBUSY Subsystem busy input for RT status word.
48 ILLCMD Illegal command input to RT, used to block RT response to an illegal command.
49 ADRINC Increment output pulse. Goes LOW at the completion of each word transfer to/from
subsystem. Can increment external address counter.
50 CHASSIS Frame ground electricity isolated from signal ground
51 WC0 LSB of current command word count field.
52 WC2 Bit 2 of word count field.
53 WC4 Bit 4 of word count field.
54 TXINH A Transmitter inhibit output signal for Channel A.
55 LMC Latched Mode Command. Logic "1" indicates current word command is a mode code
word, WC0-WC4.
56 TESTIN Factory test point. Do not connect.
57 EOM End of message output. Logic "0" occurs when BC/RT message is completed.
58 BUFENA Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem must read
bit or Status words. Enables internal 16 bit bus onto subsystem bus.
Table 9A – Pin Function Table (78 Pin DDIP) (continued)
Pin # Symbol Description
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
59 BUSACK Bus acknowledge output. LOW during DMA Handshake, in response to BUSGRNT.
60 DB1 Bit 1 of 16 bit parallel bus.
61 DB3 Bit 3 of 16 bit parallel bus.
62 DB5 Bit 5 of 16 bit parallel bus.
63 DB7 Bit 7 of 16 bit parallel bus.
64 DB9 Bit 9 of 16 bit parallel bus.
65 DB11 Bit 11 of 16 bit parallel bus.
66 DB13 Bit 13 of 16 bit parallel bus.
67 DB15 Bit 15 of 16 bit parallel bus.
68 STATERR BC output indicates one or more bits set or address mismatch in a received status
word.
69 TXDATA A Bipolar serial data output to negative input of bus transceiver.
70 RXDATA A Bipolar serial data input from positive output of bus transceiver.
71 NODT No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front end is
active.
72 RTAD0 LSB of 5 bit RT address.
73 RTAD2 Bit 2 of RT address.
74 RTAD4 Bit 4 of RT address.
75 BCSTRCV Broadcast receive. Logic "0" means the current command was a broadcast command.
76 TXDATA B Bipolar serial output to positive input of bus transceiver.
77 RXDATABBipolar serial input from negative output of bus transceiver.
78 SOM Start of message output indicates beginning of RT/BC message transfer sequence.
Table 9A – Pin Function Table (78 Pin DDIP) (continued)
Pin # Symbol Description
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21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40
1
41
2
42
3
43
4
44
5
45
6
46
7
47
8
48
9
49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20
RT/BC
BCSTART
MT
NBGRNT
STATEN
BITEN
TIMEOUT
WR
HSFAIL
BUSGRNT
DBACCEPT
LOOPERR
SSFLAG
SSBUSY
SVCREQ
ILLCMD
INCMD
ADRINC
SSER
CASE GND
TESTOUT
WC0
WC1
WC2
WC3
WC4
TXINH B
TXINH A
T/R
LMC
CHB/CHA
TESTIN
CS
EOM
OE
BUFENA
BUSREQ
BUSACK
+5 Volt
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15 (MSB)
LWORD
STATERR
MSGERR
TXDATA A
TXDATA A
RXDATA A
RXDATA A
NODT
RTADP
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RESET
BCSTRCV
TXDATA B
TXDATA B
RXDATA B
RXDATA B
12MHz
SOM
GND
CT2565
MIL-STD-1553
BUS Controller,
Remote Terminal and
DDIP Pin Connection Diagram, CT2565 and Pinout
Table 9B – CT2565 Pin Out Description
(DDIP)
Pin
#Function Pin
#Function
1RT/BC 40 GND
2MT 41 BCSTART
3STATEN 42 NBGRNT
4TIMEOUT 43 BITEN
5HSFAIL 44 WR
6DBACCEPT 45 BUSGRNT
7SSFLAG 46 LOOPERR
8SVCREQ 47 SSBUSY
9INCMD 48 ILLCMD
10 SSER 49 ADRINC
11 TESTOUT 50 CASE GND
12 WC1 51 WC0
13 WC3 52 WC2
14 TXINH B 53 WC4
15 T/R54 TXINH A
16 CHB/CHA 55 LMC
17 CS 56 TESTIN
18 OE 57 EOM
19 BUSREQ 58 BUFENA
20 + 5 Volt 59 BUSACK
21 DB0 (LSB) 60 DB1
22 DB2 61 DB3
23 DB4 62 DB5
24 DB6 63 DB7
25 DB8 64 DB9
26 DB10 65 DB11
27 DB12 66 DB13
28 DB14 67 DB15 (MSB)
29 LWORD 68 STATERR
30 MSGERR 69 TXDATA A
31 TXDATA A 70 RXDATA A
32 RXDATA A 71 NODT
33 RTADP 72 RTAD0
34 RTAD1 73 RTAD2
35 RTAD3 74 RTAD4
36 RESET 75 BCSTRCV
37 TXDATA B 76 TXDATA B
38 RXDATA B 77 RXDATA B
39 12MHz 78 SOM
BUS MONITOR
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
RT/BC
BCSTART
MT
NBGRNT
STATEN
BITEN
TIMEOUT
WR
HSFAIL
BUSGRNT
DBACCEPT
LOOPERR
SSFLAG
SSBUSY
SVCREQ
ILLCMD
INCMD
ADRINC
SSER
CASE GND
TESTOUT
WC0
WC1
WC2
WC3
WC4
TXINH B
TXINH A
T/R
LMC
CHB/CHA
TESTIN
CS
EOM
OE
BUFENA
BUSREQ
BUSACK
+5V
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15 (MSB)
LWORD
STATERR
MSGERR
TXDATA A
TXDATA A
RXDATA A
RXDATA A
NODT
RTADP
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RESET
BCSTRCV
TXDATA B
TXDATA B
RXDATA B
RXDATA B
12MHz
SOM
GROUND
Table 10 – CT2565 Pin Out Description
(FP)
Pin
#Function Pin
#Function
1N/C 42 N/C
2RT/BC 43 GROUND
3BCSTART 44 SOM
4MT 45 12MHz
5NBGRNT 46 RXDATA B
6STATEN 47 RXDATA B
7BITEN 48 TXDATA B
8TIMEOUT 49 TXDATA B
9WR 50 BCSTRCV
10 HSFAIL 51 RESET
11 BUSGRNT 52 RTAD4
12 DBACCEPT 53 RTAD3
13 LOOPERR 54 RTAD2
14 SSFLAG 55 RTAD1
15 SSBUSY 56 RTAD0
16 SVCREQ 57 RTADP
17 ILLCMD 58 NODT
18 INCMD 59 RXDATA A
19 ADRINC 60 RXDATA A
20 SSER 61 TXDATA A
21 CASE GND 62 TXDATA A
22 TESTOUT 63 MSGERR
23 WC0 64 STATERR
24 WC1 65 LWORD
25 WC2 66 DB15 (MSB)
26 WC2 67 DB14
27 WC4 68 DB13
28 TXINH B 69 DB12
29 TXINH A 70 DB11
30 T/R71 DB10
31 LMC 72 DB9
32 CHB/CHA 73 DB8
33 TESTIN 74 DB7
34 CS 75 DB6
35 EOM 76 DB5
36 OE 77 DB4
37 BUFENA 78 DB3
38 BUSREQ 79 DB2
39 BUSACK 80 DB1
40 +5V 81 DB0 (LSB)
41 N/C 82 N/C
Flat Package Pin Connection Diagram, CT2566 and Pinout
1
2
N/C
N/C N/C
N/C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
82
81
CT2565FP
MIL-STD-1553
BUS Controller,
Remote Terminal and
BUS MONITOR
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
.100
2.100
1.500
TYP
Lead 1 & ESD
Designator
1.900
1.800
Pin 19 Pin 20
Pin 59
Pin 41
Pin 2 .050
TYP
1.650
1.870
.100
.110Pin 1
.250
.250
MAX
Pin 39 Pin 40
Pin 78
Pin 22
Pin 21
Pin 60
.018 DIA
TYP
.080
.180
MAX
.010
±.002
.015
2.000
Pin 42
.095
Pin 41
2.200
MAX
Lead 1 & ESD
Designator
1.610
MAX
Designator
MAX
.400
MIN
.050 Lead Centers
41 Leads/Side
(4 Places)
Pin 82
.050
Figure 23 – Plug In Package Outline
Figure 24 – Flat Package Outline
Aeroflex Circuit Technology
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: (800) THE-1553
Specifications subject to change without notice
www.aeroflex.com/act1.htm E-Mail: sales-act@aeroflex.com
Ordering Information
Model Number Screening DESC SMD # Package
CT2565 Military Temperature, -55°C to +125°C,
Screened to the individual test methods
of MIL-STD-883
-Plug in
CT2565-FP - Flat Package
CT2565-001-1 Per SMD 5962-8858501XA Plug in
CT2565-001-2 5962-8858501XC Plug in
CT2565-201-1 5962-8858501YA Flat Package
CT2565-201-2 5962-8858501YC Flat Package