Mixed Signal ISP Flash MCU Family
C8051F70x/71x
Rev. 1.0 7/10 Copyright © 2010 by Silicon Laboratories C8051F70x/71x
Capacitance to Digital Converter
-Supports buttons, sliders, wheels, capacitive prox-
imity, and touch screen sensing
-Up to 38 input channels
-Fast 40 µs per channel conversion time
-12, 13, 14, or 16-bit output
-Auto-scan and wake-on-touch
-Auto-accumulate 4, 8, 16, 32, or 64 samples
10-Bit Analog to Digital Converter
-Up to 500 ksps
-Up to 16 external single-ended inputs
-VREF from on-chip VREF, external pin or VDD
-Internal or external start of conversion source
-Built-in temp erature senso r
Analog Comparator
-Programmable hysteresis and response time
-Configurable as interrupt or reset source
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-Low cost, complete development kit
Supply Voltage 1.8 to 3.6 V
-Built-in voltage supply monitor
High-S peed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Memory
-512 bytes internal da ta RAM (256 + 256)
-Up to 16 kB Flash; In-system programmable in 512-
byte Sectors
-Up to 32-byte data EEPROM
Digital Peripherals
-Up to 54 Port I/O with high sink current
-Hardware enhanced UART, SMBus™ (I2C compati-
ble), and enhanced SPI™ serial ports
-Four general purpose 16-bit counter/timers
-16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
-Real time clock mode using timer and crystal
Clock Sources
-24.5 MHz ±2% Oscillator Supports crystal-less
UART operation
-External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
-Can switch between clock sources on-the-fly; useful
in power saving modes
64-Pin TQFP, 48-Pin TQFP, 48-Pin QFN,
32-Pin QFN, 24-Pin QFN
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
16 kB
ISP FLASH 512 B RAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DIGITAL I/O
24.5 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
CROSSBAR
VOLTAGE
COMPARATOR
+
–
WDT
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
SPI
10-bit
500 ksps
ADC
TEMP
SENSOR
A
M
U
X
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6.0
– 6.5
32 B EEPROM
Ext. Memory I/F
Capacitive
Sense
C8051F70x/71x
2 Rev. 1.0
C8051F70x/71x
Rev. 1.0 3
Table of Contents
1. System Overview..................................................................................................... 17
2. Ordering Information............................................................................................... 26
3. Pin Definitions.......................................................................................................... 28
4. TQFP-64 Package Specifications........................................................................... 37
5. TQFP-48 Package Specifications........................................................................... 39
6. QFN-48 Package Specifications............................................................................. 41
7. QFN-32 Package Specifications............................................................................. 43
8. QFN-24 Package Specifications............................................................................. 45
9. Electrical Characteristics........................................................................................ 47
9.1. Absolute Maximum Specifications..................................................................... 47
9.2. Electrical Characteristics................................................................................... 48
10. 10-Bit ADC (ADC0)................................................................................................. 55
10.1. Output Code Formatting.................................................................................. 56
10.2. 8-Bit Mode....................................................................................................... 56
10.3. Modes of Operation......................................................................................... 56
10.3.1. Starting a Conversion.............................................................................. 56
10.3.2. Tracking Modes....................................................................................... 57
10.3.3. Settling Time Requirements.................................................................... 58
10.4. Programmable Window Detector..................................................................... 62
10.4.1. Window Detector Example...................................................................... 64
10.5. ADC0 Analog Multiplexer ................................................................................ 65
11. Temperature Sensor.............................................................................................. 67
11.1. Calibration ....................................................................................................... 67
12. Voltage and Ground Reference Options.............................................................. 69
12.1. External Voltage References........................................................................... 70
12.2. Internal Voltage Reference Options ................................................................ 70
12.3. Analog Ground Reference............................................................................... 70
12.4. Temperature Sensor Enable ........................................................................... 70
13. Voltage Regulator (REG0)..................................................................................... 72
14. Comparator0........................................................................................................... 74
14.1. Comparator Multiplexer................................................................................... 78
15. Capacitive Sense (CS0)......................................................................................... 80
15.1. Configuring Port Pins as Capacitive Sense Inputs.......................................... 81
15.2. CS0 Gain Adjustment...................................................................................... 81
15.3. Capacitive Sense Start-Of-Conversion Sources ............................................. 81
15.4. Automatic Scanning......................................................................................... 83
15.5. CS0 Comparator.............................................................................................. 84
15.6. CS0 Conversion Accumulator ......................................................................... 85
15.7. CS0 Pin Monitor .............................................................................................. 86
15.8. Adjusting CS0 For Special Situations.............................................................. 87
15.9. Capacitive Sense Multiplexer.......................................................................... 96
16. CIP-51 Microcontroller........................................................................................... 98
16.1. Instruction Set.................................................................................................. 99
C8051F70x/71x
4 Rev. 1.0
16.1.1. Instruction and CPU Timing.................................................................... 99
16.2. CIP-51 Register Descriptions........................................................................ 104
17. Memory Organization.......................................................................................... 108
17.1. Program Memory........................................................................................... 109
17.1.1. MOVX Instruction and Program Memory.............................................. 109
17.2. EEPROM Memory......................................................................................... 109
17.3. Data Memory................................................................................................. 109
17.3.1. Internal RAM......................................................................................... 109
17.3.1.1. General Purpose Registers .......................................................... 110
17.3.1.2. Bit Addressable Locations............................................................ 110
17.3.1.3. Stack .......................................................................................... 110
18. External Data Memory Interface and On-Chip XRAM....................................... 111
18.1. Accessing XRAM........................................................................................... 111
18.1.1. 16-Bit MOVX Example.......................................................................... 111
18.1.2. 8-Bit MOVX Example............................................................................ 111
18.2. Configuring the External Memory Interface................................................... 112
18.3. Port Configuration.......................................................................................... 112
18.4. Multiplexed and Non-multiplexed Selection................................................... 115
18.4.1. Multiplexed Configuration...................................................................... 115
18.4.2. Non-multiplexed Configuration.............................................................. 116
18.5. Memory Mode Selection................................................................................ 117
18.5.1. Internal XRAM Only .............................................................................. 117
18.5.2. Split Mode without Bank Select............................................................. 117
18.5.3. Split Mode with Bank Select.................................................................. 118
18.5.4. External Only......................................................................................... 118
18.6. Timing .......................................................................................................... 118
18.6.1. Non-Multiplexed Mode.......................................................................... 120
18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 120
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111....... 121
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110....................... 122
18.6.2. Multiplexed Mode.................................................................................. 123
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 123
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011....... 124
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010....................... 125
19. In-System Device Identification.......................................................................... 128
20. Special Function Registers................................................................................. 130
21. Interrupts.............................................................................................................. 137
21.1. MCU Interrupt Sources and Vectors.............................................................. 138
21.1.1. Interrupt Priorities.................................................................................. 138
21.1.2. Interrupt Latency................................................................................... 138
21.2. Interrupt Register Descriptions...................................................................... 140
21.3. INT0 and INT1 External Interrupts................................................................. 146
22. Flash Memory....................................................................................................... 148
22.1. Programming The Flash Memory.................................................................. 148
22.1.1. Flash Lock and Key Functions.............................................................. 148
C8051F70x/71x
Rev. 1.0 5
22.1.2. Flash Erase Procedure ......................................................................... 148
22.1.3. Flash Write Procedure .......................................................................... 149
22.2. Non-volatile Data Storage ............................................................................. 149
22.3. Security Options............................................................................................ 149
22.4. Flash Write and Erase Guidelines................................................................. 150
22.4.1. VDD Maintenance and the VDD Monitor .............................................. 151
22.4.2. PSWE Maintenance.............................................................................. 151
22.4.3. System Clock........................................................................................ 152
23. EEPROM ............................................................................................................... 155
23.1. RAM Reads and Writes................................................................................. 155
23.2. Auto Increment.............................................................................................. 155
23.3. Interfacing with the EEPROM........................................................................ 155
23.4. EEPROM Security......................................................................................... 156
24. Power Management Modes................................................................................. 160
24.1. Idle Mode....................................................................................................... 160
24.2. Stop Mode..................................................................................................... 161
24.3. Suspend Mode .............................................................................................. 161
25. Reset Sources...................................................................................................... 163
25.1. Power-On Reset............................................................................................ 164
25.2. Power-Fail Reset / VDD Monitor ................................................................... 165
25.3. External Reset............................................................................................... 166
25.4. Missing Clock Detector Reset ....................................................................... 166
25.5. Comparator0 Reset....................................................................................... 167
25.6. Watchdog Timer Reset.................................................................................. 167
25.7. Flash Error Reset .......................................................................................... 167
25.8. Software Reset.............................................................................................. 167
26. Watchdog Timer................................................................................................... 169
26.1. Enable/Reset WDT........................................................................................ 169
26.2. Disable WDT ................................................................................................. 169
26.3. Disable WDT Lockout.................................................................................... 169
26.4. Setting WDT Interval ..................................................................................... 169
27. Oscillators and Clock Selection......................................................................... 171
27.1. System Clock Selection................................................................................. 171
27.2. Programmable Internal High-Frequency (H-F) Oscillator.............................. 173
27.3. External Oscillator Drive Circuit. .................................................................... 175
27.3.1. External Crystal Example...................................................................... 177
27.3.2. External RC Example............................................................................ 178
27.3.3. External Capacitor Example.................................................................. 179
28. Port Input/Output................................................................................................. 180
28.1. Port I/O Modes of Operation.......................................................................... 181
28.1.1. Port Pins Configured for Analog I/O...................................................... 181
28.1.2. Port Pins Configured For Digital I/O...................................................... 181
28.1.3. Interfacing Port I/O to 5 V Logic............................................................ 182
28.1.4. Increasing Port I/O Drive Strength........................................................ 182
28.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 182
C8051F70x/71x
6 Rev. 1.0
28.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 182
28.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 184
28.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 184
28.3. Priority Crossbar Decoder............................................................................. 185
28.4. Port I/O Initialization ...................................................................................... 189
28.5. Port Match..................................................................................................... 192
28.6. Special Function Registers for Accessing and Configuring Port I/O ............. 194
29. Cyclic Redundancy Check Unit (CRC0)............................................................. 211
29.1. 16-bit CRC Algorithm..................................................................................... 212
29.2. 32-bit CRC Algorithm..................................................................................... 213
29.3. Preparing for a CRC Calculation................................................................... 214
29.4. Performing a CRC Calculation ...................................................................... 214
29.5. Accessing the CRC0 Result.......................................................................... 214
29.6. CRC0 Bit Reverse Feature............................................................................ 218
30. SMBus................................................................................................................... 219
30.1. Supporting Documents.................................................................................. 220
30.2. SMBus Configuration..................................................................................... 220
30.3. SMBus Operation.......................................................................................... 220
30.3.1. Transmitter Vs. Receiver....................................................................... 221
30.3.2. Arbitration.............................................................................................. 221
30.3.3. Clock Low Extension............................................................................. 221
30.3.4. SCL Low Timeout.................................................................................. 221
30.3.5. SCL High (SMBus Free) Timeout ......................................................... 222
30.4. Using the SMBus........................................................................................... 222
30.4.1. SMBus Configuration Register.............................................................. 222
30.4.2. SMB0CN Control Register.................................................................... 226
30.4.2.1. Software ACK Generation ............................................................ 226
30.4.2.2. Hardware ACK Generation........................................................... 226
30.4.3. Hardware Slave Address Recognition .................................................. 228
30.4.4. Data Register........................................................................................ 231
30.5. SMBus Transfer Modes................................................................................. 232
30.5.1. Write Sequence (Master)...................................................................... 232
30.5.2. Read Sequence (Master)...................................................................... 233
30.5.3. Write Sequence (Slave)........................................................................ 234
30.5.4. Read Sequence (Slave)........................................................................ 235
30.6. SMBus Status Decoding................................................................................ 235
31. Enhanced Serial Peripheral Interface (SPI0)..................................................... 241
31.1. Signal Descriptions........................................................................................ 242
31.1.1. Master Out, Slave In (MOSI)................................................................. 242
31.1.2. Master In, Slave Out (MISO)................................................................. 242
31.1.3. Serial Clock (SCK)................................................................................ 242
31.1.4. Slave Select (NSS)............................................................................... 242
31.2. SPI0 Master Mode Operation........................................................................ 242
31.3. SPI0 Slave Mode Operation.......................................................................... 244
31.4. SPI0 Interrupt Sources.................................................................................. 245
C8051F70x/71x
Rev. 1.0 7
31.5. Serial Clock Phase and Polarity.................................................................... 245
31.6. SPI Special Function Registers..................................................................... 247
32. UART0................................................................................................................... 254
32.1. Enhanced Baud Rate Generation.................................................................. 255
32.2. Operational Modes........................................................................................ 256
32.2.1. 8-Bit UART............................................................................................ 256
32.2.2. 9-Bit UART............................................................................................ 257
32.3. Multiprocessor Communications ................................................................... 258
33. Timers................................................................................................................... 262
33.1. Timer 0 and Timer 1...................................................................................... 264
33.1.1. Mode 0: 13-bit Counter/Timer............................................................... 264
33.1.2. Mode 1: 16-bit Counter/Timer............................................................... 265
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 265
33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)... ............................. 266
33.2. Timer 2 .......................................................................................................... 272
33.2.1. 16-bit Timer with Auto-Reload............................................................... 272
33.2.2. 8-bit Timers with Auto-Reload............................................................... 273
33.3. Timer 3 .......................................................................................................... 278
33.3.1. 16-bit Timer with Auto-Reload............................................................... 278
33.3.2. 8-bit Timers with Auto-Reload............................................................... 279
34. Programmable Counter Array............................................................................. 284
34.1. PCA Counter/Timer....................................................................................... 285
34.2. PCA0 Interrupt Sources................................................................................. 286
34.3. Capture/Compare Modules ........................................................................... 286
34.3.1. Edge-triggered Capture Mode............................................................... 288
34.3.2. Software Timer (Compare) Mode.......................................................... 289
34.3.3. High-Speed Output Mode ..................................................................... 290
34.3.4. Frequency Output Mode ....................................................................... 291
34.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes............... 292
34.3.5.1. 8-bit Pulse Width Modulator Mode.............................................. 292
34.3.5.2. 9/10/11-bit Pulse Width Modulator Mode.................................... 293
34.3.6. 16-Bit Pulse Width Modulator Mode.................................................... 294
34.4. Register Descriptions for PCA0..................................................................... 295
35. C2 Interface .......................................................................................................... 301
35.1. C2 Interface Registers................................................................................... 301
35.2. C2CK Pin Sharing ......................................................................................... 304
Document Change List.............................................................................................. 305
Contact Information................................................................................................... 306
C8051F70x/71x
Rev. 1.0 8
List of Figures
Figure 1.1. C8051F700/1 Block Diagram ................................................................ 18
Figure 1.2. C8051F702/3 Block Diagram ................................................................ 19
Figure 1.3. C8051F704/5 Block Diagram ................................................................ 20
Figure 1.4. C8051F706/07 Block Diagram .............................................................. 21
Figure 1.5. C8051F708/09/10/11 Block Diagram .................................................... 22
Figure 1.6. C8051F712/13/14/15 Block Diagram .................................................... 23
Figure 1.7. C8051F716 Block Diagram ................................................................... 24
Figure 1.8. C8051F717 Block Diagram ................................................................... 25
Figure 3.1. C8051F7xx-GQ TQFP64 Pinout Diagram (Top View) .......................... 32
Figure 3.2. C8051F7xx-GQ QFP48 Pinout Diagram (Top View) ............................. 33
Figure 3.3. C8051F7xx-GM QFN48 Pinout Diagram (Top View) ............................ 34
Figure 3.4. C8051F716-GM QFN32 Pinout Diagram (Top View) ............................ 35
Figure 3.5. C8051F717-GM QFN24 Pinout Diagram (Top View) ............................ 36
Figure 4.1. TQFP-64 Package Drawing .................................................................. 37
Figure 4.2. TQFP-64 PCB Land Pattern .................................................................. 38
Figure 5.1. TQFP-48 Package Drawing .................................................................. 39
Figure 5.2. TQFP-48 PCB Land Pattern .................................................................. 40
Figure 6.1. QFN-48 Package Drawing .................................................................... 41
Figure 6.2. QFN-48 PCB Land Pattern .................................................................... 42
Figure 7.1. QFN-32 Package Drawing .................................................................... 43
Figure 7.2. QFN-32 Recommended PCB Land Pattern .......................................... 44
Figure 8.1. QFN-24 Package Drawing .................................................................... 45
Figure 8.2. QFN-24 Recommended PCB Land Pattern .......................................... 46
Figure 10.1. ADC0 Functional Block Diagram ......................................................... 55
Figure 10.2. 10-Bit ADC Track and Conversion Example Timing ........................... 57
Figure 10.3. ADC0 Equivalent Input Circuits ........................................................... 58
Figure 10.4. ADC Window Compare Example: Right-Justified Data ....................... 64
Figure 10.5. ADC Window Compare Example: Left-Justified Data ......................... 64
Figure 10.6. ADC0 Multiplexer Block Diagram ........................................................ 65
Figure 11.1. Temperature Sensor Transfer Function .............................................. 67
Figure 11.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ......... 68
Figure 12.1. Voltage Reference Functional Block Diagram ..................................... 69
Figure 14.1. Comparator0 Functional Block Diagram ............................................. 74
Figure 14.2. Comparator Hysteresis Plot ................................................................ 75
Figure 14.3. Comparator Input Multiplexer Block Diagram ...................................... 78
Figure 15.1. CS0 Block Diagram ............................................................................. 80
Figure 15.2. Auto-Scan Example ............................................................................. 83
Figure 15.3. CS0 Multiplexer Block Diagram ........................................................... 96
Figure 16.1. CIP-51 Block Diagram ......................................................................... 98
Figure 17.1. C8051F70x/71x Memory Map ........................................................... 108
Figure 17.2. Flash Program Memory Map ............................................................. 109
Figure 18.1. Multiplexed Configuration Example ................................................... 115
Figure 18.2. Non-multiplexed Configuration Example ........................................... 116
C8051F70x/71x
9 Rev. 1.0
Figure 18.3. EMIF Operating Modes ..................................................................... 117
Figure 18.4. Non-multiplexed 16-bit MOVX Timing ............................................... 120
Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 121
Figure 18.6. Non-Multiplexed 8-Bit MOVX with Bank Select Timing ..................... 122
Figure 18.7. Multiplexed 16-bit MOVX Timing ....................................................... 123
Figure 18.8. Multiplexed 8-Bit MOVX without Bank Select Timing ........................ 124
Figure 18.9. Multiplexed 8-Bit MOVX with Bank Select Timing ............................. 125
Figure 23.1. EEPROM Block Diagram .................................................................. 155
Figure 25.1. Reset Sources ................................................................................... 163
Figure 25.2. Power-On and VDD Monitor Reset Timing ....................................... 164
Figure 27.1. Oscillator Options .............................................................................. 171
Figure 27.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 178
Figure 28.1. Port I/O Functional Block Diagram .................................................... 180
Figure 28.2. Port I/O Cell Block Diagram .............................................................. 181
Figure 28.3. Port I/O Overdrive Current ................................................................ 182
Figure 28.4. Crossbar Priority Decoder—Possible Pin Assignments .................... 186
Figure 28.5. Crossbar Priority Decoder in Example Configuration—
No Pins Skipped ............................................................................... 187
Figure 28.6. Crossbar Priority Decoder in Example Configuration—
3 Pins Skipped .................................................................................. 188
Figure 29.1. CRC0 Block Diagram ........................................................................ 211
Figure 30.1. SMBus Block Diagram ...................................................................... 219
Figure 30.2. Typical SMBus Configuration ............................................................ 220
Figure 30.3. SMBus Transaction ........................................................................... 221
Figure 30.4. Typical SMBus SCL Generation ........................................................ 223
Figure 30.5. Typical Master Write Sequence ........................................................ 232
Figure 30.6. Typical Master Read Sequence ........................................................ 233
Figure 30.7. Typical Slave Write Sequence ........... ............................................... 234
Figure 30.8. Typical Slave Read Sequence .......................................................... 235
Figure 31.1. SPI Block Diagram ............................................................................ 241
Figure 31.2. Multiple-Master Mode Connection Diagram ...................................... 243
Figure 31.3. 3-Wire Single Master and Single Slave Mode Connection Diagram . 243
Figure 31.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram .. 244
Figure 31.5. Master Mode Data/Clock Timing ....................................................... 246
Figure 31.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 246
Figure 31.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 247
Figure 31.8. SPI Master Timing (CKPHA = 0) ....................................................... 251
Figure 31.9. SPI Master Timing (CKPHA = 1) ....................................................... 251
Figure 31.10. SPI Slave Timing (CKPHA = 0) ....................................................... 252
Figure 31.11. SPI Slave Timing (CKPHA = 1) ....................................................... 252
Figure 32.1. UART0 Block Diagram ...................................................................... 254
Figure 32.2. UART0 Baud Rate Logic ................................................................... 255
Figure 32.3. UART Interconnect Diagram ............................................................. 256
Figure 32.4. 8-Bit UART Timing Diagram .............................................................. 256
Figure 32.5. 9-Bit UART Timing Diagram .............................................................. 257
C8051F70x/71x
Rev. 1.0 10
Figure 32.6. UART Multi-Processor Mode Interconnect Diagram ......................... 258
Figure 33.1. T0 Mode 0 Block Diagram ................................................................. 265
Figure 33.2. T0 Mode 2 Block Diagram ................................................................. 266
Figure 33.3. T0 Mode 3 Block Diagram ................................................................. 267
Figure 33.4. Timer 2 16-Bit Mode Block Diagram ................................................. 272
Figure 33.5. Timer 2 8-Bit Mode Block Diagram ................................................... 273
Figure 33.7. Timer 3 16-Bit Mode Block Diagram ................................................. 278
Figure 33.8. Timer 3 8-Bit Mode Block Diagram ................................................... 279
Figure 33.9. Timer 3 Capture Mode Block Diagram .............................................. 280
Figure 34.1. PCA Block Diagram ........................................................................... 284
Figure 34.2. PCA Counter/Timer Block Diagram ................................................... 285
Figure 34.3. PCA Interrupt Block Diagram ............................................................ 286
Figure 34.4. PCA Capture Mode Diagram ............................................................. 288
Figure 34.5. PCA Software Timer Mode Diagram ................................................. 289
Figure 34.6. PCA High-Speed Output Mode Diagram ........................................... 290
Figure 34.7. PCA Frequency Output Mode ........................................................... 291
Figure 34.8. PCA 8-Bit PWM Mode Diagram ........................................................ 292
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 293
Figure 34.10. PCA 16-Bit PWM Mode ................................................................... 294
Figure 35.1. Typical C2CK Pin Sharing ................................................................. 304
C8051F70x/71x
Rev. 1.0 11
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 27
Table 3.1. Pin Definitions for the C8051F70x/71x ................................................... 28
Table 4.1. TQFP-64 Package Dimensions .............................................................. 37
Table 4.2. TQFP-64 PCB Land Pattern Dimensions ............................................... 38
Table 5.1. TQFP-48 Package Dimensions .............................................................. 39
Table 5.2. TQFP-48 PCB Land Pattern Dimensions ............................................... 40
Table 6.1. QFN-48 Package Dimensions ................................................................ 41
Table 6.2. QFN-48 PCB Land Pattern Dimensions ................................................. 42
Table 7.1. QFN-32 Package Dimensions ................................................................ 43
Table 7.2. QFN-32 PCB Land Pattern Dimensions ................................................. 44
Table 8.1. QFN-24 Package Dimensions ................................................................ 45
Table 8.2. QFN-24 PCB Land Pattern Dimensions ................................................. 46
Table 9.1. Absolute Maximum Ratings .................................................................... 47
Table 9.2. Global Electrical Characteristics ............................................................. 48
Table 9.3. Port I/O DC Electrical Characteristics ..................................................... 49
Table 9.4. Reset Electrical Characteristics .............................................................. 49
Table 9.5. Internal Voltage Regulator Electrical Characteristics ............................. 50
Table 9.6. Flash Electrical Characteristics .............................................................. 50
Table 9.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 50
Table 9.8. Capacitive Sense Electrical Characteristics ........................................... 51
Table 9.9. EEPROM Electrical Characteristics ........................................................ 52
Table 9.10. ADC0 Electrical Characteristics ............................................................ 52
Table 9.11. Power Management Electrical Characteristics ..................................... 53
Table 9.12. Temperature Sensor Electrical Characteristics .................................... 53
Table 9.13. Voltage Reference Electrical Characteristics ....................................... 53
Table 9.14. Comparator Electrical Characteristics .................................................. 54
Table 15.1. Gain Setting vs. Maximum Capacitance and Conversion Time ........... 81
Table 15.2. Operation with Auto-scan and Accumulate .......................................... 85
Table 16.1. CIP-51 Instruction Set Summary ........................................................ 100
Table 18.1. AC Parameters for External Memory Interface ................................... 126
Table 18.2. EMIF Pinout (C8051F700/1/2/3/8/9 and C8051F710/1) ..................... 127
Table 20.1. Special Function Register (SFR) Memory Map .................................. 131
Table 20.2. Special Function Registers ................................................................. 132
Table 21.1. Interrupt Summary .............................................................................. 139
Table 22.1. Flash Security Summary .................................................................... 150
Table 28.1. Port I/O Assignment for Analog Functions ......................................... 183
Table 28.2. Port I/O Assignment for Digital Functions ........................................... 184
Table 28.3. Port I/O Assignment for External Event Trigger Functions ................. 184
Table 29.1. Example 16-bit CRC Outputs ............................................................. 212
Table 29.2. Example 32-bit CRC Outputs ............................................................. 213
Table 30.1. SMBus Clock Source Selection .......................................................... 223
Table 30.2. Minimum SDA Setup and Hold Times ................................................ 224
Table 30.3. Sources for Hardware Changes to SMB0CN ..................................... 228
C8051F70x/71x
12 Rev. 1.0
Table 30.4. Hardware Address Recognition Examples (EHACK = 1) ................... 229
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 236
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 238
Table 31.1. SPI Slave Timing Parameters ............................................................ 253
Table 32.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 261
Table 32.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 261
Table 34.1. PCA Timebase Input Options ............................................................. 285
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Modules ................. 287
C8051F70x/71x
Rev. 1.0 13
List of Registers
SFR Definition 10.1. ADC0CF: ADC0 Configuration .................................................... 59
SFR Definition 10.2. ADC0H: ADC0 Data Word MSB .................................................. 60
SFR Definition 10.3. ADC0L: ADC0 Data Word LSB .................................................... 60
SFR Definition 10.4. ADC0CN: ADC0 Control .............................................................. 61
SFR Definition 10.5. ADC0GTH: ADC0 Greater-Than Data High Byte ........................ 62
SFR Definition 10.6. ADC0GTL: ADC0 Greater-Than Data Low Byte .......................... 62
SFR Definition 10.7. ADC0LTH: ADC0 Less-Than Data High Byte .............................. 63
SFR Definition 10.8. ADC0LTL: ADC0 Less-Than Data Low Byte ............................... 63
SFR Definition 10.9. ADC0MX: AMUX0 Channel Select .............................................. 66
SFR Definition 12.1. REF0CN: Voltage Reference Control .......................................... 71
SFR Definition 13.1. REG0CN: Voltage Regulator Control .......................................... 73
SFR Definition 14.1. CPT0CN: Comparator0 Control ................................................... 76
SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection ..................................... 77
SFR Definition 14.3. CPT0MX: Comparator0 MUX Selection ...................................... 79
SFR Definition 15.1. CS0CN: Capacitive Sense Control .............................................. 88
SFR Definition 15.2. CS0CF: Capacitive Sense Configuration ..................................... 89
SFR Definition 15.3. CS0DH: Capacitive Sense Data High Byte ................................. 90
SFR Definition 15.4. CS0DL: Capacitive Sense Data Low Byte ................................... 90
SFR Definition 15.5. CS0SS: Capacitive Sense Auto-Scan Start Channel .................. 91
SFR Definition 15.6. CS0SE: Capacitive Sense Auto-Scan End Channel ................... 91
SFR Definition 15.7. CS0THH: Capacitive Sense Comparator Threshold High Byte ... 92
SFR Definition 15.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte .... 92
SFR Definition 15.9. CS0PM: Capacitive Sense Pin Monitor ....................................... 93
SFR Definition 15.10. CS0MD1: Capacitive Sense Mode 1 ......................................... 94
SFR Definition 15.11. CS0MD2: Capacitive Sense Mode 2 ......................................... 95
SFR Definition 15.12. CS0MX: Capacitive Sense Mux Channel Select ....................... 97
SFR Definition 16.1. DPL: Data Pointer Low Byte ...................................................... 104
SFR Definition 16.2. DPH: Data Pointer High Byte ..................................................... 104
SFR Definition 16.3. SP: Stack Pointer ....................................................................... 105
SFR Definition 16.4. ACC: Accumulator ..................................................................... 105
SFR Definition 16.5. B: B Register .............................................................................. 106
SFR Definition 16.6. PSW: Program Status Word ...................................................... 107
SFR Definition 18.1. EMI0CN: External Memory Interface Control ............................ 113
SFR Definition 18.2. EMI0CF: External Memory Configuration .................................. 114
SFR Definition 18.3. EMI0TC: External Memory Timing Control ................................ 119
SFR Definition 19.1. HWID: Hardware Identification Byte .......................................... 128
SFR Definition 19.2. DERIVID: Derivative Identification Byte ..................................... 128
SFR Definition 19.3. REVID: Hardware Revision Identification Byte .......................... 129
SFR Definition 20.1. SFRPAGE: SFR Page ............................................................... 132
SFR Definition 21.1. IE: Interrupt Enable .................................................................... 140
SFR Definition 21.2. IP: Interrupt Priority .................................................................... 141
SFR Definition 21.3. EIE1: Extended Interrupt Enable 1 ............................................ 142
SFR Definition 21.4. EIE2: Extended Interrupt Enable 2 ............................................ 143
C8051F70x/71x
14 Rev. 1.0
SFR Definition 21.5. EIP1: Extended Interrupt Priority 1 ............................................ 144
SFR Definition 21.6. EIP2: Extended Interrupt Priority 2 ............................................ 145
SFR Definition 21.7. IT01CF: INT0/INT1 Configuration .............................................. 147
SFR Definition 22.1. PSCTL: Program Store R/W Control ......................................... 153
SFR Definition 22.2. FLKEY: Flash Lock and Key ...................................................... 154
SFR Definition 23.1. EEADDR: EEPROM Byte Address ............................................ 156
SFR Definition 23.2. EEDATA: EEPROM Byte Data .................................................. 157
SFR Definition 23.3. EECNTL: EEPROM Control ...................................................... 158
SFR Definition 23.4. EEKEY: EEPROM Protect Key .................................................. 159
SFR Definition 24.1. PCON: Power Control ................................................................ 162
SFR Definition 25.1. VDM0CN: VDD Monitor Control ................................................ 166
SFR Definition 25.2. RSTSRC: Reset Source ............................................................ 168
SFR Definition 26.1. WDTCN: Watchdog Timer Control ............................................ 170
SFR Definition 27.1. CLKSEL: Clock Select ............................................................... 172
SFR Definition 27.2. OSCICL: Internal H-F Oscillator Calibration .............................. 173
SFR Definition 27.3. OSCICN: Internal H-F Oscillator Control ................................... 174
SFR Definition 27.4. OSCXCN: External Oscillator Control ........................................ 176
SFR Definition 28.1. XBR0: Port I/O Crossbar Register 0 .......................................... 190
SFR Definition 28.2. XBR1: Port I/O Crossbar Register 1 .......................................... 191
SFR Definition 28.3. P0MASK: Port 0 Mask Register ................................................. 192
SFR Definition 28.4. P0MAT: Port 0 Match Register .................................................. 193
SFR Definition 28.5. P1MASK: Port 1 Mask Register ................................................. 193
SFR Definition 28.6. P1MAT: Port 1 Match Register .................................................. 194
SFR Definition 28.7. P0: Port 0 ................................................................................... 195
SFR Definition 28.8. P0MDIN: Port 0 Input Mode ....................................................... 195
SFR Definition 28.9. P0MDOUT: Port 0 Output Mode ................................................ 196
SFR Definition 28.10. P0SKIP: Port 0 Skip ................................................................. 196
SFR Definition 28.11. P0DRV: Port 0 Drive Strength ................................................. 197
SFR Definition 28.12. P1: Port 1 ................................................................................. 197
SFR Definition 28.13. P1MDIN: Port 1 Input Mode ..................................................... 198
SFR Definition 28.14. P1MDOUT: Port 1 Output Mode .............................................. 198
SFR Definition 28.15. P1SKIP: Port 1 Skip ................................................................. 199
SFR Definition 28.16. P1DRV: Port 1 Drive Strength ................................................. 199
SFR Definition 28.17. P2: Port 2 ................................................................................. 200
SFR Definition 28.18. P2MDIN: Port 2 Input Mode ..................................................... 200
SFR Definition 28.19. P2MDOUT: Port 2 Output Mode .............................................. 201
SFR Definition 28.20. P2SKIP: Port 2 Skip ................................................................. 201
SFR Definition 28.21. P2DRV: Port 2 Drive Strength ................................................. 202
SFR Definition 28.22. P3: Port 3 ................................................................................. 202
SFR Definition 28.23. P3MDIN: Port 3 Input Mode ..................................................... 203
SFR Definition 28.24. P3MDOUT: Port 3 Output Mode .............................................. 203
SFR Definition 28.25. P3DRV: Port 3 Drive Strength ................................................. 204
SFR Definition 28.26. P4: Port 4 ................................................................................. 204
SFR Definition 28.27. P4MDIN: Port 4 Input Mode ..................................................... 205
SFR Definition 28.28. P4MDOUT: Port 4 Output Mode .............................................. 205
C8051F70x/71x
Rev. 1.0 15
SFR Definition 28.29. P4DRV: Port 4 Drive Strength ................................................. 206
SFR Definition 28.30. P5: Port 5 ................................................................................. 206
SFR Definition 28.31. P5MDIN: Port 5 Input Mode ..................................................... 207
SFR Definition 28.32. P5MDOUT: Port 5 Output Mode .............................................. 207
SFR Definition 28.33. P5DRV: Port 5 Drive Strength ................................................. 208
SFR Definition 28.34. P6: Port 6 ................................................................................. 208
SFR Definition 28.35. P6MDIN: Port 6 Input Mode ..................................................... 209
SFR Definition 28.36. P6MDOUT: Port 6 Output Mode .............................................. 209
SFR Definition 28.37. P6DRV: Port 6 Drive Strength ................................................. 210
SFR Definition 29.1. CRC0CN: CRC0 Control ........................................................... 215
SFR Definition 29.2. CRC0IN: CRC Data Input .......................................................... 216
SFR Definition 29.3. CRC0DATA: CRC Data Output ................................................. 216
SFR Definition 29.4. CRC0AUTO: CRC Automatic Control ........................................ 217
SFR Definition 29.5. CRC0CNT: CRC Automatic Flash Sector Count ....................... 217
SFR Definition 29.6. CRC0FLIP: CRC Bit Flip ............................................................ 218
SFR Definition 30.1. SMB0CF: SMBus Clock/Configuration ...................................... 225
SFR Definition 30.2. SMB0CN: SMBus Control .......................................................... 227
SFR Definition 30.3. SMB0ADR: SMBus Slave Address ............................................ 229
SFR Definition 30.4. SMB0ADM: SMBus Slave Address Mask .................................. 230
SFR Definition 30.5. SMB0DAT: SMBus Data ............................................................ 231
SFR Definition 31.1. SPI0CFG: SPI0 Configuration ................................................... 248
SFR Definition 31.2. SPI0CN: SPI0 Control ............................................................... 249
SFR Definition 31.3. SPI0CKR: SPI0 Clock Rate ....................................................... 250
SFR Definition 31.4. SPI0DAT: SPI0 Data ................................................................. 250
SFR Definition 32.1. SCON0: Serial Port 0 Control .................................................... 259
SFR Definition 32.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 260
SFR Definition 33.1. CKCON: Clock Control .............................................................. 263
SFR Definition 33.2. TCON: Timer Control ................................................................. 268
SFR Definition 33.3. TMOD: Timer Mode ................................................................... 269
SFR Definition 33.4. TL0: Timer 0 Low Byte ............................................................... 270
SFR Definition 33.5. TL1: Timer 1 Low Byte ............................................................... 270
SFR Definition 33.6. TH0: Timer 0 High Byte ............................................................. 271
SFR Definition 33.7. TH1: Timer 1 High Byte ............................................................. 271
SFR Definition 33.8. TMR2CN: Timer 2 Control ......................................................... 275
SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 276
SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 276
SFR Definition 33.11. TMR2L: Timer 2 Low Byte ....................................................... 277
SFR Definition 33.12. TMR2H Timer 2 High Byte ....................................................... 277
SFR Definition 33.13. TMR3CN: Timer 3 Control ....................................................... 281
SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 282
SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 282
SFR Definition 33.16. TMR3L: Timer 3 Low Byte ....................................................... 283
SFR Definition 33.17. TMR3H Timer 3 High Byte ....................................................... 283
SFR Definition 34.1. PCA0CN: PCA Control .............................................................. 295
SFR Definition 34.2. PCA0MD: PCA Mode ................................................................ 296
C8051F70x/71x
16 Rev. 1.0
SFR Definition 34.3. PCA0PWM: PCA PWM Configuration ....................................... 297
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 298
SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 299
SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte ..................................... 299
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 300
SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte ........................... 300
C2 Register Definition 35.1. C2ADD: C2 Address ...................................................... 301
C2 Register Definition 35.2. DEVICEID: C2 Device ID ............................................... 302
C2 Register Definition 35.3. REVID: C2 Revision ID .................................................. 302
C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control ........................ 303
C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data ............................ 303
C8051F70x/71x
Rev. 1.0 17
1. System Overview
C8051F70x/71x devices are fully integrated, system-on-a-chip, capacitive sensing mixed-signal MCUs.
Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part
ordering numbers.
High-speed pipeli ned 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Capacitive Sense interface with 38 input channels
10-bit 500 ksps single-ended ADC with 16 external channels and integrated temperature sen sor
Precision calibrated 24.5 MHz internal oscillator
16 kB of on-chip Flash memory
512 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general -purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with three capture/compare modules
On-chip internal voltage reference
On-chip Watchdog timer
On-chip Power-On Reset and Supply Monitor
On-chip Vol tage Comparator
54 general purpose I/O
With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F70x/71x
devices are tru ly stand-a lone, syste m-o n-a -chip so lutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peri pherals for
power savings.
The C8051F70x/71x processors include Silicon Laboratories’ 2-Wire C2 Debug and Programming inter-
face, which allows non-intrusive (uses no o n-chip resources), full speed, in-circuit de bugging using the pro-
duction MCU install ed in the final ap plication. This debug logic support s inspection of memory, viewing and
modification of special function registers, setting breakpoint s, sing le stepping, and run and ha lt comma nds.
All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins
can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant
of input signals up to 2 V above the VDD supply, with the exception of P0.3. See Table 2.1 for ordering
information. Block diagrams of the devices in the C8051F70x/71x family are shown in Fig ure 1.1.
C8051F70x/71x
18 Rev. 1.0
Figure 1.1. C8051F700/1 Block Diagram
System Clock
Configuration
Debug /
Programming
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 3
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
External
Clock
Circuit
Precision
Inte r nal
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
External Memory
Interface
Control
Address
Data
P6
P4 / P3
P5
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
. . .
. . .
P0.0 / VRE F
P0.1 / AGN D
P0.2 / XTAL 1
P0.3 / XTAL 2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.5
Capacitive
Sense
(‘F700 Only)
CIP-51 8051
Co ntro ller C o re
256 Byte RAM
256 Byte XRAM
32 Bytes EEPROM
15 kB Flash Memory
C2CK/RST
C2D
C8051F70x/71x
Rev. 1.0 19
Figure 1.2. C8051F702/3 Block Diagram
System Clock
Configuration
Debug /
Programming
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 3
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
External
Clock
Circuit
Precision
Internal
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
XTAL1
Regulator Core Power
VDD
GND
Periphera l Pow er
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
Ex ternal Memo r y
Interface
Control
Address
Data
P6
P4 / P3
P5
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
. . .
. . .
P0.0 / VREF
P0.1 / AGND
P0.2 / XTAL1
P0.3 / XTAL2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.5
Capacitive
Sense
(‘F702 Only)
CIP-51 8051
Co ntr olle r Core
16 kB Flash Memory
256 Byte RAM
256 Byte XRAM
C2CK/RST
C2D
C8051F70x/71x
20 Rev. 1.0
Figure 1.3. C8051F704/5 Block Diagram
System C lock
Configuration
Debug /
Programming
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 4
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
CIP-51 8051
Controller Core
256 Byte RAM
External
Clock
Circuit
Precision
Intern a l
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
256 Byte XRAM
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
32 Bytes EEPROM
Cap acitive
Sense
15 kB Flash Memory
(‘F70 4 O n ly)
. . .
. . .
. . .
. . .
. . .
P0.0 / VREF
P0.1 / AGND
P0 .2 / X T AL 1
P0 .3 / X T AL 2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0
P2.7
P3.0
P3.7
P4.0
P4.3
P5.0
P5.7
P6.0
P6.5
(8 I/O)
(8 I/O)
(8 I/O)
(4 I/O)
(6 I/O)
C2CK/RST
C2D
C8051F70x/71x
Rev. 1.0 21
Figure 1.4. C8051F706/07 Block Diagram
System Clock
Configuration
Debug /
Programm ing
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 4
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
CIP-51 8051
Con troller Co re
16 kB Flash Mem ory
256 Byte RAM
External
Clock
Circuit
Precision
Intern a l
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
256 Byte XRAM
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
. . .
. . .
P0.0 / VREF
P0.1 / AGND
P0.2 / XTAL1
P0.3 / XTAL2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0
P2.7
P3.4
P3.7
P4.0
P4.3
P5.0
P5.7
P6.3
P6.5
Capacitive
Sense
(‘F706 Only)
(8 I/O )
(4 I/O )
(8 I/O )
(4 I/O )
(3 I/O )
C2CK/RST
C2D
C8051F70x/71x
22 Rev. 1.0
Figure 1.5. C8051F708/09/10/11 Block Diagram
System Clock
Configuration
Debug /
Programming
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 3
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
External
Clock
Circuit
Precision
Internal
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
External M e mory
Interface
Control
Address
Data
P6
P4 / P3
P5
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
. . .
. . .
P0.0 / VREF
P0.1 / AGND
P0.2 / XTAL1
P0.3 / XTAL2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.5
Capacitive
Sense
CIP-51 8051
Controller Core
256 Byte RAM
256 Byte XRAM
8 kB Flash Memory
(‘F708/10 Only)
32 Bytes EEPROM
(‘F708/09 Only)
C2CK/RST
C2D
C8051F70x/71x
Rev. 1.0 23
Figure 1.6. C8051F712/13/14/15 Block Diagram
System Clock
Configuration
Debug /
Programm ing
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 4
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
CIP-51 8051
C o ntro ller Core
8 kB F lash Me m ory
256 Byte RA M
External
Clock
Circuit
Precision
Internal
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
256 Byte XRAM
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
XTem p S ensor
Comparator
+
-
VDD
VDD
VREF
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
. . .
. . .
P0 .0 / VREF
P0 .1 / AGN D
P0 .2 / XTAL 1
P0 .3 / XTAL 2
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0
P2.7
P3.4
P3.7
P4.0
P4.3
P5.0
P5.7
P6.3
P6.5
Capacitive
Sense
(8 I/O )
(4 I/O )
(8 I/O )
(4 I/O)
(3 I/O )
32 Bytes EEPROM
(‘F71 2 /13 O n ly)
(‘F712/14 Only)
C2CK/RST
C2D
C8051F70x/71x
24 Rev. 1.0
Figure 1.7. C8051F716 Block Diagram
System C lock
Configuration
Debug /
Programming
Hardware
Digital Peripherals
UART
Timers 0,
1, 2, 4
SMBus
Priority
Crossbar
Decoder
Crossbar Control
Port I/O C onfiguration
CIP-51 8051
Co n tro lle r C o re
16 kB F lash M e m ory
256 Byte RAM
External
Clock
Circuit
Precision
Internal
Oscillator
XTAL2
Power On
Reset
Reset
SYSCLK
256 Byte XRAM
XTAL1
Regulator Core Power
VDD
GND
Peripheral Power
Analog Peripherals
10-bit
500 ksp s
ADC
A
M
U
XTemp Sensor
Comparator
+
-
VDD
VDD
VREF
SFR
Bus
PCA
WDT
SPI
Timer 3 /
RTC
Port 0
Drivers
Port 2
Drivers
Port 3
Drivers
Port 5
Drivers
Port 6
Drivers
. . .
. . .
. . .
P0.3 / XTAL2
P0.4
P0.5
P2.0
P2.7
P3.0
P3.6
P5.0
P5.7
P6.3
P6.5
Cap acitive
Sense
(8 I/O)
(7 I/O)
(8 I/O)
P6.4
C2CK/RST
C2D
C8051F70x/71x
Rev. 1.0 25
Figure 1.8. C8051F717 Block Diagram
C8051F70x/71x
Rev. 1.0 26
2. Ordering Information
All C8051F70x/71x devices have the following features:
25 MIPS (Peak)
Calibrated Internal Oscillator
SMBus/I2C
UART
Programmable counter array (3 channels)
4 Timers (16-bit)
1 Comparator
Pb-Free (RoHS compliant) package
512 bytes RAM
In addition to the features listed abov e, each device in the C805 1F70x/71x family has a set of features that
vary across the produc t line . See Table 2.1 for a complete list of the uniq ue fe atur e sets for each de vice in
the family.
C8051F70x/71x
27 Rev. 1.0
Table 2.1. Product Selection Guide
Part
Number
Digital
Port I/Os
Capacitive Sense
Channels
Flash
Memory
(kB)
EEPROM
(Bytes)
External Memory
Interface
10-bit
500 ksps
ADC
ADC
Channels
Temperature
Sensor
Package (RoHS)
C8051F700-GQ 54 38 15 32 Y Y 16 Y TQFP-64
C8051F701-GQ 54 38 15 32 Y N — —TQFP-64
C8051F702-GQ 54 38 16 —Y Y 16 Y TQFP-64
C8051F703-GQ 54 38 16 — Y N — —TQFP-64
C8051F704-GQ 39 27 15 32 N Y 12 Y TQFP-48
C8051F704-GM 39 27 15 32 N Y 12 Y QFN-48
C8051F705-GQ 39 27 15 32 N N — — TQFP-48
C8051F705-GM 39 27 15 32 N N — — QFN-48
C8051F706-GQ 39 27 16 —NY12YTQFP-48
C8051F706-GM 39 27 16 —NY12YQFN-48
C8051F707-GQ 39 27 16 — N N — — TQFP-48
C8051F707-GM 39 27 16 — N N — — QFN-48
C8051F708-GQ 54 38 8 32 Y Y 16 Y TQFP-64
C8051F709-GQ 54 38 832YN — —TQFP-64
C8051F710-GQ 54 38 8 — Y Y 16 Y TQFP-64
C8051F711-GQ 54 38 8 — Y N — —TQFP-64
C8051F712-GQ 39 27 832NY12YTQFP-48
C8051F712-GM 39 27 832NY12YQFN-48
C8051F713-GQ 39 27 832NN — — TQFP-48
C8051F713-GM 39 27 832NN — — QFN-48
C8051F714-GQ 39 27 8 — NY12YTQFP-48
C8051F714-GM 39 27 8 — NY12YQFN-48
C8051F715-GQ 39 27 8 — N N — — TQFP-48
C8051F715-GM 39 27 8 — N N — — QFN-48
C8051F716-GM 29 26 16 —NY3YQFN-32
C8051F717-GM 20 18 16 — N N — — QFN-24
Lead finish material on all devices is 100% matte tin (Sn).
C8051F70x/71x
Rev. 1.0 28
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F70x/71x
Name TQFP64 TQFP48
QFN48 QFN32 QFN24 Type Description
VDD 8, 24,
41, 57 8, 20, 44 27 21 Power Supply Voltage.
GND 9, 25,
40, 56 9, 21,
30, 43 Center 20 Ground.
RST /
C2CK
58 45 28 22 D I/O
D I/O
Device Reset. Open-drain output of internal
POR or VDD monitor.
Clock signal for the C2 Debug Interface.
C2D 59 46 29 23 D I/O Bi-directional data signal for the C2 Debug
Interface.
P0.0 /
VREF
55 42 — — D I/O or
A In
A In
Port 0.0.
ADC0 Input.
External VREF input.
P0.1/
AGND
54 41 — — D I/O or
A In Port 0.1.
ADC0 Input.
External AGND input.
P0.2 /
XTAL1
53 40 — — D I/O or
A In
A In
Port 0.2.
ADC0 Input.
External Clock Pin. This pin can be used for
crystal clock mode.
P0.3 /
XTAL2
52 39 26 — D I/O or
A In
A I/O or
D In
Port 0.3.
ADC0 Input.
External Clock Pin. This pin can be used for
RC, crystal, and CMOS clock modes.
P0.4 51 38 25 19 D I/O or
A In Port 0.4.
ADC0 Input.
P0.5 50 37 24 18 D I/O or
A In Port 0.5.
ADC0 Input.
P0.6 49 36 — — D I/O or
A In Port 0.6.
ADC0 Input.
C8051F70x/71x
29 Rev. 1.0
P0.7 48 35 — — D I/O or
A In Port 0.7.
ADC0 Input.
P1.0 47 34 — — D I/O or
A In Port 1.0.
ADC0 Input.
P1.1 46 33 — — D I/O or
A In Port 1.1.
ADC0 Input.
P1.2 45 32 — — D I/O or
A In Port 1.2.
ADC0 Input.
P1.3 44 31 — — D I/O or
A In Port 1.3.
ADC0 Input.
P1.4 43 — — — D I/O or
A In Port 1.4.
ADC0 Input.
P1.5 42 — — — D I/O or
A In Port 1.5.
ADC0 Input.
P1.6 39 — — — D I/O or
A In Port 1.6.
ADC0 Input.
P1.7 38 — — — D I/O or
A In Port 1.7.
ADC0 Input.
P2.0 37 29 23 17 D I/O or
A In Port 2.0.
CS0 input pin 1.
P2.1 36 28 22 16 D I/O or
A In Port 2.1.
CS0 input pin 2.
P2.2 35 27 21 15 D I/O or
A In Port 2.2.
CS0 input pin 3.
P2.3 34 26 20 14 D I/O or
A In Port 2.3.
CS0 input pin 4.
P2.4 33 25 19 13 D I/O or
A In Port 2.4.
CS0 input pin 5.
P2.5 32 24 18 12 D I/O or
A In Port 2.5.
CS0 input pin 6.
P2.6 31 23 17 11 D I/O or
A In Port 2.6.
CS0 input pin 7.
P2.7 30 22 16 10 D I/O or
A In Port 2.7.
CS0 input pin 8.
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name TQFP64 TQFP48
QFN48 QFN32 QFN24 Type Description
C8051F70x/71x
Rev. 1.0 30
P3.0 29 — 15 — D I/O or
A In Port 3.0.
CS0 input pin 9.
P3.1 28 — 14 — D I/O or
A In Port 3.1.
CS0 input pin 10.
P3.2 27 — 13 — D I/O or
A In Port 3.2.
CS0 input pin 11.
P3.3 26 — 12 — D I/O or
A In Port 3.3.
CS0 input pin 12.
P3.4 23 19 11 — D I/O or
A In Port 3.4.
CS0 input pin 13.
P3.5 22 18 10 — D I/O or
A In Port 3.5.
CS0 input pin 14.
P3.6 21 17 9 — D I/O or
A In Port 3.6.
CS0 input pin 15.
P3.7 20 16 — — D I/O or
A In Port 3.7.
CS0 input pin 16.
P4.0 19 15 — 9 D I/O or
A In Port 4.0.
CS0 input pin 17.
P4.1 18 14 — 8 D I/O or
A In Port 4.1.
CS0 input pin 18.
P4.2 17 13 — 7 D I/O or
A In Port 4.2.
CS0 input pin 19.
P4.3 16 12 — 6 D I/O or
A In Port 4.3.
CS0 input pin 20.
P4.4 15 — — 5 D I/O or
A In Port 4.4.
CS0 input pin 21.
P4.5 14 — — 4 D I/O or
A In Port 4.5.
CS0 input pin 22.
P4.6 13 — — 3 D I/O or
A In Port 4.6.
CS0 input pin 23.
P4.7 12 — — 2 D I/O or
A In Port 4.7.
CS0 input pin 24.
P5.0 11 11 8 - D I/O or
A In Port 5.0.
CS0 input pin 25.
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name TQFP64 TQFP48
QFN48 QFN32 QFN24 Type Description
C8051F70x/71x
31 Rev. 1.0
P5.1 10 10 7 — D I/O or
A In Port 5.0.
CS0 input pin 26.
P5.2 7 7 6 — D I/O or
A In Port 5.2.
CS0 input pin 27
P5.3 6 6 5 — D I/O or
A In Port 5.3.
CS0 input pin 28.
P5.4 5 5 4 — D I/O or
A In Port 5.4.
CS0 input pin 29.
P5.5 4 4 3 — D I/O or
A In Port 5.5.
CS0 input pin 30.
P5.6 3 3 2 — D I/O or
A In Port 5.6.
CS0 input pin 31.
P5.7 2 2 1 — D I/O or
A In Port 5.7.
CS0 input pin 32.
P6.0 1 — — — D I/O Port 6.0.
CS0 input pin 33.
P6.1 64 — — — D I/O Port 6.1.
CS0 input pin 34.
P6.2 63 — — — D I/O Port 6.2.
CS0 input pin 35.
P6.3 62 1 32 — D I/O Port 6.3.
CS0 input pin 36.
P6.4 61 48 31 1 D I/O Port 6.4.
CS0 input pin 37.
P6.5 60 47 30 24 D I/O Port 6.5.
CS0 input pin 38.
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name TQFP64 TQFP48
QFN48 QFN32 QFN24 Type Description
C8051F70x/71x
Rev. 1.0 32
Figure 3.1. C8051F7xx-GQ TQFP64 Pinout Diagram (Top View)
C8051F700/01/02/03/08/09/10/11
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P6.1
P6.2
P6.3
P6.4
P6.5
C2D
RST/C2CK
VDD
GND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
VDD
GND
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P6.0
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
VDD
GND
P5.1
P5.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P3.7
P3.6
P3.5
P3.4
VDD
GND
P3.3
P3.2
P3.1
P3.0
P2.7
P2.6
P2.5
C8051F70x/71x
33 Rev. 1.0
Figure 3.2. C8051F7xx-GQ QFP48 Pinout Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
P4.3
P0.6
P0.4
P0.3
P0.2
VDD
P1.0
P0.7
P2.4
P2.3
P2.1
P2.0
P0.5
P6.4
P2.2
P6.5
P5.5
GND
P5.0
P5.6
GND
P0.0
P0.1
P6.3
RST/C2CK
C2D
P5.7
GND
13
14
15
16
17
18
19
20
21
22
23
24
P1.2
P1.1
C8051F704/05/06/07/
12/13/14/15
P5.2
VDD
P5.4
P5.3
P5.1
P1.3
P2.5
GND
P2.7
P2.6
VDD
P3.6
P3.5
P3.4
P3.7
P4.2
P4.1
P4.0
C8051F70x/71x
Rev. 1.0 34
Figure 3.3. C8051F7xx-GM QFN48 Pinout Diagram (Top View)
P4.3
P0.6
P0.4
P0.3
P0.2
VDD
P1.0
P0.7
P2.4
P2.3
P2.1
P2.0
P0.5
P6.4
P2.2
P6.5
P5.5
GND
P5.0
P5.6
GND
P0.0
P0.1
P6.3
RST/C2CK
C2D
P5.7
GND
P1.2
P1.1
C8051F704/05/06/07/
12/13/14/15
P5.2
VDD
P5.4
P5.3
P5.1
P1.3
P2.5
GND
P2.7
P2.6
VDD
P3.6
P3.5
P3.4
P3.7
P4.2
P4.1
P4.0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C8051F70x/71x
35 Rev. 1.0
Figure 3.4. C8051F716-GM QFN32 Pinout Diagram (Top View)
3
4
5
1
223
22
21
24
31
32
29
30
C8051F716
6
20
19
27
28
10
11
12
9
13
14
P6.5
P6.3
P6.4
P2.1
P0.5
P2.0
P2.2
P2.3
P2.4
P3.4
P3.6
P3.5
P3.3
P3.2
P3.1
P5.5
P5.7
P5.6
P5.4
P5.3
P5.2
25
26P0.3
P0.4
15
16
P3.0
P2.7
18
17
P2.5
P2.6
7
8
P5.1
P5.0
RST/C2CK
C2D
VDD
GND
C8051F70x/71x
Rev. 1.0 36
Figure 3.5. C8051F717-GM QFN24 Pinout Diagram (Top View)
3
4
5
1
217
16
15
18
23
24
21
22
C8051F717
6
14
13
19
20
8
9
10
7
11
12
RST/C2CK
P6.5
C2D
VDD
GND
P0.4
P2.1
P0.5
P2.0
P2.2
P2.3
P2.4
P4.0
P4.2
P4.1
P2.7
P2.6
P2.5
P4.6
P6.4
P4.7
P4.5
P4.4
P4.3 GND
C8051F70x/71x
Rev. 1.0 37
4. TQFP-64 Package Specifications
Figure 4.1. TQFP-64 Package Drawing
Table 4.1. TQFP-64 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A — — 1.20 E 12.00 BSC.
A1 0.05 — 0.15 E1 10.00 BSC.
A2 0.95 1.00 1.05 L 0.45 0.60 0.75
b 0.17 0.22 0.27 aaa — — 0.20
c 0.09 — 0.20 bbb — — 0.20
D 12.00 BSC. ccc — — 0.08
D1 10.00 BSC. ddd — — 0.08
e 0.50 BSC. Θ0°3.5°7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ACD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
38 Rev. 1.0
Figure 4.2. TQFP-64 PCB Land Pattern
Table 4.2. TQFP-64 PCB Land Pattern Dimensions
Dimension Min Max
C1 11.30 11.40
C2 11.30 11.40
E 0.50 BSC
X0.200.30
Y1.401.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60 μm minimum, all the way around the pad.
Ste ncil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls shou ld be used to assure good
solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
Rev. 1.0 39
5. TQFP-48 Package Specifications
Figure 5.1. TQFP-48 Package Drawing
Table 5.1. TQFP-48 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A — — 1.20 E 9.00 BSC.
A1 0.05 — 0.15 E1 7.00 BSC.
A2 0.95 1.00 1.05 L 0.45 0.60 0.75
b 0.17 0.22 0.27 aaa 0.20
c 0.09 — 0.20 bbb 0.20
D 9.00 BSC. ccc 0.08
D1 7.00 BSC. ddd 0.08
e 0.50 BSC. Θ0° 3.5° 7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-0 26, variation ABC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
40 Rev. 1.0
Figure 5.2. TQFP-48 PCB Land Pattern
Table 5.2. TQFP-48 PCB Land Pattern Dimensions
Dimension Min Max
C1 8.30 8.40
C2 8.30 8.40
E 0.50 BSC
X1 0.20 0.30
Y1 1.40 1.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60 μm minimum, all the way around the pad.
Ste ncil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls shou ld be used to assure good
solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
Rev. 1.0 41
6. QFN-48 Package Specifications
Figure 6.1. QFN-48 Package Drawing
Table 6.1. QFN-48 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A 0.80 0.90 1.00 E2 3.90 4.00 4.10
A1 0.00 — 0.05 L 0.30 0.40 0.50
b 0.18 0.23 0.30 L1 0.00 — 0.10
D 7.00 BSC. aaa — — 0.10
D2 3.90 4.00 4.10 bbb — — 0.10
e 0.50 BSC. ccc — — 0.05
E 7.00 BSC. ddd — — 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. 3.This drawing conforms to JEDEC outline MO-220, variation VKKD-4 except for features D2 and
L which are toleranced per supplie r designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
42 Rev. 1.0
Figure 6.2. QFN-48 PCB Land Pattern
Table 6.2. Q FN-48 PCB Land Pattern Dimensions
Dimension Min Max
e 0.50 BSC
C1 6.80 6.90
C2 6.80 6.90
X1 0.20 0.30
X2 4.00 4.10
Y1 0.75 0.85
Y2 4.00 4.10
Notes:
General
1. All dimensions shown are in mill imeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specificat ion.
3. This Land Pattern Design is based on IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Mat erial Condition (LMC) is calculated
based on a Fabrication Allowance of 0.05 mm.
Solder Mask De si g n
5. All metal p a ds are t o be non-sol der mask defined (NSMD). Cle arance bet ween th e sold er mask and t he metal p ad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste releas e.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 3x3 array of 1.20 mm square openings on 1.40 mm pit ch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder past e is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
C8051F70x/71x
Rev. 1.0 43
7. QFN-32 Package Specifications
Figure 7.1. QFN-32 Package Drawing
Table 7.1. QFN-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.80 0.90 1.00 E2 3.50 3.60 3.70
A1 0.00 0.02 0.05 L 0.30 0.35 0.40
b 0.18 0.25 0.30 L1 0.00 — 0.10
D 5.00 BSC. aaa 0.15
D2 3.50 3.60 3.70 bbb 0.10
e 0.50 BSC. ddd 0.05
E 5.00 BSC. eee 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, L and L1 which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
44 Rev. 1.0
Figure 7.2. QFN-32 Recommended PCB Land Pattern
Table 7.2. Q FN-32 PCB Land Pattern Dimensions
Dimension Min Max Dimension Min Max
C1 4.60 X2 3.60 3.70
C2 4.60 Y1 0.45 0.55
E 0.50 Y2 3.60 3.70
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is base d on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils ).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 1.0 mm openings on a 1.25 mm pitch should be used for the center pad to
assure the proper paste volume.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
C8051F70x/71x
Rev. 1.0 45
8. QFN-24 Package Specifications
Figure 8.1. QFN-24 Package Drawing
Table 8.1. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.70 0.75 0.80 L 0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 — 0.15
b 0.18 0.25 0.30 aaa — — 0.15
D 4.00 BSC. bbb — — 0.10
D2 2.55 2.70 2.80 ddd — — 0.05
e 0.50 BSC. eee — — 0.08
E 4.00 BSC. Z — 0.24 —
E2 2.55 2.70 2.80 Y — 0.18 —
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F70x/71x
46 Rev. 1.0
Figure 8.2. QFN-24 Recommended PCB Land Pattern
Table 8.2. Q FN-24 PCB Land Pattern Dimensions
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X2 2.70 2.80
C2 3.90 4.00 Y1 0.65 0.75
E 0.5 0 BSC Y2 2.70 2.80
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. This Land Pattern Design is base d on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils ).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
C8051F70x/71x
Rev. 1.0 47
9. Electrical Characteristics
9.1. Absolute Maximum Specifications
Table 9.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on RST or any Port I/O Pin
(except P0.3) with respect to GND –0.3 — VDD +2.0 V
Voltage on P0.3 with respect to GND –0.3 — VDD +0.3 V
Voltage on VDD with respect to GND Regulator in Normal Mode
Regulator in Bypass Mode –0.3
–0.3 —
—4.2
1.98 V
V
Maximum Total current through VDD
and GND ——500mA
Maximum output current sunk by RST
or any Port pin ——100mA
Note: S tresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation list ings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
C8051F70x/71x
48 Rev. 1.0
9.2. Electrical Characteristics
Table 9.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Supply Voltage1 Regulator in Normal Mode
Regulator in Bypass Mode 1.8
1.7 3.0
1.8 3.6
1.9 V
V
Digital Supply Current with
CPU Active (Normal Mode2,3)VDD = 1.8 V, Clock = 25 MHz
VDD = 1.8 V, Clock = 1 MHz
VDD = 1.8 V, Clock = 32 kHz
VDD = 3.0 V, Clock = 25 MHz
VDD = 3.0 V, Clock = 1 MHz
VDD = 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
5.0
1.2
175
5.5
1.3
190
6.5
—
—
7.0
—
—
mA
mA
µA
mA
mA
µA
Digital Supply Current with
CPU Inactive (Idle Mode2,3)VDD = 1.8 V, Clock = 25 MHz
VDD = 1.8 V, Clock = 1 MHz
VDD = 1.8 V, Clock = 32 kHz
VDD = 3.0 V, Clock = 25 MHz
VDD = 3.0 V, Clock = 1 MHz
VDD = 3.0 V, Clock = 32 kHz
—
—
—
—
—
—
2.5
180
90
3.2
200
110
4.0
—
—
4.5
—
—
mA
µA
µA
mA
µA
µA
Digital Supply Current
(shutdown)3Stop/suspend mode, Reg On, 25 °C — 80 90 µA
Stop/suspend mode, Reg Bypass, 25 °C — 2 4 µA
Digital Supply RAM Data
Retention Voltage —1.3— V
Specified Operating
Temperature Range –40 — +85 °C
SYSCLK
(system clock frequency) See Note 3. 0 — 25 MHz
Tsysl (SYSCLK low time) 18 — — ns
Tsysh (SYSCLK high time) 18 — — ns
Notes:
1. Analog performance is not guaranteed when VDD is below 1.8 V.
2. Includes bias current for internal voltage regulator.
3. SYSCLK must be at least 32 kHz to enable debugging.
C8051F70x/71x
Rev. 1.0 49
Table 9.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max Units
Output High Voltage High Drive Strength
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
Low Drive Strength
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
VDD –0.7
VDD –0.1
—
VDD –0.7
VDD –0.1
—
—
—
VDD –0.8
—
—
VDD –0.8
—
—
—
—
—
—
V
V
V
V
V
V
Output Low Voltage High Drive Strength
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
Low Drive Strength
IOL = 1.4 mA
IOL = 10 µA
IOL = 4 mA
—
—
—
—
—
—
—
—
1.0
—
—
1.0
0.6
0.1
—
0.6
0.1
—
V
V
V
V
V
V
Input High Voltage 0.75 x VDD ——V
Input Low Voltage — — 0.6 V
Input Leakag e
Current Weak Pullup Off
Weak Pullup On, VIN = 0 V –1
——
25 1
50 µA
µA
Table 9.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage IOL = 8.5 mA,
VDD = 1.8 V to 3.6 V ——0.6V
RST Input High Voltage 0.75 x VDD ——V
RST Input Low Voltage — — 0.3 x VDD VDD
RST Input Pullup Current RST = 0.0 V — 25 50 µA
VDD POR Ramp Time — — 1 ms
VDD Monitor Threshold (VRST) 1.7 1.75 1.8 V
Missing Clock Detector
Timeout Time from last system clock
rising edge to reset initiation 100 500 1000 µs
Reset T ime Delay Delay between r elease of any
reset source and code
execution at location 0x0000
——30µs
Minimum RST Low Time to
Generate a System Reset 15 — — µs
VDD Monitor Turn-on Time VDD = VRST – 0.1 V — 50 — µs
VDD Monitor Supply Current — 25 30 µA
C8051F70x/71x
50 Rev. 1.0
Table 9.5. Internal Voltage Regulator Electrical Characteristics
VDD = 3.0 V, –4 0 to +85 °C unless ot he rwis e sp ec if ied .
Parameter Conditions Min Typ Max Units
Input Voltage Range 1.8 — 3.6 V
Bias Current Normal mode, 25 °C — 80 90 µA
Bypass mode, 25 °C — 2 4 µA
Table 9.6. Flash Electrical Characteristics
Parameter Conditions Min Typ Max Units
Flash Size* C8051F702/3/6/7, C8051F716/7
C8051F700/1/4/5
C8051F708/9, C8051F710/1/2/3/4/5
16384
15360
8192
bytes
bytes
bytes
Endurance (Er as e/ Write) 10000 — — cycles
Erase Cycle Time 25 MHz Clock 15 20 26 ms
Write Cycle Time 25 MHz Clock 15 20 26 µs
Clock Speed During Flash
Write/Erase Operations 1——MHz
*Note: Includes Security Lock Byte.
Table 9.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use facto ry-cal ibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency IFCN = 11b 24 24.5 25 MHz
Oscillator Supply Current 25 °C, VDD = 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
— 350 650 µA
C8051F70x/71x
Rev. 1.0 51
Table 9.8. Capacitive Sense Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Single Conversion Time112-bit Mode
13-bit Mode (default)
14-bit Mode
16-bit Mode
20
21
23
26
29
31
33
38
40
42.5
45
50
µs
Number of Channels 64-pin Packages
48-pin Packages
32-pin Packages
24-pin Packages
38
27
26
18
Channels
Capacitance per Code Default Configuration — 1 — fF
External Capacitive Load CS0CG = 111b (Default)
CS0CG = 000b —
——
—45
500 pF
pF
External Series Impedance CS0CG = 111b (Default) — — 50 kΩ
Quantization Noise12 RMS
Peak-to-Peak —
—3
20 —
—fF
fF
Power Supply Current CS module bias current, 25 °C — 50 60 µA
CS module alone, maximum code
output, 25 °C — 90 105 µA
Wake-on-CS threshold (suspend mode
with regulator and CS module on)3— 130 145 µA
Notes:
1. Conversion time is specified with the default configuratio n.
2. RMS Noise is equivalent to one standard deviation. Peak-to -peak noise encompasses ±3.3 standard
deviations. The RMS noise value is specified with the default configuration.
3. Includes only current from regulator, CS module, and MCU in suspend mode.
C8051F70x/71x
52 Rev. 1.0
Table 9.9. EEPROM Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use facto ry-cal ibrated settings.
Parameter Conditions Min Typ Max Units
Write to EEPROM from RAM — 3 ms
Read of EEPROM to RAM — 50 x TSYSCLK —µs
Endurance (Writes) 300000 — — cy cle s
Clock Speed During EEPROM
Write Operations 1——MHz
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Table 9.10. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 10 bits
Integral Nonlinearity — ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic — ±0.5 ±1 LSB
Offset Error –2 0 2 LSB
Full Scale Error –2 0 2 LSB
Offset Temperature Coef ficient — 45 — ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion 56 60 — dB
Total Harmonic Distortion Up to the 5t h ha rm o nic — 72 — dB
Spurious-Free Dynamic Range — –75 — dB
Conversion Rate
SAR Conversion Clock — — 8.33 MHz
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode 13
11 —
——
—clocks
clocks
Track/Hold Acquisition Time VDD >= 2.0 V
VDD < 2.0 V 300
2.0 —
——
—ns
µs
Throughput Rate — — 500 ksps
Analog Inputs
ADC Input Voltage Range 0 — VREF V
Sampling Capacitance 1x Gain
0.5x Gain —
—5
3—
—pF
pF
Input Multiplexer Impedance — 5 — kΩ
Power Specifications
Power Supply Current Operating Mode, 500 ksps — 600 1000 µA
Power Supply Rejection — –70 — dB
C8051F70x/71x
Rev. 1.0 53
Table 9.11. Power Management Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified. Use facto ry-cal ibrated settings.
Parameter Conditions Min Typ Max Units
Idle Mode Wake-Up time 2 — 3 SYSCLKs
Suspend Mode Wake-Up Time — 250 — ns
Table 9.12. Temperature Sensor Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Linearity — 1 — °C
Slope — 3.27 — mV/°C
Slope Error* — ±65 — µV/°C
Offset Temp = 0 °C — 868 — mV
Offset Error* Temp = 0 °C — ±15.3 — mV
*Note: Represents one standard deviation from the mean.
Table 9.13. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.6 V; –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Internal High-Speed Reference (REFSL[1:0] = 11)
Output Voltage 25 °C ambient 1.55 1.59 1.70 V
Turn-on Time — — 1.7 µs
Supply Current — 200 — µA
External Reference (REF0E = 0)
Input Voltage Range 0 — VDD
Input Current Sample Rate = 500 ksps; VREF = 3.0 V — 7 — µA
C8051F70x/71x
54 Rev. 1.0
Table 9.14. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 300 — ns
CP0+ – CP0– = –100 mV — 200 — ns
Response Time:
Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 400 — ns
CP0+ – CP0– = –100 mV — 350 — ns
Response Time:
Mode 2, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 570 — ns
CP0+ – CP0– = –100 mV — 870 — ns
Response Time:
Mode 3, Vcm* = 1.5 V CP0+ – CP0– = 100 mV — 1500 — ns
CP0+ – CP0– = –100 mV — 4500 — ns
Common-Mode Rejection Ratio — 1 4 mV/V
Positive Hysteresis 1 Mode 2, CP0HYP1–0 = 00 — 0 1 mV
Positive Hysteresis 2 Mode 2, CP0HYP1–0 = 01 2 5 10 mV
Positive Hysteresis 3 Mode 2, CP0HYP1–0 = 10 7 10 20 mV
Positive Hysteresis 4 Mode 2, CP0HYP1–0 = 11 10 20 30 mV
Negative Hysteresis 1 Mode 2, CP0HYN1–0 = 00 — 0 1 mV
Negative Hysteresis 2 Mode 2, CP0HYN1–0 = 01 2 5 10 mV
Negative Hysteresis 3 Mode 2, CP0HYN1–0 = 10 7 10 20 mV
Negative Hysteresis 4 Mode 2, CP0HYN1–0 = 11 10 20 30 mV
Inverting or Non-Inverting Input
Voltage Range –0.25 — VDD + 0.25 V
Input Offset Voltage –7.5 — 7.5 mV
Power Specifications
Power Supply Rejection — 0.1 — mV/V
Powerup Time — 10 — µs
Supply Current at DC Mode 0 — 25 — µA
Mode 1 — 10 — µA
Mode 2 — 3 — µA
Mode 3 — 0.5 — µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
C8051F70x/71x
Rev. 1.0 55
10. 10-Bit ADC (ADC0)
ADC0 on the C8051F700/2/4/6/8 and C8051F710/2/4/6 is a 500 ksps, 10-bit successive-approximation-
register (SAR) ADC with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a pro-
grammable window detector. The ADC is fully configurable under software control via Special Function
Registers. The ADC may be configured to measure various different signals using the analog multiplexer
described in Section “10.5. ADC0 Analog Multiplexer” on page 65. The voltage reference for the ADC is
selected as described in Section “11. Temperature Sensor” on page 67. The ADC0 subsystem is enabled
only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is
in low power shutdown when this bit is logic 0.
Figure 10.1. ADC0 Functional Block Diagram
ADC0CF
AMP0GN0
AD08BE
AD0LJST
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100 CNVSTR Inp ut
Window
Compare
Logic
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN
From
AMUX0 X1 or
X0.5
AMP0GN0
C8051F70x/71x
56 Rev. 1.0
10.1. Output Code Formatting
The ADC measures the input volt age with refe rence to GND. The registers ADC0H and ADC0L contain the
high and low bytes of the output conversion cod e from the ADC at the completion of each conversion. Dat a
can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are
represented as 10-bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example
codes are shown below for both right-justified and left-justified data. Unused bit s in the ADC0H and ADC0L
registers are se t to 0.
10.2. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 w ill put the ADC in 8-bit mode. In 8-bit mode, only the 8
MSBs of data are converted, and the ADC0H register holds the results. The AD0LJST bit is ignored for 8-
bit mode. 8-bit conversions take two fewer SAR clock cycles than 10-bit conversions , so the conv ersion is
completed faster, and a 500 ksps sampling rate can be achieved with a slower SAR clock.
10.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
10.3.1. Starti ng a Conversion
A conversion can be initiated in one of six ways, depen ding on the programmed st ates of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if
Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section
“33. Ti mers” on page 262 for timer configuration.
Import ant Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digi-
tal Crossbar. See Section “28. Port Input/Output” on page 180 for details on Por t I/O configuration.
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
C8051F70x/71x
Rev. 1.0 57
10.3.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin im mediately, without the extra tracking time. For internal start-of-conver-
sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 w ill track either when A D0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 10.2 for track and convert timing details. Delayed conversion mode is
useful when AMUX settings are frequently changed, due to the settling time requirements described in
Section “10.3. 3. Settling Time Requirements” on page 58.
Figure 10.2. 10-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
AD0TM=1 Track Convert Track
AD0TM=0 Track or
Convert Convert Track
SAR
Clocks
SAR
Clocks
B. ADC Timing for Internal Trigger Source
CNVSTR
(AD0CM[2:0]=1xx)
AD0TM=1
A. ADC Timing for External Trigger Source
Track Convert N/CAD0TM=0
Track Convert Track
*Conversion Ends at rising edge of 12th clock i n 8-bit Mode
*Conversion Ends at rising edge of 15th clock i n 8-bit Mode
*Conversion Ends at rising edge of 12th clock i n 8-bit Mode
12345678910 1112*13 14
12345678910 11 12 13 1415*16 17
N/C
SAR Clocks
*Conversion Ends at rising edge of 15th clock i n 8-bit Mode
SAR
Clocks
12345678910 11 12 13 1415*16 17
123456789
10 1112*13 14
C8051F70x/71x
58 Rev. 1.0
10.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 samplin g capacitance, and the accur acy required for the convers ion. In delay ed tracking mode,
three SAR clocks are used for tracking at the start of every conversion. For many applications, these three
SAR clocks will meet the minimum tracking time requirements.
Figure 10.3 shows the equivalent ADC0 input circuit. The required AD C0 settling time for a g iven settling
accuracy (SA) may be approximated by Equation 10.1. See Table 9.10 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Equation 10.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 10.3. ADC0 Equivalent Input Circuits
t2n
SA
-------

RTOTALCSAMPLE
×ln=
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
MUX Select
Input Pin
Note: See electrical specification tables f or RMUX and CSAMPLE parameters.
C8051F70x/71x
Rev. 1.0 59
SFR Address = 0xBC; SFR Page = F
SFR Definition 10.1. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD0LJST AD08BE AMP0GN0
Type R/W R/W R/W R/W
Reset 11111001
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clo ck b y the followin g eq uatio n, wher e
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
2AD0LJSTADC0 Left Justify Selec t.
0: Data in ADC0H:ADC0L registers ar e rig ht-ju stif ied .
1: Data in ADC0H:ADC0L registers ar e left-justif i ed .
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1AD08BE8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0AMP0GN0ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
AD0SC SYSCLK
CLKSAR
-----------------------1–=
C8051F70x/71x
60 Rev. 1.0
SFR Address = 0xBE; SFR Page = 0
SFR Address = 0xBD; SFR Page = 0
SFR Definition 10.2. ADC0H: ADC0 Data Word MSB
Bit76543210
Name ADC0H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7:2 will read 000000b. Bit s 1–0 are the upper 2 bits of the 10-
bit ADC0 Data Word.
For AD0LJST = 1: Bits 7:0 are the most-significant bits of the 10-bit ADC0 Data Word.
Note: In 8-bit mode AD0LJST is ignored, and ADC0H holds the 8-bit data word.
SFR Definition 10.3. ADC0L: ADC0 Data Word LSB
Bit76543210
Name ADC0L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7:0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7:6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
always read 0.
Note: In 8-bit mode AD0LJST is ignored, and ADC0L will read back 00000000b.
C8051F70x/71x
Rev. 1.0 61
SFR Address = 0xE8; SFR Page = All Pages; Bit-Addressable
SFR Definition 10.4. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM[2:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7AD0ENADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6AD0TMADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continu o us unle ss a con -
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A star t-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion.
5AD0INTADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a da ta conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4AD0BUSYADC0 Busy Bit. Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[2:0] =
000b
3 AD0WINT ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data ma tch has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
11x: Res erved.
C8051F70x/71x
62 Rev. 1.0
10.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limit s, and notifies the system whe n a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comp arison values. The window detector flag can be programmed to in dicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Address = 0xC4; SFR Page = 0
SFR Address = 0xC3; SFR Page = 0
SFR Definition 10.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit76543210
Name ADC0GTH[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 10.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit76543210
Name ADC0GTL[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
C8051F70x/71x
Rev. 1.0 63
SFR Address = 0xC6; SFR Page = 0
SFR Address = 0xC5; SFR Page = 0
SFR Definition 10.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit76543210
Name ADC0LTH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 10.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit76543210
Name ADC0LTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTL[7:0] ADC0 Less-T han Data Word Low-Order Bits.
C8051F70x/71x
64 Rev. 1.0
10.4.1. Window Detector Example
Figure 10.4 shows two example window comparisons for right-justified data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 10.5 shows an example using left-justi-
fied data with the same comparison values.
Figure 10.4. ADC Window Compare Example: Right-Justified Data
Figure 10.5. ADC Window Compare Example: Left-Justified Data
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
C8051F70x/71x
Rev. 1.0 65
10.5. ADC0 Analog Multiplexer
ADC0 on the C8051F700/2/4/6/8 and C8051F71 0/2/4/6 u ses an ana log inpu t multiplexe r to sel ect the pos-
itive input to the ADC. Any of the following may be selected as the positive input: Port 0 or Port 1 I/O pins,
the on-chip temperature sensor, or the positive power supply (V DD). The ADC0 input channel is selected in
the ADC0MX register described in SFR Definition 10.9.
Figure 10.6. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set the corresponding bit in register PnMDIN to 0. To force the Crossbar to skip a Port pin, set the
correspond ing bit in register PnSKIP to 1. See Section “2 8. Port Input/O utput” on page 180 for more Port
I/O configuration details.
ADC0
Temp
Sensor
AMUX
VREG Output
ADC0MX
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
P0.0
P1.7
VDD
GND
C8051F70x/71x
66 Rev. 1.0
SFR Address = 0xBB; SFR Page = 0
SFR Definition 10.9. ADC0MX: AMUX0 Channel Select
Bit76543210
Name AMX0P[4:0]
Type RRR R/W
Reset 00011111
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Car e.
4:0 AMX0P[4:0] AMUX0 Positive Input Selection.
64-Pin Devices 48-Pin Devices 32-Pin Devices
00000 P0.0 P0.0 —
00001 P0.1 P0.1 —
00010 P0.2 P0.2 —
00011 P0.3 P0.3 P0.3
00100 P0.4 P0.4 P0.4
00101 P0.5 P0.5 P0.5
00110 P0.6 P0.6 —
00111 P0.7 P0.7 —
01000 P1.0 P1.0 —
01001 P1.1 P1.1 —
01010 P1.2 P1.2 —
01011 P1.3 P1.3 —
01100 P1.4 — —
01101 P1.5 — —
01110 P1.6 — —
01111 P1.7 — —
10000 Temp Sensor Temp Sensor Temp Sensor
10001 VREG Output VREG Output VREG Output
10010 VDD VDD VDD
10011 GND GND GND
10100–11111 no input selected
C8051F70x/71x
Rev. 1.0 67
11. Temperature Sensor
An on-chip temperature sensor is included on the C8051F700/2/4/6/8 and C8051F710/2/4/6 which can be
directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the
temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor.
The temperature sensor transfer function is shown in Figure 11.1. The output voltage (VTEMP) is the posi-
tive ADC input when the ADC multiplexer is set correctly. The TEMPE bit in register REF0CN enables/dis-
ables the temperature sensor, as described in SFR Definitio n 12.1. While disabled, the te mperature sensor
defaults to a high impedance state and any ADC measurements performed on the sensor will result in
meaningless data. Refer to Table 9.12 for the slope and offset parameters of the temperature sensor.
Figure 11.1. Temperature Sensor Transfer Function
11.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is r ecommended. Typically a 1-po int (offset) calibration includes the follo wing steps:
1. Control/measure th e ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the ADC’s input.
4. Calculate the offset characteristics, and store this value in non-volatile me mory for use with subseque nt
temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 °C.
Temperature
Voltage
VTEMP = (Slope x TempC) + Offset
Offset (V at 0 Celsius)
Slope (V / deg C)
TempC = (VTEMP - Offset) / Slope
C8051F70x/71x
68 Rev. 1.0
Parameters that affect ADC measurement, in particular the voltage reference value, will also affect tem-
perature measurement.
Figure 11.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00
Temperature (d egrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
C8051F70x/71x
Rev. 1.0 69
12. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, the on-chip
voltage reference, or one of two power supply voltages (see Figure 12.1). The ground reference MUX
allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedi-
cated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 71.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external volt age referen ce, P0.0/VREF should be configured as an analog input and
skipped by the Digital Crossbar. When using AGND as the ground reference to ADC0, P0.1/AGND should
be configured as an analog input and skipp ed by th e Digit al Cro ssbar. Refer to Section “28. Port Input/Out-
put” on page 180 for complete Port I/O configuration det ail s. The external refe renc e volt age must be withi n
the range 0 ≤VREF ≤VDD and the external ground reference must be at the same DC voltage potential as
GND.
Figure 12.1. Voltage Reference Functional Block Diagram
P0.0/VREF
R1
VDD External
Voltage
Reference
Circuit
GND
00
01
10
11
REF0CN
REFSL0
TEMPE
BIASE
REFSL1
REFGND
Recom m ended
Bypass Capacitors
+
4.7 uF 0.1 uF
Internal 1.8 V
Regulated Digital Supply
VDD
Internal 1.6 V
High Speed Reference
GND
P0.1/AGND
REFGND
0
1
To Analog MuxTem p Sensor
EN
Bias Generator
To A DC, In tern a l
Oscillator,
Reference,
TempSensor
EN
IOSCEN
C8051F70x/71x
70 Rev. 1.0
12.1. External Voltage References
To use an external voltage reference, REF SL[1:0] should be set to 00. Bypass capacitors should be adde d
as recommended by the manufacturer of the external voltage reference.
12.2. Internal Voltage Reference Options
A 1.6 V high-speed reference is included on-chip. The high speed internal reference is selected by setting
REFSL[1:0] to 11. When selected, the high-speed internal reference will be automatically enabled on an
as-needed basis by ADC0.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD) or the 1.8 V regulated digital supply voltage as the reference
source, REFSL[1:0] should be set to 01 or 10, respectively.
12.3. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog measure-
ments, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 is taken from the P0.1/AGND pin. Any external sensors sampled by ADC0 should be referenced to
the P0.1/AGND pin. The separate analog ground reference option is enabled by setting REFGND to 1.
Note that when using this option, P0.1/AGND must be connected to the same potential as GND.
12.4. Temperature Sensor Enable
The TEMPE bit in register REF0CN en ab les the te mpe rature sensor. While disabled, the temperature sen-
sor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in
meaningless data.
C8051F70x/71x
Rev. 1.0 71
SFR Address = 0xD2; SFR Page = F
SFR Definition 12.1. REF0CN: Voltage Reference Control
Bit76543210
Name REFGND REFSL TEMPE BIASE
Type R R R/W R/W R/W R/W R/W R
Reset 00010000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5REFGNDAnalog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground refer ence is the P0.1/AGND pin.
4:3 REFSL Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage refere nc e is the VDD pin.
10: The ADC0 voltage refere nc e is the intern al 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.6 V high-speed voltage reference.
2 TEMPE Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1 BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0 Unused Read = 0b; Write = Don’t Care.
C8051F70x/71x
Rev. 1.0 72
13. Voltage Regulator (REG0)
C8051F70x/71x devices include an internal voltage regulator (REG0) to regulate the internal core supply
to 1.8 V from a VDD supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to help
reduce current consumption in low-power applications. These modes are accessed through the REG0CN
register (SFR Definition 13.1). Electrical characteristics for the on-chip regulator are specified in Table 9.5
on page 50
If an external regulator is used to power the device, the internal regulator may be put into bypass mode
using the BYPASS bit. The internal regulator should never be placed in bypass mode unless an
external 1.8 V regulator is used to supply VDD. Doing so could cause permanent damage to the
device.
Under default conditions, when the device enters STOP mode the internal regulator will remain on. This
allows any enabled reset so urce to gene rate a reset for the device and bring the device out of ST OP mode.
For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal
power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin or
a full power cycle of the device are the only methods of generating a reset.
C8051F70x/71x
73 Rev. 1.0
SFR Address = 0xB9; SFR Page = F
SFR Definition 13.1. REG0CN: Voltage Regulator Control
Bit76543210
Name STOPCF BYPASS
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7STOPCFStop Mode Configur ation.
This bit configures the regulator’s behavior when the device enters STOP mode.
0: Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: Regulator is shut do wn in STOP mode. Only the RST pin or power cycle can reset
the device.
6 BYPASS Bypass Internal Regulator.
This bit places the regulator in bypass mod e, allowing the core to run directly from the
VDD supply pin.
0: Normal Mode—Regulator is on and regulates VDD down to the core voltage.
1: Bypass Mode—Regulator is in bypass mode, and the microcontroller core operates
directly from the VDD supply voltage.
IMPORTANT: Bypass mode is for use with an ext ernal regulator as the supply
voltage only. Never place the regulator in bypass mode when the VDD supply
volt age is g reater than t he spe cifications g iven in Table 9.1 on page 47. Doing so
may cause permanent damage to the device.
5:0 Reserved Reserved. Must Write 000000b.
C8051F70x/71x
Rev. 1.0 74
14. Comparator0
C8051F70x/71x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 14.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “28.4. Port I/O Initializ ation” on page 189). Comparator0 ma y also be used as a reset so urce (see
Section “25.5. Comparator0 Reset” on page 167).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“14.1. Comparator Multiplexer” on page 78.
Figure 14.1. Comparator0 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Compar ator output ( if assigne d to a Port I/O pin via the Cr ossbar) defaults to the logic low st ate,
and the power supply to the comparator is turned off. See Section “28.3. Priority Crossbar Decoder” on
page 185 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.2 5 V to (VDD) + 0.25 V without damage or upset. The comple te Comparator elec-
trical specifications are given in Section “9. Electrical Characteristics” on page 47.
VDD
Reset
Decision
Tree
+
- Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
CP0 -
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Interrupt
0
1
0
1
CP0RIF
CP0FIF
0
1
CP0EN 0
1
EA
Comparator
Input Mux
CPT0CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
C8051F70x/71x
75 Rev. 1.0
The Comparator re sponse time may b e configured in software vi a the CPT0MD regis ter (see SFR Defini -
tion 14.2). Selecting a longer response time reduces the Compara tor supply current.
Figure 14.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program bo th the amount of hysteresis volt age (referred to the input volt a ge) and the posi tive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 14.1). The amount of negative hysteresis volt a ge is deter mined by the setting s of
the CP0HYN bits. As shown in Figure 14.2, settings of 20, 10 or 5 mV of negative hysteresis can be pro-
grammed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-e dge and falling-edge output transitions. (For Inter-
rupt enable and prior ity con trol, see Section “2 1.1. MCU Interrupt Sources and Vectors” on p age 138). The
CP0FIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Compar-
ator0 falling-edge interrupt mask is enabled by setting CP0FIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Compar-
ator is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGU RATI ON
+
_
CP0+
CP0- CP0
VIN+
VIN- OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
C8051F70x/71x
Rev. 1.0 76
SFR Address = 0x9B; SFR Page = 0
SFR Definition 14.1. CPT0CN: Comp arator0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 CP0EN Comp arator0 Enable Bit.
0: Comparator0 Disab led .
1: Comparator0 Enab led .
6CP0OUTComparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIFComparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIFComparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F70x/71x
77 Rev. 1.0
SFR Address = 0x9D; SFR Page = 0
SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type RRR/WR/WRR R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, W rite = Don’t Care.
5CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and po wer consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F70x/71x
Rev. 1.0 78
14.1. Comparator Multiplexer
C8051F70x/71x devices include an analog input multiplexer to connect Port I/O pins to the comparator
inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 14.3). The CMX0P2–
CMX0P0 bits select the Comparator0 positive input; the CMX0N2–CMX0N0 bits select the Comparator0
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Po rt co nfigur ation reg ister, and configured to be skipped by th e
Crossbar (for details on Port configuration, see Section “28.6. Special Function Registers for Accessing
and Configuring Port I/O” on page 194).
Figure 14.3. Comparator Input Multiplexer Block Diagram
-
+
CP0 -
CP0 +
CPT0MX
CMX0P0
CMX0P1
CMX0P2
CMX0N2
CMX0N1
CMX0N0
GND
VDD
P1.0
P1.2
P1.4
P1.6
P1.1
P1.3
P1.5
P 1 .7 / P 2 .0 *
*P1.7 on 64 and 48-pin devices, P2.0 on 32 and 24-pin devices
C8051F70x/71x
79 Rev. 1.0
SFR Address = 0x9F; SFR Page = 0
SFR Definition 14.3. CPT0MX: Comparator0 MUX Selection
Bit76543210
Name CMX0N[2:0] CMX0P[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7 Unused Read = 0b; Write = don’t care.
6:4 CMX0N[2:0] Comparator0 Negative Input MUX Selection.
64-Pin Devices 48-Pin Device s 32-Pin Devices 24-Pin Devices
000 P1.1 P1.1 — —
001 P1.3 P1.3 — —
010 P1.5 — — —
011 P1.7 — P2.0 (see note) P2.0 (see note)
100-111 No input
selected. No input
selected. No input
selected. No input
selected.
3 Unused Read = 0b; Write = don’t care.
2:0 CMX0P[2:0] Comparator0 Positive Input MUX Selection.
64-Pin Devices 48-Pin Devices 32-Pin Devices 24-Pin Devices
000 P1.0 P1.0 — —
001 P1.2 P1.2 — —
010 P1.4 — — —
011 P1.6 — (P1.6—see note) (P1.6—see note)
100-111 No input
selected. No input
selected. No input
selected. No input
selected.
Note: On 32 and 24-pin devices, P2.0 can be used as the negative comparator input, for detecting low-level signals
near the GND or VDD supply rails. The P1.6 setting for the positive input should be used in conjunction with
the selection of P2.0 as the negative input. P1.6 should be configured for push-pull mode and driven to the
desired supply rail. Although P1.6 is not connected to a device pin in these packages, it is still a valid signal
internally.
C8051F70x/71x
Rev. 1.0 80
15. Capacitive Sense (CS0)
The Capacitive Sense subsystem uses a capacitance-to-digital circuit to determine the capacitance on a
port pin. The module can take measurements from different port pins using the module’s analog multi-
plexer. The module is enabled only when the CS0EN bit (CS0CN) is set to 1. Otherwise the module is in a
low-power shutdown state. The module can be configured to take measurements on one port pin or a
group of port pins, using auto-scan. A selectable gain circuit allows the designer to adjust the maximum
allowable capacitance. An accumulator is also included, which can be configured to average multiple con-
versions on an input channel. Interrupts can be generated when CS0 completes a conversion or when the
measured value crosses a threshold defined in CS0THH:L.
Figure 15.1. CS0 Block Diagram
Capacitance to
Digital Converter
Timer 0 O ve rflow
Timer 2 O ve rflow
Timer 1 O ve rflow
Start
Conversion
000 CS0BUSY (W )
CS0CMPF
001
010
011
100 Timer 3 Overflow
Greater Than
Compare Logic
101 Initiated con tin uou sly
CS0THH:L
CS0DH:L
Auto-Scan
Logic
CS0SS CS0SE
CS0MX
22-Bit Accumulator
110
111 Initiated continuously
when auto-scan
enabled
Reserved
CS0CN
CS0CMPF
CS0CMPEN
CS0BUSY
CS0INT
CS0PME
CS0EN
CS0CF
CS0ACU0
CS0ACU1
CS0ACU2
CS0CM0
CS0CM1
CS0CM2
AMUX
. . . 1x-8x
CS0MD1
CS0CG0
CS0CG1
CS0CG2
CS0DR0
CS0DR1
CS0MD2
CS0IA0
CS0IA1
CS0IA2
CS0DT0
CS0DT1
CS0DT2
CS0CR0
CS0CR1
CS0PM
CSPMMD0
CSPMMD1
CP0PM
PIOPM
PCAPM
SMBPM
SPIPM
UAPM
Pin Monitor
Port I/O and
Peripherals
12, 13, 14, or 16 bi ts
C8051F70x/71x
81 Rev. 1.0
15.1. Configuring Port Pins as Capacitive Sense Inputs
In order for a po rt pin to be measur ed by CS0, that po rt pin must be con figured as an ana log input (see “28.
Port Input/Output” ). Configuring the input multiplexer to a port pin not configured as an analog input will
cause the capacitance-to-digital converter to output incorrect measurements.
Note: When CS0 begins a conversion to measure capacitance on a port pin, CS0 grounds all other port pins that
meet the following requirements:
- The port pin is accessible by the CS0 input multip lexer.
- The port pin is configured as an analog input.
- The port latch contains a 0.
15.2. CS0 Gain Adjustment
The gain of the CS0 circuit can be adjusted in integer increments from 1x to 8x (8x is the default). High
gain gives the best sensitivity and resolution for small capacitors, such as those typically implemented as
touch-sensitive PCB features. To measure larger capacitance values, the gain can be lowered. However,
lower gain values will af fect the o verall conversio n time. SeeTable 15.1 for more details on the gain adjust-
ment. The bits CS0CG[2:0] in regist er CS0M D1 set th e ga in va lue .
15.3. Capacitive Sense Start-Of-Conversion Sources
A capacitive sense conversion can be initiated in one of seven ways, depending on the programmed state
of the CS0 start of conversion bits (CS0CF6:4). Conversions may be initiated by one of the following:
1. Writing a 1 to the CS0BUSY bit of register CS0CN
2. Timer 0 over flow
3. Timer 2 over flow
4. Timer 1 over flow
5. Timer 3 over flow
6. Convert continuously
7. Convert continuously with auto-scan enabled
Table 15.1. Gain Setting vs. Maximum Capacitance and Conversion Time
CS0CG[2:0] (Gain) Maximum Total Capacitance (pF)1Conversion Time (µs)2
000b (1x) 520 178
001b (2x) 260 93
010b (3x) 175 66
011b (4x) 130 52
100b (5x) 105 43
101b (6x) 85 38
110b (7x) 75 34
111b (8x) 65 31
Notes:
1. The maximum total capacitance values listed in this table are for guidance only, and are not a specification.
The total measured capacit ance will include internal capacita nce as well as external parasitics, and the actual
external capacitance being measured. Please refer to the Electrical Specifications for details on the maximum
external capacitance.
2. Conversion times are nominal, and listed for 13-bit conversions with all other CS0 settings at their defa ult
values.
C8051F70x/71x
Rev. 1.0 82
If CS0BUSY is used to initiate conversions, and then polled to determine if the conversion is finished, at
least one clock cycle must be inserted between setting CS0BUSY to 1 and polling the CS0BUSY bit.
Conversions can be configured to be initiated continuously through one of two methods. CS0 can be con-
figured to convert at a single channel continuously or it can be configured to convert continuously with
auto-scan enabled. When configured to convert continuously, conversions will begin after the CS0BUSY
bit in CS0CF has been set. An interrupt will be generated if CS0 conversion complete interrupts are
enabled by setting the ECSCPT bit (EIE2.0).
The CS0 module uses a method of successive a pproxim ation to d etermine the valu e of an exter nal capac-
itance. The number of bits the CS0 module converts is adjustable using the CS0CR bits in register
CS0MD2. Conversions are 13 bits long by default, but they can be adjusted to 12, 13, 14, or 16 bits
depending on the needs of the application. Unconverted bits will be set to 0. Shorter conversion lengths
produce faster conversion rates, and vice-versa. Applications can take advantage of faster conversion
rates when the unconverted bits fall below the noise floor.
Note: CS0 conversion complete interrupt behavior depends on the settings of the CS0 accumulator. If CS0 is
configured to accumulate multiple conversions on an input channel, a CS0 conversion complete interrupt will
be generated only after the last conversion completes.
C8051F70x/71x
83 Rev. 1.0
15.4. Automatic Scanning
CS0 can be configured to automatically scan a seque nc e of co ntigu ous CS0 input channe ls by co nfigu ring
and enabling auto-scan. Using auto-scan with the CS0 comparator interrupt enabled allows a system to
detect a change in measured capacitance without requiring any additional dedicated MCU resources.
Auto-scan is enabled by setting the CS0 start-of-conversion bits (CS0CF6:4 ) to 111b. After enabling auto -
scan, the sta rting an d en ding chan nel s sho uld be set to appr op riate va lues in CS0SS and CS0 SE, respe c-
tively. Writing to CS0SS when auto-scan is enabled will cause the value written to CS0SS to be copied into
CS0MX. After being enabled, writing a 1 to CS0BUSY will start auto-scan conversions. When auto-scan
completes the number of conversions defined in the CS0 accumulator bits (CS0CF2:0), auto-scan config-
ures CS0MX to the next sequential port pin configured as an analog input an d begins a conversion o n that
channel. The scan sequence continues until CS0MX reaches the ending input channel value defined in
CS0SE.
Note: All other CS0 pins configured for analog input with a 0 in the port latch are grounded during the conversion.
After the final channel conversion, auto-scan configures CS0MX back to the starting input channel. For an
example system configured to use auto-scan, pleas e see Figure “15.2 Auto-Scan Example” on page 83.
Note: Auto-scan attempts one conversion on a CS0MX channel regardless of whether that channel’s port pin has
been configured as an analog input. Auto-scan will also complete the current rotation when the device is halted
for debugging.
If auto-scan is enabled when the device enters suspend mode, auto-scan will remain enabled and running.
This feature allows the device to wake from suspend through CS0 greater-than comparator event on any
configured capacitive sense input included in the auto-scan sequence of inputs.
Figure 15.2. Auto-Scan Example
SFR Configuration:
A
D
A
A
D
D
D
D
D
A
A
A
A
A
A
A
P2.0
PxMDIN bit
Port Pin
0
CS0MX
Channel
P2.1 1
P2.2 2
P2.3 3
P2.4 4
P2.5 5
P2.6 6
P2.7 7
P3.0 8
P3.1 9
P3.2 10
P3.3 11
P3.4 12
P3.5 13
P3.6 14
P3.7 15
CS0SS = 0x02
CS0S E = 0 x0D
P2MDIN = 0xF2
P3MDIN = 0x04
CS0CF = 0x70
CS0CN = 0x80 Enables CS0
Enables Auto-scan
as start-of-
conversion source
Sets P2 .2 as Auto-
scan starting channel
Sets P3 .5 as Auto-
scan ending channel
Configures P2.3,
P2.2, P2.0 as analog
inputs
Configures P3.0-P3.1
and P3.3-P3.7 as
analog inputs
Scans on channels
not configured as
analog inputs result
in indeterminate
values that cannot
trigger a CS0
Greater Than
Interrupt e ven t
C8051F70x/71x
Rev. 1.0 84
15.5. CS0 Comparator
The CS0 comparator compares the latest capacitive sense conversion result with the value stored in
CS0THH:CS0THL. If the result is less than or equal to the stored value, the CS0CMPF bit( CS0CN:0) is set
to 0. If the result is greater than the stored value, CS0CMPF is set to 1.
If the CS0 conversion accumulator is configured to accumulate multiple conversions, a comparison will not
be made until the last conversion has been accumulated.
An interrupt will be generated if CS0 greater-than comparator interrupts are enabled by setting the ECS-
GRT bit (EIE2.1) when the comparator sets CS0CMPF to 1.
If auto-scan is running when the comparator sets the CS0CMPF bit, no further auto-scan initiated conver-
sions will start until firmware sets CS0BUSY to 1.
A CS0 greater-than comparator event can wake a device from suspend mode. This featur e is useful in sys-
tems configured to continuously sample one or more capacitive sense channels. The device will remain in
the low-power suspend state until the captured value of one of the scanned channels causes a CS0
greater-than comparator event to occur. It is not necessary to have CS0 comparator interrupts enabled in
order to wake a device from susp end with a greater-than event.
For a summary of behavior with different CS0 comparator, auto-scan, and auto accumulator settings,
please see Table 15.2.
C8051F70x/71x
85 Rev. 1.0
15.6. CS0 Conversion Accumulator
CS0 can be configured to accumulate multiple conversi ons on an inpu t channel. The number of samples to
be accumulated is config ured using the CS0ACU2:0 bits (CS0CF2:0). Th e accu mulato r can accumu late 1,
4, 8, 16, 32, or 64 samples. After the defined number of samples have been accumulated, the result is
divided by either 1, 4, 8, 16, 32, or 64 (depending on the CS0ACU[2:0] setting) and copied to the
CS0DH:CS0DL SFRs.
Table 15.2. Operation with Auto-scan and Accumulate
Auto-Scan Enabled
Accumulator Enabled
CS0 Conversion
Complete
Interrupt
Behavior
CS0 Greater Than Interrupt
Behavior CS0MX Behavior
NNCS0INT Interrupt
serviced after 1
conversion com-
pletes
Interrupt serviced after 1 con-
version completes if value in
CS0DH:CS0DL is greater than
CS0THH:CS0THL
CS0MX unchanged.
NYCS0INT Interrupt
serviced after M
conversions com-
plete
Interrupt serviced after M con-
versions complete if value in
CS0DH:CS0DL (post accumu-
late and divide) is greater than
CS0THH:CS0THL
CS0MX unchanged.
YNCS0INT Interrupt
serviced after 1
conversion com-
pletes
Interrupt serviced after con-
version completes if value in
CS0DH:CS0DL is greater than
CS0THH:CS0THL;
Auto-Scan stopped
If greater-than comparator detects conver-
sion value is greate r th an
CS0THH:CS0THL, CS0MX is left
unchanged; otherwise, CS0MX updates to
the next channel (CS0MX + 1) and wrap s
back to CS0SS after passing CS0SE
YYCS0INT Interrupt
serviced after M
conversions com-
plete
Interrupt serviced after M con-
versions complete if value in
CS0DH:CS0DL (post accumu-
late and divide) is greater than
CS0THH:CS0THL; Auto-Scan
stopped
If greater-than comparator detects conver-
sion value is greate r th an
CS0THH:CS0THL, CS0MX is left
unchanged; otherwise, CS0MX updates to
the next channel (CS0MX + 1) and wrap s
back to CS0SS after passing CS0SE
M = Accumulator setting (1x, 4x , 8x, 16x, 32x, 64x)
C8051F70x/71x
Rev. 1.0 86
15.7. CS0 Pin Monitor
The CS0 module provides accurate conversions in all operating modes of the CPU, peripherals and I/O
ports. Pin monitoring circuits are provided to improve interference immunity from high-current output pin
switching. The Capacitive Sense Pin Monitor register (CS0PM, SFR Definition 15.9) controls the operation
of these pin monitors.
Conversions in the CS0 module are immune to any change on digital inputs and immune to most output
switching. Even high-speed serial data transmission will not affect CS0 operation as long as the output
load is limited. Output changes that switch large loads such as LEDs and heavily-loaded communications
lines can affect conv er sio n a cc ur ac y. For this reason, the CS0 modu le inc l ud es p in m o nit or ing cir cu i ts that
will, if enabled, automatically adjust conversion timing if necessary to eliminate any effect from high-current
output pin switching.
The pin monitor enable bit should be set for any output signal that is expected to drive a large load.
Example: The SMBus in a system is heavily loaded with multiple slaves and a long PCB route. Set the
SMBus pin monitor enable, SMBPM = 1.
Example: Timer2 controls an LED on Port 1, pin 3 to provide variable dimming. Set the Port SFR write
monitor enable, PIOPM = 1.
Example: The SPI bus is used to communicate to a nearby host. The pin monitor is not needed because
the output is not heavily loaded, SPIPM remains = 0, the default reset state.
Pin monitors sho uld no t be en ab le d un less th ey are required . Th e p in m on ito r wo rks by re pe a tin g an y p or -
tion of a conversion that may have been corrupted by a change on an output pin. Setting pin monitor
enables bits will slow CS0 conversions.
The frequency of CS0 retry operations can be limited by setting the CSPMMD bits. In the default (reset)
state, all converter retry requests will be performed. This is the recommended setting for all applications.
The number of retries per conversion can be limited to either two or four retries by changing CSPMMD.
Limiting the number of retries per conversion ensures that even in circumstances where extremely fre-
quent high-power output switching occurs, conversions will be completed, though there may be some loss
of accuracy due to switching noise.
Activity of the pin monitor circuit can be detected by reading the Pin Monitor Event bit, CS0PME, in register
CS0CN. This bit will be set if any CS0 converter retries have occurred. It remains se t until cleared by soft-
ware or a device reset.
C8051F70x/71x
87 Rev. 1.0
15.8. Adjusting CS0 For Special Situations
There are several configuration options in the CS0 module designed to modify the operation of the circuit
and address special situations. In particular, any circuit with more than 500 Ω of series impedance
between the sensor and the device pin may require adjustments for optimal performance. Typical applica-
tions which may require adjustme nts includ e th e followin g :
Touch panel sensors fabricated using a resistive conductor such as indium-tin-oxide (ITO).
Circuits using a high-value series resistor to isolate the sensor element for high ESD protection.
Most systems will require no fine tuning, and the default settings for CS0DT, CS0DR, and CS0IA
should be used.
C8051F70x/71x
Rev. 1.0 88
SFR Address = 0x9A; SFR Page = 0
SFR Definition 15.1. CS0CN: Capacitive Sense Control
Bit7654 3 210
Name CS0EN CS0PME CS0INT CS0BUSY CS0CMPEN CS0CMPF
Type R/W R/W R/W R/W R/W R R R
Reset 0000 0 000
Bit Name Description
7CS0ENCS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
6 CS0PME CS0 Pin Monitor Event.
Set if any converter re- try request s have occurred due to a pin moni tor event. This
bit remains set until cleared by firmware.
5CS0INTCS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
4 CS0BUSY CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
3 CS0CMPEN CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator e nabled.
2:1 Unused Read = 00b; Write = Don’t care
0 CS0CMPF CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greate r than the value set by CS0 THH and CS0THL since the last
time CS0CMPF was cleared.
C8051F70x/71x
89 Rev. 1.0
SFR Address = 0x9E; SFR Page = 0
SFR Definition 15.2. CS0CF: Capacitive Sense Configuration
Bit76543210
Name CS0CM[2:0] CS0ACU[2:0]
Type R R/W R/W R/W R R/W R/W R/W
Reset 00000000
Bit Name Description
7 Unused Read = 0b; Write = Don’t care
6:4 CS0CM[2:0] CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Conversion initiated on overflow of Timer 3.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
3 Unused Read = 0b; Write = Don’t care
2:0 CS0ACU[2:0] CS0 Accumulator Mode Select.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples
100: Accumulate 32 samples.
101: Accumulate 64 samples.
11x: Reserved.
C8051F70x/71x
Rev. 1.0 90
SFR Address = 0xAA; SFR Page = 0
SFR Address = 0xA9; SFR Page = 0
SFR Definition 15.3. CS0DH: Capacitive Sense Data High Byte
Bit76543210
Name CS0DH[7:0]
Type RRRRRRRR
Reset 00000000
Bit Name Description
7:0 CS0DH CS0 Data High Byte.
Stores the high byte of the last completed 16-bit Capacitive Sense conversion.
SFR Definition 15.4. CS0DL: Capacitive Sense Data Low Byte
Bit76543210
Name CS0DL[7:0]
Type RRRRRRRR
Reset 00000000
Bit Name Description
7:0 CS0DL CS0 Data Low Byte.
Stores the low byte of the last completed 16-bit Capacitive Sense conversion.
C8051F70x/71x
91 Rev. 1.0
SFR Address = 0x92; SFR Page = F
SFR Address = 0x93; SFR Page = F
SFR Definition 15.5. CS0SS: Cap acitive Sense Auto-Scan Start Channel
Bit76543210
Name CS0SS[5:0]
Type RR R/W
Reset 00000000
Bit Name Description
7:6 Unused Read = 00b; Write = Don’t care
5:0 CS0SS[5:0] Starting Channel for Auto-Scan.
Sets the first CS0 ch annel to be se lected by the mux for Cap acitive Se nse conver-
sion when auto-scan is enabled and active. All channels detailed in CS0MX SFR
Definition 15.12 are possible choices for this register.
When auto-scan is enabled, a write to CS0SS will also update CS0MX.
SFR Definition 15.6. CS0SE: Cap acitive Sense Auto-Scan End Channel
Bit76543210
Name CS0SE[5:0]
Type RR R/W
Reset 00000000
Bit Name Description
7:6 Unused Read = 000b; Write = Don’t care
5:0 CS0SE[5:0] Ending Channel for Auto-Scan.
Sets the last CS0 channel to be selected by the mux for Cap acitive Sense conver-
sion when auto-scan is enabled and active. All channels detailed in CS0MX SFR
Definition 15.12 are possible choices for this register.
C8051F70x/71x
Rev. 1.0 92
SFR Address = 0x97; SFR Page = 0
SFR Address = 0x96; SFR Page = 0
SFR Definition 15.7. CS0THH: Capacitive Sense Comparator Threshold High Byte
Bit76543210
Name CS0THH[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Description
7:0 CS0THH[7:0] CS0 Comparator Threshold High Byte.
High byte of the 16-bit value compared to the Capacitive Sense conve rsion re sult.
SFR Definition 15.8. CS0THL: Capacitive Sense Comparator Threshold Low Byte
Bit76543210
Name CS0THL[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Description
7:0 CS0THL[7:0] CS0 Comp arator Threshold Low Byte.
Low byte of the 16-bit value comp ared to the Capacitive Sense conversion result.
C8051F70x/71x
93 Rev. 1.0
SFR Address = 0x9F; SFR Page = F
SFR Definition 15.9. CS0PM: Capacitive Sense Pin Monitor
Bit76543210
Name UAPM SPIPM SMBPM PCAPM PIOPM CP0PM CSPMMD[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Description
7 UAPM UART Pin Monitor Enable.
Enables monitoring of the UART TX pin.
6 SPIPM SPI Pin Monitor Enable.
Enables monitoring SPI output pins.
5SMBPM
SMBus Pin Monitor Enable.
Enables monitoring of the SMBus pins.
4 PCAPM PCA Pin Monitor Enable.
Enables monitoring of PCA output pins.
3 PIOPM Port I/O Pin Monitor Enable.
Enables monitoring of writes to the port latch registers.
2 CP0PM CP0 Pin Monitor Enable.
Enables monitoring of the comparator CP0 (synchronous) output.
1:0 CSPMMD[1:0] CS0 Pin Monitor Mode.
Selects the o peration to take when a monitored signal changes state.
00: Always retry bit cycles on a pin state change.
01: Retry up to twice on consecutive bit cycles.
10: Retry up to four times on consecutive bit cycles.
11: Reserved.
C8051F70x/71x
Rev. 1.0 94
SFR Address = 0xAD; SFR Page = 0
SFR Definition 15.10. CS0MD1: Capacitive Sense Mode 1
Bit76543210
Name CS0DR[1:0] CS0CG[2:0]
Type R R/W R R/W R/W R/W
Reset 00000111
Bit Name Description
7:6 Unused Read = 00b; Write = Don’t care
5:4 CS0DR[1:0] CS0 Double Reset Select.
These bits adjust the secondary CS0 reset time. For most touch-sensitive
switches, the default (fastest) value is sufficient, and these bits should not be
modified.
00: No additional time is used for secondary reset (recommended for most
switches)
01: An additional 0.75 µs is used for secondary reset.
10: An additional 1.5 µs is used for secondary reset.
11: An additional 2.25 µs is used for secondary reset.
3 Unused Read = 0b; Write = Don’t care
2:0 CS0CG[2:0] CS0 Reference Gain Select.
These bit s select the "gain " applied to the cur rent used to char ge an inte rnal refer-
ence capacitor. Lower gain values decrease the current setting, and increase
both the size of the capacitance that can be measured with the CS0 module, and
the base conversion time. Refer to “15.2. CS0 Gain Adjustment” on page 81 for
more information.
000: Gain = 1x
001: Gain = 2x
010: Gain = 3x
011: Gain = 4x
100: Gain = 5x
101: Gain = 6x
110: Gain = 7x
111: Gain = 8x (default)
C8051F70x/71x
95 Rev. 1.0
SFR Address = 0xBE; SFR Page = F
SFR Definition 15.11. CS0MD2: Capacitive Sense Mode 2
Bit76543210
Name CS0CR[1:0] CS0DT[2:0] CS0IA[2:0]
Type R/W R/W R/W
Reset 01000000
Bit Name Description
7:6 CS0CR[1:0] CS0 Conversion Rate.
These bits co ntrol the conversion rate of the CS0 module. See the ele ctrical spec-
ifications table for specific timing.
00: Conversion s las t 12 int erna l C S0 clocks and are 12 bits in length.
01: Conversion s las t 13 int erna l C S0 clocks and are 13 bits in length.
10: Conversion s las t 14 int erna l C S0 clocks and are 14 bits in length.
11: Conversions last 16 internal CS0 clocks.and are 16 bits in length.
5:3 CS0DT[2:0] CS0 Discharge Time.
These bits ad just the primary CS0 reset time. For most touch-sensitive switches,
the default (fastest) value is sufficient, and these bits should not be modified.
000: Discharge time is 0.75 µs (recommended for most switches)
001: Discharge time is 1.0 µs
010: Discharge time is 1.2 µs
011: Discharge time is 1.5 µs
100: Discharge time is 2 µs
101: Discharge time is 3 µs
110: Discharge time is 6 µs
111: Discharge time is 12 µs
2:0 CS0IA[2:0] CS0 Output Current Adjustment.
These bit s allow the user to adjust the output curre nt used to char ge up the cap ac-
itive sensor element. For most touch-sensitive switches, the default (highest) cur -
rent is sufficient, and these bits should not be mo dif ied .
000: Full Current (recommended for most switches)
001: 1/8 Current
010: 1/4 Current
011: 3/8 Current
100: 1/2 Current
101: 5/8 Current
110: 3/4 Current
111: 7/ 8 Cur re n t
C8051F70x/71x
Rev. 1.0 96
15.9. Capacitive Sense Multiplexer
The input multiplexer can be controlled through two methods. The CS0MX register can be written to
through firmware, or the r egister can be configured automatically using the modules auto-sca n functionality
(see “15.4. Automatic Scanning” ).
Figure 15.3. CS0 Multiplexer Block Diagram
CS0
CS0MUX
CS0MX
CS0UC
CS0MX5
CS0MX4
CS0MX3
CS0MX2
CS0MX1
CS0MX0
P2.0
P6.5
C8051F70x/71x
97 Rev. 1.0
SFR Address = 0x9C; SFR Page = 0
SFR Definition 15.12. CS0MX: Capacitive Sense Mux Channel Select
Bit76543210
Name CS0UC CS0MX[5:0]
Type R/W R/W R/W
Reset 00000000
Bit Name Description
7CS0UCCS0 Unconnected.
Disconnects CS0 from all port pins, regardless of the selected channel.
0: CS0 connected to port pins
1: CS0 disconnected from port pins
6 Reserved Write = 0b
5:0 CS0MX[5:0] CS0 Mux Channel Select.
Selects one of the 38 input channels for Capacitive Sense conversion.
Value 64-pin 48-pin 32-pin 24-pin Value 64-pin 48-pin 32-pin 24-pin
000000 P2.0 P2.0 P2.0 P2.0 010011 P4.3 P4.3 — P4.3
000001 P2.1 P2.1 P2.1 P2.1 010100 P4.4 — — P4.4
000010 P2.2 P2.2 P2.2 P2.2 010101 P4.5 — — P4.5
000011 P2.3 P2.3 P2.3 P2.3 010110 P4.6 — — P4.6
000100 P2.4 P2.4 P2.4 P2.4 010111 P4.7 — — P4.7
000101 P2.5 P2.5 P2.5 P2.5 011000 P5.0 P5.0 P5.0 —
000110 P2.6 P2.6 P2.6 P2.6 011001 P5.1 P5.1 P5.1 —
000111 P2.7 P2.7 P2.7 P2.7 011010 P5.2 P5.2 P5.2 —
001000 P3.0 — P3.0 — 011011 P5.3 P5.3 P5.3 —
001001 P3.1 — P3.1 — 011100 P5.4 P5.4 P5.4 —
001010 P3.2 — P3.2 — 011101 P5.5 P5.5 P5.5 —
001011 P3.3 — P3.3 — 011110 P5.6 P5.6 P5.6 —
001100 P3.4 P3.4 P3.4 — 011111 P5.7 P5.7 P5.7 —
001101 P3.5 P3.5 P3.5 — 100000 P6.0———
001110 P3.6 P3.6 P3.6 — 100001 P6.1———
001111 P3.7 P3.7 — — 100010 P6.2———
010000 P4.0 P4.0 — P4.0 100011 P6.3 P6.3 P6.3 —
010001 P4.1 P4.1 — P4.1 100100 P6.4 P6.4 P6.4 P6.4
010010 P4.2 P4.2 — P4.2 100101 P6.5 P6.5 P6.5 P6.5
C8051F70x/71x
Rev. 1.0 98
16. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in “C2 Interface” on page 301), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 16.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 emplo ys a p ipeli ned architectu re tha t grea tly increases it s instr uction throug hput over the st an-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 16.1. CIP-51 Block Diagram
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Reset Inpu t
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER SRAM
D8
STACK POINTER
D8
C8051F70x/71x
99 Rev. 1.0
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
16.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the st and ard MCS-51 ™ instru c-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
16.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock c ycles in length. How ever, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 16.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26 50 5 14 7 3 1 2 1
C8051F70x/71x
Rev. 1.0 100
Table 16.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract regis ter fro m A with bo rrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
C8051F70x/71x
101 Rev. 1.0
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
Table 16.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F70x/71x
Rev. 1.0 102
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 2 2/3
JNC rel Jump if Carry is not set 2 2/3
JB bit, rel Jump if direct bit is set 3 3/4
JNB bit, rel Jump if direct bit is not set 3 3/4
JBC bit, rel Jump if direct bit is set and clear bit 3 3/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 L on g su br ou tin e call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 2 2/3
JNZ rel Jump if A does not equal zero 2 2/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 4/5
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, re l Compare immediate to indirect and jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3
DJNZ direct, rel Decrement direct byte and jump if not zer o 3 3/4
NOP No operation 1 1
Table 16.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F70x/71x
103 Rev. 1.0
Notes on Registers, Oper ands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location ’s address. This cou ld be a direct-access Data RAM locatio n (0x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr16—16-bit destina tion address use d by LCALL and LJMP. The destination may be an ywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
C8051F70x/71x
Rev. 1.0 104
16.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the data sheet associated with their corresponding system function.
SFR Address = 0x82; SFR Page = All Pages
SFR Address = 0x83; SFR Page = All Pages
SFR Definition 16.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 16.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
C8051F70x/71x
105 Rev. 1.0
SFR Address = 0x81; SFR Page = All Pages
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
SFR Definition 16.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The S t ack Pointer holds the location of the top of the stack. The st ack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 16.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
C8051F70x/71x
Rev. 1.0 106
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
SFR Definition 16.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
C8051F70x/71x
107 Rev. 1.0
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
SFR Definition 16.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CYCarry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6ACAuxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) th e high order nibble. It is cleared to logic 0 by all other arith-
metic opera tions .
5F0User Flag 0.
This is a bit-addres sable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OVOverflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide- by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1User Flag 1.
This is a bit-addres sable, general purpose flag for use under software control.
0PARITYParity Flag.
This bit is set to logic 1 if the sum of the eigh t bits in the accumulator is odd and cleared
if the sum is even.
C8051F70x/71x
Rev. 1.0 108
17. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F70x/71x device family is shown in Figure 17.1
Figure 17.1. C8051F70x/71x Memory Map
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Ad dressin g
Only)
0x80
0xFF Special Function
Register's
(Direct Addres sing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indir e ct
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 256 Bytes
(accessable using MOVX
instruction)
0x0000
0x00FF
Same 256 bytes as from
0x0000 to 0x01FF, wrapped
on 256-byte boundaries
0x0100
0xFFFF
16 K Bytes FLASH
(In-System
Programmable in 51 2
Byte Sectors)
0x0000
Lock Byte0x3FFF
0x3FFE
C8051F702/3/6/7 and
C8051F716/7
15 K Bytes FLASH
(In-System
Programmable in 51 2
Byte Sectors)
0x0000
Lock Byte0x3BFF
0x3BFE
C8051F700/1/4/5
8 K Bytes FLASH
(In-System
Programmable in 51 2
Byte Sectors)
0x0000
Lock Byte0x1FFF
0x1FFE
C8051F708/9 and
C8051F710/1/2/3/4/5
C8051F70x/71x
109 Rev. 1.0
17.1. Program Memory
The members of the C8051F70x/71x device family contain 16 kB (C8051F702/3/6/7 and C8051F16/7),
15 kB (C8051F700/1/4/5), or 8 kB (C8051F708/9 and C8051F710/1/2/3/4/5) of re-programmable Flash
memory that can be used as non-volatile program or data storage. The last byte of user code space is
used as the security lock byte (0x3FFF on 16 kB devices, 0x3BFF on 15 kB devices and 0x1FFF on 8 kB
devices).
Figure 17.2. Flash Program Memory Map
17.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F70x/71x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mech anism for the C8051F7 0x/71x to up date progra m code and use the pro gram mem-
ory space for non-volatile data storage. Refer to Section “22. Flash Memory” on page 148 for further
details.
17.2. EEPROM Memory
The C8051F700/1/4/5/8/9 and C8051F712/3 contain EEPROM emulation hardware, which uses Flash
memory to emulate a 32-byte EEPROM memory sp ace for non-volatile data storage. The EEPROM dat a is
accessed through a RAM buffer for increased speed. More details about the EEPROM can be found in
Section “23. EEPROM” on page 155.
17.3. Data Memory
The C8051F70x/71x device family includes 512 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 256 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 17.1 for reference.
17.3.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 b ytes of data memory. Loca tions 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
Lock Byte
0x0000
0x3FFF
0x3FFE
FLASH memory organized in
512-byt e pages
0x3E00
Flash Mem ory Space
Lock Byte Page
Lock Byte
0x0000
0x3BFF
0x3BFE
0x3A00
Flash Mem ory S pace
Lock Byte Pa ge
Lock Byte
0x0000
0x1FFF
0x1FFE
0x1E00
Flash Mem ory Sp ace
Lock Byte Page
C8051 F70 2/3/6/7 and
C8051F716/7
C8051F700/1/4/5
C8051 F708/9 an d
C8051F710/1/2/3/4/5
C8051F70x/71x
Rev. 1.0 110
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 1 28 bytes of data mem ory ar e acce ssible on ly by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 17.1 illustrates the data memory organization of the
C8051F70x/71x.
17.3.1.1. General Purpose Registers
The lower 32 bytes of dat a memory, locations 0x00 through 0x1F, may be addressed as four banks of g en-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 16.6). This allows
fast context switching when entering subr outin es and interrupt se rvice routines. In direct addr essing mod es
use registers R0 and R1 as index registers.
17.3.1.2. Bit Addressable Locations
In addition to direct access to d ata memory or ganize d as bytes, the sixteen dat a memor y locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x2 0 has bit addre ss 0x00 while bit 7 of the byte at 0x20 has bit addre ss
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
17.3.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
C8051F70x/71x
Rev. 1.0 111
18. External Data Memory Interface and On-Chip XRAM
For C8051F70x/71x devices, 256 B of RAM are included on-chip and mapped into the external data mem-
ory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the
C8051F700/1/2/3/8/9 and C8051F710/1 devices, which can be used to a ccess of f-ch ip data memories and
memory-mapped devices connected to the GPIO ports. The external memory space may be accessed
using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect
addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as
@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Reg-
ister (EMI0CN, shown in SFR Definition 18.1).
Note: The MOVX instruction can also be used for writing to the Flash me mory. See Section “22. Flash Memory” on
page 148 for details. The MOVX instruction accesses XRAM by default.
18.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
18.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)
MOVX A, @DPTR ; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed thro ugh th e SFR regi ster s DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
18.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the cont ents of the EMI0CN SF R to dete rmine the upp er 8-bit s
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV EMI0CN, #12h ; load high byte of address into EMI0CN
MOV R0, #34h ; load low byte of address into R0 (or R1)
MOVX a, @R0 ; load contents of 0x1234 into accumulator A
C8051F70x/71x
112 Rev. 1.0
18.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common).
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
5. Set up timing to inte r fac e with off-chip memor y or per iph er a ls.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition .
18.3. Port Configuration
The EMIF pinout is shown in Figure 18.2 on Page 127
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches for those pins. See Section “28. Port Input/Output” on page 180 for more
information about Port operation and configuration. The Port latches should be explicitly configured to
“park” the External Memory Interface pins in a dormant state, most commonly by setting them to a
logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are actin g as Inpu ts (Data[7:0] dur ing a READ ope rati on, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
C8051F70x/71x
Rev. 1.0 113
SFR Address = 0xAA; SFR Page = F
SFR Definition 18.1. EMI0CN: External Memory Interface Control
Bit76543210
Name PGSEL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 PGSEL[7:0] XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-b it MOVX command, effectively selecting a 256-byte p age of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
C8051F70x/71x
114 Rev. 1.0
SFR Address = 0xC7; SFR Page = F
SFR Definition 18.2. EMI0CF: External Memory Configuration
Bit76543210
Name EMD2 EMD[1:0] EALE[1:0]
Type RR/W
Reset 00000011
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care.
4EMD2EMIF Multiplex Mode Select Bit.
0: EMIF operates in multiplexed address/data mode
1: EMIF operates in non-multiplexed mode (separate address and data pins)
3:2 EMD[1:0] EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Accesses below the 256 B boundary are directed
on-chip. Accesses above the 256 B boundary are directed off-chip. 8- bit off-chip MOVX
operations use current contents of the Address high port latches to resolve the upper
address byte. To access off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 256 B boundary are directed on-
chip. Accesses above the 256 B boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
C8051F70x/71x
Rev. 1.0 115
18.4. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
18.4.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 18.1.
In Multiplexed m ode, the extern al MOVX ope ration c an be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longe r dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “18.6.2. Multiplexed Mode” on page 123 for more information.
Figure 18.1. Multiplexed Configuration Example
ADDRESS/DATA BUS
ADDRESS BUS
E
M
I
F
A[15:8]
AD[7:0]
WR
RD
ALE
64 K X 8
SRAM
OE
WE
I/O[7:0]
74HC373
G
DQ
A[15:8]
A[7:0]
CE
VDD
8(Optional)
C8051F70x/71x
116 Rev. 1.0
18.4.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-
multiplexed Configuration is shown in Figure 18.2. See Section “18.6.1. Non-Multiplexed Mode” on
page 120 for more information about Non-multiplexed operation.
Figure 18.2. Non-multiplexed Configuration Example
ADDRESS BUS
E
M
I
F
A[15:0]
64 K X 8
SRAM
A[15:0]
DATA BUSD[7:0] I/O[7:0]
VDD
8
WR
RD OE
WE
CE
(Optional)
C8051F70x/71x
Rev. 1.0 117
18.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 18.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 18.2). These modes are summarized below.
More information about the different modes can be found in Section “18.6. Timing” on page 118.
Figure 18.3. EMIF Operating Modes
18.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 4 kB boundaries. As an
example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-b yte of the ef fe ctive address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
18.5.2. Split Mode without Bank Select
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the content s of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Addre ss Bus du ring an off-chip acces s. Th is allo ws th e use r to ma nip ulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “S plit Mode with Bank Select” described below. The lower 8-bit s of the Address Bus A[7:0]
are driven, dete rmined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or of f-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
EMI0CF[3:2] = 00 0xFFFF
0x0000
EMI0CF[3:2] = 11 0xFFFF
0x0000
EMI0CF[3:2] = 01 0xFFFF
0x0000
EMI0CF[3:2] = 10
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0xFFFF
0x0000
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
C8051F70x/71x
118 Rev. 1.0
18.5.3. Split Mode with Bank Select
When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the content s of EMI0CN to determine whether the memory access is on-
chip or of f-chip. The up per 8-bit s of th e Address Bus A[1 5:8] are determin ed by EMI0CN, and the lower
8-bits o f the Address Bus A[7:0] are d etermined by R0 or R1. All 16-bit s of the Add ress Bus A[15:0] are
driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
18.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off- chip sp ace. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0 ] ar e dr ive n du rin g the off-chip trans act ion .
18.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 18.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for /ALE + 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 18.1 lists the ac parameters for the External
Memory Interface, and Figure 18.4 through Figure 18.9 show the timing diagrams for the different External
Memory Interface modes and MOVX operations.
C8051F70x/71x
Rev. 1.0 119
SFR Address = 0xEE; SFR Page = F
SFR Definition 18.3. EMI0TC: External Memory Timing Control
Bit76543210
Name EAS[1:0] EWR[3:0] EAH[1:0]
Type R/W R/W R/W
Reset 11111111
Bit Name Function
7:6 EAS[1:0] EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2 EWR[3:0] EMIF WR and RD Pulse-Wid th Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse wid th = 12 SYSCLK cycles.
1100: WR and RD pulse widt h = 13 SYSCLK cycles.
1101: WR and RD pulse widt h = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0 EAH[1:0] EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
C8051F70x/71x
120 Rev. 1.0
18.6.1. Non-Multiplexed Mode
18.6.1.1. 16-bit MOVX: EMI0CF [4 :2 ] = 101, 110, or 111
Figure 18.4. Non-multiplexed 16-bit MOVX Timing
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPL
EMIF WRITE DATA
TACH
TWDH
TACW
TACS
TWDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPL
TACH
TRDH
TACW
TACS
TRDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 16-bi t WRITE
Nonmuxed 16-bit READ
C8051F70x/71x
Rev. 1.0 121
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing
EMIF ADDRESS (8 LSBs) from R0 or R1
EMIF WRITE DATA
TACH
TWDH
TACW
TACS
TWDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 LSBs) from R0 or R1
TACH
TRDH
TACW
TACS
TRDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 8-bi t WRITE with out Ban k Sel ec t
Nonmuxed 8-bit READ without Bank Select
C8051F70x/71x
122 Rev. 1.0
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110
Figure 18.6. Non-Multiplexed 8-Bit MOVX with Bank Select Timing
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from R0 or R1
EMIF WRITE DATA
TACH
TWDH
TACW
TACS
TWDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from R0 or R1
TACH
TRDH
TACW
TACS
TRDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 8-bit WRITE with Bank Select
Nonmuxed 8-bit READ with Bank Select
C8051F70x/71x
Rev. 1.0 123
18.6.2. Multiplexed Mode
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Figure 18.7. Multiplexed 16-bit MOVX Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from DPH
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
DPL
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 16-bit WRITE
Muxed 16-bit READ
C8051F70x/71x
124 Rev. 1.0
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Figure 18.8. Multiplexed 8-Bit MOVX without Bank Select Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 8-bit WRITE Without Bank Select
Muxed 8-bit READ Without Bank Select
l
C8051F70x/71x
Rev. 1.0 125
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Figure 18.9. Multiplexed 8-Bit MOVX with Bank Select Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 8-bit WRITE with Bank Select
Muxed 8-bit READ with Bank Select
C8051F70x/71x
126 Rev. 1.0
C8051F70x/71x
Rev. 1.0 126
Table 18.1. AC Parameters for External Memory Interface
Parameter Description Min* Max* Units
TACS Address/Control Setup Time 0 3 x TSYSCLK ns
TACW Address/Control Pulse Width TSYSCLK 16 x TSYSCLK ns
TACH Address/Control Hold Time 0 3 x TSYSCLK ns
TALEH Address Latch Enable High Time TSYSCLK 4 x TSYSCLK ns
TALEL Address Latch Enable Low Time TSYSCLK 4 x TSYSCLK ns
TWDS Write Data Setup Time TSYSCLK 19 x TSYSCLK ns
TWDH Write Data Hold Time 0 3 x TSYSCLK ns
TRDS Read Data Setup Time 20 — ns
TRDH Read Data Hold Time 0 — ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F70x/71x
127 Rev. 1.0
Table 18.2. EMIF Pinout (C8051F700/1/2/3/8/9 and C8051F710/1)
Multiplexed Mode Non Multiplexed Mode
Signal Name Port Pin Signal Name Port Pin
RD P6.1 RD P6.1
WR P6.0 WR P6.0
ALE P6.2 D0 P5.0
D0/A0 P5.0 D1 P5.1
D1/A1 P5.1 D2 P5.2
D2/A2 P5.2 D3 P5.3
D3/A3 P5.3 D4 P5.4
D4/A4 P5.4 D5 P5.5
D5/A5 P5.5 D6 P5.6
D6/A6 P5.6 D7 P5.7
D7/A7 P5.7 A0 P4.0
A8 P4.0 A1 P4.1
A9 P4.1 A2 P4.2
A10 P4.2 A3 P4.3
A11 P4.3 A4 P4.4
A12 P4.4 A5 P4.5
A13 P4.5 A6 P4.6
A14 P4.6 A7 P4.7
A15 P4.7 A8 P3.0
— — A9 P3.1
—— A10P3.2
—— A11P3.3
—— A12P3.4
—— A13P3.5
—— A14P3.6
—— A15P3.7
C8051F70x/71x
Rev. 1.0 128
19. In-System Device Identification
The C8051F70x/71x has SFRs that identify the device family and derivative. These SFRs can be read by
firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the same
firmware image to run on MCUs with different memory sizes and peripherals, and dynamically changing
functionality to suit the capabilities of that MCU.
In order for firmware to identify the MCU, it must read three SFRs. HWID describes the MCU’s family,
DERIVID describes the specific derivative within that device family, and REVID describes the hardware
revision of the MCU.
SFR Address = 0xC4; SFR Page = F
SFR Address = 0xEC; SFR Page = F
SFR Definition 19.1. HWID: Hardware Identification Byte
Bit76543210
Name HWID[7:0]
Type RRRRRRRR
Reset 00011110
Bit Name Description
7:0 HWID[7:0] Hardware Identification Byte.
Describes the MCU family.
0x1E: Devices covered in this document (C8051F70x/71x)
SFR Definition 19.2. DERIVID: Derivative Identification Byte
Bit76543210
Name DERIVID[7:0]
Type RRRRRRRR
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Description
7:0 DERIVID[7:0] Derivative Identification Byte.
Shows the C8051F70x/71x derivative being used.
0xD0: C8051F700; 0xD1: C8051F701; 0xD2: C8051F702; 0xD3: C8051F703
0xD4: C8051F704; 0xD5: C8051F705; 0xD6: C8051F706; 0xD7: C8051F707
0xD8: C8051F708; 0xD9: C8051F709; 0xDA: C8051F710; 0xDB: C8051F711
0xDC: C8051F712; 0xDD: C8051F713; 0xDE: C8051F714; 0xDF: C8051F715
0xE0: C8051F716; 0xE1: C8051F717
C8051F70x/71x
129 Rev. 1.0
SFR Address = 0xAD; SFR Page = F
SFR Definition 19.3. REVID: Hardware Revision Identification Byte
Bit76543210
Name REVID[7:0]
Type RRRRRRRR
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Description
7:0 REVID[7:0] Hardware Revision Identification Byte.
Shows the C8051F70x/71x hardware revision being used.
For example, 0x00 = Revision A.
C8051F70x/71x
Rev. 1.0 130
20. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F70x/71x's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F70x/71x. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 20.1 lists the SFRs implemented in the C8051F70x/71x device family.
The SFR regist ers are access ed anytime the direct a ddressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON 0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 20.2, for a detailed description of each register.
C8051F70x/71x
131 Rev. 1.0
Table 20.1. Special Function Register (SFR) Memory Map
Addr SFR
Page 0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 0
FSPI0CN PCA0L
P0DRV PCA0H
P1DRV PCA0CPL0
P2DRV PCA0CPH0
P3DRV P4DRV P5DRV VDM0CN
F0 0
FBP0MDIN P1MDIN P0MAT
P2MDIN P0MASK
P3MDIN P4MDIN P5MDIN P6MDIN
E8 0
FADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
DERIVID PCA0MD EMI0TC RSTSRC
E0 0
FACC P1MAT
XBR0 P1MASK
XBR1 WDTCN IT01CF EIE1 EIE2
D8 0
FPCA0CN CRC0DATA PCA0CPM0 PCA0CPM1 PCA0CPM2
D0 0
FPSW EEDATA REF0CN P0SKIP P1SKIP P2SKIP
C8 0
FTMR2CN TMR2RLL TMR2RLH TMR2L TMR2H EIP1 EIP2
C0 0
FSMB0CN SMB0CF
P6DRV SMB0DAT ADC0GTL ADC0GTH
HWID ADC0LTL
EECNTL ADC0LTH
EEKEY EMI0CF
B8 0
FIP REG0CN SMB0ADR ADC0MX
SMB0ADM ADC0CF ADC0L
CLKSEL ADC0H
CS0MD2 OSCICL
B0 0
FP3 P6 P5 OSCXCN EEADDR FLKEY
A8 0
FIE CS0DL
OSCICN CS0DH
EMI0CN P4 CS0MD1
REVID P3MDOUT
A0 0
FP2 SPI0CFG
PCA0PWM SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
98 0
FSCON0 SBUF0 CS0CN
P4MDOUT CPT0CN
P5MDOUT CS0MX
P6MDOUT CPT0MD CS0CF CPT0MX
CS0PM
90 0
FP1 TMR3CN
CRC0CN TMR3RLL
CS0SS TMR3RLH
CS0SE TMR3L
CRC0IN TMR3H
CRC0FLIP CS0THL
CRC0AUTO CS0THH
CRC0CNT
88 0
FTCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 0
FP0 SP DPL DPH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
Notes:
1. SFR addresses ending in 0x0 or 0x8 (leftmost column) are bit-addressable.
2. SFRs indicated with bold lettering and shaded cells are available on both SFR Page 0 and F.
C8051F70x/71x
Rev. 1.0 132
SFR Address = 0xA7; SFR Page = All Pages
SFR Definition 20.1. SFRPAGE: SFR Page
Bit76543210
Name SFRPAGE[7:0]
Type R/W
Reset 00000000
Bit Name Description
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C80 51 core uses when re ading or modifyin g SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
Table 20.2. Special Function Registers
SFRs are listed in alphab et ica l or d er. All undefined SFR location s ar e re se rve d
Register Address Page Description Page
ACC 0xE0 All Pages Accumulator 105
ADC0CF 0xBC F ADC0 Configuration 59
ADC0CN 0xE8 All Pages ADC0 Control 61
ADC0GTH 0xC4 0 ADC0 Greater-Than Comp are High 62
ADC0GTL 0xC3 0 ADC0 Greater-Than Comp are Low 62
ADC0H 0xBE 0 ADC0 High 60
ADC0L 0xBD 0 ADC0 Low 60
ADC0LTH 0xC6 0 ADC0 Less-Than Compare Word High 63
ADC0LTL 0xC5 0 ADC0 Less-Than Compare Word Low 63
ADC0MX 0xBB 0 AMUX0 Multiplexer Channel Select 66
B0xF0 All Pages B Register 106
CKCON 0x8E All Pages Clock Control 263
CLKSEL 0xBD F Clock Select 263
CPT0CN 0x9B 0 Comparator0 Control 76
CPT0MD 0x9D 0 Comparator0 Mode Selection 77
CPT0MX 0x9F 0 Com parator0 MU X Selec tion 79
CRC0AUTO 0x96 F CRC0 Automatic Control Register 217
CRC0CN 0x91 F CRC0 Control 215
CRC0CNT 0x97 F CRC0 Automatic Flash Sector Count 217
CRC0DATA 0xD9 F CRC0 Data Output 216
CRC0FLIP 0x95 F CRC0 Bit Flip 218
CRC0IN 0x94 F CRC Data Input 216
C8051F70x/71x
133 Rev. 1.0
CS0CN 0x9A 0 CS0 Control 88
CS0DH 0xAA 0 CS0 Data High 90
CS0DL 0xA9 0 CS0 Data Low 90
CS0CF 0x9E 0 CS0 Configuration 89
CS0MD1 0xAD 0 CS0 Mode 1 94
CS0MD2 0xBE F CS0 Mode 2 95
CS0MX 0x9C 0 CS0 Mux 97
CS0PM 0x9F F CS0 Pin Monitor 93
CS0SE 0x93 F Auto Scan End Channel 91
CS0SS 0x92 F Auto Scan Start Channel 91
CS0THH 0x97 0 CS0 Digital Compare Threshold High 92
CS0THL 0x96 0 CS0 Digital Compare Threshold Low 92
DERIVID 0xEC F Derivative Identification 128
DPH 0x83 All Pages Data Pointer High 104
DPL 0x82 All Pages Data Pointer Low 104
EEADDR 0xB6 All Pages EEPROM Byte Address 156
EECNTL 0xC5 F EEPROM Control 158
EEDATA 0xD1 All Pages EEPROM Byte Data 157
EEKEY 0xC6 F EEPROM Protect Key 159
EIE1 0xE6 All Pages Extended Interrupt Enable 1 142
EIE2 0xE7 All Pages Extended Interrupt Enable 2 143
EIP1 0xCE F Extended Interrupt Priority 1 144
EIP2 0xCF F Extended Interrupt Priority 2 145
EMI0CF 0xC7 F EMIF Configuration 114
EMI0CN 0xAA F EMIF Control 113
EMI0TC 0xEE F EMIF Timing Control 119
FLKEY 0xB7 All Pages Flash Lock And Key 154
HWID 0xC4 F Hardware Identification 128
IE 0xA8 All Pages Interrupt Enable 140
IP 0xB8 All Pages Interrupt Priority 141
IT01CF 0xE4 F INT0/INT1 Configuration 147
OSCICL 0xBF F Internal Oscillator Calibration 173
OSCICN 0xA9 F Internal Oscillator Control 174
OSCXCN 0xB5 F External Oscillator Control 176
P0 0x80 All Pages Port 0 Latch 195
P0DRV 0xF9 F Port 0 Drive Strength 197
P0MASK 0xF4 0 Port 0 Mask 192
P0MAT 0xF3 0 Port 0 Match 193
Table 20.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefined SFR location s ar e re se rve d
Register Address Page Description Page
C8051F70x/71x
Rev. 1.0 134
P0MDIN 0xF1 F Port 0 Input Mode Configuration 195
P0MDOUT 0xA4 F Port 0 Output Mode Configuration 196
P0SKIP 0xD4 F Port 0 Skip 196
P1 0x90 All Pages Port 1 Latch 197
P1DRV 0xFA F Port 1 Drive Strength 199
P1MASK 0xE2 0 P0 Mask 193
P1MAT 0xE1 0 P1 Match 194
P1MDIN 0xF2 F Port 1 Input Mode Configuration 198
P1MDOUT 0xA5 F Port 1 Output Mode Configuration 198
P1SKIP 0xD5 F Port 1 Skip 199
P2 0xA0 All Pages Port 2 Latch 200
P2DRV 0xFB F Port 2 Drive Strength 202
P2MDIN 0xF3 F Port 2 Input Mode Configuration 200
P2MDOUT 0xA6 F Port 2 Output Mode Configuration 201
P2SKIP 0xD6 F Port 2 Skip 201
P3 0xB0 All Pages Port 3 Latch 202
P3DRV 0xF C F Port 3 Drive Strength 204
P3MDIN 0xF4 F Port 3 Input Mode Configuration 203
P3MDOUT 0xAF F Port 3 Output Mode Configuration 203
P4 0xAC All Pages Port 4 Latch 204
P4DRV 0xF D F Port 4 Drive Strength 206
P4MDIN 0xF5 F Port 4 Input Mode Configuration 205
P4MDOUT 0x9A F Port 4 Output Mode Configuration 205
P5 0xB3 All Pages Port 5 Latch 206
P5DRV 0xFE F Port 5 Drive Strength 208
P5MDIN 0xF6 F Port 5 Input Mode Configuration 207
P5MDOUT 0x9B F Port 5 Output Mode Configuration 207
P6 0xB2 All Pages Port 6 Latch 208
P6DRV 0xC1 F Port 6 Drive Strength 210
P6MDIN 0xF7 F Port 6 Input Mode Configuration 209
P6MDOUT 0x9C F Port 6 Output Mode Configuration 209
PCA0CN 0xD8 All Pages PCA Control 295
PCA0CPH0 0xFC 0 PCA Capture 0 High 300
PCA0CPH1 0xEA 0 PCA Capture 1 High 300
PCA0CPH2 0xEC 0 PCA Capture 2 High 300
PCA0CPL0 0xFB 0 PCA Capture 0 Low 300
PCA0CPL1 0xE9 0 PCA Capture 1 Low 300
PCA0CPL2 0xEB 0 PCA Capture 2 Low 300
Table 20.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefined SFR location s ar e re se rve d
Register Address Page Description Page
C8051F70x/71x
135 Rev. 1.0
PCA0CPM0 0xDA F PCA Module 0 Mode Register 298
PCA0CPM1 0xDB F PCA Module 1 Mode Register 298
PCA0CPM2 0xDC F PCA Module 2 Mode Register 298
PCA0H 0xFA 0 PCA Counter High 299
PCA0L 0xF9 0 PCA Counter Low 299
PCA0MD 0xED F PCA Mode 296
PCA0PWM 0xA1 F PCA PWM Configuration 297
PCON 0x87 All Pages Power Control 162
PSCTL 0x8F All Pages Program Store R/W Control 153
PSW 0xD0 All Pages Program Status Word 107
REF0CN 0xD2 F Volt age Reference Control 71
REG0CN 0xB9 F Voltage Regulator Control 73
REVID 0xAD F Revision ID 129
RSTSRC 0xEF All Pages Reset Source Configuration/Status 168
SBUF0 0x99 All Pages UART0 Data Buffer 260
SCON0 0x98 All Pages UART0 Control 259
SFRPAGE 0xA7 All Pages SFR Page 132
SMB0ADM 0xBB F SMBus Sla ve Add r ess mas k 2 3 0
SMB0ADR 0xBA F SMBus Sla ve Add r ess 229
SMB0CF 0xC1 0 SMBus Configuration 225
SMB0CN 0xC0 All Pages SMBus Control 227
SMB0DAT 0xC2 0 SMBus Data 231
SP 0x81 All Pages Stack Pointer 105
SPI0CFG 0xA1 0 SPI0 Configuration 248
SPI0CKR 0xA2 F SPI0 Clock Rate Control 250
SPI0CN 0xF8 All Pages SPI0 Control 249
SPI0DAT 0xA3 0 SPI0 Data 250
TCON 0x88 All Pages Timer/Counter Control 268
TH0 0x8C All Pages Timer/Counter 0 High 271
TH1 0x8D All Pages Timer/Counter 1 High 271
TL0 0x8A All Pages Timer/Counter 0 Low 270
TL1 0x8B All Pages Timer/Counter 1 Low 270
TMOD 0x89 All Pages Timer/Counter Mode 269
TMR2CN 0xC8 All Pages Timer/Counter 2 Control 275
TMR2H 0xCD 0 Timer/Counter 2 High 277
TMR2L 0xCC 0 Timer/Counter 2 Low 277
TMR2RLH 0xCB 0 Timer/Counter 2 Reload High 276
TMR2RLL 0xCA 0 Timer/Counter 2 Reload Low 276
Table 20.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefined SFR location s ar e re se rve d
Register Address Page Description Page
C8051F70x/71x
Rev. 1.0 136
TMR3CN 0x91 0 Timer/Counter 3 Control 281
TMR3H 0x95 0 Timer/Counter 3 High 283
TMR3L 0x94 0 Timer/Counter 3 Low 283
TMR3RLH 0x93 0 Timer/Counter 3 Reload High 282
TMR3RLL 0x92 0 Timer/Counter 3 Reload Low 282
VDM0CN 0xFF All Pages VDD Monitor Control 166
WDTCN 0xE3 All Pages Watchdog Timer Control 170
XBR0 0xE1 F Port I/O Crossbar Control 0 190
XBR1 0xE2 F Port I/O Crossbar Control 1 191
All other SFR Locations Reserved
Table 20.2. Special Function Registers (Continued)
SFRs are listed in alphab et ica l or d er. All undefined SFR location s ar e re se rve d
Register Address Page Description Page
C8051F70x/71x
Rev. 1.0 137
21. Interrupts
The C8051F70x/71x includes an extended interrupt system supporting several interrupt sources with two
priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins var-
ies according to the specific version of the device. Each interrupt source has one or more asso cia ted in te r-
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt
condition, the associated interrupt-pending flag is set to logic 1.
If interrupt s are ena bled for the sour ce, an interrupt req uest is generated when the inter rupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin executio n of an interrupt service routine ( ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt requ est had not occurred. If inter rupt s are not enabled, the inter rupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrup t enabl e s are recogn ized. Setting th e EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags ar e auto matically cleare d by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by sof twar e before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
C8051F70x/71x
138 Rev. 1.0
21.1. MCU Interrupt Sources and Vectors
The C8051F70x/71x MCUs support 16 interrupt sources. Software can simulate an interrupt by setting an
interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated
and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt
sources, associated vector addresses, priority order and control bits are summarized in Table 21.1. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s) .
21.1.1. Interrupt Priorities
Each interrupt source can be in dividua lly prog ra mmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the defa ult. If two interrupt s are recognize d simultane ously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 21.1.
21.1.2. Interrupt Latency
Interrupt response time depen ds on the state of the CPU when the in te rrupt occur s. Pending interru pts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to serv ice the pendin g inte rrup t. Th eref ore, the maxim um r espo nse tim e for an int errupt (when no
other interrupt is currently being serviced or the ne w interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
C8051F70x/71x
Rev. 1.0 139
Table 21.1. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0
(INT0)0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1
(INT1)0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4 RI0 (SCON0.0)
TI0 (SCON0.1) Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5 TF2H (TMR2CN.7)
TF2L (TM R2CN.6) Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6 SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y ESPI0
(IE.6) PSPI0
(IP.6)
SMB0 0x003B 7 SI (SMB0CN.0) Y N ESMB0
(EIE1.0) PSMB0
(EIP1.0)
Port Match 0x0043 8 None N/A N/A EMAT
(EIE1.1) PMAT
(EIP1.1)
ADC0
Window Compare 0x004B 9 AD0WINT (ADC0CN.3) Y N EWADC0
(EIE1.2) PWADC0
(EIP1.2)
ADC0 Conversion
Complete 0x0053 10 AD0INT (ADC0CN.5) Y N EADC0
(EIE1.3) PADC0
(EIP1.3)
Programmable
Counter Array 0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n) Y N EPCA0
(EIE1.4) PPCA0
(EIP1.4)
Comparator0 0 x00 6 3 12 CP0FIF (CPT 0 CN. 4)
CP0RIF (CPT0CN.5) NNECP0
(EIE1.5) PCP0
(EIP1.5)
RESERVED
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TM R3CN.6) NNET3
(EIE1.7) PT3
(EIP1.7)
CS0 Conversion
Complete 0x007B 15 CS0INT (CS0CN.5) N N ECSCPT
(EIE2.0) PSCCPT
(EIP2.0)
CS0 Greater Than
Compare 0x0083 16 CS0CMPF (CS0CN.0) N N ECSGRT
(EIE2.1) PSCGRT
(EIP2.1)
C8051F70x/71x
140 Rev. 1.0
21.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions fo r the peripheral and the behavior of its interrupt- pending flag(s).
SFR Address = 0xA8; SFR Page = All Pages; Bit-Addressable
SFR Definition 21.1. IE: Interrupt Enable
Bit76543210
Name EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EAEnable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6 ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit set s the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4 ES0 Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3ET1Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2 EX1 Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1ET0Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0 EX0 Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
C8051F70x/71x
Rev. 1.0 141
SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable
SFR Definition 21.2. IP: Interrupt Priority
Bit76543210
Name PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type R R/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7 Unused Read = 1b, Write = Don't Care.
6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2Timer 2 Interrupt Priority Control.
This bit sets the priority of th e Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4 PS0 UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt se t to high priority level.
3PT1Timer 1 Interrupt Priority Control.
This bit sets the priority of th e Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2 PX1 External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0Timer 0 Interrupt Priority Control.
This bit sets the priority of th e Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0 PX0 External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
C8051F70x/71x
142 Rev. 1.0
SFR Address = 0xE6; SFR Page = All Pages
SFR Definition 21.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name ET3 Reserved ECP0 EPCA0 EADC0 EWADC0 EMAT ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ET3Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupt.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6 Reserved Must write 0.
5ECP0Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 rising edge or falling edge interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF and CP0FIF flags.
4 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3 EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2EWADC0Enable Window Comparison ADC0 interrupt.
This bit sets the masking of ADC0 Window Comparison interrup t.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1EMATEnable Port Match Interrupts.
This bit sets the masking of the Port Match event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0 ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
C8051F70x/71x
Rev. 1.0 143
SFR Address = 0xE7; SFR Page = All Pages
SFR Definition 21.4. EIE2: Extended Interrupt Enable 2
Bit76543210
Name ECSGRT ECSCPT
Type RRRRRRR/WR/W
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b; Write = don’t care.
1ECSGRT
Enable Capacitive Sense Greater Than Comparator Interrupt.
0: Disable Capacitive Sen se Greater Than Comparator interrupt.
1: Enable interrupt requests generated by CS0CMPF.
0ECSCPT
Enable Capacitive Sense Conversion Complete Interrupt.
0: Disable Capacitive Sense Conversion Complete interrupt.
1: Enable interrupt requests generated by CS0INT.
C8051F70x/71x
144 Rev. 1.0
SFR Address = 0xCE; SFR Page = F
SFR Definition 21.5. EIP1: Extended Interrupt Priority 1
Bit76543210
Name PT3 Reserved PCP0 PPCA0 PADC0 PWADC0 PMAT PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PT3Timer 3 Interrupt Priority Control.
This bit sets the priority of th e Timer 3 interrupt.
0: Timer 3 interrupt set to low priority level.
1: Timer 3 interrupt set to high priority level.
6 Reserved Must write 0b.
5PCP0Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 rising edge or falling edge interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2PWADC0ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1PMATPort Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
C8051F70x/71x
Rev. 1.0 145
SFR Address = 0xCF; SFR Page = F
SFR Definition 21.6. EIP2: Extended Interrupt Priority 2
Bit76543210
Name Reserved Reserved Reserved Reserved Reserved Reserved PSCGRT PSCCPT
Type RRRRRRR/WR/W
Reset 00000000
Bit Name Function
7:2 Reserved Must Write 000000b.
1 PSCGRT Capacitive Sense Greater Than Comparator Priority Control.
This bit sets the priority of the Capacitive Sense Greater Than Comparator interrupt.
0: CS0 Greater Than Comparator interrupt set to low priority level.
1: CS0 Greater Than Comparator set to high priority level.
0 PSCCPT Capacitive Sense Conversion Complete Priority Control.
This bit sets the priority of the Capacitive Sense Conversion Complete interrupt.
0: CS0 Conversion Complete set to low priority level.
1: CS0 Conversion Complete set to high priority level.
C8051F70x/71x
146 Rev. 1.0
21.3. INT0 and INT1 External Interrupts
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT 1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “33.1. Timer 0 and Timer 1” on page 264) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 21.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “28.3. Priority Crossbar
Decoder” on page 185 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge- sensitive , th e corres pon ding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interr upt request will be
generated.
IT0 IN0PL INT0 Interrupt IT1 IN1PL INT1 Interrupt
1 0 Active low, edge sensitive 1 0 Active low, edge sensitive
1 1 Active high, edge sensitive 1 1 Active high, edge sensitive
0 0 Active low, level sensitive 0 0 Active low, level sensitive
0 1 Active high, level sensitive 0 1 Active high, level sensitive
C8051F70x/71x
Rev. 1.0 147
SFR Address = 0xE4; SFR Page = F
SFR Definition 21.7. IT01CF: INT0/INT1 Configuration
Bit76543210
Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000001
Bit Name Function
7IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
C8051F70x/71x
Rev. 1.0 148
22. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non -volatile data storag e. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash byte s
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 9.6 for complete Flash memory electrical characteristics.
22.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “35. C2
Interface” on page 301.
The Flash memory can be pr ogrammed by so ftware using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming Flash memory using
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSC TL.0) to logic 1 (this direc ts the MOVX wr ites to target Flas h mem ory); and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software.
Note: A minimum SYSCLK frequency is required for writing or erasing Flash memory, as detailed in Section
“Table 9.6. Flash Electrical Characteristics” on page 50.
For detailed guidelines on programming Flash from firmware, please see Section “22.4. Flash Write and
Erase Guidelines” on page 150.
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases Flash memory from software. Fur-
thermore, there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Any attempt to write or erase Flash memory while the VDD Monitor is disabled, or not
enabled as a reset source, will cause a Flash Error device reset.
22.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 22.2.
22.1.2. Flash Erase Procedure
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Save current interrupt state and disabl e interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
C8051F70x/71x
149 Rev. 1.0
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE and PSEE bits.
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 512-byte page to be erased.
Note: Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of Flash security settings and restriction s affecting Flash erase
operations, please see Section “22.3. Security Options” on page 149.
22.1.3. Flash Write Procedure
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte loc ation to be prog rammed should be erased befo re a new value is written.
The recommended procedure for writing a single byte in Flash is as follows:
1. Save current interrupt state and disabl e interrupts.
2. Ensure that the Flash byte has been erased (has a value of 0xFF).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Note: Flash security settings may prevent writes to some areas of Flash, such as the reserved area. For a summary
of Flash security settings and restrictions affecting Flash write operations, please see Section “22.3. Security
Options” on page 149.
22.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction.
Note: MOVX read instruct ions always target XRAM.
22.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (re ads, writes, and e rase s) by u npr otected code or the C2 interface. Th e F lash secu-
rity mechanism allows the user to lock all Flash pages, starting at page 0, by writing a non-0xFF value to
the lock byte. Note that writing a non-0xFF value to the lock byte will lock all pages of FLASH from
reads, writes, an d erases, including the page containing the lock byte.
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
C8051F70x/71x
Rev. 1.0 150
unlocked pages, and user firmware execu ting on locked pages. Table 22.1 summarizes the Flash security
features of the C8051F70x/71x devices.
22.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating rang e of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F70x/71x devices for the Flash to be successfully modified. If either
the VDD Monitor or t he VDD Monitor re set s ource is not enab le d, a Flash Error Dev ic e Re set will b e
generated when the firmware attempts to modify the Flash.
Table 22.1. Flash Security Summary
Action C2 Debug
Interface User Firmware executing from:
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte) Permitted Permitted Permitted
Read, Write or Erase locked pages
(except page with Lock Byte) Not Permitted FEDR Permitted
Read or Write page containing Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read or Write page containing Lock Byte
(if any page is locked) Not Permitted FEDR Permitted
Read contents of Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read contents of Lock Byte
(if any page is locked) Not Permitted FEDR Permitted
Erase page containing Lock Byte
(if no pages are locked) Permitted FEDR FEDR
Erase page containing Lock Byte - Unlock all pages
(if any page is locked) Only by C2DE FEDR FEDR
Lock additional pages
(change '1's to '0's in the Lock Byte) Not Permitted FEDR FEDR
Unlock individual pages
(change '0's to '1's in the Lock Byte) Not Permitted FEDR FEDR
Read, Write or Erase Reserved Area Not Permitted FEDR FEDR
C2DE - C2 Device Erase (Erases all Flash page s including the page containing the Lock Byte)
FEDR - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset)
- All prohibited opera tions that ar e perfor med vi a the C2 interface a re ignore d (do no t cause de vice reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
C8051F70x/71x
151 Rev. 1.0
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
22.4.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power sup ply to ensure that the sup ply volt ag es listed in the Absolute M aximum Ratin gs
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an extern al VDD brownout circuit to the /RST pin of the device that
holds the device in reset until VDD reaches the minimum device oper ating volt age and r e-assert s /RST
if VDD drops below the minimum device operating voltage.
3. Keep the on- chip VDD Monitor en abled and enable the VDD Monitor as a rese t source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentatio n for more deta ils. Make certain th at there are no delays in sof tware between en abling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web site.
Note: On C8051F70x/71x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On C8051F70x/71x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added preca u tio n, explic itly en ab le the VDD Mo n ito r and en ab le the VDD Monito r as a re se t
source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exampl e, "RSTSRC =
0x02" is correct, bu t "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator , for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
22.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that set s PSWE to a 1 to write Flash bytes and one rout ine in code that set s
both PSWE and PSEE both to a 1 to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance out side the "PSWE = 1;... PSWE = 0;" area. Code e xamples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web site.
9. Disable inte r ru pts prior to set tin g PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enable d by software.
10.Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions re gardin g how to explicitly locate variables in different memory
areas.
11.Add address bounds checking to the routin es that write or erase Flash memor y to en sure th at a routine
called with an illegal address does not result in modification of the Flash.
C8051F70x/71x
Rev. 1.0 152
22.4.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is oper ating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
13.If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
Additional Flash recommendations and examp le cod e can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories web site.
C8051F70x/71x
153 Rev. 1.0
SFR Address =0x8F; SFR Page = All Pages
SFR Definition 22.1. PSCTL: Program Store R/W Control
Bit76543210
Name PSEE PSWE
Type RRRRRRR/WR/W
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b, Write = don’t care.
1 PSEE Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase th e en tir e page that
conta ins the location addressed by the MOVX instruction. The value of the da ta byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash prog ra m memory eras ur e en ab led.
0 PSWE Pro g ram Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
C8051F70x/71x
Rev. 1.0 154
SFR Address = 0xB7; SFR Page = All Pages
SFR Definition 22.2. FLKEY: Flash Lock and Key
Bit76543210
Name FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock an d Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flas h writ es /e ra se s disa ble d un til th e nex t re set.
C8051F70x/71x
Rev. 1.0 155
23. EEPROM
C8051F700/1/4/5/8/9 and C8051F712/3 devices have hardware which emulates 32 bytes of non-volatile,
byte-programmable EEPROM data space. The module mirrors each non-volatile byte through 32 bytes of
volatile data sp ace. This dat a sp ace can be access ed indirectly through EEADDR and EEDATA. Users can
copy the complete 32-byte image between EEPROM space and volatile space using controls in the
EECNTL SFR.
Figure 23.1. EEPROM Block Diagram
23.1. RAM Reads and Writes
In order to perform EEPROM reads and writes, the EEPROM control logic must be enabled by setting
EEEN (EECNTL.7).
32 bytes of RAM can be accessed indirectly through EEADDR and EEDATA. To write to a byte of RAM,
write address of byte to EEADDR and then write the value to be written to EEDATA. To read a byte from
RAM, write address of byte to be read to EEADDR. The value stored at that address can then be read from
EEDATA.
23.2. Auto Increment
When AUTOINC (EECNTL.0) is set, EEADDR will increment by one after each write to EEDATA and each
read from EEDATA. When Auto Increment is enabled and EEADDR reaches the top address of dedicated
RAM space, the next write to or read from EEDATA will cause EEADDR to wrap along the address bound-
ary, which will set the address to 0.
23.3. Interfacing with the EEPROM
The EEPROM is accessed through the dedicated 32 bytes of RAM. Writes to EEPROM are allowed only
after writes have been enabled (see “23.4. EEPROM Security” ). The contents of the EEPROM can be
uploaded to the RAM by setting EEREAD (EECNTL.2). Contents of RAM can be downloaded to EEPROM
by setting EEWRT (EENTL.1).
Note: A minimum SYSCLK frequency is required for writing EEPROM memory, as detailed in Section
“Table 9.9. EEPROM Electrical Characteristics” on page 52.
EEKEY
32 Bytes
EEPROM
32 By te s RAM
EEPROM Control
Logic
EEADDR EEDATA
EECNTL
EEEN
EEREAD
EEWRT
AUTOINC
C8051F70x/71x
156 Rev. 1.0
23.4. EEPROM Security
RAM can only be downloaded to EEPROM after firmware writes a sequence of two bytes to EEKEY. In
order to enable EEPROM writes:
1. Write the first EEPROM key code byte to EEKEY: 0x55
2. Write the second EEPROM key code byte to EEKEY: 0xAA
After a EEPROM writes have been enabled and a single write has executed, the control logic locks
EEPROM writes until the two-byte unlock sequence has been entered into EEKEY again.
The protection state of the EEPROM can be observed by reading EEPSTATE (EEKEY2:0). This state can
be read at any time without affecting the EEPROM’s protection state.
If the two-byte unlock sequence is entered incorrectly, or if a write is attempted without first entering the
two-byte sequence, EEPROM writes will be locked until the next power-on reset.
SFR Address = 0xB6; SFR Page = All Pages
SFR Definition 23.1. EEADDR: EEPROM Byte Address
Bit76543210
Name EEADDR[4:0]
Type RRR R/W
Reset 00000000
Bit Name Description
7:5 Unused Read = 000b; Write = Don’t Care
4:0 EEADDR[4:0] EEPROM Byte Address
Selects one of 32 EEPROM bytes to read/write.
C8051F70x/71x
Rev. 1.0 157
SFR Address = 0xD1; SFR Page = All Pages
SFR Definition 23.2. EEDATA: EEPROM Byte Data
Bit76543210
Name EEDATA[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 EEDATA[7:0] E2PROM Data
The EEDATA register is
used to read bytes from the
EEPROM space and write
bytes to EEPROM space.
Writes byte to location
stored in EEADDR. Returns contents at loca-
tion stored in EEADDR.
C8051F70x/71x
158 Rev. 1.0
SFR Address = 0xC5; SFR Page = F
SFR Definition 23.3. EECNTL: EEPROM Control
Bit76543210
Name EEEN EEREAD EEWRT AUTOINC
Type R/W R R/W
Reset 00000001
Bit Name Description
7 EEEN EEPROM Enable.
0: EEPROM control logic disabled.
1: EEPROM control logic enabled. EEPROM reads and writes can be performed.
6:4 Reserved Reserved. Read = variable; Write = Don’t Care
3 Reserved Reserved. Read = 0b, Write = 0
2 EEREAD EEPROM 32-Byte Read.
0: Does nothing.
1: 32 bytes of EEPROM Data will be read from Flash to internal RAM.
1EEWRITE
EEPROM 32-Byte Write.
0: Does nothing.
1: 32 bytes of EEPROM Data will be written from internal RAM to Flash.
0 AUTOINC Auto Increme nt.
0: Disable auto-increment.
1: Enable auto-increment.
C8051F70x/71x
Rev. 1.0 159
SFR Address = 0xC6; SFR Page = F
SFR Definition 23.4. EEKEY: EEPROM Protect Key
Bit76543210
Name EEKEY EEPSTATE/EEKEY
Type WR/W
Reset 00000000
Bit Name Description Write Read
7:0 EEKEY EEPROM Key.
Protects the EEPROM from
inadvertent writes and
erases.
The sequence 0x55
0xAA must be written to
enable EEPROM writes
and erases
1:0 EEPSTATE EEPROM Protection State.
These bytes show whether
Flash writes/erases have
been enabled, disabled, or
locked.
00: Write/Er ase is not
enabled
01: The first key has
been written
10: Write /Erase is
enabled
11: EEPROM is locked
from further
writes/erases
C8051F70x/71x
Rev. 1.0 160
24. Power Management Modes
The C8051F70x/71x devices have three software programmable power management modes: Idle, Stop,
and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode
is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
wake on events such as a Port Mismatch, Comparator low output, or a Timer 3 overflow. Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode and Suspend mode consume the least
power because the ma jority of the device is shut down with no clocks active. SFR Definition 24.1 describes
the Power Control Register (PCON) used to control the C8051F70x/71x's Stop and Idle power manage-
ment modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition
27.3).
Although the C8051F70x/71x has Idle, Stop, and Suspend modes available, more control over the device
power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption
considerably, at the expense of reduced functionality.
24.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during the
execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Therefore, inst ructions that set the IDLE bit should be followed by an instruction that has two
or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This featur e protect s the system fr om an unintende d permanen t shut d own in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
softwar e prio r to en terin g th e Idle mo de if the WDT was initially configured to allow this operat ion. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “26. Watchdog Timer” on
page 169 for more information on the use and configuration of the WDT.
C8051F70x/71x
161 Rev. 1.0
24.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Dete ctor sho uld be d isabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
24.3. Suspend Mode
Suspend mode allows a system running from the internal oscillator to go to a very low power state similar
to S t op mode, but the processor ca n be awakened by cert ain event s without requiring a re set of the device.
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maint ain their o riginal da t a. Most digit al p eriphera ls are n ot active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source.
Note that the clock divider bits CLKDIV[2:0] in register CLKSEL must be set to "divide by 1" when entering
Suspend mode.
Suspend mode can be terminated by five types of events, a port match (described in Section “28.5. Port
Match” on p a ge 192), a Timer 3 overflow (described in Section “33.3 . Timer 3” on page 278), a comp ar ator
low output (if enabled), a capacitive sense greater-than comparator interrupt, or a device reset event. In
order to run Timer 3 in Suspend mode, the timer must be configured to clock from the external clock
source/8. When Suspend mode is terminated, the device will continue execution on the instruction follow-
ing the one that set th e SUSPEND bit. If the wake event (por t match or T imer 3 overflow) was configured to
generate an interrupt, the interrupt will be serviced upon waking the device. If Suspend mode is terminated
by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execu-
tion at address 0x 00 00 .
Note: The device will still enter Suspend mode if a wake source is "pending", and the device will not wake on
such pending sources . It is important to ensure that the intended wake source will trigger after the device
enters Suspend mode. For example, if a CS0 conversion completes and the interrupt fires before the device is
in Suspend mode, that interrupt cannot trigger the wake event. Because port match events are level-sensitive,
pre-existing port match events will trigger a wake, as long as the match condition is still present when the
device enters Suspend.
C8051F70x/71x
Rev. 1.0 162
SFR Address = 0x87; SFR Page = All Pages
SFR Definition 24.1. PCON: Power Control
Bit76543210
Name GF[5:0] STOP IDLE
Type R/W R/W R/W
Reset 00000000
Bit Name Function
7:2 GF[5:0] General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1STOPStop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
0IDLEIDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
C8051F70x/71x
Rev. 1.0 163
25. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the re set state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
Figure 25.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Rese t
Reset
Funnel
Px.x
Px.x
EN SWRSF
System
Clock CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Errant
FLASH
Operation
RST
(wired-OR)
Power On
Reset
'0'
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
C8051F70x/71x
164 Rev. 1.0
25.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 25.2. plots the
power-on and VDD monitor reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 10 ms.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to deter mine if a po we r- up wa s the cause of re se t. T he conten t of inter na l da ta mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Figure 25.2. Power-On and VDD Monitor Reset Timing
Power-On
Reset
VDD
Monitor
Reset
RST
t
VDD Supply
Logic HIGH
Logic LOW TPORDelay
VDD
VRST
VDD
C8051F70x/71x
Rev. 1.0 165
25.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a re set stat e (see Figure 25.2). When VDD returns
to a level above V RST, the C IP-51 will be released fr om the res et state. Even though internal data memory
contents a re not alter ed by the po wer-fail r eset, it is impossible to dete rmine if V DD dropped b elow th e level
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD monitor is
enabled af ter power- on resets. It s defined st ate (enabled /disabled) is not altered by any other rese t source.
For example, if the VDD monitor is disab led by code and a sof tware reset is perfor med, the VDD monitor will
still be disabled after the reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this i s not desirabl e
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the V DD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 25.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Section “9. Electrical Characteristics” on page 47 for complete electrical characteristics
of the VDD monitor.
C8051F70x/71x
166 Rev. 1.0
SFR Address = 0xFF; SFR Page = All Pages
25.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pi n genera tes a reset; a n externa l pullup a nd/or de coupling o f th e RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “9. Electrical Characteristics”
on page 47 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exte r-
nal reset.
25.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit th at is t riggered by the s yst em clock . If the syst em
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
SFR Definition 25.1. VDM0CN: VDD Monitor Control
Bit7654321 0
Name VDMEN VDDSTAT
Type R/WRRRRRR R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7VDMENVDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Defi-
nition 25.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6VDDSTATVDD Statu s.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above th e V DD monitor threshold.
5:0 Unused Read = Varies; Write = Don’t care.
C8051F70x/71x
Rev. 1.0 167
25.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should b e enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from gene rating an unwanted reset. Th e Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
25.6. Watchdog Timer Reset
The programmable Watchdog Timer (WDT) can be used to prevent software from running out of control
during a system malfunction. The WDT function can be enabled or disabled by software as described in
Section “26. Watchdog Timer” on page 169. If a system malfunction prevents user software from updating
the WDT, a reset is generated and the WDTRSF bit (RSTSRC.3) is set to 1. The state of the RST pin is
unaf fected by this reset.
25.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a MOVX
write operation targets an address above address 0x3DFF.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address
above address 0x3DFF.
A Program read is attempted above user code space. This occurs when user code attempts to branch to an
address above 0x3DFF.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section “22.3. Security
Options” on page 149 ).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The st ate of the RST p in is unaf fected by
this reset.
25.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
C8051F70x/71x
168 Rev. 1.0
SFR Address = 0xEF; SFR Page = All Pages
SFR Definition 25.2. RSTSRC: Reset Source
Bit76543210
Name FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R R R/W R/W R R/W R/W R
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7 Unused Unused. Don’t care. 0
6FERRORFlash Error Reset Flag. N/A Set to 1 if Flash
read/write/erase error
caused the last reset.
5 C0RSEF C omparator0 Reset Enab le
and Flag. Writing a 1 enables
Comparator0 as a reset
source (active-low).
Set to 1 if Comparator0
caused the last reset.
4SWRSFSoftware Reset Force and
Flag. Writing a 1 forces a sys-
tem reset. Set to 1 if last reset was
caused by a write to
SWRSF.
3 WDTRSF Watchdog Timer Reset Flag. N/A Set to 1 if W atchdog T im er
overflow caused the last
reset.
2 MCDRSF Missing Clock Detector
Enable and Flag. Writing a 1 ena bles the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1PORSFPower-On / VDD Monitor
Reset Flag, and VDD monitor
Reset Enable.
Writing a 1 enables the
VDD monitor as a reset
source.
Writing 1 to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
Set to 1 anytime a power-
on or VDD monitor reset
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
0PINRSFHW Pin Reset Flag . N/A Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
C8051F70x/71x
Rev. 1.0 169
26. Watchdog Timer
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow
will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application sof t-
ware before overflow. If the system experiences a software or hardware malfunction preventing the soft-
ware from restarting the WDT, the WDT will overflow and cause a reset.
Following a reset the WDT is automatically enabled and running with the default maximum time interval. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once
locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by
this reset.
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measur es the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in SFR Definition 26.1.
26.1. Enable/Reset WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-
tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.
26.2. Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT:
CLR EA ; disable all interrupts
MOV WDTCN,#0DEh ; disable software watchdog timer
MOV WDTCN,#0ADh
SETB EA ; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
26.3. Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always
intending to use the watchdog should write 0xFF to WDTCN in the initialization code.
26.4. Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
4^(3+WDTCN[2-0]) x Tsysclk ;where Tsysclk is the system clock period.
For a 3 MHz system clock, this provides an interval range of 0.021 to 349.5 ms. WDTCN.7 must be logic 0
when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b
after a system reset.
C8051F70x/71x
170 Rev. 1.0
SFR Address = 0xE3; SFR Page = All Pages
SFR Definition 26.1. WDTCN: Watchdog Timer Control
Bit7654321 0
Name WDT[7:0]
Type R/W
Reset 0001011 1
Bit Name Description Write Read
7:0 WDT[7:0] WDT Control. Writing 0xA5 both
enables and reloads the
WDT.
Writing 0xDE followed
within 4 system clocks by
0xAD disables the WDT.
Writing 0xFF locks out
the disable featur e.
4 WDTSTATUS Watchdog Status Bit. 0: WDT is inactive
1: WDT is active
2:0 WDTTIMEOUT Watchdog Timeout Interval
Bits. WDTCN[2:0] bits set the
Watchdog Timeout Inter-
val. When writing these
bits, WDTCN[7] must be
set to 0.
C8051F70x/71x
Rev. 1.0 171
27. Oscillators and Clock Selection
C8051F70x/71x devices include a programmable internal high-frequency oscillator and an external oscilla-
tor drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the
OSCICN and OSCICL regist ers, as show n in Fig ure 27.1. The system clock can be sourced by the exter-
nal oscillator circuit or the internal oscillator (default). The internal oscillator offers a select able post-scaling
feature, which is initially set to divide the clock by 8.
Figure 27.1. Oscillator Options
27.1. System Clock Selection
The system clock source for the MCU can be selected using the CLKSEL register. The clock selected as
the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching between two clock divide
values, the transition may take up to 128 cycles of the undivided clock source. The CLKRDY flag can be
polled to determine when the new clock divide value has been applied. The clock divider must be set to
"divide by 1" when entering Suspend mode. The system clock source may also be switched on-the-fly. The
switchover takes effect after one clock period of the slower oscillator.
Clock Divider
OSC
Programmable
Internal C lock
Generator
Input
Circuit
EN
SYSCLK
n
OSCICL OSCICN
IOSCEN
IFRDY
SUSPEND
STSYNC
SSE
IFCN1
IFCN0
OSCXCN
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
Option 4 – CMOS M ode
XTAL2
Option 2 – RC Mode
VDD
XTAL2
Option 3 – C Mode
XTAL2
XTAL1
XTAL2
Option 1 – Crystal Mode
10MΩ
CLKSEL
CLKDIV2
CLKDIV1
CLKDIV0
CLKRDY
CLKSL1
CLKSL0
CLKRDY
Clock Divider
n
C8051F70x/71x
172 Rev. 1.0
SFR Address = 0xBD; SFR Page= F
SFR Definition 27.1. CLKSEL: Clock Select
Bit7 6 543210
Name CLKRDY CLKDIV[2:0] Reserved CLKSEL[2:0]
Type R R/W R/W R/W R R/W R/W R/W
Reset 0 0000000
Bit Name Function
7CLKRDYSystem Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4 CLKDIV System Clock Divide r Bits.
Selects the clock division to be applied to the selected source (internal or external).
000: Selected clock is divided by 1.
001: Selected clock is divided by 2.
010: Selected clock is divided by 4.
011 : Selected clock is divided by 8.
100: Selected clock is divided by 16.
101: Selected clock is divided by 32.
110: Sele ct ed clock is divide d by 64.
111: Selected clock is divided by 128.
3 Reserved Read = 0b. Must write 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Internal Oscillator
001: External Oscillator
All other values reserved.
C8051F70x/71x
Rev. 1.0 173
27.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F70x/71x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register
as defined by SFR Definition 27.2.
On C8051F70x/71x devices, OSCICL is factory calibrate d to obtain a 24.5 MHz base fre qu en cy.
The internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg-
ister OSCICN. The divide value defaults to 8 following a reset.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The maximum deviation from the center frequency is ±0.75%. The
output frequency updates occur every 32 cycles and the step size is typically 0.25% of the center fre-
quency.
SFR Address = 0xBF; SFR Page = F
SFR Definition 27.2. OSCICL: Internal H-F Oscillator Calibration
Bit76543210
Name OSCICL[6:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
6:0 OSCICL[7:0] Internal Oscillator Calib ration Bits.
These bits determine the internal oscillator period. When set to 00000000b, the H-F
oscillator operates at its fastest setting. When set to 11111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
C8051F70x/71x
174 Rev. 1.0
SFR Address = 0xA9; SFR Page = F
SFR Definition 27.3. OSCICN: Internal H-F Oscillator Control
Bit765 43210
Name IOSCEN IFRDY SUSPEND STSYNC SSE IFCN[1:0]
Type R/W R R/W R R/W R R/W
Reset 11000000
Bit Name Function
7IOSCENInternal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6IFRDYInternal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4 STSYNC Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than Timer 3
has brought the oscillator out of suspend mode, it make take up to three timer clocks
before the timer can be read or written.
0: Timer 3 registers can be read safely.
1: Timer 3 register reads and writes should not be performed.
3SSESpread Spectrum Enable.
Spread spectrum enable bit.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
2 Unused Read = 0b; Write = Don’t Care
1:0 IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
C8051F70x/71x
Rev. 1.0 175
27.3. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 27.1. A
10 MΩ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 27.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 27.4).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “28.3. Priority Crossbar
Decoder” on page 185 for Crossbar configuration. Additionally, when usin g the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “28.4. Port
I/O Initialization” on page 189 for details on Port input mode selection.
C8051F70x/71x
176 Rev. 1.0
SFR Address = 0xB5; SFR Page = F
SFR Definition 27.4. OSCXCN: External Oscillator Control
Bit76543210
Name XTLVLD XOSCMD[2:0] XFCN[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7XTLVLDC rystal Oscillator Va li d Fl ag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
6:4 XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 st age.
3 Unused Read = 0; Write = Don’t Care
2:0 XFCN[2:0] External Oscillator Frequency Control Bits.
Set according to the desired frequency for Crystal or RC mode.
Set according to the desired K Factor for C mo de.
XFCN Crystal Mode RC Mode C Mode
000 f ≤ 32 kHz f ≤ 25 kHz K Factor = 0.87
001 32 kHz < f ≤ 84 kHz 25 kHz < f ≤ 50 kHz K Factor = 2.6
010 84 kHz < f ≤ 225 kHz 50 kHz < f ≤ 100 kHz K Factor = 7.7
011 225 kHz < f ≤ 590kHz 100kHz < f ≤ 200 kHz K Factor = 22
100 590 kHz < f ≤ 1.5 MHz 200 kHz < f ≤ 400 kHz K Factor = 65
101 1.5 MHz < f ≤ 4MHz 400kHz < f ≤ 800 kHz K Factor = 180
110 4 MHz < f ≤ 10 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 664
111 10 MHz < f ≤ 30 MHz 1.6 MHz < f ≤ 3.2 M Hz K Factor = 1590
C8051F70x/71x
Rev. 1.0 177
27.3.1. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 27.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 27.4 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillator source.
When the crystal oscillator is first enabled, the oscillator amplitude detection circ uit requires a s ettling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system cloc k. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The rec-
ommended procedure is:
1. Force XTAL1 and XTAL2 to a low state. This involves enabling the Crossbar and writing 0 to the port
pins associated with XTAL1 and XTAL2.
2. Configure XTAL1 and XTAL2 as analog inputs.
3. Enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD = 1.
6. If desired, en able the Missin g Clo ck Det ec tor.
7. Switch the system clock to the external oscillator.
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The desired load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data
sheet when completing these calculations.
For examp le, a tun ing-fo rk crystal of 32 .768 kHz with a recomm ended load capacitance of 1 2.5 pF should
use the configuration shown in F igure 27.1, Option 1. The tot al value of the capacitors and the stray capa c-
itance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capa citance of 12.5 pF across the crystal, as shown in Figure 27.2.
C8051F70x/71x
178 Rev. 1.0
Figure 27.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram
27.3.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circ uit should be configured as
shown in Figure 27.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation , where
f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in
kΩ.
Equation 27.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF:
f = 1.23( 103) / RC = 1.23 ( 103) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 27.4, the required XFCN setting is 010b.
XTAL1
XTAL2
10MΩ
22pF*22pF* 32.768 kHz
* Capacitor values depend on
crystal specificatio ns
f1.23 103
×RC×()⁄=
C8051F70x/71x
Rev. 1.0 179
27.3.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 27.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the frequency of oscillation according to Equation , where f = the frequency of oscil-
lation in MHz, C = the capacitor value in pF, and VDD = the MCU power supply in Volts.
Equation 27.2. C Mode Oscillator Frequency
For example: Assume VDD = 3.0 V and f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is d esired, select the K Factor from the tab le in SFR Definition 27.4
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
fKF()RV
DD
×()⁄=
C8051F70x/71x
Rev. 1.0 180
28. Port Input/Output
Digital and analog resources are available through 64 I/O pins. Each of the Port pins P0.0–P2.7 can be
defined as general-purp ose I/O (GPIO), assigned to one of th e in te rnal dig ital resources, or assigne d to an
analog function as shown in Figure 28.4. The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Cr ossbar Decoder. The state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder.
The registers XBR0 and XBR1, defined in SFR Definition 28.1 and SFR Definition 28.2, are used to select
internal digital functions.
All Port I/Os except P0.3 are tolerant of voltages up to 2 V above the VDD supply (refer to Figure 28.2 for
the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output
Mode registers (PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in
Section “9. Electrical Characteristics” on page 47.
Figure 28.1. Port I/O Functional Block Diagram
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
Port M atch
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
4
PCA
2
CP0
Outputs
SPI 4
P1.0
8
(Port Latches)
P0 (P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
8
PnMDOUT,
PnMDIN , P nDRV
Registers
P1.7
P2.0
P2.7
To Analog Peripherals
(ADC0, C P0, VREF, XTAL)
E x te rn al In te rru p ts
EX0 and EX1
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
P4
I/O
Cells
P5
I/O
Cells
P6
I/O
Cells
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.5
To CS0
C8051F70x/71x
181 Rev. 1.0
28.1. Port I/O Modes of Operation
Port pins P0.0 - P6.5 use the Port I/O cell shown in Figure 28.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a
high impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = 1), both the
high and low port I/O drive circuits are explicitly disabled on all crossbar pins.
28.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, Capacitive Sense input, external os cillator input/output,
VREF output, or AGND connection should be configured for analog I/O (PnMDIN.n = 0). When a pin is
configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins config-
ured for analog I/O will always read back a value of 0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
28.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external event trigger functions, or as
GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes
(push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driv er disabled; ther efore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
low drivers turned off) when the output logic value is 1.
When a digit al I/O cell is placed in the high im pedan ce st ate, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize powe r consumption, and they may be globally disabled by
setting WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or
driven to a valid logic st ate to mi nimize power consum ption. Po rt pins configured for digit al I/O always read
back the logic state of the Port pad, regar dless of the output logic valu e of the Por t pi n.
Figure 28.2. Port I/O Cell Block Diagram
GND
VDD VDD
(WEAK)
PORT
PAD
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
WEAKPUD
(Weak Pull-Up Disable)
C8051F70x/71x
Rev. 1.0 182
28.1.3. Interfacing Port I/O to 5 V Logic
All Port I/O configured for digit al, open-drain o peration are cap able of interfacing to digit al logic operating at
a supply voltage up to 2 V higher than VDD and less than 5.25 V. An external pull-up resistor to the higher
supply voltage is typically required for most systems.
Import ant No te: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150 µA to flow into the Port pin when the supply voltage is between (VDD + 0. 6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 28.3 shows the input current characteristics of por t pins driven above VDD. The port pin
requires 150 µA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
Figure 28.3. Port I/O Overdrive Current
28.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “9. Electrical Characteris-
tics” on page 47 for the difference in output drive strength be tween the two modes.
28.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.7 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digi-
tal or external interrupt functions should be configured for digital I/O.
28.2.1. Assigning Port I/O Pins to Analog Functions
Table 2 8.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog f unctions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Table 28.1 shows the
potential mapping of Port I/O to each analog function.
+
-Vtest
IVtest
VDD
IVtest
(µA)
Vtest (V)
0
-10
-150
VDD VDD+0.7
I/O
Cell
Port I/O Overdrive Current vs. VoltagePort I/O Overdrive Test Circuit
C8051F70x/71x
183 Rev. 1.0
Table 28.1. Port I/O Assignment for Analog Functions
Analog Function Potentially Assignable
Port Pins SFR(s) used for
Assignment
ADC Input P0.0–P1.7 AMX0P, AMX0N ,
PnSKIP, PnMDIN
Comparator0 Input P1.0–P1.7 CPT0MX, PnSKIP,
PnMDIN
CS0 Input P2.0–P6.5 PnMDIN
Voltage Refe rence (VREF0) P0.0 REF0CN, P0SKIP,
PnMDIN
Ground Reference (AGND) P0.1 REF0CN, P0SKIP
External Oscillator in Crystal Mode (XTAL1) P0.2 OSCXCN, P0SKIP,
P0MDIN
External Oscillator in RC, C, or Crystal Mode (XTAL2) P0.3 OSCXCN, P0SKIP,
P0MDIN
C8051F70x/71x
Rev. 1.0 184
28.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digit al functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins sele cted for use as GPIO should hav e their correspo nding bit in PnSKIP set
to 1. Table 28.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
28.2.3. Assigning Port I/O Pins to External Event Trigger Functions
External event trigger functions can be used to trigger an interrupt or wake the device from a low power
mode when a transition occurs on a digital I/O pin. The event trigger functions do not require dedicated
pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP = 0).
External event trigger functions cannot be used on pins configured for analog I/O. Table 28.3 shows all
available external event trigger functions.
Table 28.2. Port I/O Assignment for Digital Functions
Digital Function Potentially Assignable Port Pins SFR(s) used for
Assignment
UART0, SPI0, SMBus, CP0,
CP0A, SYSCLK, PCA0
(CEX0-2 and ECI) , T0 or T1 .
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P2. 7 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
pins to P0.4 and P0.5.
XBR0, XBR1
Any pin used for GPIO P0.0–P6.5 P0SKIP, P1SKIP,
P2SKIP
External Memory Interface P3.0–P6.2 EMI0CF
Table 28.3. Port I/O Assignment for External Event Trigger Functions
Event Trigger Function Potentially Assignable Port Pins SFR(s) used for
Assignment
External Interrupt 0 P0.0–P0.7 IT01CF
External Interrupt 1 P0.0–P0.7 IT01CF
Port Match P0.0–P1.7 P0MASK, P0MAT
P1MASK, P1MAT
C8051F70x/71x
185 Rev. 1.0
28.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When
a digital resour ce is selected, the least-significant unassigned Por t pin is assigned to that resource (exclud-
ing UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when
assigning the next selected resource. The potential crossbar pin assignments are shown in Figure 28.4.
Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The
PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions,
or GPIO. The Cros sbar skips selected pin s as if the y were already assigned, and moves to the next unas-
signed pin. Figure 28.5 shows an example crossbar configuration with no pins skipped. Figure 28.6 shows
the same example with pins P0.2, P0.3 and P1.0 skipped.
If a Port pin is claimed by a pe rip heral witho ut use of the Crossbar, its corresponding PnSKIP bit should be
set. This applies to P0.0 if VREF is used, P0.1 if AGND is used, P0.3 and/or P0.2 if the external oscillator
circuit is enabled, P0.6 if the ADC is configured to use the external conversion start signal (CNVSTR), and
any selected ADC or Comparator inputs. It is also important to skip any pins that do not exist for the pack-
age being used.
Registers XBR0 and XBR1 are used to assign the dig ital I/O re so urce s to the phys ic al I/O Port pi ns. When
the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when
the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UA RT0 pin
assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is
always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been
assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSS-
MD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
C8051F70x/71x
Rev. 1.0 186
Figure 28.4. Crossbar Priority Decoder—Possible Pin Assignments
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
01234567
P0Port
Pin Number
Special
Function
Signals
VREF
XTAL2
CNVSTR
00000000
P0SKIP
Pin Skip
Settings
AGND
XTAL1
SCK
MISO
MOSI
NSS*
01234567
P1
00000000
P1SKIP
0 1 2 3 4 5 6 7
P2
0 0 0 0 0 0 0 0
P2SKIP
The crossbar peripherals are assigned in priority order from top to bottom, according to this
diagram.
These boxes represent Port pin s which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are
enabled, the Crossba r should be manually configured to skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
* NSS is only pinned out when the SPI is in 4-wire mode.
C8051F70x/71x
187 Rev. 1.0
Figure 28.5. Crossbar Priority Decoder in Example Configuration—No Pins Skipped
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0 1 2 3 4 5 6 7
P0Port
Pin Number
Special
Function
Signals
VREF
XTAL2
CNVSTR
0 0 0 0 0 0 0 0
P0SKIP
Pin Skip
Settings
AGND
XTAL1
SCK
MISO
MOSI
NSS*
01234567
P1
00000000
P1SKIP
01234567
P2
00000000
P2SKIP
TX0 and RX0 are fixed at these locations
The other peripherals are assig ned based on
pin availability, in priority order.
This example shows a crossbar configuration with XBR0 = 0x07 and XBR1 = 0x43.
These boxes represent Port pins which are assigned to a peripheral.
C8051F70x/71x
Rev. 1.0 188
Figure 28.6. Crossbar Priority Decoder in Example Configuration—3 Pins Skipped
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0 1 2 3 4 5 6 7
P0Port
Pin Number
Special
Function
Signals
VREF
XTAL2
CNVSTR
0 0 1 1 0 0 0 0
P0SKIP
Pin Skip
Settings
AGND
XTAL1
SCK
MISO
MOSI
NSS*
0 1 2 3 4 5 6 7
P1
1 0 0 0 0 0 0 0
P1SKIP
0 1 2 3 4 5 6 7
P2
0 0 0 0 0 0 0 0
P2SKIP
This example shows a crossbar configuration with XBR0 = 0x07 and XBR1 = 0x43.
These boxes represent Port pins which are assigned to a peripheral.
P0.2 Skipped
P0.3 Skipped
P1.0 Skipped
If a pin is skipped, it is not available for
assignment, and the crossbar will move
the assignment to the next available pin
C8051F70x/71x
189 Rev. 1.0
28.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped b y the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bi ts in PnSKIP). Port input mo de is set in the PnMDIN register, where a 1 indicates a
digital inpu t, and a 0 indica tes an analog inpu t. All pins default to digit al inpu ts on reset. See SFR Definition
28.8 for the PnMDIN register details.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
C8051F70x/71x
Rev. 1.0 190
SFR Address = 0xE1; SFR Page = F
SFR Definition 28.1. XBR0: Port I/O Crossbar Register 0
Bit76543210
Name CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5CP0AE
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0URT0E
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
C8051F70x/71x
191 Rev. 1.0
SFR Address = 0xE2; SFR Page = F
SFR Definition 28.2. XBR1: Port I/O Crossbar Register 1
Bit7 6543210
Name WEAKPUD XBARE T1E T0E ECIE PCA0ME[1:0]
Type R/W R/W R/W R/W R/W R R/W R/W
Reset 0 0000000
Bit Name Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6 XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5T1ET1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
4T0ET0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
3ECIEPCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
2 Unused Read = 0b; W rite = Don’t Care.
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
C8051F70x/71x
Rev. 1.0 192
28.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft -
ware controlled value stored in th e PnMATCH registers specifies the expe cted or normal logic va lues of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft -
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Address = 0xF4; SFR Page = 0
SFR Definition 28.3. P0MASK: Port 0 Mask Register
Bit76543210
Name P0MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MASK[7:0] Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
C8051F70x/71x
193 Rev. 1.0
SFR Address = 0xF3; SFR Page = 0
SFR Address = 0xE2; SFR Page = 0
SFR Definition 28.4. P0MAT: Port 0 Match Register
Bit76543210
Name P0MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
SFR Definition 28.5. P1MASK: Port 1 Mask Register
Bit76543210
Name P1MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
C8051F70x/71x
Rev. 1.0 194
SFR Address = 0xE1; SFR Page = 0
28.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output da ta value at each pin . When reading, the logic levels of the Port's inpu t pins are re turned
regardless of the XBRn settings (i.e., even when the pin is as signed to another signal by the Crossbar, the
Port register can alwa ys read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when opera ting o n a Port SFR ar e the fo llowing: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an in di vidua l bit in a Por t SFR. Fo r these instru ctio ns, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corr es po n ding Pn SKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar . All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have th eir PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 28.6. P1MAT: Port 1 Match Register
Bit76543210
Name P1MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
C8051F70x/71x
195 Rev. 1.0
SFR Address = 0x80; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF1; SFR Page = F
SFR Definition 28.7. P0: Port 0
Bit76543210
Name P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 28.8. P0MDIN: Port 0 Input Mode
Bit76543210
Name P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P0.n pin is configured for analog mode.
1: Correspon din g P0.n pin is not conf igu re d fo r an alo g mode .
C8051F70x/71x
Rev. 1.0 196
SFR Address = 0xA4; SFR Page = F
SFR Address = 0xD4; SFR Page = F
SFR Definition 28.9. P0MDOUT: Port 0 Output Mode
Bit76543210
Name P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Correspon ding P0 .n Ou tp u t is push-p u ll.
SFR Definition 28.10. P0SKIP: Port 0 Skip
Bit76543210
Name P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
C8051F70x/71x
197 Rev. 1.0
SFR Address = 0xF9; SFR Page = F
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
SFR Definition 28.11. P0DRV: Port 0 Drive Strength
Bit76543210
Name P0DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0DRV[7:0] Drive Streng th Configuration Bits for P0.7–P0.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
SFR Definition 28.12. P1: Port 1
Bit76543210
Name P1[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
C8051F70x/71x
Rev. 1.0 198
SFR Address = 0xF2; SFR Page = F
SFR Address = 0xA5; SFR Page = F
SFR Definition 28.13. P1MDIN: Port 1 Input Mode
Bit76543210
Name P1MDIN[7:0]
Type R/W
Reset 1*1111111
Bit Name Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P1.n pin is configured for analog mode.
1: Correspon din g P1.n pin is not conf igu re d fo r an alo g mode .
Note: On C8051F716 and C8051F717 devices, P1.7 will default to analog mode. If the P1MDIN register is written
on the C8051F716 and C8051F717 devices, P1.7 should always be configured as analog.
SFR Definition 28.14. P1MDOUT: Port 1 Output Mode
Bit76543210
Name P1MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Correspon ding P1 .n Ou tp u t is push-p u ll.
C8051F70x/71x
199 Rev. 1.0
SFR Address = 0xD5; SFR Page = F
SFR Address = 0xFA; SFR Page = F
SFR Definition 28.15. P1SKIP: Port 1 Skip
Bit76543210
Name P1SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
SFR Definition 28.16. P1DRV: Port 1 Drive Strength
Bit76543210
Name P1DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1DRV[7:0] Drive Streng th Configuration Bits for P1.7–P1.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
C8051F70x/71x
Rev. 1.0 200
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF3; SFR Page = F
SFR Definition 28.17. P2: Port 2
Bit76543210
Name P2[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P2[7:0] Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
SFR Definition 28.18. P2MDIN: Port 2 Input Mode
Bit76543210
Name P2MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P2.n pin is configured for analog mode.
1: Correspon din g P2.n pin is not conf igu re d fo r an alo g mode .
C8051F70x/71x
201 Rev. 1.0
SFR Address = 0xA6; SFR Page = F
SFR Address = 0xD6; SFR Page = F
SFR Definition 28.19. P2MDOUT: Port 2 Output Mode
Bit76543210
Name P2MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Correspon ding P2 .n Ou tp u t is push-p u ll.
SFR Definition 28.20. P2SKIP: Port 2 Skip
Bit76543210
Name P2SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2SKIP[3:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
C8051F70x/71x
Rev. 1.0 202
SFR Address = 0xFB; SFR Page = F
SFR Address = 0xB0; SFR Page = All Pages; Bit Addressable
SFR Definition 28.21. P2DRV: Port 2 Drive Strength
Bit76543210
Name P2DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2DRV[7:0] Drive Streng th Configuration Bits for P2.7–P2.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P2.n Output has low output drive strength.
1: Corresponding P2.n Output has high output drive strength.
SFR Definition 28.22. P3: Port 3
Bit76543210
Name P3[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P3[7:0] Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
C8051F70x/71x
203 Rev. 1.0
SFR Address = 0xF4; SFR Page = F
SFR Address = 0xAF; SFR Page = F
SFR Definition 28.23. P3MDIN: Port 3 Input Mode
Bit76543210
Name P3MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P3.n pin is configured for analog mode.
1: Correspon din g P3.n pin is not conf igu re d fo r an alo g mode .
SFR Definition 28.24. P3MDOUT: Port 3 Output Mode
Bit76543210
Name P3MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Correspon ding P3 .n Ou tp u t is push-p u ll.
C8051F70x/71x
Rev. 1.0 204
SFR Address = 0xFC; SFR Page = F
SFR Address = 0xAC; SFR Page = All Pages
SFR Definition 28.25. P3DRV: Port 3 Drive Strength
Bit76543210
Name P3DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3DRV[7:0] Drive Streng th Configuration Bits for P3.7-P3.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P3.n Output has low output drive strength.
1: Corresponding P3.n Output has high output drive strength.
SFR Definition 28.26. P4: Port 4
Bit76543210
Name P4[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P4[7:0] Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
C8051F70x/71x
205 Rev. 1.0
SFR Address = 0xF5; SFR Page = F
SFR Address = 0x9A; SFR Page = F
SFR Definition 28.27. P4MDIN: Port 4 Input Mode
Bit76543210
Name P4MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P4MDIN[7:0] Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P4.n pin is configured for analog mode.
1: Correspon din g P4.n pin is not conf igu re d fo r an alo g mode .
SFR Definition 28.28. P4MDOUT: Port 4 Output Mode
Bit76543210
Name P4MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P4MDOUT[7:0] Output Configuration Bits for P4.7–P4.0 (respectively).
These bits are ignored if the corresponding bit in register P4MDIN is logic 0.
0: Corresponding P4.n Output is open-drain.
1: Correspon ding P4 .n Ou tp u t is push-p u ll.
C8051F70x/71x
Rev. 1.0 206
SFR Address = 0xFD; SFR Page = F
SFR Address = 0xB3; SFR Page = All Pages
SFR Definition 28.29. P4DRV: Port 4 Drive Strength
Bit76543210
Name P4DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P4DRV[7:0] Drive Streng th Configuration Bits for P4.7–P4.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P4.n Output has low output drive strength.
1: Corresponding P4.n Output has high output drive strength.
SFR Definition 28.30. P5: Port 5
Bit76543210
Name P5[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P5[7:0] Port 5 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P5.n Port pin is logic
LOW.
1: P5.n Port pin is logic
HIGH.
C8051F70x/71x
207 Rev. 1.0
SFR Address = 0xF6; SFR Page = F
SFR Address = 0x9B; SFR Page = F
SFR Definition 28.31. P5MDIN: Port 5 Input Mode
Bit76543210
Name P5MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P5MDIN[7:0] Analog Configuration Bits for P5.7–P5.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P5.n pin is configured for analog mode.
1: Correspon din g P5.n pin is not conf igu re d fo r an alo g mode .
SFR Definition 28.32. P5MDOUT: Port 5 Output Mode
Bit76543210
Name P5MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P5MDOUT[7:0] Output Configuration Bits for P5.7–P5.0 (respectively).
These bits are ignored if the corresponding bit in register P5MDIN is logic 0.
0: Corresponding P5.n Output is open-drain.
1: Correspon ding P5 .n Ou tp u t is push-p u ll.
C8051F70x/71x
Rev. 1.0 208
SFR Address = 0xFE; SFR Page = F
SFR Address = 0xB2; SFR Page = All Pages
SFR Definition 28.33. P5DRV: Port 5 Drive Strength
Bit76543210
Name P5DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P5DRV[7:0] Drive Streng th Configuration Bits for P5.7–P5.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P5.n Output has low output drive strength.
1: Corresponding P5.n Output has high output drive strength.
SFR Definition 28.34. P6: Port 6
Bit76543210
Name P6[5:0]
Type RR R/W
Reset 00111111
Bit Name Description Write Read
7:6 Unused Read = 00b; Write = Don’t Care
5:0 P6[5:0] Port 6 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P6.n Port pin is logic
LOW.
1: P6.n Port pin is logic
HIGH.
C8051F70x/71x
209 Rev. 1.0
SFR Address = 0xF7; SFR Page = F
SFR Address = 0x9C; SFR Page = F
SFR Definition 28.35. P6MDIN: Port 6 Input Mode
Bit76543210
Name P6MDIN[5:0]
Type RR R/W
Reset 00111111
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care
5:0 P6MDIN[5:0] Analog Configuration Bits for P6.5–P6.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disable d.
0: Corresponding P6.n pin is configured for analog mode.
1: Correspon din g P6.n pin is not conf igu re d fo r an alo g mode .
SFR Definition 28.36. P6MDOUT: Port 6 Output Mode
Bit76543210
Name P6MDOUT[5:0]
Type RR R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care
5:0 P6MDOUT[5:0] Output Configuration Bits for P6.5–P6.0 (respectively).
These bits are ignored if the corresponding bit in register P6MDIN is logic 0.
0: Corresponding P6.n Output is open-drain.
1: Correspon ding P6 .n Ou tp u t is push-p u ll.
C8051F70x/71x
Rev. 1.0 210
SFR Address = 0xC1; SFR Page = F
SFR Definition 28.37. P6DRV: Port 6 Drive Strength
Bit76543210
Name P6DRV[5:0]
Type RR R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care
5:0 P6DRV[5:0] Drive Streng th Configuration Bits for P6.5–P6.0 (resp ectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P6.n Output has low output drive strength.
1: Corresponding P6.n Output has high output drive strength.
C8051F70x/71x
Rev. 1.0 211
29. Cyclic Redundancy Check Unit (CRC0)
C8051F70x/71x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a
16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0
posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi-
rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 29.1. CRC0 also has a bit
reverse register for quick data manipulation.
Figure 29.1. CRC0 Block Diagram
CRC0IN 8
CRC0DAT
CRC0CN
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
4 to 1 MUX
RESULT
32
8 8 8 8
8
CRC0AUTO
CRC0CNT
Automat ic CRC
Controller Flash
Memory
8
CRC0FLIP
Write
CRC0FLIP
Read
C8051F70x/71x
212 Rev. 1.0
29.1. 16-bit CRC Algorithm
The C8051F70x/71x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16 -b it CRC algo rith m perfo rm e d by th e ha rd wa re :
1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration of
the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
2. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with the
polynomial (0x1021).
3. If the MSB of the CRC result is not set, left-shift the CRC result.
4. Repeat at Step 2 for the number of input bits (8).
For example, the 16-bit C80 51F70x/71x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input){
unsigned char i; // loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
return CRC_acc; // Return the final remainder (CRC value)
}
Table 29.1 lists example input values and the associated outputs using the 16-bit C8051F70x/71x CRC
algorithm (an initial value of 0xFFFF is used):
Table 29.1. Example 16-bit CRC Outputs
Input Output
0x63 0xBD35
0xAA, 0xBB, 0xCC 0x6CF6
0x00, 0x00, 0xAA, 0xBB, 0xCC 0xB166
C8051F70x/71x
Rev. 1.0 213
29.2. 32-bit CRC Algorithm
The C8051F70x/71x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-3 2 algo-
rithm is "reflected", meaning that all of the inp ut bytes and the final 32-bit output a re bit-re versed in the pro-
cessing engine. The following is a description of a simplified CRC algorithm that produces results identical
to the hardware:
1. XOR the least-significant byte of the cur rent CRC result with the input byte. If this is the first iterati on of
the CRC unit, the current CRC result will be the set initial value (0x00000000 or 0xFFFFFFFF).
2. Right-shift the CRC result.
3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial (0xEDB8 8320).
4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit C80 51F70x/71x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input){
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
}
return CRC_acc; // Return the final remainder (CRC value)
}
Table 29.2 lists example input values and the associated outputs using the 32-bit C8051F70x/71x CRC
algorithm (an initial value of 0xFFFFF FFF is used):
Table 29.2. Example 32-bit CRC Outputs
Input Output
0x63 0xF9462090
0xAA, 0xBB, 0xCC 0x41B207B3
0x00, 0x00, 0xAA, 0xBB, 0xCC 0x78D129BC
C8051F70x/71x
214 Rev. 1.0
29.3. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
29.4. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated af ter each byte is written . The CRC engine may also be configur ed to
automatically perform a CRC on one or more Flash sectors. The f ollowing ste ps can be us ed t o autom ati-
cally perform a CRC on Flash memory.
1. Prepar e CRC0 for a CRC calculation as shown above.
2. Write the index of th e starting page to CRC0AUTO.
3. Set the AUTOEN bit in CRC0AUTO.
4. Write the number of Flas h s ec to rs to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 512 bytes.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The CPU will
not execute code any additional code until the CRC operation completes.
6. Clear the AUTOEN bit in CRC0AUTO.
7. Read the CRC result using the procedure below.
29.5. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is t argeted by re ad and write opera tions on CRC0DAT and increment af ter each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or addi-
tional data is written to CRC0IN.
C8051F70x/71x
Rev. 1.0 215
SFR Address = 0x91; SFR Page = F
SFR Definition 29.1. CRC0CN: CRC0 Control
Bit76543210
Name CRC0SEL CRC0INIT CRC0VAL CRC0PNT[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care.
4 CRC0SEL CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3 CRC0INIT CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
2 CRC0VAL CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000 000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC re sult.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
C8051F70x/71x
216 Rev. 1.0
SFR Address = 0x94; SFR Page = F
SFR Address = 0xD9; SFR Page = F
SFR Definition 29.2. CRC0IN: CRC Data Input
Bit76543210
Name CRC0IN[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 29.1
SFR Definition 29.3. CRC0DATA: CRC Data Output
Bit76543210
Name CRC0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
C8051F70x/71x
Rev. 1.0 217
SFR Address = 0x96; SFR Page = F
SFR Address = 0x97; SFR Page = F
SFR Definition 29.4. CRC0AUTO: CRC Automatic Control
Bit76543210
Name AUTOEN CRCCPT Reserved CRC0ST[4:0]
Type R/W
Reset 01000000
Bit Name Function
7AUTOENAutomatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6 CRCCPT Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Code execution is stopped during
a CRC calculation, therefore reads from firmware will always return 1.
5 Reserved Reserved. Must write 0.
4:0 CRC0ST[4:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting ad dress of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 512.
SFR Definition 29.5. CRC0CNT: CRC Automatic Flash Sector Count
Bit76543210
Name CRC0CNT[5:0]
Type RR R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include when performing an
automatic CRC calculation. Th e base address of the last flash sector included in
the automatic CRC calculation is equal to (CRC0ST + CRC0CNT) x 512.
C8051F70x/71x
218 Rev. 1.0
29.6. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 29.1. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
SFR Address = 0x95; SFR Page = F
SFR Definition 29.6. CRC0FLIP: CRC Bit Flip
Bit76543210
Name CRC0FLIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0FLIP[7:0] CRC0 Bit Flip.
Any byte written to CRC0FLIP is read back in a bit-reversed order , i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
C8051F70x/71x
Rev. 1.0 219
30. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SM Bus is compliant wit h the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, dependin g on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface m ay opera te as a ma ster an d/or slav e, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., sof tware accept s/r ejects slave addresses, an d ge ner at es ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 30.1.
Figure 30.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflo w
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567 SMB0DAT SDA
FILTER
N
SMB0ADR
S
L
V
4
S
L
V
2
S
L
V
1
S
L
V
0
G
C
S
L
V
5
S
L
V
6
S
L
V
3
SMB0ADM
S
L
V
M
4
S
L
V
M
2
S
L
V
M
1
S
L
V
M
0
E
H
A
C
K
S
L
V
M
5
S
L
V
M
6
S
L
V
M
3
Arbitration
SCL Synchronization
Hardware ACK Generation
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
IRQ Generation
C8051F70x/71x
220 Rev. 1.0
30.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
30.2. SMBus Configuration
Figure 30.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; diff erent de vices on the bus may o perate at d ifferent voltage levels. The bi-d ire c-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on th e bus is limited only by th e requ irem ent that the ri se
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 30.2. Typical SMBus Configuration
30.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. It is not necessary to specify one device
as the Master in a system; any device who transmits a START and a slave address becomes the master
for the duration of th at transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 30.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bi t (R/W) occupies the least-significan t bit position of th e address byte. The d irection bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
VDD = 5V
Master
Device Slave
Device 1 Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SDA
SCL
C8051F70x/71x
Rev. 1.0 221
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer , the master
generates a STOP condition to terminate the transaction and free the bus. Figure 30.3 illustrates a typic al
SMBus transaction.
Figure 30.3. SMBus Transaction
30.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bu s. A de vice is a “recei ver” when an ad dress or dat a byte is being se nt
to it from another device on the bus. The transmitter controls the SDA line during the ad dress or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK ph ase of the transfer, during which time the receiver controls the SDA line.
30.3.2. Arbitration
A master may star t a transfer on ly if the bus is free. The b us is free af ter a ST OP con dition or after the SCL
and SDA lines remain high for a specified time (see Section “30.3.5. SCL High (SMBus Free) Timeout” on
page 222). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interru ption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
30.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
30.3.4. SCL Low Timeout
If the SCL line is held low b y a slave device on the bus, no fur ther communica tion is possible . Furthermore,
the master ca nnot for ce the SCL lin e high to co rrect th e error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
SLA6
SDA SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
C8051F70x/71x
222 Rev. 1.0
overflow after 25 ms (and SMBTOE set), the T im er 3 interrupt service routine can be used to reset (disabl e
and re-enable) the SMBus in the event of an SCL low timeout.
30.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
30.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycl e so that sof tware may read the receive d ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware ackn owled ge ment is en able d,
these interrupts are always generated after the ACK cycle. See Section 30.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 30.4.2;
Table 30.5 provide s a qu i ck SMB 0CN dec od i ng ref er en ce .
30.4.1. SMBus Configuration Re gi st er
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current tra ns fe r) .
C8051F70x/71x
Rev. 1.0 223
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 30.1.The selected
clock source may be shared by other peripherals so long as the timer is left running at all times. For exam-
ple, T i mer 1 overflows may generate the SMBu s and UA R T baud rates simu ltan eously. T i mer configu ration
is covered in Section “33. Timers” on page 262.
Equation 30.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 30.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus ), the typ ica l SMBu s bit rate is approximated by Equation 30.2.
Equation 30.2. Typical SMBus Bit Rate
Figure 30.4 shows the typical SCL generation described by Equation 30.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 30.1.
Figure 30.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit ext ends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL tran sitions from low-to- high.
The minimum SDA hold time defin es the absolute minimum time that the curre nt SDA value remains stabl e
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements o f 250 ns and 300 ns, respectively. Table 30.2 shows the min-
Table 30.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0 0 Timer 0 Overflow
0 1 Timer 1 Overflow
1 0 Ti mer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow
THighMin TLowMin 1
fClockSourceOverflow
----------------------------------------------
==
BitRate fClockSourceOverflow
3
----------------------------------------------
=
SCL
Timer Source
Overflows
SCL High Ti meoutT
Low
T
High
C8051F70x/71x
224 Rev. 1.0
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “30.3.4. SCL Low Timeout” on page 221). The SMBus interface will force Timer 3 to
reload while SCL is hig h, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free T imeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 30.4).
Table 30.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0Tlow – 4 system clocks
or
1 system clock + s/w delay*3 system clocks
1 11 system clocks 12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the out going ACK value, s/w delay is zero.
C8051F70x/71x
Rev. 1.0 225
SFR Address = 0xC1; SFR Page = 0
SFR Definition 30.1. SMB0CF: SMBus Clock/Configuration
Bit76543210
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Type R/W R/W R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ENSMBSMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6INHSMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not gene rate an interrupt when slave
events occur. This effectively removes the SMBus sla ve from the bus. Master Mode
interrupts are not affected.
5BUSYSMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4 EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 30.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3SMBTOESMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
T i mer 3 to reload while SCL is high an d allows Timer 3 to count when SCL goes low.
If T imer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2SMBFTESMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0] SMBus Clock Source Selection.
These two bit s select th e SMBus clock sour ce, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 30.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
C8051F70x/71x
226 Rev. 1.0
30.4.2. SMB0CN Control Regi st er
SMB0CN is used to control the interface and to provide status information (see SFR Definition 30.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a st atus vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving da ta for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and ST O ar e also used to gene rate START and STOP co nditions when op er ating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus be comes fr ee (STA is no t cleared by hard ware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginn ing and end of each transfe r, after each byte frame, or
when an arbitration is lost; see Table 30.3 for more details.
Import ant Note About t he SI Bit : The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
30.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
30.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 30.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the A CK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is no t used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 30.3 lists all sources for hardw are changes to the SM B0CN bits. Refer to Table 30.5 for SMBu s sta-
tus decoding using the SMB0CN register.
C8051F70x/71x
Rev. 1.0 227
SFR Address = 0xC0; SFR Page = All Pages; Bit-Addressable
SFR Definition 30.2. SMB0CN: SMBus Control
Bit76543210
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Type RRR/WR/WRRR/WR/W
Reset 00000000
Bit Name Description Read Write
7 MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6TXMODESMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a tran smitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5STASMBus Start Flag. 0: No Start or repeate d
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STOSMBus Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3ACKRQSMBus Acknowledge
Request. 0: No Ack requested
1: ACK requested N/A
2ARBLOSTSMBus Arbitration Lost
Indicator. 0: No arbitration error.
1: Arbitration Lost N/A
1ACKSMBus Acknowledge. 0: NACK received.
1: ACK received. 0: Send NACK
1: Send ACK
0SISMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending 0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
C8051F70x/71x
228 Rev. 1.0
30.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 30.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 30.3) and the SMBus Slave Address Mask register (SFR Definition 30.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address ma sk SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit w ill be treated as a “don’t care” for comparison purposes. In this
Table 30.3. Sources for Hardware Changes to SMB0CN
Bit Set by Hardware When: Cleared by Hardware When:
MASTER A START is generated. A STOP is generated.
Arbitration is lost.
TXMODE
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
STA A START followed by an address byte is
received. Must be cleared by software.
STO
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A pending STOP is generated.
ACKRQ A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
After each ACK cycle.
ARBLOST
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
Each time SI is cleared.
ACK The incoming ACK value is low
(ACKNOWLEDGE). The incoming ACK value is high
(NOT ACKNOWLEDGE).
SI
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Must be cleared by software.
C8051F70x/71x
Rev. 1.0 229
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 30.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions.
SFR Address = 0xBA; SFR Page = F
Table 30.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0] Slave Address Mask
SLVM[6:0] GC bit Slave Addresses Recognized by
Hardware
0x34 0x7F 0 0x34
0x34 0x7F 1 0x34, 0x00 (General Call)
0x34 0x7E 0 0x34, 0x35
0x34 0x7E 1 0x34, 0x35, 0x00 (General Call)
0x70 0x73 0 0x70, 0x74, 0x78, 0x7C
SFR Definition 30.3. SMB0ADR: SMBus Slave Address
Bit76543210
Name SLV[6:0] GC
Type R/W R/W
Reset 00000000
Bit Name Function
7:1 SLV[6:0] SMBus Hardware Slave Address.
Defines the SMBus Slave Addr ess(es) for automatic hardware acknowledge ment.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked again st the inc om in g ad dr es s. Th is allo ws mu ltip le addre sse s to be
recognized.
0GCGeneral Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
C8051F70x/71x
230 Rev. 1.0
SFR Address = 0xBB; SFR Page = F
SFR Definition 30.4. SMB0ADM: SMBus Slave Address Mask
Bit76543210
Name SLVM[6:0] EHACK
Type R/W R/W
Reset 11111110
Bit Name Function
7:1 SLVM[6:0] SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compa red with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the correspondin g bit in SL V[6:0]. Bit s set to 0 are ignored (can b e either
0 or 1 in the incoming address).
0EHACKHardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Ena bled.
C8051F70x/71x
Rev. 1.0 231
30.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmi tted or one that has just been
received. Software may safely read or write to the data r egister when th e SI flag is set. Sof tware sho uld not
attempt to ac cess the SMB0DAT re gister wh en the SMBu s is enabled a nd the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte prese nt on the bu s. In th e even t of lost arb i-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Address = 0xC2; SFR Page = 0
SFR Definition 30.5. SMB0DAT: SMBus Data
Bit76543210
Name SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contains a byte of dat a to be transmitted on the SMBus
serial interface or a byte th at has just been received on the SMBu s serial interface.
The CPU can read fr om or write to this re gister whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
C8051F70x/71x
232 Rev. 1.0
30.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters M aster Mod e a ny time a START is generated, and rem ains i n
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. The position of the ACK interrupt when operating as a receiver depends on
whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs before the
ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is
enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK generation
is enabled or not.
30.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the ad dress byt e, and a tra nsmitte r during all data bytes. The SMBu s interfac e gener -
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the ST O bit is set and a ST OP is generated. The interface will switch
to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 30.5
shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes
may be transmitted. Notice that all of the “d at a byte tran sferred” interru pt s occur after the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
Figure 30.5. Typical Master Write Sequence
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F70x/71x
Rev. 1.0 233
30.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the a ddress byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave o n SDA while th e SMBus outp ut s the seria l clock. The sla ve transmit s one o r more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hard ware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master T r ansmitter Mode if SMB0-
DAT is written while an active Master Receiver. Figure 30.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupt s occur at diff erent places in the sequence, depend ing on whethe r hardware ACK gen-
eration is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after
the ACK when hardware ACK generation is enabled.
Figure 30.6. Typical Master Read Sequence
Data ByteData Byte A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F70x/71x
234 Rev. 1.0
30.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slav e device. The slave in this transfer w ill be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hard ware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. The interface will switch to Slave Trans-
mitter Mode if SMB0DAT is written w hile an active Slave Receiver. Figure 30.7 shows a typical slave write
sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that
the ‘data byte transferred’ interrupts occur at different places in the sequence, depend ing on wheth er hard-
ware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation dis-
abled, and after the ACK when hardware ACK generation is enabled.
Figure 30.7. Typical Slave Write Sequence
PWSLASData ByteData Byte A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmit ted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F70x/71x
Rev. 1.0 235
30.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the inter face enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK g eneration
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detecte d. If the r eceived slav e address is acknowled ged, zero or mo re data bytes are tr ans-
mitted. If the receiv ed sl ave ad dress is ac knowle dged, data should be writ ten to SMB0DAT to be trans mit-
ted. The interfa ce ent ers slav e tran smitt er mo de, and tr ansm its one or more by tes of d ata. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). T he in te rf ac e exits slave t ra ns mit te r m o de after re ce ivin g a STOP.
The interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter
interrupt. Figure 30.8 shows a typical slave read sequence. Two transmitted data b ytes ar e shown, though
any number of bytes may be transmitted. Notice that all of th e “ data byte transferred” in terr up ts occur after
the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Figure 30.8. Typical Slave Read Sequence
30.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 30.5 describes the typical actions when hardware slave address
recognition and ACK gene ration is disabled. Table 30.6 describes the typical actio ns when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allo wed by hardware but do not conform to the SMBus specification.
PRSLASData ByteData Byte A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmit ted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F70x/71x
236 Rev. 1.0
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer. 01X —
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer. 11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
0 0 X 1000
Master Receiver
1000 1 0 X A master data byte was
received; ACK requ ested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 1000
Send NACK to indicate last by te,
and send STOP. 010 —
Send NACK to indicate last by te,
and send STOP followed by
START.
1101110
Send ACK followed by repeated
START. 1011110
Send NACK to indicate last by te,
and send repeated START. 1001110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 1 1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 0 1100
C8051F70x/71x
Rev. 1.0 237
Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X —
Slave Receiver
0010
10X
A slave address + R/W was
received; ACK requ ested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 0 0 0 —
11X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received address. 0 0 0 —
Reschedule failed transfer;
NACK received address. 1001110
0001 00X
A STOP was detected while
addresse d as a Slav e Trans-
mitter or Slave Rec eiver. Clear STO. 00X —
11X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 —
0000 1 0 X A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT. 0 0 1 0000
NACK received byte. 0 0 0 —
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vecto r Exp e ct ed
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F70x/71x
238 Rev. 1.0
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X Lost arbitration du e to a
detected STOP. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 1 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 0 0 0 —
Reschedule failed transfer. 1 0 0 1110
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 00X1100
1100
000
A master dat a or ad dress byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer. 01X —
001
A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into
SMB0DAT. 00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer. 11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0 0 1 1000
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vecto r Exp e ct ed
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F70x/71x
Rev. 1.0 239
Master Receiver
1000
001
A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 1000
Set NACK to indica te next dat a
byte as the last data byte;
Read SMB0DAT.
0 0 0 1000
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
000
A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP. 0 1 0 —
Read SMB0DAT; Send STOP
followed by START. 1101110
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001
A slave byte was transmitted;
ACK rece ived. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01X
A Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0 X X An illegal STOP or bus error
was detected while a Slave
Transmission was in progress. Clear STO. 00X —
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F70x/71x
240 Rev. 1.0
Slave Receiver
0010
00X
A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
01X
Lost arbitra tio n as m ast er ;
slave address + R/W received;
ACK sent.
If Write, Set ACK for first data
byte. 0 0 1 0000
If Read, Load SMB0DAT with
data byte 0 0 X 0100
Reschedule failed transfer 1 0 X 1110
0001 00X
A STOP was detected while
addresse d as a Slav e Trans-
mitter or Slave Rec eiver. Clear STO. 00X —
01X
Lost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 000 —
0000 0 0 X A slave byte was received.
Set ACK for next data byte;
Read SMB0DAT. 0 0 1 0000
Set NACK for next data byte;
Read SMB0DAT. 0 0 0 0000
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X Lost arbitration du e to a
detected STOP. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 0 1 X Lost arbitration while transmit-
ting a dat a byte as master. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 10X1110
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F70x/71x
Rev. 1.0 241
31. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be conf igured as a ch ip-select ou tput in master mode, or disabled fo r 3-wire operation. Addi tional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 31.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
C8051F70x/71x
242 Rev. 1.0
31.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
31.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master d evice an d an in put to s lave d evices. I t
is used to serially trans fer data from the ma ster to th e slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
31.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impeda nce st ate when the SPI module is d isabled and when th e SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
31.1.3. Serial Clock (SCK)
The serial cl ock (SCK) signal is an outp ut from the ma ster device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
31.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wir e mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 31.2, Figure 31.3, and Figure 31.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects t he pinout of the devic e. Wh en in 3- wire maste r or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “28. Port Input/Output” on page 180 for general purpose
port I/O and crossbar information.
31.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfe r s o n a SPI bus. SPI0 is plac ed in m ast er m od e by se ttin g the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift registe r, and a data transf er begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
C8051F70x/71x
Rev. 1.0 243
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfer s the content s of it s sh if t register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three di ffer ent modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable th e master SPI0 when anothe r master is accessing th e bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being sla ve devices while th ey are not a cting as the system master device . In multi -mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 31.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-m aster mod e is active wh en NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, an d is not mapped to an external por t pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 31.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using gene ral-p urpose I/O pi ns. Figur e 31.4 shows a connection diagra m for a master device i n
4-wire master mode and two slave devices.
Figure 31.2. Multiple-Master Mode Connection Diagram
Figure 31.3. 3-Wire Single Master and Single Slave Mode Connection Diagram
Master
Device 2
Master
Device 1
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
C8051F70x/71x
244 Rev. 1.0
Figure 31.4. 4-Wire Single Master Mode and Slav e Mode Connection Diagram
31.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counte r in the SPI0 logic cou nts SCK edges. When 8 bit s have be en shif ted th rough the shif t reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffe red, and are placed in the transmit bu f fer first. If the shif t re gister is e mpty, the content s of the tra nsmit
buffer will immediately be transferred into the shift register. When the s hift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active wh en NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0 CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is res et on a falling edge of NSS. The NSS signal must
be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 31.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with th e SPIEN bit. Figure 31.3 shows a connection diagram between a slave device in 3-
wire slave mod e and a ma ster device.
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
C8051F70x/71x
Rev. 1.0 245
31.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow an other master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the re ceive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
31.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same cloc k phase and polar ity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 31.5. For slave mode, the clock and
data relatio nship s are shown in Figure 31.6 and Figure 31.7. CKPHA should be set to 0 on both th e master
and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 31.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum dat a transfe r rate (bit s/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not ne ed to r eceive dat a from the slave (i.e., half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the seri al input data synchr onously with the slave’s
system clock.
C8051F70x/71x
246 Rev. 1.0
Figure 31.5. Master Mode Data/Clock Timing
Figure 31.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mo de)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
C8051F70x/71x
Rev. 1.0 247
Figure 31.7. Slave Mode Data/Clock Timing (CKPHA = 1)
31.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wir e Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
C8051F70x/71x
248 Rev. 1.0
SFR Address = 0xA1; SFR Page = 0
SFR Definition 31.1. SPI0CFG: SPI0 Configuration
Bit7654321 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type R R/W R/W R/W R R R R
Reset 0000011 1
Bit Name Function
7 SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6 MSTEN Master Mode Enable.
0: Disable master mo de . Op er at e in slave mode.
1: Enable master mode. Operate as a master.
5 CKPHA SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on secon d edge of SCK period.*
4CKPOLSPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3 SLVSEL Slave Selected Flag.
This bit is set to logic 1 whenever th e NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2 NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMTShift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift re gister from the transmit buf fer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0 RXBMT Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 31.1 for timing parameters.
C8051F70x/71x
Rev. 1.0 249
SFR Address = 0xF8; SFR Page = All Pages; Bit-Addressable
SFR Definition 31.2. SPI0CN: SPI0 Control
Bit7654321 0
Name SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Type R/W R/W R/W R/W R/W R R/W
Reset 0000011 0
Bit Name Function
7 SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6WCOLWrite Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. Whe n
this occurs, the write to SPI0DAT will be ignored, and the transmit buf fer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hard ware, and must be cleared by software.
5MODFMode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4 RXOVRN Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and th e last bi t of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatic ally cleared by ha rd wa re , an d mu st be clear ed by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects be tween the following NSS operation modes:
(See Section 31.2 and Section 31.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is no t routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1 TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buf fer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0 SPIEN SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
C8051F70x/71x
250 Rev. 1.0
SFR Address = 0xA2; SFR Page = F
SFR Address = 0xA3; SFR Page = 0
SFR Definition 31.3. SPI0CKR: SPI0 Clock Rate
Bit7654321 0
Name SCR[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SCR[7:0] SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Definition 31.4. SPI0DAT: SPI0 Data
Bit7654321 0
Name SPI0DAT[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
fSCK SYSCLK
2 SPI0CKR[7:0] 1+()×
-----------------------------------------------------------
=
fSCK 2000000
241+()×
--------------------------
=
fSCK 200kHz=
C8051F70x/71x
Rev. 1.0 251
Figure 31.8. SPI Master Timing (CKPHA = 0)
Figure 31.9. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH
T
MCKL
MOSI
T
MIS
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIH
SCK*
T
MCKH
T
MCKL
MISO
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIS
C8051F70x/71x
252 Rev. 1.0
Figure 31.10. SPI Slave Timing (CKPHA = 0)
Figure 31.11. SPI Slave Timing (CKPHA = 1)
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SEZ
T
SDZ
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SEZ
T
SDZ
C8051F70x/71x
Rev. 1.0 253
Table 31.1. SPI Slave Timing Parameters
Parameter Description Min Max Units
Master Mode Timing (See Figure 31.8 and Figure 31.9)
TMCKH SCK High Time 1 x TSYSCLK —ns
TMCKL SCK Low Time 1 x TSYSCLK —ns
TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 — ns
TMIH SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing (See Figure 31.10 and Figure 31.11)
TSE NSS Falling to First SCK Edge 2 x TSYSCLK —ns
TSD Last SCK Edge to NSS Rising 2 x TSYSCLK —ns
TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns
TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns
TCKH SCK High Time 5 x TSYSCLK —ns
TCKL SCK Low Time 5 x TSYSCLK —ns
TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK —ns
TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK —ns
TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns
TSLH Last SCK Edge to MISO Change
(CKPHA = 1 ONLY) 6xT
SYSCLK 8xT
SYSCLK ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F70x/71x
Rev. 1.0 254
32. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud ra te su pport allows a wide r ange of clock sour ces to gene rate standard baud rates (det ails
in Section “32.1. Enhanced Baud Rate Generation” on page 255). Received data buff ering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always acces s the buf fe red Receive r egister;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardwa re when the CPU vectors to the in terrupt ser vice routine. They must be cleared manu ally
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Figure 32.1. UART0 Block Diagram
UART Baud
Rate Generator
RI
SCON
RI
TI
RB8
TB8
REN
MCE
SMODE
Tx Control
Tx Clock Send
SBUF
(TX Shift )
Start
Data
Write to
SBUF
Crossbar
TX
Shift
Zero Detector
Tx IRQ
SET
QD
CLR
Stop Bit
TB8
SFR Bus
Serial
Port
Interrupt
TI
Port I/O
Rx Contr o l
Start
Rx Clock
Load
SBUF
Shift 0x1FF RB8
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF
Read
SBUF
SFR Bus
Crossbar
RX
SBUF
(RX Latch)
C8051F70x/71x
255 Rev. 1.0
32.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 32.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Figure 32.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “33.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 265). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 32.1-A and
Equation 32.1-B.
Equation 32.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as desc ribed in Section “33. Timers” on page 262. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 32.1 through Table 32.2. The
internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.
RX Timer
Start
Detected
Overflow
Overflow
TH1
TL1
TX Clock
2
RX Cl ock
2
Timer 1 UART
UartBaudRate 1
2
---T1_Overflow_Rate×=
T1_Overflow_Rate T1CLK
256 TH1–
--------------------------
=
A)
B)
C8051F70x/71x
Rev. 1.0 256
32.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 32.3.
Figure 32.3. UART Interconnect Diagram
32.2.1. 8-Bit UART
8-Bit UART mode uses a tot al of 10 bits per dat a byte: one st art bit, e ight dat a bit s (LSB first) , and one sto p
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag ( SCON0.1) is set at th e end of the transm ission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these condition s ar e me t, the eigh t bits of data is stored in SBUF0, the sto p bit is stored in RB8 0 an d the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 32.4. 8-Bit UART Timing Diagram
OR
RS-232 C8051xxxx
RS-232
LEVEL
XLTR
TX
RX
C8051xxxx
RX
TX
MCU RX
TX
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
C8051F70x/71x
257 Rev. 1.0
32.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user so f twa re. It ca n be assigned the value of the p ari ty flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must b e logic 1 (when M CE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 32.5. 9-Bit UART Timing Diagram
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE D8
C8051F70x/71x
Rev. 1.0 258
32.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth dat a bit. When a master p rocessor wa nts to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses ca n be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 32.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F70x/71x
259 Rev. 1.0
SFR Address = 0x98; SFR Page = All Pages; Bit-Addressable
SFR Definition 32.1. SCON0: Serial Port 0 Control
Bit76543210
Name S0MODE MCE0 REN0 TB80 RB80 TI0 RI0
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7S0MODESerial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6 Unused Read = 1b, Write = Don’t Care.
5MCE0Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4REN0Receive Enable.
0: UART0 reception disabled.
1: UART0 reception ena bled.
3TB80Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2RB80Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1TI0Transmit Interrupt Flag.
Set by hardware when a byte of data has been tr ansmitted by UAR T0 (af te r the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 in terrupt is enable d, setting this bit causes the CPU to vector to the UAR T0
interrupt se rvic e ro ut ine . This bit must be cleared manually by software.
0RI0Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
C8051F70x/71x
Rev. 1.0 260
SFR Address = 0x99; SFR Page = All Pages
SFR Definition 32.2. SBUF0: Serial (UART0) Port Data Buffer
Bit76543210
Name SBUF0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register a nd a receive latch reg ister .
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
C8051F70x/71x
261 Rev. 1.0
Table 32.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud
Rate%
Error
Oscillator
Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
Internal Osc.
230400 –0.32% 106 SYSCLK XX21 0xCB
115200 –0.32% 212 SYSCLK XX 1 0x96
57600 0.15% 426 SYSCLK XX 1 0x2B
28800 –0.32% 848 SYSCLK/4 01 0 0x96
14400 0.15% 1704 SYSCLK/12 00 0 0xB9
9600 –0.32% 2544 SYSCLK/12 00 0 0x96
2400 –0.32% 10176 SYSCLK/48 10 0 0x96
1200 0.15% 20448 SYSCLK/48 10 0 0x2B
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 33.1.
2. X = Don’t care.
Table 32.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud
Rate%
Error
Oscillator
Divide
Factor
Timer Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
External Osc.
230400 0.00% 96 SYSCLK XX210xD0
115200 0.00% 192 SYSCLK XX 1 0xA0
57600 0.00% 384 SYSCLK XX 1 0x40
28800 0.00% 768 SYSCLK / 12 00 0 0xE0
14400 0.00% 1536 SYSCLK / 12 00 0 0xC0
9600 0.00% 2304 SYSCLK / 12 00 0 0xA0
2400 0.00% 9216 SYSCLK / 48 10 0 0xA0
1200 0.00% 18432 SYSCLK / 48 10 0 0x40
SYSCLK from
Internal Osc.
230400 0.00% 96 EXTCLK / 8 11 0 0xFA
115200 0.00% 192 EXTCLK / 8 11 0 0xF4
57600 0.00% 384 EXTCLK / 8 11 0 0xE8
28800 0.00% 768 EXTCLK / 8 11 0 0xD0
14400 0.00% 1536 EXTCLK / 8 11 0 0xA0
9600 0.00% 2304 EXTCLK / 8 11 0 0x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 33.1.
2. X = Don’t care.
C8051F70x/71x
Rev. 1.0 262
33. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 3
offers the ability to be clocked from the external oscillator while the device is in Suspend mode, and can be
used as a wake-up source. This allows for implementation of a very low-power system, including RTC
capability.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 33.1 for pre-scaled clock selection) .
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incr emented on each hi gh-to-low tran sition at the sele cted input pin ( T0 or T1). Event s with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Timer 0 and Timer 1 Modes: Timer 2 Modes: Timer 3 Modes:
13-bit counter/timer 16-bit tim er with au to -r elo a d 16-bit timer with au to -r elo a d
16-bit counter/timer
8-bit counter/timer with
auto-reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counter/timers
(Timer 0 only)
C8051F70x/71x
263 Rev. 1.0
SFR Address = 0x8E; SFR Page = All Pages
SFR Definition 33.1. CKCON: Clock Control
Bit76543210
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MHTimer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3MLTimer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MHTimer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2MLTimer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clo ck supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1Timer 1 Clock Select.
Selects the clo ck source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Cl oc k Pres ca ler :
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
C8051F70x/71x
Rev. 1.0 264
33.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 inte rrupts can be en abled b y settin g the ET0 bit in the I E regis-
ter (Section “21.2 . Interrupt Register Descriptions” on page 140); Timer 1 interrupt s ca n b e ena bled by se t-
ting the ET1 bit in the IE register (Section “21.2. Interrupt Register Descriptions” on page 140). Both
counter/timers operate in on e of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
33.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low tr ansitions at the selected Timer 0 input pi n (T0) increment the timer register (Refer to Section
“28.3. Priority Crossbar Decoder” on page 185 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 33.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 21.7). Setting
GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (s ee Se ct ion “2 1. 2. Interrup t
Register Descriptions” on page 140), facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit reg ister for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 21.7).
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
C8051F70x/71x
265 Rev. 1.0
Figure 33.1. T0 Mode 0 Block Diagram
33.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures T imer 0 and T i mer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TC ON.4) e nables th e timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as d efined by bit IN0PL in register IT01CF ( see Section “21.3. INT0 and INT1 Exte rnal
Interrupts” on page 146 for details on the external input signals INT0 and INT1).
TCLK TL0
(5 bits) TH0
(8 bits)
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL XOR
T0M
C8051F70x/71x
Rev. 1.0 266
Figure 33.2. T0 Mode 2 Block Diagram
33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals.
While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run
Timer 1 while Time r 0 is in M ode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, con figure it for
Mode 3.
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 bits)
Reload
TH0
(8 bits)
0
1
0
1
SYSCLK
Pre-s caled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
T0M
C8051F70x/71x
267 Rev. 1.0
Figure 33.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock TR1 TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
T0M
C8051F70x/71x
Rev. 1.0 268
SFR Address = 0x88; SFR Page = All Pages; Bit-Addressable
SFR Definition 33.2. TCON: Timer Control
Bit76543210
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF1 Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5 TF0 Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interr upt 1 service routine in edge-triggered mode.
2IT1Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive.
/INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 21.7).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
1IE0External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by sof twa re but i s automa tically cleared when the CPU vectors to the
External Interr upt 0 service routine in edge-triggered mode.
0IT0Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 21.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
C8051F70x/71x
269 Rev. 1.0
SFR Address = 0x89; SFR Page = All Pages
SFR Definition 33.3. TMOD: Timer Mode
Bit76543210
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled on ly when TR1 = 1 AND INT 1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 21.7).
6C/T1Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3GATE0Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled on ly when TR0 = 1 AND INT 0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 21.7).
2C/T0Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11 : Mo d e 3, Two 8-bit Counter/Timers
C8051F70x/71x
Rev. 1.0 270
SFR Address = 0x8A; SFR Page = All Pages
SFR Address = 0x8B; SFR Page = All Pages
SFR Definition 33.4. TL0: Timer 0 Low Byte
Bit76543210
Name TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 33.5. TL1: Timer 1 Low Byte
Bit76543210
Name TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
C8051F70x/71x
271 Rev. 1.0
SFR Address = 0x8C; SFR Page = All Pages
SFR Address = 0x8D; SFR Page = All Pages
SFR Definition 33.6. TH0: Timer 0 High Byte
Bit76543210
Name TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 33.7. TH1: Timer 1 High Byte
Bit76543210
Name TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
C8051F70x/71x
Rev. 1.0 272
33.2. Timer 2
T imer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L ( low byte) and TMR2H ( high byte). Timer 2 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in capture mode to capture rising edges of the
Comparator 0 output.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the sy stem clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. The external oscillator source divided by 8 is synchronized with the system clock.
33.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 33.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow fro m 0x FF to 0x00.
Figure 33.4. Timer 2 16-Bit Mode Block Diagram
Ex te rn a l Cloc k / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F70x/71x
273 Rev. 1.0
33.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 33.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflo ws. If Timer 2 interrupts are e nabled and TF2LEN (TMR2CN.5) is set, a n in terr upt is g ene r-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by soft ware.
Figure 33.5. Timer 2 8-Bit Mo de Block Diagram
T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR2
External Clock / 8
SYSCLK / 12 0
1
T2XCLK
1
0
TMR2H
TMR2RLH Reload
Reload
TCLK TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F70x/71x
Rev. 1.0 274
33.2.3. Comparator 0 Capture Mode
The capture mode in Timer 2 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 2 capture mode is enabled by setting TF2CEN
to 1 and T2SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2
reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or meas uring the frequency of
a low-level analog signal.
Figure 33.6. Timer 2 Capture Mode Block Diagram
SYSCLK
0
1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2L TMR2H
TCLK
TR2
TMR2RLL TMR2RLH
Capture
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
TF2LEN
TF2CEN Interrupt
SYSCLK / 12
T2XCLK
External Clock / 8
Comparator 0
Output
0
1
C8051F70x/71x
275 Rev. 1.0
SFR Address = 0xC8; SFR Page = All Pages; Bit-Addressable
SFR Definition 33.8. TMR2CN: Timer 2 Control
Bit76543210
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK
Type R/W R/W R/W R/W R/W R/W R R/W
Reset 00000000
Bit Name Function
7 TF2H Timer 2 High Byte Overflow Flag.
Set by hardware whe n the Timer 2 hi gh byt e ove r flow s fro m 0x FF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not au to m at ically cleared by hardware .
6 TF2L Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5 TF2LEN Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4TF2CENTimer 2 Comparator Capture Enable.
When set to 1, this bit enables Timer 2 Comparator Capture Mode. If TF2 CEN is set,
on a rising edge of the Co mparat or 0 ou tp ut the curr en t 16 -b it tim er valu e in
TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL. If Timer 2 interrupts are also
enabled, an interrupt will be generated on this event.
3 T2SPLIT Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
2TR2Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mod e .
1 Unused Read = 0b; Write = Don’t Care.
0T2XCLKTimer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to
select between the external clock and the system clock for eithe r timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F70x/71x
Rev. 1.0 276
SFR Address = 0xCA; SFR Page = 0
SFR Address = 0xCB; SFR Page = 0
SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit76543210
Name TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit76543210
Name TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
C8051F70x/71x
277 Rev. 1.0
SFR Address = 0xCC; SFR Page = 0
SFR Address = 0xCD; SFR Page = 0
SFR Definition 33.11. TMR2L: Timer 2 Low Byte
Bit76543210
Name TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 33.12. TMR2H Timer 2 High Byte
Bit76543210
Name TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TM R 2H re gis te r con tains the hig h by te of the 16- bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
C8051F70x/71x
Rev. 1.0 278
33.3. Timer 3
T imer 3 is a 16-bit timer for med by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte ). Timer 3 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal high-frequency oscillator drives the system clock while Timer 3 is clocked by an external oscillator
source. The external oscillator source divided by 8 is synchronized with the system clock when in all oper-
ating modes except suspend. When the internal oscillator is placed in suspend mode, The external clock/8
signal can directly drive the timer. This allows the use of an external clock to wake up the device from sus-
pend mode. The timer will con tinue to run in suspend mo de an d count up. Wh en the timer ov erflow occurs,
the device will wake from suspend mode, and begin executing code again. The timer value may be set
prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device.
If a wake-up source other than the timer wakes the device from suspend mode, it may take up to three
timer clocks before the timer registers can be read or written. During this time, the STSYNC bit in register
OSCICN will be set to 1, to indicate that it is not safe to read or write the timer registers.
33.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 33.7,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow fro m 0x FF to 0x00.
Figure 33.7. Timer 3 16-Bit Mode Block Diagram
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
TF3CEN
TF3L
TF3H
T3XCLK
TR3
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
External Clock / 8
SYSCLK / 12
T3XCLK
0
1
C8051F70x/71x
279 Rev. 1.0
33.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is s et, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 33.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode. Timer 3 can also be used in capture mode to capture rising
edges of the Comparator 0 output.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 clock select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bits (T3XCLK in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled , an interrupt is gene rated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 33.8. Timer 3 8-Bit Mo de Block Diagram
T3MH T3XCLK TMR3H Clock
Source T3ML T3XCLK TMR3L Clock
Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR3
1
0
TMR3H
TMR3RLH Reload
Reload
TCLK TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK
TR3
To ADC
External Clock / 8
SYSCLK / 12
T3XCLK
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
0
1
C8051F70x/71x
Rev. 1.0 280
33.3.3. Comparator 0 Capture Mode
The capture mode in Timer 3 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 3 capture mode is enabled by setting TF3CEN
to 1 and T3SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3
reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set (triggering an interrupt if Timer 3 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 3 clock. The Timer 3 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or meas uring the frequency of
a low-level analog signal.
Figure 33.9. Timer 3 Capture Mode Block Diagram
SYSCLK
0
1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3L TMR3H
TCLK
TR3
TMR3RLL TMR3RLH
Capture
TMR3CN
T3SPLIT
TF3CEN
TF3L
TF3H
T3XCLK
TR3
TF3LEN
TF3CEN Interrupt
SYSCLK / 12
T3XCLK
External Clock / 8
Comparator 0
Output
0
1
C8051F70x/71x
281 Rev. 1.0
SFR Address = 0x91; SFR Page = 0
SFR Definition 33.13. TMR3CN: Timer 3 Control
Bit76543210
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK
Type R/W R/W R/W R/W R/W R/W R R/W
Reset 00000000
Bit Name Function
7 TF3H Timer 3 High Byte Overflow Flag.
Set by hardware whe n the Timer 3 hi gh byt e ove r flow s fro m 0x FF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Tim er 3
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5 TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CENTimer 3 Comparator Capture Enable.
When set to 1, this bit enables T imer 3 Comp arator Capture Mode. If TF3CEN is set,
on a rising edge of the Co mparat or 0 ou tp ut the curr en t 16 -b it tim er valu e in
TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL. If T imer 3 interrupts are also
enabled, an interrupt will be generated on this event.
3 T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2TR3Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mod e .
1 Unused Read = 0b; Write = Don’t Care.
0T3XCLKTimer 3 External Clock Select.
This bit select s the extern al clock source for Timer 3. If Timer 3 is in 8-bit mode, th is
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to
select between the external clock and the system clock for eithe r timer.
0: System clock divided by 12.
1: External clock divided by 8 (synchronized with SYSCLK when not in suspend).
C8051F70x/71x
Rev. 1.0 282
SFR Address = 0x92; SFR Page = 0
SFR Address = 0x93; SFR Page = 0
SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit76543210
Name TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit76543210
Name TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
C8051F70x/71x
283 Rev. 1.0
SFR Address = 0x94; SFR Page = 0
SFR Address = 0x95; SFR Page = 0
SFR Definition 33.16. TMR3L: Timer 3 Low Byte
Bit76543210
Name TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 33.17. TMR3H Timer 3 High Byte
Bit76543210
Name TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register cont a ins the high byte o f th e 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
C8051F70x/71x
Rev. 1.0 284
34. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, T imer 0 overflows, or
an external clock signal on the ECI input pin. Each capture/compare module may be co nfigured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“34.3. Capture/Compare Modules” on page 286). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 34.1
Figure 34.1. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
C8051F70x/71x
285 Rev. 1.0
34.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register .
Reading the PCA0L Regist er first guaran tees an a ccurate r eading of the entire 16 -bit PCA0 cou nter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 34.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Figure 34.2. PCA Counter/Timer Blo ck Diagram
Table 34.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0 0 0 System clock divided by 12
0 0 1 System clock divided by 4
0 1 0 Timer 0 overflow
0 1 1 High-to-low transitions on ECI (max rate = system clock divided
by 4)
100System clock
1 0 1 External oscillator source divided by 8*
1 1 x Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
E
C
F
C
P
S
1
C
P
S
0
C
P
S
2
IDLE
0
1PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
C8051F70x/71x
Rev. 1.0 286
34.2. PCA0 Interrupt Sources
Figure 34.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, and CCF2), which are set according to the oper ation mode o f that modu le. These
event flags are always set when the trigger condition occurs. Each of these flags can be individually
selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV
for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual
interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by setting th e EA
bit and the EPCA0 bit to logic 1.
Figure 34.3. PCA Interrupt Block Diagram
34.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 34.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA capture/compare module’s operating mode. All modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
E
C
F
C
P
S
1
C
P
S
0
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow 0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 2)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
0
1
Set 8, 9, 10, or 11 bit Opera tion
C8051F70x/71x
287 Rev. 1.0
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number 76543210765 4:2 1:0
Capture triggered by positive edge on CEXn XX10000A0XBXXXXX
Capture triggered by negative edge on CEXn XX01000A0XBXXXXX
Capture triggered by any transition on CEXn XX11000A0XBXXXXX
Software Timer XC00100A0XBXXXXX
High Speed Output XC00110A0XBXXXXX
Frequency Output XC00011A0XBXXXXX
8-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, thi s generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/C ompare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
C8051F70x/71x
Rev. 1.0 288
34.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it in to the corr esponding mo dule 's 16- bit ca pture/co mpare register ( PCA0CPLn an d
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn re gister ar e u sed to sele ct th e type o f tr an si-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compar e Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatica lly cleared by har dware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Figure 34.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
x 000xx
C8051F70x/71x
289 Rev. 1.0
34.3.2. Software Timer (Compare) Mode
In Softwa re Timer mode, the PCA counter/timer value is comp are d to the mod ule' s 16- bit ca pture/ co mpare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatica lly cleared by har dware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared b y sof t ware. Settin g the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 34.5. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C8051F70x/71x
Rev. 1.0 290
34.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically clear ed by hard ware wh en the C PU vectors to the inte rrupt serv ice rout ine, and m ust be cle ared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its st ate, and not toggle on the next
match even t.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 34.6. PCA High-Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C8051F70x/71x
291 Rev. 1.0
34.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then de fined by Equation 34.1.
Equation 34.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the mat ched value in PCA0CP Ln.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. The MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn flag for
the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the chan-
nel are equal.
Figure 34.7. PCA Frequency Output Mode
FCEXn FPCA
2PCA0CPHn×
-----------------------------------------
=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F70x/71x
Rev. 1.0 292
34.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes
Each module can be u sed inde pende ntly to gen erate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configure d for 8/9/10/11-bit PWM mode will us e
the same cycle leng th. It is not possible to configure on e channel for 8- bit PWM mode and anothe r for 11-
bit mode (for exam p le) . Ho wever, othe r PCA chan ne ls ca n b e co nfigu re d to Pi n Captu r e, Hig h -Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
34.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is va ried using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on th e CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 34.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/comp ar e
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (r ising edge) occurs. The COVF flag in PCA0PWM can be used to dete ct the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 34.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 34.2. 8-Bit PWM Duty Cycle
Using Equation 34.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 34.8. PCA 8-Bit PWM Mode Diagram
Duty Cycle 256 PCA0CPHn–()
256
---------------------------------------------------
=
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x000
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
C
O
V
F
C8051F70x/71x
293 Rev. 1.0
34.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be vari ed by writin g to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When th e counter over flo ws fr om
the Nth bit, CEXn is asserted low (see Figure 34.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by th e CLS E L bits in register P CA0 PWM .
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 34.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 34.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Duty Cycle 2NPCA0CPn–()
2N
--------------------------------------------
=
N-bit Comparator
PCA0H:L
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
CEXn Crossbar Port I/O
Enable
Overflow of Nth Bit
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset R/W when
ARSEL = 1
R/W when
ARSEL = 0 Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
C
O
V
F
C8051F70x/71x
Rev. 1.0 294
34.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 34.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 34.4. 16-Bit PWM Duty Cycle
Using Equation 34.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 34.10. PCA 16-Bit PWM Mode
Duty Cycle 65536 PCA0CPn–()
65536
-----------------------------------------------------
=
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Comparator CEXn Crossbar Port I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F70x/71x
295 Rev. 1.0
34.4. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Address = 0xD8; SFR Page = All Pages; Bit-Addressable
SFR Definition 34.1. PCA0CN: PCA Control
Bit76543210
Name CF CR CCF2 CCF1 CCF0
Type R/W R/W R R R R/W R/W R/W
Reset 00000000
Bit Name Function
7CFPCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x00 00.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to th e PCA inte rrupt service r outin e. This b it is not au toma tically cleared
by hardware and must be cleared by software.
6CRPCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:3 Unused Read = 000b; Write = Don’t care
2:0 CCF[2:0] PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
C8051F70x/71x
Rev. 1.0 296
SFR Address = 0xED; SFR Page = F
SFR Definition 34.2. PCA0MD: PCA Mode
Bit76543210
Name CIDL CPS2 CPS1 CPS0 ECF
Type R/W R R R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CIDLPCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6:4 Unused Read = 000b, Write = don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 over flow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110-111: Reserved
0ECFPCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
C8051F70x/71x
297 Rev. 1.0
SFR Address = 0xA1; SFR Page = F
SFR Definition 34.3. PCA0PWM: PCA PWM Configuration
Bit76543210
Name ARSEL ECOV COVF CLSEL[1:0]
Type R/W R/W R/W R R R R/W
Reset 00000000
Bit Name Function
7ARSELAuto-Reload Register Select.
This bit selects whethe r to re ad an d writ e the norm a l PCA ca ptu r e/c om pare re gist er s
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Aut o- Re loa d re gisters have no func tion .
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6ECOVCycle Overflow Interrupt Enable .
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5COVFCycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th , 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was clea red.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Read = 000b; Write = don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channe ls config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
C8051F70x/71x
Rev. 1.0 298
SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC
SFR Pages: PCA0CPM0 = F, PCA0CPM1 = F, PCA0CPM2 = F
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode
Bit76543210
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6ECOMnComparator Function Enable.
This bit enables the compar ator function for PCA module n when set to 1.
5 CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATnMatch Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a m odule's capture/comp are register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGnToggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1PWMnPulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16 -b it mo de is used if PWM1 6n is set to log ic 1. If the TOGn bit is
also set, the module operate s in Frequency Output Mode.
0ECCFnCapture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
C8051F70x/71x
299 Rev. 1.0
SFR Address = 0xF9; SFR Page = 0
SFR Address = 0xFA; SFR Page = 0
SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte
Bit76543210
Name PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte
Bit76543210
Name PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 34.1).
C8051F70x/71x
Rev. 1.0 300
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB,
SFR Pages: PCA0CPL0 = 0, PCA0CPL1 = 0, PCA0CPL2 = 0,
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC,
SFR Pages: PCA0CPH0 = 0, PCA0CPH1 = 0, PCA0CPH2 = 0,
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte
Bit76543210
Name PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this reg i ste r wi l l clea r the module’s ECOMn bit to a 0.
SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte
Bit76543210
Name PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’ s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
C8051F70x/71x
Rev. 1.0 301
35. C2 Interface
C8051F70x/71x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash pro-
gramming and in-system debugging with the production part installed in the end application. The C2 inter-
face operates using o nly two pins: a bi- directional da t a signal (C2D) , and a clock input ( C2CK). See the C2
Interface Specification for details on the C2 protocol.
35.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming functions through the
C2 interface. All C2 reg isters are accessed through the C2 interface as de scribed in the C2 Interfa ce Spec-
ification.
C2 Register Definition 35.1. C2ADD: C2 Address
Bit76543210
Name C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the tar get Data register
for C2 Data Read and Data Write commands.
Address Name Description
0x00 DEVICEID Selects the Device ID Register (read only)
0x01 REVID Selects the Revision ID Register (read only)
0x02 FPCTL Selects the C2 Flash Programming Control Register
0xBF FPDAT Selects the C2 Flash Data Registe r
0x96 CRC0AUTO* Selects the CRC0AUTO Register
0x97 CRC0CNT* Selects the CRC0CNT Register
0x91 CRC0CN* Selects the CRC0CN Register
0xD9 CRC0DATA* Selects the CRC0DATA Register
0x95 CRC0FLIP* Selects the CRC0FLIP Register
0x94 CRC0IN* Selects the CRC0IN Register
Note: CRC registers and functions are described in Section “29. Cyclic Redundancy Check Unit (CRC0)” on
page 211.
C8051F70x/71x
302 Rev. 1.0
C2 Address: 0x00
C2 Address: 0x01
C2 Register Definition 35.2. DEVICEID: C2 Device ID
Bit76543210
Name DEVICEID[7:0]
Type R/W
Reset 00011110
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x1E (C8051F70x/71x).
C2 Register Definition 35.3. REVID: C2 Revision ID
Bit76543210
Name REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
C8051F70x/71x
Rev. 1.0 303
C2 Address: 0x02
C2 Address: 0xBF
C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control
Bit76543210
Name FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] C2 Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the followin g codes must be written in order: 0x02, 0x01. Once
C2 Flash programming is enabled, a system reset must be issued to resume normal
operation.
C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data
Bit76543210
Name FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses . Valid comm a nd s ar e lis te d be low.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
C8051F70x/71x
304 Rev. 1.0
35.2. C2CK Pin Sharing
The C2CK pin is shared with the RST signal on this device family. If the RST pin is used by other parts of
the system, debugging and programming the device can still be accomplished without disrupting the rest of
the system. If this is desired, it is normally necessary to add a resistor to isolate the system’s reset line
from the C2CK signal. This external resistors would not be necessary for production boar ds, where deb ug-
ging capabilities are not needed. A typical isolation configuration is shown in Figure 35.1.
Figure 35.1. Typical C2CK Pin Sharing
The configuration in Figure 35.1 assumes the RST pin on the target device is used as an input only. Addi-
tional resistors may be necessary depending on the specific application.
C2D
C2CK
RST
C2 Interfac e Master
C8051F70x/71x
Rev. 1.0 305
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
Updated “Electrical Characteristics” on page 47.
Updated “Port Input/Output” on page 180.
Revision 0.4 to Revision 0.5
Removed Incorrect Pin Connections in Figure 1.4 on page 21 and Figure 1.6 on page 23.
Updated Specifications in Section “9. Electrical Characteristics” on page 47.
Updated Section “15. Capacitive Sense (CS0)” on page 80 for clarity.
Corrected “CJNE A, direct, rel” instruction timing in Table 16.1.
Noted that a minimum SYSCLK speed is required for Flash writes or erases in Section
“22.1. Programming The Flash Memory” on page 148, and for EEPROM writes in Section
“23.3. Interfacing with the EEPROM” on page 155.
Corrected P0.3 overvoltage capabilities throughout document.
Revision 0.3 to Revision 0.4
Updated Section “1 5. Capacitive Sense (CS0)” on page 80 to reflect Revision B enhancements.
Added C8051F716 and C8051F717 devices, package information, and features.
Updated Register 19.1, “HWID: Hardware Identification Byte,” on page 128.
Corrected minor typogr aphical and formatting errors throughout document.
Revision 0.2 to Revision 0.3
Corrected Dimension D in the QFN-48 Package Specifications.
Updated Table 9.1 on page 47.
Updated Register 10.1, “ADC0CF: ADC0 Configuration,” on page 59.
Updated Register 14.3, “CPT0MX: Comparator0 MUX Selection,” on page 79.
Updated Section “2 8. 1.1. Port Pins Configured for Analo g I/O ” on page 181.
Updated Registe r 35.2, “DEVICE ID: C2 Device ID,” on page 302.
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