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54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter
Check for Samples: 54AC169,54ACT169
1FEATURES DESCRIPTION
The 'AC/'ACT169 is fully synchronous 4-stage
2• ICC Reduced by 50% up/down counter. The 'AC/'ACT169 is a modulo-16
• Synchronous Counting and Loading binary counter. It features a preset capability for
• Built-In Lookahead Carry Capability programmable operation, carry lookahead for easy
cascading and a U/D input to control the direction of
• Presettable for Programmable Operation counting. All state changes, whether in counting or
• Outputs Source/Sink 24 mA parallel loading, are initiated by the LOW-to-HIGH
• 'ACT has TTL-Compatible Inputs transition of the Clock. ®
• Standard Microcircuit Drawing (SMD)
– 5962-91603
Logic Symbols Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
P0–P3Parallel Data Inputs
PE Parallel Enable Input
U/D Up-Down Count Control Input
Q0–Q3Flip-Flop Outputs
TC Terminal Count Output
Figure 1. IEEE/IEC
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2is a registered trademark of ~Fairchild Semiconductor.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagrams
Figure 2. Pin Assignment for CDIP and CLGA Figure 3. Pin Assignment for LCCC
See Package Numbers NFE and NAD See Package Number NAJ
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
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FUNCTIONAL DESCRIPTION
The 'AC/'ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data
input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state
at least a setup time before the rising edge of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode
Select Table. When PE is LOW, the data on the P0–P3inputs enters the flip-flops on the next rising edge of the
Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input
then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW,
provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count
Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state
occurs, the 'AC169 will return to the legitimate sequence within two counts. Since the TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC
as a clock signal is not recommended (see logic equations below).
1. Count Enable = CEP •CET • PE
2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET
3. Down: TC = Q0• Q1•Q2•Q3•(Down)•CET
Table 1. Mode Select Table(1)
Action on Rising
PE CEP CET U/D Clock Edge
L X X X Load (Pnto Qn)
H L L H Count Up (Increment)
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
(1) H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagrams
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Diode Current (IIK) VI=−0.5V −20 mA
VI= VCC + 0.5V +20 mA
DC Input Voltage (VI)−0.5V to VCC + 0.5V
DC Output Diode Current (IOK) VO=−0.5V −20 mA
VO= VCC + 0.5V +20 mA
DC Output Voltage (VO)−0.5V to VCC + 0.5V
DC Output Source or Sink Current (IO) ±50 mA
DC VCC or Ground Current per Output Pin (ICC or IGND) ±50 mA
Storage Temperature (TSTG)−65°C to +150°C
Junction Temperature (TJ) CDIP 175°C
(1) Absolute Maximum Ratings are those values beyond which damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading
variables. Texas Instruments does not recommend operation of FACT circuits outside databook specifications.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC) 'AC 2.0V to 6.0V
'ACT 4.5V to 5.5V
Input Voltage (VI) 0V to VCC
Output Voltage (VO) 0V to VCC
Operating Temperature (TA) 54AC/ACT −55°C to +125°C
Minimum Input Edge Rate (ΔV/Δt) 'AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (ΔV/Δt) 'ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V 125 mV/ns
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DC CHARACTERISTICS FOR 'AC FAMILY DEVICES 54AC
Symbol Parameter VCC TA= Units Conditions
(V) −55°C to +125°C
Specifiied Limits
VIH Minimum High Level 3.0 2.1 VOUT = 0.1V
Input Voltage 4.5 3.15 V or VCC −0.1V
5.5 3.85
VIL Maximum Low Level 3.0 0.9 VOUT = 0.1V
Input Voltage 4.5 1.35 V or VCC −0.1V
5.5 1.65
VOH Minimum High Level 3.0 2.9 IOUT =−50 μA
Output Voltage 4.5 4.4 V
5.5 5.4 See(1)
VIN = VIL or VIH
3.0 2.4 IOH =−12 mA
4.5 3.7 V IOH =−24 mA
5.5 4.7 IOH =−24 mA
VOL Maximum Low Level 3.0 0.1 IOUT = 50 μA
Output Voltage 4.5 0.1 V
5.5 0.1 See(1)
VIN = VIL or VIH
3.0 0.50 IOL = 12 mA
4.5 0.50 V IOL = 24 mA
5.5 0.50 IOL = 24 mA
IIN Maximum Input 5.5 ±1.0 μA VI= VCC, GND
Leakage Current
IOLD Minimum Dynamic 5.5 50 mA VOLD = 1.65V Max
Output Current(2)
IOHD 5.5 −50 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 80.0 μA VIN = VCC
Supply Current or GND
(1) All outputs loaded; thresholds on input associated with output under test.
(2) Maximum test duration 2.0 ms, one output loaded at a time.
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DC CHARACTERISTICS FOR 'ACT FAMILY DEVICES 54ACT
Symbol Parameter VCC TA= Units Conditions
(V) −55°C to +125°C
Specified Limits
VIH Minimum High Level 4.5 2.0 V VOUT = 0.1V
Input Voltage 5.5 2.0 or VCC −0.1V
VIL Maximum Low Level 4.5 0.8 V VOUT = 0.1V
Input Voltage 5.5 0.8 or VCC −0.1V
VOH Minimum High Level 4.5 4.4 V IOUT =−50 μA
Output Voltage 5.5 5.4 See(1)
VIN = VIL or VIH
4.5 3.70 V IOH =−24 mA
5.5 4.70 IOH =−24 mA
VOL Maximum Low Level 4.5 0.1 V IOUT = 50 μA
Output Voltage 5.5 0.1 See(1)
VIN = VIL or VIH
4.5 0.50 V IOL = 24 mA
5.5 0.50 IOL = 24 mA
IIN Maximum Input 5.5 ±1.0 μA VI= VCC, GND
Leakage Current
ICCT Maximum 5.5 1.6 mA VI= VCC −2.1V
ICC/Input
IOLD Minimum Dynamic 5.5 50 mA VOLD = 1.65V Max
Output Current(2)
IOHD 5.5 −50 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 80.0 μA VIN = VCC
Supply Current or GND
(1) All outputs loaded; thresholds on input associated with output under test.
(2) Maximum test duration 2.0 ms, one output loaded at a time.
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AC ELECTRICAL CHARACTERISTICS 54AC
VCC TA=−55°C Fig.
Units
Symbol Parameter (V)(1) to +125°C No.
CL= 50 pF
Min Max
fmax Maximum Clock 3.3 55 MHz
Frequency 5.0 75
tPLH Propagation Delay 3.3 1.0 15.0
CP to Qn5.0 1.5 12.0 ns
(PE HIGH or LOW)
tPHL Propagation Delay 3.3 1.0 16.5
CP to Qn5.0 1.5 13.0 ns
(PE HIGH or LOW)
tPLH Propagation Delay 3.3 3.0 22.0 ns
CP to TC 5.0 3.0 16.0
tPHL Propagation Delay 3.3 3.0 22.0 ns
CP to TC 5.0 3.0 16.0
tPLH Propagation Delay 3.3 1.0 18.5 ns
CET to TC 5.0 1.5 13.0
tPHL Propagation Delay 3.3 1.0 16.0 ns
CET to TC 5.0 1.5 11.0
tPLH Propagation Delay 3.3 1.0 18.5 ns
U/D to TC 5.0 1.5 13.0
tPHL Propagation Delay 3.3 1.0 16.5 ns
U/D to TC 5.0 1.5 12.0
(1) Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V.
AC OPERATING REQUIREMENTS 54AC
VCC TA=−55°C
Symbol Parameter (V)(1) to +125°C Units Fig.
CL= 50 pF No.
Specified Minimum
tsSetup Time, 3.3 7.0
HIGH or LOW 5.0 4.5 ns
Pnto CP
thHold Time, HIGH or LOW 3.3 2.0 ns
Pnto CP 5.0 2.5
tsSetup Time, 3.3 13.5
HIGH or LOW 5.0 9.0 ns
CEP to CP
thHold Time, HIGH or LOW 3.3 0.5 ns
CEP to CP 5.0 2.5
tsSetup Time, 3.3 13.5
HIGH or LOW 5.0 9.0 ns
CET to CP
(1) Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V.
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AC OPERATING REQUIREMENTS (continued) 54AC
VCC TA=−55°C
Symbol Parameter (V)(1) to +125°C Units Fig.
CL= 50 pF No.
Specified Minimum
thHold Time, HIGH or LOW 3.3 0.5 ns
CET to CP 5.0 2.5
tsSetup Time, 3.3 8.5
HIGH or LOW 5.0 6.5 ns
PE to CP
thHold Time, HIGH or LOW 3.3 0.5 ns
PE to CP 5.0 2.0
tsSetup Time, 3.3 13.0
HIGH or LOW 5.0 9.0 ns
U/D to CP
thHold Time, HIGH or LOW 3.3 0.5 ns
U/D to CP 5.0 2.0
twCP Pulse Width, 3.3 5.0 ns
HIGH or LOW 5.0 5.0
AC ELECTRICAL CHARACTERISTICS 54ACT
VCC TA=−55°C Fig.
Symbol Parameter (V)(1) to +125°C Units No.
CL= 50 pF
Min Max
fmax Maximum Clock 5.0 75 MHz
Frequency
tPLH Propagation Delay
CP to Qn5.0 1.5 12.5 ns
(PE HIGH or LOW)
tPHL Propagation Delay
CP to Qn5.0 1.5 12.5 ns
(PE HIGH or LOW)
tPLH Propagation Delay 5.0 1.5 16.5 ns
CP to TC
tPHL Propagation Delay 5.0 1.5 16.5 ns
CP to TC
tPLH Propagation Delay 5.0 1.5 13.5 ns
CET to TC
tPHL Propagation Delay 5.0 1.5 13.5 ns
CET to TC
tPLH Propagation Delay 5.0 1.5 14.5 ns
U/D to TC
tPHL Propagation Delay 5.0 1.5 14.5 ns
U/D to TC
(1) Voltage Range 5.0 is 5.0V ±0.5V.
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AC OPERATING REQUIREMENTS 54ACT
VCC TA=−55°C Fig.
Symbol Parameter (V)(1) to +125°C Units No.
CL= 50 pF
Specified Minimum
tsSetup Time,
HIGH or LOW 5.0 4.5 ns
Pnto CP
thHold Time, HIGH or LOW 5.0 2.5 ns
Pnto CP
tsSetup Time,
HIGH or LOW 5.0 9.0 ns
CEP to CP
thHold Time, HIGH or LOW 5.0 2.5 ns
CEP to CP
tsSetup Time,
HIGH or LOW 5.0 9.0 ns
CET to CP
thHold Time, HIGH or LOW 5.0 2.5 ns
CET to CP
tsSetup Time,
HIGH or LOW 5.0 6.5 ns
PE to CP
thHold Time, HIGH or LOW 5.0 2.0 ns
PE to CP
tsSetup Time,
HIGH or LOW 5.0 9.0 ns
U/D to CP
thHold Time, HIGH or LOW 5.0 2.0 ns
U/D to CP
twCP Pulse Width, 5.0 5.0 ns
HIGH or LOW
(1) Voltage Range 5.0 is 5.0V ±0.5V.
CAPACITANCE
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC = Open
CPD Power Dissipation Capacitance 60.0 pF VCC = 5.0V
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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