DP83220V - National Semiconductor

TL/F/11724

DP83220 CDL Twisted Pair FDDI Transceiver Device

ADVANCE INFORMATION

October 1992

DP83220

CDLTM Twisted Pair FDDI Transceiver Device

General Description

The Copper Data Link (CDL) Transceiver is an integrated

circuit designed to interface directly with the National Semi-

conductor FDDI Chip Set or other FDDI PHY silicon, allow-

ing low cost FDDI compatible data links over copper based

media. The DP83220 Transceiver, with the proper compen-

sation selected, will allow links of up to 100 meters over

both Shielded Twisted Pair (STP) and Datagrade unshielded

Twisted Pair (DTP). CDL surpasses a Bit Error Rate (BER)

of k1c10b12 over both STP and DTP. The CDL is de-

signed to meet the SDDI specification for FDDI transmission

across Type 1 STP cable when used in conjunction with the

appropriate transformer/filter module from Pulse Engineer-

ing.

Features

YFully compatible with current FDDI PHY standard

YFully compatible with the SDDI PMD specification

YRequires a single a5V supply

YIsolated TX and RX power supplies for minimum noise

coupling

YAllows use of Type 1 STP and Category 5 DTP cables

YNo Transmit Clock required

YLoopback feature for board diagnostics

YLink Detect input provided

Block Diagram

Transmit Section

TL/F/11724–1

Receive Section

TL/F/11724–2

FIGURE 1. DP83220 Transceiver Block Diagram

CDLTM, CDDTM, CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

1.0 Functional Description

The CDL Transceiver consists of nine major functional

blocks as shown in

Figure 1.

The Transmit section includes

the following: the Delay Line, the Delay Line Calibrator, the

Media Format Logic, and the Current Output Driver circuitry

with its bias circuitry. The Delay Line accepts the NRZI en-

coded data from the PMRDgpins and provides a short

‘‘memory’’ of the bit that preceded the bit currently being

transmitted. The Delay Line Calibrator allows the use of an

external resistor which governs the time calibration of the

delay line. The Delay Line outputs the data via taps which

are tied to the Media Format Logic. The encoding logic is

dependent on the state of the Media Select pin. The encod-

ed data is routed to the Current Output Driver, through the

TXOgoutput pins and transformer coupled to the media.

The Receive section consists of the following: a differential

input amplifier, Signal Detect circuitry, a Loopback Multi-

plexer, and differential 100K output drivers for data and Sig-

nal Detect. The Receive signal is input to the RXIgpins

from the receive isolation transformer. The input signal is

sensed by the Signal Detect circuit. The input signal also

drives a differential input amplifier whose output is coupled

to the Loopback Mux logic. The ‘sel’ input which is driven by

LBEN controls which data stream, RXIgor Loopback data,

is routed to the differential 100K Output Driver. When in

Loopback mode, the Signal Detect output driver is forced

true. When receiving data from copper media, the signal

detect circuit provides valid states to the Signal Detect out-

put driver depending on the amplitude of the incoming sig-

nal and also allows the PMIDgoutputs to switch. Cable

Detect is the final gating function for data reception. If no

media is detected, the transceiver will generate a logic low

Signal Detect which will inhibit data reception by the PHY.

1.1 SDDI OPERATION

The CDL allows full compatibility with the current SDDI

specification. By allowing the MSEL pin to float, which

forces the pin to VCC/2 internally, the SDDI mode of opera-

tion is selected. The appropriate transmit voltage amplitude

must also be set by selecting a value of 2.6 kXfor the

TXREF resistor.

Finally, it is important to note that the CDL must be used in

conjunction with the Pulse Engineering 8.3 magnetics mod-

ule in order to conform to the current SDDI specification. No

special terminations are required in connecting the Pulse

Engineering 8.3 module to the CDL. (Refer to the typical

SDDI schematic,

Figure 9.

)

2.0 Pinout Summary

Signal Pin No. Description Type

VCC 13, 26 VCC Supply

GND 14, 22 GND Supply

RXVCC 4, 27 Receive VCC Supply

RXGND 3, 28 Receive GND Supply

TXVCC 5, 11 Transmit VCC Supply

TXGND 7, 10 Transmit GND Supply

EXTVCC 23 External VCC Supply

RXIg2, 1 Receive Data Inputs Current In

PMIDg25, 24 Physical Media Indicate Data ECL Out

PMRDg15, 16 Physical Media Request Data ECL In

TXOg9, 8 Transmit Data Outputs Current Out

SDg20, 21 Signal Detect Outputs ECL Out

TXREF 6 Transmit Amplitude Reference Current Out

DELREF 12 Delay Line Calibration Reference Current Out

LBEN 19 Loopback Enable CMOS In

MSEL 17 Media Select 3-Level Select

CDET 18 Cable Detect Bar CMOS Schmitt Trigger In

3.0 Pin Definitions

VCC (13,26): Positive power supply for the 100K ECL com-

patible circuitry. The Transceiver operates from a single

a5V

DC power supply.

GND (14,22): Return path for the 100K ECL compatible cir-

cuitry power supply.

RXVCC (4,27): Positive power supply for the small signal

receive circuitry. This power supply is intentionally separat-

ed from others to eliminate receive errors due to coupled

supply noise.

RXGND (3,28): Return path for the receive power supply

circuitry. This Power supply return is intentionally separated

from others to eliminate receive errors due to coupled sup-

ply noise.

TXVCC (5,11): Positive power supply required by the analog

portion of the transmit circuitry. This power supply is inten-

tionally separated from the others to prevent supply noise

from coupling to the transmit outputs.

TXGND (7,10): Return path for the analog transmit power

supply circuitry. This supply return is intentionally separated

from others to prevent supply noise from being coupled to

the transmit outputs.

EXTVCC (23): Positive power supply for receiver output cir-

cuitry.

RXIg(2,1): Balanced differential line receiver inputs. Sig-

nals meeting the input threshold for a given media type are

output through PMIDgas differential ECL.

PMIDg(25,24): 100K ECL compatible differential outputs

used as the source of the receive data for the DP83231

Clock Recover Device (CRDTM ).

PMRDg(15,16): Differential 100K compatible 4B5B NRZI

transmit data inputs originating from the DP83251/55 Physi-

cal Layer Device (PLAYERTM ).

TXOg(9,8): Differential current driver outputs precompen-

sated for twisted pair cable.

SDg(20,21): Differential 100K ECL compatible Signal De-

tect outputs indicating that a valid signal is present at the

RXIginputs.

DELREF (12): A resistor is connected between this pin and

GND. The value of this resistor controls the current into the

delay line calibrator which, in turn controls the delay time of

the delay line.

TXREF (6): A resistor is connected between this pin and

TXGND. The value of this resistor controls the signal ampli-

tude of the TXOgdata which drives the twisted pair.

LBEN (19): TTL compatible CMOS Loopback Enable input

pin selects the internal loopback path which effectively

routes the PMRDgdata to the PMIDgdifferential outputs.

MSEL (17): The Media Select input controls the compensa-

tion and output current required to drive to 100 meters of

either STP or DTP media. This is a tri-Ievel control pin.

When forced to a low voltage, STP compensation is select-

ed. Forcing a high voltage level will select the DTP compen-

sation mode. Forcing a median voltage allows the device to

operate in the transparent mode by deasserting pre-empha-

sis.

CDET (18): The Cable Detect input is provided to support

the option of external Cable Detection circuitry. With CDET

low, the CDL transceiver functions normally. When CDET is

high, the signal detect output is forced low which inhibits

data reception by the PHY. The exception is in the case of

Loop Back, where Signal Detect is forced high regardless.

28-Pin PLCC

TL/F/11724–3

Order Number DP83220V

See NS Package Number V28A

FIGURE 2. Pin Configuration TL/F/11724–4

FIGURE 3. System Connection Diagram

4.0 Electrical Characteristics

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Conditions Min Typ Max Units

VCC Logic Power Referenced to GND b0.5 6.0 V

RXVCC Received Power Referenced to RXGND b0.5 6.0 V

TXVCC Transmit Power Referenced to TXGND b0.5 6.0 V

EXTVCC ECL Output Power Referenced to GND b0.5 6.0 V

IECL DC Output Current (High) b50 mA

ESD TBD

Tstorage Storage Temperature b65 a150 §C

4.1 RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Conditions Min Typ Max Units

VCC Supply Voltage 4.5 5.0 5.5 V

TAOperating Temperature 0 25 70 §C

PDPower Dissipation 600 mW

4.2 DC ELECTRICAL CHARACTERISTICS TAe25§C

Symbol Parameter Conditions Min Typ Max Units

VIHt TTL High Level Input 2.0 V

VILt TTL Low Level Input 0.8 V

VIHschmitt Schmitt High Level Input 3.7 V

VILschmitt Schmitt Low Level Input 1.5 V

VIHmsel MSEL High Level Input 3.7 V

VILmsel MSEL Low Level Input 1.5 V

VIMmsel MSEL Middle Level Input VCC/2 V

VIHe ECL High Level Input VCC b1165 VCC b870 mV

VILe ECL Low Level Input VCC b1830 VCC b1475 mV

VOHe ECL High Level Output Refer to

Figure 4

VCC b1035 VCC b870 mV

VOLe ECL Low Level Output Refer to

Figure 4

VCC b1830 VCC b1605 mV

ICC1 Refer to

Figure 4

90 mA

ICCT Total Supply Current Refer to

Figure 4

145 mA

ITXO1 Transmit Current 1 Transmit Current / 100XZO20 mA

ITXO2 Transmit Current 2 Transmit Current / 150XZO15 mA

SDTHon Sig Det Turn-On Threshold Refer to

Figure 5,

Note 1 60 mV

SDTHoff Sig Det Turn-Off Threshold Refer to

Figure 5,

Note 1 15 mV

4.3 AC ELECTRICAL CHARACTERISTICS TAe25§C

Symbol Parameter Conditions Min Typ Max Units

tTXr/f TX Driver Rise and Fall Into 25Xin Parallel with 50 pF 1.6 ns

tTXr/f TX Driver Rise and Fall Into 37.5Xin Parallel with 50 pF 2.5 ns

tTXpd TX Propagation Delay From PMRDgto TXOg6ns

RXpd RX Propagation Delay From RXIgto PMIDg10 ns

TTXskew TX Driver Skew 0 ps

Note 1: Subject to change.

4.0 Electrical Characteristics (Continued)

TL/F/11724–5

FIGURE 4. ICC Diagram

TL/F/11724–6

FIGURE 5. Signal Detect Threshold

4.0 Electrical Characteristics (Continued)

TL/F/11724–7

FIGURE 6. Transmit Timing

TL/F/11724–8

FIGURE 7. Receive Timing

4.0 Electrical Characteristics (Continued)

4.3 TRANSMIT DATA AND CURRENT DRIVER OUTPUT

TXDn TXDnb1I

TXOaITXOb

00(I

max (I2)I

max

01(I

max 0

10 0(I

max

11(I

max (I1)I

max

TL/F/11724–9

FIGURE 8. Typical Pre-Emphasized Current Waveform, ITXOa

TABLE I. Media Select

Mode MSEL

STP k1.5V

DTP l3.7V

SDDI Float

TABLE II. Data Paths and Signal Detect

LBEN CDET Data @PMIDgSDa

0 1 RXIg0

0 0 RXIg1

1 1 PMRDg1

1 0 PMRDg1

Note: This table assumes that minimum signal’s levels required by Signal

Detect have been met.

4.0 Electrical Characteristics (Continued)

TL/F/11724–10

Refer to the Pulse Engineering datasheet for detailed information on the 8.3 SDDI magnetics module.

FIGURE 9. Typical Schematic for SDDI Application

DP83220 CDL Twisted Pair FDDI Transceiver Device

Physical Dimensions inches (millimeters)

28-Pin Plastic Leaded Chip Carrier (V)

Order Number DP83220V

NS Package Number V28A

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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