January 1993
7-433
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4073BMS, CD4081BMS
CD4082BMS
CMOS AND Gate
Pinout
CD4073BMS
TOP VIEW
CD4081BMS
TOP VIEW
CD4082BMS
TOP VIEW
A
B
D
E
F
K = D • E • F
VSS
VDD
G
H
I
L = G • H • I
J = A • B • C
C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
J = A • B
K = C • D
C
D
VSS
VDD
H
G
M = G •H
L = E • F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
J = A • B • C • D
D
C
B
A
NC
VSS
VDD
K = E • F • G • H
H
G
F
E
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
Features
• High-Voltage Types (20V Rating)
• CD4073BMS Triple 3-Input AND Gate
• CD4081BMS Quad 2-Input AND Gate
• CD4082BMS Dual 4-Input AND Gate
• Medium Speed Operation:
- tPLH, tPHL = 60ns (typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4073BMS, CD4081BMS and CD4082BMS AND gates
provide the system designer with direct implementation of
the AND function and supplement the existing family of
CMOS gates.
The CD4073BMS, CD4081BMS and CD4082BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP *H4Q †H4H
Frit Seal DIP *H1B
Ceramic Flatpack *H3W
*CD4073B, CD4081B †CD4082B
File Number 3324
7-434
CD4073BMS, CD4081BMS, CD4082BMS
Functional Diagram
CD4073BMS
CD4081BMS
CD4082BMS
10 L
VSS
VDD
14
7
I
H
G
11
12
13
9J
A
B
C
1
2
8
6K
D
E
F
3
4
5
A
B
C
D
E
F
G
H
1
2
5
6
8
9
12
13
3
4
10
11
J
K
L
M
VSS
VDD
14
7
1
13
J
K
VSS
VDD
14
7
D
C
B
A
E
F
G
H
2
3
4
5
9
10
11
12
7-435
Specifications CD4073BMS, CD4081BMS, CD4082BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-.5µA
2 +125oC-50µA
VDD = 18V, VIN = VDD or GND 3 -55oC-.5µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-436
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay TPHL
TPLH VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns
10, 11 +125oC, -55oC - 338 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - .25 µA
+125oC - 7.5 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- .5 µA
+125oC-15µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- .5 µA
+125oC-30µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC7-V
Propagation Delay TPHL
TPLH VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 90 ns
7-437
Specifications CD4073BMS, CD4081BMS, CD4082BMS
Transition Time TTHL
TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 2.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - SSI IDD ±0.1µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-438
Specifications CD4073BMS, CD4081BMS, CD4082BMS
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
PART NUMBER CD4073BMS
Static Burn-In 1
Note 1 6, 9, 10 1 - 5, 7, 8, 11 - 13 14
Static Burn-In 2
Note 1 6, 9, 10 7 1 - 5, 8, 11 - 14
Dynamic Burn-
In Note 1 - 7 14 6, 9, 10 1, 5, 8, 11 - 13
Irradiation
Note 2 6, 9, 10 7 1 - 5, 8, 11 - 14
PART NUMBER CD4081BMS
Static Burn-In 1
Note 1 3, 4, 10, 11 1, 2, 5 - 9, 12, 13 14
Static Burn-In 2
Note 1 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,
12 - 14
Dynamic Burn-
In Note 1 - 7 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12,
13
Irradiation
Note 2 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,
12 - 14
PART NUMBER CD4082BMS
Static Burn-In 1
Note 1 1, 6, 8, 13 2 - 5, 7, 9 - 12 14
Static Burn-In 2
Note 1 1, 6, 8, 13 7 2 - 5, 9 - 12, 14
Dynamic Burn-
In Note 1 6, 8 7 14 1, 3 2 - 5, 9 - 12
Irradiation
Note 2 1, 6, 8, 13 7 2 - 5, 9 - 12, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
7-439
CD4073BMS, CD4081BMS, CD4082BMS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
FIGURE 2. LOGIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
FIGURE 3. SCHEMATIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
FIGURE 4. LOGIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
n
p
*
2 (3, 13)
nn
*
1 (4, 12)
*
8 (5, 11)
p
n
p
n
p
n
p
9 (6, 10)
p
n
VSS
VDD
p
p
n
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
VSS
J
9 (6, 10)
2 (3, 13)
1 (4, 12) A
B
8 (5, 11) C
n
p
ALL INPUTS PROTECTED BY
*CMOS PROTECTION NETWORK
*
2 (5, 9, 12)
p
n
3 (4, 10, 11)
VDD
VSS
n
p
nn
p
n
p
VDD
VSS
*
1 (6, 8, 13)
p
J
3 (4, 10, 11)
2 (5, 9, 12)
1 (6, 8, 13) A
B
7-440
CD4073BMS, CD4081BMS, CD4082BMS
FIGURE 5. SCHEMATIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
FIGURE 6. LOGIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
Typical Performance Characteristics
FIGURE 7. TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
n
p
ALL INPUTS PROTECTED BY
*
CMOS PROTECTION NETWORK
*
3 (11)
p
VDD
n
p
*
2 (12)
n
p
nn
p
n
p
p
VDD
VSS
n
p
*
4 (10)
p
VSS
n
p
*
5 (9)
n
p
n
VSS n
VDD
VSS
J
1 (13)
3 (11)
2 (12) D
C
5 (9)
4 (10) B
A
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
5
OUTPUT VOLT AGE (VO) (V)
SUPPLY VOLTAGE (VDD) = 15V
0 5 10 15 20 25
10
15
20
INPUT VOLTAGE (VIN) (V)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
50
PROPAGA TION DELAY TIME (TPHL, THLH) (ns)
SUPPLY VOLTAGE (VDD) = 15V
10
LOAD CAPACITANCE (CL) (pF)
25
75
100
125
150
175
200
0 2030 4050 6070 8090 100
7-441
CD4073BMS, CD4081BMS, CD4082BMS
FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONPER
GATE AS A FUNCTION OF FREQUENCY
Typical Performance Characteristics (Continued)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOLT AGE (VDD) = 5V
10V
5V
TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
10V
5V 10V
CL = 15pF
CL = 50pF
864286422
INPUT FREQUENCY (fI) (kHz)
11010
2103104
864 2864
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
104
103
102
10
105
POWER DISSIPATION PER GATE (PD) (µW)
442
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CD4073BMS, CD4081BMS, CD4082BMS
Chip Dimensions and Pad Layouts
CD4081BMS CD4082BMS
CD4073BMS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches