DEVICE SPECIFICATION LOGIC ARRAYS AMCG Q20000 TURBO ECL/TTL Q20000 FEATURES * Up to 18,777 gates, channelless architecture * 100 ps equivalent gate delays * Low power (0.5-1.0 mW/gate) * 10K, 10KH, 100K ECL and mixed ECL/TTL capability Structured arrays with 1.25 GHz PLLs! High precision programmable delay line macros Speed/power programmability Single cell 25 and 50 ohm parallel termination drive * Symmetrical rise and fall times Operation over commercial, industrial and military environmental conditions * Up to 100% utilization DESCRIPTION The AMCC Q20000 Series of logic arrays is com- prised of nine products ranging in density from 450 to 18,777 equivalent gates including structured arrays with 1.25 GHz PLLs.! The Q20000 TURBO ECL/ TTL series is optimized to provide high perfor- mance and proven reliability to todays advanced hi-rel commercial, industrial and military semicustom applications. Q20000 arrays are designed to operate at frequen- cies as high as 1.25 GHz. These Turbo arrays achieve this very high performance by combining an advanced process with innovative AC-coupled active drive circuitry. The combination of this advanced pro- cess and patented circuit design technique has achieved operating performance efficiencies as much as eight times greater than previous bipolar families. An extensive library of SSI, MSI and LSI logic macros, including phase-locked loops and high resolution pro- grammable delay lines, is currently available in con- Figure 6. 20080 Die pty Table 9, Performance Summary PARAMETER VALUE Typical gate delay * 100-250 ps Maximum taggle frequency 1.25 GHz Maximum TTL input frequency 100 MHz Maximum TTL output frequency 60 MHz Maximum ECL input frequency (DIFF) 1.25 GHz Maximum ECL output frequency single ended 350 MHz Darlington (single ended, mixed mode only) 600 MHz differential 1.0 GHz cmt? 1.25 GHz ECL WO pair delay (min/max) 330/560 ps junction with AMCCs MacroMatrix design kit. The library features speed/power options that allow the de- signer to maximize critical path speed and density while minimizing overall chip power. MacroMatrix is avail- able for Mentor 8.x for both HP7XX and SUN platforms. Table 10. Q20000 TURBO ECL/TTL Product Summary Parameter Q20004 | Q20010 | Q20025 | a20045 | a20080 | a20120 |a20P010'|a20P025'|q20m100 Equivalent Gates -Flip Fiop 4 450 979 2687 4520 7494 12518 649 2178 8980 -Full Adder 671 1469 4032 6782 11242 18777 973 3272 13475 Core Cells 123 267 733 1233 2044 3414 177 595 2450 (/O Cell Count 30 68 102 130 164 200 34 51 195 Structured Array Blocks - - - - - - PLL PLL Memory Power (W) <1W 1-2 2-3 35 5-9 8-14 | 1.5-2.5 2-4 10-17 Refer to the Q20000 TURBO + PLL section of this data sheet for further information. 2 Based opon the use of complex macros and availability of speed/power options. 31.25 GHz CML output available in Q20P010 and Q20P025 only. 4 Computed using 11 gate equivalent, 3 cell 3:1 MUXed D Flip-Flop FF48 Macro. 5 Computed using 11 gate equivalent, 2 cell, One bit Full Adder, ADOS Macro. Available 1/O signals depends upon package and macro selection. Some I/O macros utilize more than one I/O cell, ? Assumes 50% Inputs, 50% Outputs, Mixed mode supply. Utilization determines actual array power dissipation. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Mm 048900e 0003948 45h 11-13AMCG Q20000 TURBO ECL/TTL LOGIC ARRAYS TECHNOLOGY The Q20000 Series of ultra high performance ECUTTL logic arrays is fabricated using a one micron bipolar process incorporating polysilicon emitter contacts, trench oxide isolation and an advanced base emitter structure (Figure 7). The 1um wide trench reduces the collector substrate capacitance to less than half and doubles packing density when compared to con- ventional oxide isolated devices. The minimum emitter feature size of 1pm x 2um (.6 x 1.6 effective) combined with the low capacitance of the double poly, trench isolated process, achieves a cut-off frequency (F;) of 14 GHz. The three level metal inter- connect system employs fine pitch geometries of 44m first, 5um second and 7um for the third level of metal. Figure 7. Process Cross Section BASE EMITTER COLLECTOR Onde] P Atk I ones Pe Te wer tt riot N+ N+ Ne DESIGN INNOVATIONS Conventional ECL structures use an output emitter follower biased with a static current source. When replicated and used hundreds or thousands of times per array these static current sources consume large amounts of current. As gate densities increase, this static current becomes a large power burden. To overcome this power burden, AMCC developed a patented dynamic discharge circuit (Figure 8) in place of the static current source for the emitter fol- lower. This dynamic discharge circuit is comprised of a capacitively coupled active pull down arrangement. The static power requirements when using this inno- vative technique are reduced substantially. Output skews between rising and falling edge delays are virtually eliminated and are significantly less affected by interconnect loading. This circuit technique in ef- fect Turbo Charges the output. M@ 0848900e 0003945 350 11-14 Figure 8 Q20000 Internal Cell Turbo Driver The Turbo circuit is beneficial for circuits operating at frequencies as high as 600 MHz and is used in implementing the majority of macro functions in Q20000 series designs. For circuit paths operating between 600 MHz and 1.25 GHz, the Q20000 Series Macro Library includes functions with the traditional ECL output emitter follower structure. The I/O cell also benefits from the innovative Turbo design. Off chip skews for ECL outputs (10KH or 100K) as well as loading effects versus conventional emitter follower structures are greatly improved. If a dua! sup- ply is available, the I/O cell can be configured with a Darlington output stage plus Turbo. This option gives a single VO cell the ability to drive a 25 ohm parallel terminated line at reduced switch current, thereby re- ducing power requirements. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMCG LOGIC ARRAYS Q20000 TURBO ECL/TTL et ieee tied ARCHITECTURE ARRAY ARCHITECTURE The Q20000 Series utilizes a channelless architec- ture called Sea-of-Cells. The Sea-of-Cells organi- zation eliminates the dedicated routing channels between cells used in channeled array architectures, thereby effectively doubling the core density. Utiliza- tion is maintained at above 95% because of three levels of metal interconnect and AMCCs state-of- the-art place and route software. First level metal is used primarily for macro definition while second and third metal levels handle inter-macro routing. The re- duced static power of the Turbo cell allows power and ground distribution to be interspersed on the second and third metal levels, eliminating the need for a dedicated power plane. Figure 9. Q20080 Die Organization Core Generator Cell TTT TO = 2 IC DOr ROT | HOE EUMTET CNT MCanremnne ner nT I eS Ieee ETT ROOM MMT Maree ne} PAROLE Tene] LLL RCT CSD A vcvceypuncoscuvecoued est 194090 OONT ec oe OVA TCAEB LEELA) Bt eT Oe EEE SU 0 CTU UO aU CEM PTET et ae U OM UMNO IG) Gaua En enn re kay BUC UT EET OTe c Mi Ue ee Te SRT OMT DIOL Nene esr i STERIC URC NCTC SOT TIO SOTO eit /O Cell Core Cell See UTTER On TOMI nant) Re a ae Reference STOTT TMM Lor nnn Pet | HOTTIE LION, SORT TCT Lacan PETIT IIITEMn cnn TUT Lae TT Generator VON Hava Da eon cvceag pea orc euera vie rLve MU ou TheNMEL AU TTUAE CUAL Ci 1 TCC OM TIMI. MOTTE SN] 2! STII TUT TOT | TOTTI PTE NU ear TTT] HTT RTT On It MTL Unt ECT] CHUCKLED RPC ESSA DCCC} Like previous ECL logic array families from AMCC, the internal core cell of the Q20000 Series uses togic efficient three level series gated structures. The three level structure can operate over the full military temperature (-55C ambient to +125C case) and voltage range of ECL 10KH or 100K logic because of AMCCs unique design. Table 10 lists representative macro functions and the number of cells required for implementation of each. A latch can be implemented in only one cell. oS, a oe a a5 e oO OO 04 The I/O cells are designed to interface with either 10KH, 100K or TTL thresholds. For over 600 MHz operation, a differential CML output structure is also available for use with selected 1/O cells and package pins. Each I/O cell in the array family can be either an input or an output. Bi-directional operation is achieved by paralleling any two adjacent I/O cells. The flexible /O structure of the Q20000 family allows operation in either 100% ECL, 100% TTL and mixed ECL/TTL I/O in either dua! supply or single supply configurations. Table 10. Functional Density MACRO FUNCTION usage | mano Flip-Flop with AR; A/AN outputs 2 FF12 Flip-Flop with EXORed Data; Q output 2 FFe2 Flip-Flop with 3:1 MUXed Data, Q output 3 FF48 D Latch 1 LA11 4:1 Mux 2 MxX21 2 Input Exclusive-OR, Y output 1 EX30 4-Bit Carry Look Ahead Adder 24 ADDOO 4-Bit Counter with AR, AS 26 CTRO2 8-Bit Comparator 40 CMPO0O STRUCTURED ARRAYS: Three members of the Q20000 TURBO ECL/TTL family feature embedded functions. The Q20P025 and Q20P010 arrays include a 1.25GHz PLL with 2500 and 1000 usable logic gates, respectively. The Q20M100 array includes eight 32 x 18 bit RAM blocks (total 4K) and 10,000 usable gates. For de- tailed information on the arrays featuring on-chip PLLs, refer to the Q20000 TURBO + PLL pages later in this section. For detailed information on the arrays featuring RAM blocks, see the Q20M100 data sheet on the AMCC website (www.amcec.com). Applied Micro Circuits Corporation Mm 0885900e 0003950 00e 6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333 11-15AMCG Q20000 TURBO ECL/TTL LOGIC ARRAYS LOGIC CELL FUNCTIONS HIGH SPEED/LOW POWER MACROS The Q20000 Series macro library offers maximum flexibility in the optimization of circuit performance and power consumption. A full complement of mac- ros is offered with low power, standard and high speed options. The high speed options require somewhat more power than standard options, but provide a significant improvement in propagation de- lay and/or maximum operating frequency. The low power versions of macros can be used to reduce power consumption in non-critical paths. Table 11 illustrates the speed, power and frequency tradeoffs for the three options of one sample macro. Table 11. Macro Speed Power Options: Example High Low GT65 8-INPUT OR Speed Standard Power Tpp min/max (ps)! 87/160 103/189 | 167/298 lee (mA) 1.12 0.776 0.455, Max Operating Freq. (MHz){ 1200 800 600 1Tpd = [TpD..) + TPD,) /2. Path shown is any input to Y output. DIFFERENTIAL MACROS The Q20000 family offers a wide range of differential macros to facilitate high speed designs. Both core and I/O macros are available to allow fully differentia! paths and maximize the noise immunity and speed of your design. These differential macros are in- cluded as a standard part of the AMCC Design Kit. Ask your AMCC rep for more details. INTERNAL LOGIC CELL CAPABILITIES The Q20000 Series internal logic cells are alt identi- cal in structure and are uniformly positioned in a Sea-Of-Cells matrix across the internal core area of the array. Each cell contains 13 uncommitted tran- sistors and 13 resistors. The cells are individually configurable to provide a variety of logic functions by placing macros from the Q20000 Series macro li- brary. The macro library provides SSI, MSI and some basic LSI functions. Higher functionality mac- ros provide the advantages of higher speed, lower power and increased circuit density over a logically equivalent SSI macro implementation. FLEXIBLE /O STRUCTURE The 20000 Series I/O cells are configurable to pro- vide a universal range of interface options for both single and dual supply modes. The mixed ECL/TTL capabilities allow interface to both technologies on a single chip without the use of external transtators. Refer to Table 12 to see the wide variety of available interface options, which can be mixed as required by each design. Table 12. Signal Interface Options INPUT BIDIRECTIONAL OUTPUT TTL Totem Pole TTL TTL Transceivers TTL Tri-State TTL Open Collector ECL 10K and 10KH ECL 10K and 10KH ECL 10K and 10KH Transceivers ECL 100K ECL 100K Transceiver ECL 100K CML CML Open Collector ECL INTERFACE The Q20000 Series arrays can interface to standard and positive reference (+5V) ECL 10K, 10KH and 100K levels. ECL inputs can enter the array from any I/O cell and, in some cases, may be connected directly to core cells without additional buffering. Ad- ditionally, signals can be input differentially to re- move common mode noise. ECL outputs can leave the arrays from any {I/O cell. Different configurations of the I/O cells provide for a 50 ohm or 25 ohm output drive. Differential CML outputs are available for high frequency paths. The Q20000 Series allows for a special type of ECL output macro which incorporates a Darlington output configuration. These macros maintain standard ECL 10K, 10KH and 100K output levels, while netting an improvement in drive capability and toggle fre- quency over standard ECL outputs. While requiring dual power supplies, the Darlington output macros will accommodate 25 or 50 ohm loads in a single /O location while maintaining ECL standard levels. Bidirectional ECL operation is available using two adjacent I/O cells. Mm 0oaacsade 0003951 TH5 Applied Micro Circuits Corporation 11-16 6195 Lusk Bivd., San Diego, CA 92121 * (619) 450-9333AMCC Q20000 TURBO ECL/TTL LOGIC ARRAYS TTL INTERFACE TTL inputs can be placed in any I/O cell. Once on-chip, TTL signals are automatically converted to internal volt- age levels for internal logic operations. Signals leaving the array are translated from an inter- nal voltage level to TTL level in the I/O cell. Following this translation, TTL outputs are available in totem pole, 3-state or open collector configurations. TTL out- puts, like inputs, can be located in any I/O cell. Bidirectional TTL operation is available in single cell and dual I/O cell implementations. CUSTOM MACROS AMCC has developed a macro development system to simplify the design and implementation of custom mac- ros. This tool suite uses a correct-by-construction ap- proach to insure that macros meet all the pertinent design rules and parametrics. As individual circuit ap- plications warrant, macros with unique characteristics can be developed to optimize a customer's design. POWER SUPPLY CONFIGURATIONS On the Q20000 Series arrays there are four basic inter- face configurations: single-supply ECL, single supply PECL, dual-supply mixed TTL/ECL and single-supply mixed TTLVYECL. Power supply requirements for each mode of operation are shown in Table 13. Table 13. YO Power Supply Configuration VO MODE Vos Voc ECL 100K -4.2 to -4.8 V! - ECL 10K, 10KH 4.7 to -5.7V - ECL 100K/TTL -4.2 to -4.8V" 4.5 to 5.5V ECL 10K, 10KH/TTL | -4.7 to -5.7V 4.5 to 5.5V PECL 100K . 4.5 to 5.5V PECL 10K, 10KH . 4.5 to 5.5V PECL 100K/TTL - 4.5 to 5.5V PECL 10K, 10KH/TTL . 4.5 to 5.5V May be configured with a -5.7 supply. Consult AMCC for DC parametrics. Applied Micro Circuits Corporation 6195 Lusk Blyd., San Diego, CA 92121 * (619) 450-9333 | 0464900e 0903952 5945 11-17AMCG PACKAGING THE Q20000 TURBO ECL/TTL logic array family is available in a range of standard packages including thermally enhanced plastic, surface-mountable ceramic chip carriers and ceramic pin grid arrays (see Table 14). Other package types, including ball grid arrays will be supported as required by new ASIC opportunities. For additional details, consult the AMCC website (www.amcec.com) and check out the AMCC Packaging Guide. Table 14. Q20000 TURBO ECL/TTL Family Packaging Matrix PKG DESCRIPTION/ DIE NAME Q20004 ; Q20010 | Q20025 | Q20045 | Q20080 {| Q20120 Plastic 28 PLCC Plastic 44 PLCC Plastic 68 PLCC Plastic 68 PLCC/EDQUAD Plastic 52 PQFP Plastic 80 PQFP/EDQUAD Plastic 100 PQFP/EDQUAD Plastic 120 PQFP/EDQUAD Plastic 160 PQFP/EDQUAD Plastic 208 PQFP/EDQUAD Ceramic 100 LDCC Ceramic 132 LDCC Ceramic 196 LDCC Ceramic 224 LDCC Ceramic 100 PGA Ceramic 149 PGA Ceramic 209 PGA Ceramic 251 PGA Ceramic 300 PGA Applied Micro Circuits Corporation 11-18 M@ 0889002 0003953 41) 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333Q20000 TURBO + PLL LOGIC ARRAYS WITH ON-CHIP PLLs all tl lata FEATURES * On-chip high frequency phase-locked loop Up to 1.25 GHz capability * Edge jitter as low as 10ps (rms) and 50 ps (pk-pk) * 900 to 3000 gates of customizable digital logic * Utilizes proven Q20000 Series macro library 100 ps equivalent gate delays Low power (0.5-1.0 mW/gate) 10K, 10KH, 100K ECL, PECL and mixed ECL/TTL capability Speed/power programmable logic and /O * Operation over commercial and military ranges * Up to 95% utilization of digital logic * Full logic simulation modeling support of PLL functions Table 15. Performance Summary Parameter Value Phase-Locked Loop Operating Frequency 125 MHz-1.25 GHz Edge Jitter (pkpk) 50-100 ps Residual BER 10E-12 Acquisition Time (typical) 1.0 us Digital Typical Gate Delay 100-250 ps Maximum Toggle Frequency 1.25 GHz Maximum TTL input Frequency | 100 MHz Maximum TTL Output Frequency} 80 MHz Maximum ECL Input Frequency | 1.25 GHz Maximum ECL Output Frequency} 1.25 GHz Table 16. Product Summary Q20P010 Q20P025 Equivalent Gates Full Adder Method 928 3120 Flip-flop Method 637 2142 Internal Logic Cells 177 595 1/0 Pins 1 PLL Related Loop Filter 0 0 Signals 12 12 Powers & Grounds 8 8 Digital Signals up to34? up to 51? Powers & Grounds 20 22 AC Monitor & Thermal 4 4 Diode Maximum Total Power (W) 1.5-3 2-3 1 See Table 17 for packaging options. 2 Actual number of signal pins available depends on package choice. Figure 10. Q20000 TURBO + PLL Architecture Program- mable Divider Voltage Controlled Oscillator (VCO) Phase Detector Loop Phase-Locked Loop | Fite: APPLICATIONS High speed datacom * Video shift registers * High performance telecom Frequency synthesis * Timing generation circuits * Self-timed systems DESCRIPTION The AMCC Q20P010 and Q20P025 PLL logic arrays offer gate densities of 900 and 3000 equivalent gates with an on-chip high frequency phase-locked loop. Combining a PLL with user-definable Q20000 series arrays, the Q20P010 and Q20P025 are tailored for high speed serial communication, video, and clock generation applications. Clock synthesis and clock recovery macros are available for the on-chip phase-locked loop. Speed options ranging from 125 MHz to 1.25 GHz are avail- able. Complete simulation models, implementing ail CSU/CRU functions, are available for digital logic simulation on Mentor workstations as well as the LASAR simulator. Lock detect, local and link loopback features are also supported. For the digital logic portion of the array, an extensive library of SSI and MSI macros is available as part of AMCCs MacroMatrix design kit. Latches, parallel- to-serial converters, encode/decode functions, high speed shift registers, bit error rate computation and divide-down counters can easily be assembled to operate in conjunction with the phase-locked loop to meet specific application needs. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 mm 08489002 0003954 756 11-19AMCC DEVICE ARCHITECTURE Q20000 TURBO + PLL DIGITAL LOGIC The @20000 Series is the industry's first ECL logic array family to utilize a channelless architecture called Sea-of-Cells. The Sea-of-Cells organization eliminates the dedicated routing channels between cells thereby doubling the core density. Utilization is maintained at greater than 95% due to three layer metal interconnect and AMCCs state-of-the-art place and route system. A full complement of SSI and MSI macros is offered with low power, standard and high speed options. For more information on the Q20000 TURBO + PLL digital logic, see the AR- CHITECTURE and LOGIC CELL FUNCTIONS para- graphs in this section of the data book (pages 11-15 and 11-16). To minimize noise injection from the core logic into the PLL section of the device, all core logic must be operated synchronously with the PLL. Figure 11. Phase-Locked Loop Block Diagram PHASE-LOCKED LOOP MACROS A selection of clock synthesis and clock recovery macros are available for the on-chip phase-locked loop. PLL center frequencies of 1000, 1062, 1244 and 1250 MHz are available with user selectable di- vide ratios of 1, 2, 4, and 8. This results in speed options of 125, 133, 155, 250, 266, 311, 500, 531, 622, 625, 1000, 1062, 1244 and 1250 MHz that are available to operate synchronously with the logic in the digital portion of the array. Additional frequency options can be created to meet specific design re- quirements. AMCC defined loop filter components for each frequency option have been established for applications with divide ratios up to 500, transition densities from 30% to 70%, and run lengths up to 64-bit times. Lock detect, local and link loopback features are also supported in any of these configu- rations. ' I ' Loop | Filter | I ' SLL Phase Detector +M JUUL +N Voltage Controlled Oscillator (VCO) Applied Micro Circuits Corporation Me 0689002 0003955 694 mm 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 11-20AMCC Q20000 TURBO + PLL DEVICE ARCHITECTURE et cia il ttl ieee ENCODING/DECODING High speed datacom and telecom applications fre- quently require a standard encoding scheme to en- sure favorable bit stream characteristics and inter-operability. AMCC offers an encoder/decoder scheme implemented using standard macro library components. Popular in datacom applications, IBMs 8B/10B encoding scheme offers DC-balance and short run lengths in an efficiently architected imple- mentation. The 8B/10B macros are available under a licensing and nondisclosure agreement. CMI encod- ing and decoding blocks, especially popular in telecom applications where copper is the transmis- sion medium, are available as well. Other encoding and decoding schemes can easily be designed as needed using the digital portion of the Q20P010 and Q20P025 arrays. Figure 12. Representative Transmitter Block Diagram FLEXIBLE !/0 STRUCTURE The Q20P010 and Q20P025 array I/O cells are configurable to provide a flexible range of interface options. The I/O cells are designed to interface with standard (-5.2V or 4.5V) and positive reference (+5V) ECL 10KH and ECL 100K or TTL thresholds. The mixed ECL/TTL capabilities allow interface to both technologies on a single chip without the use of external translators. For dual power supply devices, the I/O is also capable of a Darlington-type ECL out- put which provides significant improvement in drive capability, toggle frequency, and power dissipation over standard ECL outputs. [REFCKINPAN] (E) Raf. Chic In 2 | Ref Ck Out. [REFCKOUT} Lock Detect. [LOCKDET) (T} + Phase [BYTCLKIPN] = Byte_Cik 2, Detector (DIVNCNT<0:2>) Bit Cik Divide Control {RST} Reget, {TSTAST) Tst_Reset (TSTCLKEN} (1) = Teat_Clk En | [ > Lock Detect AS, {LOCKDETA] Loop Fikter Voltage Controlled Oacilator Tasten {TESTEN] v Serial Ck Out [SERCLKOP] [SEROATEN} Serial Data En nN 2, [Serial Data Ou [SERDATOPAY (6) (LPDATOPAN] (E) () ect F oan (LKLPCKIP/N] (E) Link Ck int 2 MUX a) (SERDATIPAN] -Sarial Oata In 2 a4 [LKLPOTIP/N] (E) Link Loop Data in| 2, MUX [LNKLPEN) Link Loop En Tt [LOCLPEN} Loopback En [WCOOEN] Veo En Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 + (619) 450-9333 J O&88900e 0003954 Seo 11-21AMCCG ON-CHIP PLL OVERVIEW Q20000 TURBO + PLL PHASE-LOCKED LOOP The basic phase-locked loop components are shown in the PLL block diagram (Figure 11). The loop con- sists of a phase detector, which compares the phase difference between the VCO and the reference input, a loop filter, which converts the phase detector out- put into a smooth DC voltage, and the VCO, which generates a frequency based on its input voltage. PLL building blocks differ for clock synthesis and clock recovery. This is due in large part to the differ- ences in reference inputs to the phase detector. In the case of the clock synthesis PLL (see Figure 12), the reference input is a very stable crystal-based source. For clock recovery from a serial data stream (see Figure 13), the reference input has varying tran- sition density; i.e., different run lengths of 1s and 0s with short term frequency variations. Since the loop filter generates a control voltage for the VCO input based on the output of the phase detector, different sets of loop filter components must be specified for clock synthesis versus clock recovery applications. Figure 13. Representative Receiver Block Diagram In addition, appropriate filter components will be re- quired for different encoding schemes, acquisition time requirements and system noise environments. AMCC provides selectable sets of on-chip resistors and capacitors appropriate for specific system condi- tions. SPECIAL FEATURES Lock Detect For clock recovery macros, lock detect indicates the phase state of the PLL relative to the incoming data stream. Control pins from the core logic area permit lock detect to be indicated after 512, 1024, 2048, or 4096 bit times depending upon loop filter param- eters. On CRU macros, if the serial data inputs have an instantaneous phase jump, the CRU will not indi- cate out-of-lock state, but will recover correct phase alignment within the pre-loaded bit times. For the CSU macro, lock detect indicates the phase state of the PLL relative to the incoming reference clock. (LCKDETOY] [REFCKINPAN} (E) [SERDATIPM] (E} [LPOATIPAg (E) [LOCLPEN] {ACACTL<O:19] [BYTCLKIP] (DIVNCNT<0:2>} ITSTCLKEN] (1) (RST) [TSTRST] [ACQCONT} {REFCKOUT] [LOCKDET] (1) [LOCKDETA] (TESTEN] [SERCLKOP] Out [FRKCNT] Loop Clock Ow [LKLPCKOPM] (E) Data [SERDATOP] Loop Data Out (LKLPOTOP/N] (E} 11-22 MH 0849002 0003957 4b? Applied Micro Circuits Corporation 6195 Lusk Bivd., San Diego, CA 92121 (619) 450-9333AMCG Q20000 TURBO + PLL ON-CHIP PLL OVERVIEW S=trw_> eee LOOPBACK MODE Local Loopback Local and link loopback are supported for both datacom or telecom applications. Local loopback re- quires both a transmit chip and a receive chip. When enabled, serial encoded data from the transmit chip is sent to the receive chip where the clock is ex- tracted and the data decoded. The parallel data out- put by the receiver is then sent to the subsystem for verification. This loopback mode provides the capa- bility to perform offline testing of the interface to guarantee the integrity of the serial channel before enabling the transmission medium, and allows sys- tem diagnostics. Link Loopback Link loopback provides a means for link testing. When link loopback mode is enabled, the transmitter Figure 14. Loopback Diagram accepts serial clock and data from the receiver chip. The serial data is reclocked using the link loopback clock to minimize the data distortion and then trans- mitted via the serial data output pins. Link loopback can also be used to implement a repeater function. In this case, clock jitter and data distortion will deter- mine the allowable number of repeaters in the path. TEST/BYPASS MODE Clock recovery and clock synthesis macros have testability input pins to aid in functional testing or PLL clock bypass tests. Test Clock Enable places the macros into test mode. An externally generated clock can then be input via the reference clock in- puts. The PLL clock bypass path is typically capable of operating at up to 1.25 GHz to allow at speed testing of the chip functions, or for applications in which a user selectable external clock signal needs to be supported. Datain [_ > Control | Transmitter Link Loopback Local Loopback H Receiver Data Out < CLK < > Data Out Receiver - CLK t Local Loopback Link Loopback ' ' ! h Transmitter Ki Data In t- Control Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Mm 0469002 0003954 3T3 11-23AMCC FREQUENCY SYNTHESIS MACROS Q20000 TURBO + PLL Clock Synthesis Macros The clock synthesis PLL will generate a high fre- quency clock in phase with the input reference. A typical frequency multiplication factor is 20, and mul- tipliers as high as 500 have been implemented. Criti- cal parameters for the clock synthesis PLL are jitter and accuracy. AMCC loop filter components are set to optimize the loop for minimum phase jitter and maximum accuracy, with less emphasis on acquisi- tion time. Loop filter parameters can be varied by AMCC on a custom basis. Specifications input Reference Frequency The input reference frequency can be a selected divide ratio of the syn- thesized clock frequency. Reference Clock Jitter The reference clock needs to be generated from a stable source such as a crystal oscillator. The allowable rms jitter cannot exceed .04% of the reference clock pulse width. Input Reference Stability The reference clock stability should be better than 100 ppm. Acquisition Time The loop acquisition time will depend on the loop filter parameters. (1.0 us to 10 ps values are typical). Edge jitter The output edge jitter will depend on the loop filter parameters. (50 to 100 ps (pk-pk) val- ues are typical). Supply Voltage Sensitivity Power supply noise rejection will be between 40 and 60 dB depending on the noise spectrum. Clock Recovery Macros The clock recovery PLL will generate a clock which is at the same frequency and 180 degrees out of phase with the serial data input. This generates clock and data outputs from the incoming serial bit stream which feeds the subsequent parallel conver- sion. An external clock reference is used to reduce initial acquisition time and to provide stability in the absence of serial data. The filter parameters are set to optimize the loop for the anticipated serial data input characteristics. These include: maximum run length and transition density of 1s or 0s, and the jitter associated with the fiber optic link. Loop filter parameters can be varied on a custom basis by AMCC. Specifications Input Reference Frequency The input reference frequency can be a selected divide ratio of the VCO clock frequency. The maximum divide ratio is 500. Reference Clock Jitter The reference clock needs to be generated from a stable clock source such as a crystal oscillator. For maximum perfor- mance rms jitter should not exceed .04% of the ref- erence clock pulse width. Input Reference Stability The reference clock stability should be less than 100 ppm. Acquisition Time The loop acquisition time will depend on the loop filter parameters. (1.0 us to 10 us values are typical) Edge Jitter The edge jitter will depend on the loop filter parameters and the serial data input speci- fications. (50 ps to 100 ps (pk-pk) values are typical) Supply Voltage Sensitivity Power supply noise rejection will be between 40 and 60 dB depending on the noise spectrum. Data Rate The possible serial data rates from which a clock can be recovered will be grouped around the VCO center frequency, with integer di- vide ratios of 1, 2, 4, 8, etc. Allowed Data Jitter The allowed input data jitter will be a function of the required acquisition time, along with the loop filter parameters, data rate, and bit error rate. The jitter specification includes duty cycle distortion, random jitter and data dependent jitter. Pull In Range The pull in range of the VCO is +6%. Bit Error Rate Bit error rates of 10-12 or lower are achievable. Applied Micro Circuits Corporation 11-24 MM 04689002 0003959 23ST MM 6195 tusk Blvd., San Diego, CA 92121 + (619) 450-9333AMCG HIGH SPEED I/O CONNECTIONS HIGH SPEED I/O CONNECTIONS The high speed ECL compatible differential inputs in both the CRU and CSU macros have a built in 1002 termination resistor across the differential pair, Q20000 TURBO + PLL elimi- put and output connections. nating terminating components in loopback and data Figure 15. High Speed Input and Output Applications paths and ensuring low jitter interfaces. Figure 15 shows some examples of high speed CSU/CRU in- _________, CSU LPDATOP to CRU LPDATIP to MoM | Electrical 330 Q VEE to High Speed CRU Input CRU LKLPCLOP to CSU LKLPCKIP CRU LKLPDTOP to CSU LKLPDTIP + + High Speed CRU/CSU Output Intema! 100 Q to High Speed CSU/CRU Input termination SERDATIP 330 Interna! 100 2 ECL Compatible Output L_ termination to CRU High Speed Input 500 100.2 REFCLK Trans. 2V ~ Line = . = 0.1 LF intemal 100 Q Unbalanced ECL Signal Source termination Electrical to 100 2 : Optical Zoe CSU Serial Data Output to E/O Transmitter Transmitter| Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Me 0489002 0003560 T51 11-25AMCCG Q20000 TURBO + PLL PACKAGING PACKAGING The Q20000 TURBO + PLL arrays are available in a range of standard packages including plastic, ther- mally enhanced plastic (EDQUAD), and surface- mountable ceramic chip carriers. Packages have been custom designed as necessary to offer con- trolled impedance on high speed signai lines and minimum digital noise Injection to the PLL area. Table 17 provides a matrix illustrating many of the packages available for these products. Other pack- aging options are available on an as needed basis. Table 17. Q20000 TURBO + PLL Family Pack- aging Matrix PKG DESCRIPTION/ DIE NAME Q20P010 Plastic 44 PLCC X Plastic 44 PLCC/EDQUAD Plastic 68 PLCC Plastic 68 PLCC/EDQUAD Plastic 52 TQFP/EDQUAD Plastic 80 PQFP/EDQUAD Plastic 100 PQFP/EDQUAD Plastic 120 PQFP/EDQUAD Ceramic 68 LDCC mM] mK | OS] OK | OOK Ceramic 100 LDCC Ceramic 132 LDCC Q20P025 11-26 mm 088900e 0003961 195 Applied Micro Circuits Corporation 6195 Lusk Blyd., San Diego, CA 92121 * (619) 450-9333AMCG Q20000 TURBO ECL/TTL TIMING VERNIERS ee ei TIMING VERNIER PD01S The PDO1S is a programmable delay macro in the Q20000 TURBO family that provides a timing genera- tion or deskew function for precision timing applications such as ATE, instrumentation, clock distribution, and high speed busses. Key features of the PDO1S include: * Up to 30 delay lines per array possible * Local macro voltage regulation for superior crosstalk performance * Cascadable for greater delay range * 64 core cells in size * Ring oscillator mode for testability * 7 decode bits for 127 selectable delay steps A differential signal is applied to input pins A/AN, is modified with the addition of a delay specified by the binary input address pins D[6:0], and emerges at out- put pins Y/YN. The test enable input (TE) is held high for normal operation. When the TE input is set low to put the vernier into the test mode, the Y/YN output is internally inverted and fed back to the A/AN input. This allows the PDO1S to function as a ring oscillator and enables operation verification. Changing the binary code of address pins D[6:0], changes the frequency of oscillations of the PDO1S macro, allowing for convenient testing of accuracy through delta frequency measure- ments. Table 18. Performance Summary PDO1S Pp02s Delay Step Resolution (typ) 40 ps 320 ps Delay Step Resolution (max) 60 ps 340 ps Minimum delay range 2.1 ns t.8 ns IEE (typ) 40 mA 21mA Max frequency 400 MHz 400 MHz Minimum pulse width 1.25 ns 1.25 ns Minimum propagation delay 2.0 ns 1.0 ns Linearity to D1 ? YES Monotonic? YES YES Figure 16. Functional Block Diagram A 1 Y-. ANT Programmable Delay ' 1 1 t t TE BO 61 D2 03 B4 DS 06 ATL VERNIER CHARACTERISTICS * (Y,YN) = (A,AN) * NOMINAL DELAY = (20*D0 + 40D1 + 80*D2 + 160*D3 + 320D4 + 640*D5 + 1280D6 +2000)ps * TE = Low, Puts PD0O1S into Ring Oscillator Mode TE = High, Normal Mode TIMING VERNIER PDO2S The PDO2S is a programmable delay macro with identical characteristics to the PDO1S, but it does not include the three least significant bits. It is designed to be cascaded to the PDO1S, thereby adding steps and increasing the delay range of the vernier while keeping the functionality identical. , Key features of the PD02S include: * Up to fifteen 4 ns verniers (PD01S + PDO2S) per array possible * Local macro voltage regulation for superior crosstalk performance * Can be cascaded with additional PD02 macros to add delay in 2ns (typ) increments A differential signal is applied to input pins A/AN, and outputs Y/YN drive the A/AN inputs of a PD01S or another PDO2S macro. An incrementai delay is added by the PD02S which is specified by the binary input address pins D[6:3], and the signal emerges at outputs Y/YN. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 ME 0489002 00039b2 325 mm 11-27AMCG APPLICATION EXAMPLE Requirements: 5ns span, 20ps typical delay resolu- tion, 60ps worst case delay resolution. Solution: 1 PD01S cascaded with 2 PDO2S macros. See Figure 17. Figure 17. Timing Vernier Applications Example PD02S YN PDO2S D3 D4 DS D6 D3 D4 DS D6 Applied Micro Circuits Corporation 11-28 ME 0889002 0003963 760 MM 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMC Q20000 TURBO ECL/TTL LOGIC ARRAYS DESIGN INTERFACE AMCC has structured its circuit design interface to pro- vide maximum flexibility while ensuring design correct- ness. For implementations using a Mentor workstation, AMCC provides MacroMatrix software. MacroMatrix works in conjunction with Mentor 8.X to provide the fol- lowing capabilities: * Schematic Capture * Logic Simulation * Pre-Layout Delay Estimation (Front Annota tion) * Array and Technology-Specific Rules Checks (ERCs) * Estimated Power Computation * Layout Netlist Generation * Post-Layout Timing Verification (Back Annota tion) * Graphical Floor Planning (IPL) * Dynamic Timing and Test Vector Analysis (RaceCheck) Upon submission of the design database to AMCC, a comprehensive review of the circuit is performed mak- ing use of the very same EWS and MacroMatrix tools used by the designer. No golden simulator is em- ployed to verify the timing of the design. No translation of the logic data is required so the chance of non design-related errors is virtually eliminated. AMCC DESIGN SERVICES AMCC also provides a number of additional support services including: * Acontinually updated Website located at www.amec.com * Local and factory applications engineering support * Thorough design documentation Full design implementation - Turnkey Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 + (619) 450-9333 umm 0649002 OOOSJ5SLY4 LT? 11-29AMCC OPERATING CONDITIONS Q20000 TURBO ECL/TTL Table 19, Recommended Operating Conditions-Commercial Parameter Min Nom Max Units ECL Supply Voltage'* (Weg) Veg = 0 10K, 10KH Mode 4.94 5.2 -5.46 Vv 100K Mode 4.2 -4.5 -4.8 Vv ECL Input Signal - 1.0 3.0 ns Rise/Fall Time ECL Input Voltage 2.0 Vv TTL Supply Voltage (V,,.) 4.75 5.0 5.25 PECL Supply Voltage 4.75 5.0 5.25 Vv TTL Output Current Low (1,,) 20 mA 0 70 4 Operating Temperature (ambient) (ambient) Cc Junction Temperature 130 c Table 20, Recommended Operating Conditions-Military Parameter Min Nom Max Units ECL Supply Voltage* (ee) Vor = 10K, 10KH Mode 4.7 5.2 5.7 Vv 100K Mode -4.5 -45 -4.87 Vv ECL input Signat - 1.0 3.0 ns Rise/Fall Time TTL Supply Voltage (V,,.)' 4.5 5.0 5.5 Vv PECL Supply Voltage 4.75 5.0 5.25 TTL Output Current Low (1,,) 20 mA . -55 125 . Operating Temperature (ambient) (case) Cc Junction Temperature 150 C Table 21. Absolute Maximum Ratings ECL Supply Voltage V,, (V,, = 0) -8.0 VDC ECL Input Voltage (V,, = 0) GND to -2.0 V ECL Output Source Current (continuous) SOMA DC TTL Supply Voltage (V_, = 0) 7.0V TTL input Voltage V,,. (V,,. = 0) 5.5V -55C (ambient) to +125C (case) Operating Junction Temperature T, +150C Storage Temperature -65C to +150C Operating Temperature 1 Power sequencing is required on all dual supply ECL/TTL circuits. The positive supply must be turned on at feast 30 ms before the negative supply. 2 For ECL circuits using a Vit = Vcc - 2V termination supply extemally, this supply should be turned on at least 30 ms after the Voc supply. 3 -5.7V is possible. Consult AMCC for ECL 100K DC parametric operating at this voltage. 4 Long term exposure at these limits may result in permanent change or damage to the circuits. Actual circuit operation at these conditions is not recommended nor implied. ME 0oaa8900e 00035965 533 Applied Micro Circuits Corporation 11-30 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMCG a OPERATING CONDITIONS Q20000 TURBO ECL/TTL em Table 22. AC Electrical Characteristics com MIL Symbol Parameter Conannons O'C/+70C | -85C/+125C | nit Min | Max | Min | Max tpp-ECL ECL Input Propagation Delay Including Buffer IE94S 59 263 57 281 ps tp FTL TTL Input Propagation Dealy Including Buffer IT50H 93 535 65 602 ps topp-ECL ECL Output Propagation Delay - Darlington OK40S No Load 185 | 340 | 157 | 356 ps toppt TTL bey Propagation Standard OT67S No Load 2213 | 4292 | 2056 | 4375 | ps leo Internal Equivalent Gate Power 120 250 120 250 ps tandard 105 175 105 175 ps Fant Internal Flip/Flop Toggle Freq. | High Speed 1,25 1.25 | GHz Single-Ended 600 600 { MHz F,-ECL Packate P Frequency at Spear High g00 800 | MHz Driver 1.25 1.25 | GHz Single-Ended 350 350 | MHz FECL ECL Output Frequency at Differencial 1.25 1.25 | GHz on Package Pin' Darlington 600 600 | MHz CML 1.25 1.25 | GHz FTL TTL Input Frequency at Standard 60 60 | MHz m Package Pin High Speed 100 100 | MHz FE -TTL TTL Output Frequency at Low Power 20 20 | MHz a Package Pin Standard 80 45 | MHz Table 23, ECL 10K Input/Output DC Characteristics Veg = -5.2V! ea Unit -65'C oc 25C 70C 125C Voimar Vgq7850 Vger?70 Vog"730 Vpg"850 Vegr575 mv Vusmax Vgq7800 Vo7720 Vgg"680 Voq7600 Vgq7525 mv Vormin? Vog7 1080 Voe-1000 Vg980 Vogr920 Vogr850 mv Vanin? Voor 1255 Vor 1145 Veg? 105 Veg 1045 Voor1000 | mv Vimar Veg 1510 Veg? 1490 Vog71475 Voor 1450 Vogr1400 | mv Voimer Vog71 655 Voq7 1625 Vo71620 Voe71585 Voc71545 | mv Voumin Veg" 1980 Veg1980 Veg" 1980 Veqr1980 V._-1980 | mV Vicmin Vgg72000 Vgq72000 Veq*2000 Vgq"2000 V,_2000 | mv |? (max) 30 30 30 30 30 pA 1? (max) -5 -5 5 -.5 -6 pA Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Me 0489002 0003956b 47T 11-31AMCG Table 24. ECL 100K Input/Output DC Characteristics Vee = -4.5 V? Comm 07/+70C MIL -557/+125C Symbol Parameter Test DC Conditions Unit Min Typ Max Min Typ Max Vou Output Voltage HIGH _| Loading is 50 Ohms to -2V V5_71053 V5850 |} Vg9-1080 Voc7835 | mV Vo Output Voltage LOW | Loading is 50 Ohms to -2V Vog71830 Vog71605 | V,,1880 Vo1595 | mV Vinee | Input Voltage HIGH Maximum input voltage HIGH | V,,-1145 Vo_7800 | V,,-1145 Vo_-800 | mV Vime | INput Voltage LOW Maximum input voltage LOW | V,,-1950 Vog-1475 | V,,-1950 Vog-1475 | mV \? Input LOW Current Vin = Virmax 0.5 0.5 pA i? Input HIGH Current Vin = Viemax 30 30 pA Table 25. TTL Input/Output DC Characteristics Comm 07+70C Mil -55/+125C Symbol Parameter Test DC Conditions Unit Nin Typ* | Max Min Typ Max Guaranteed input HIGH 5 Vie Input HIGH Voltage voltage for all inputs 2.0 2.0 Vv Guaranteed input LOW & vi Input LOW Voltage voltage for ail inputs 0.8 0.8 Vv Vix Input clamp diode voltage Vog = Min, 1, = -18 mA -8 1.2 8 1.2 v oH Output HIGH Voltage Vog= Min, |,, =-1 mA 27 3.4 24 3.4 Vv ly =4mA 0.4 0.4 Vv Vor Output LOW Voltage Veo = Min \o, = 20 MA 0.5 0.5 Vv Output off current HIGH _ _ . lozn (3-state) Vog = Max, Vou, = 2.4V 50 50 -50 50 pA Output off* current LOW _ . Low (3-state) Veg + Max, Vou, = 0.4V 50 50 -50 50 HA Ia Input HIGH current Veg = Max, Viy = 2.7V 50 50 LA \, input HIGH current at MAX Veg = Max, V,, = 5.5V 1.0 1.0 mA 1,8 Input LOW current Veg = Max, V,, = 0.5V -0.4 -0.4 mA log Output short circuit current Vog = Max, Voyy = 0.5V -25 -100 -25 -100 mA 1 Data measured with Vee = -5.2 + .1V (or Vec = 5.0 + .1V for +5V ref. ECL 10K) assuming a +50C rise between ambient (Ta) and junction temperature (Ty) for -55C, 0C, +25C and +70C, and a +25C rise for +125C. Specifications will vary based upon Ty. See AMCC Packaging and Design Guides concerning Voy and Vor adjustments associated with Ty for packages and operating conditions. Per fan-in. Data measured at thermal equilibrium, with maximum Ty not to exceed recommended limits. See AMCC Packaging Guide to compute Ty for specific package and operating conditions. For +5V ref. ECL 100K, Voy and VoL specifications will vary based upon power supply. See AMCC Design Guide for adjustment factors. Typical limits are at 25C, Vcc = 5.0V. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment. Use extreme care in defining input levels for dynamic testing. Many outputs may be changed at once, so there will be significant noise at the device pins and they may not actually reach Vit or Vin until the noise has settled. AMCC recommends using ViLs0.4V and Vin>2.4V for dynamic TTL testing and Virmin and Vinmax for ECL testing. For standard speed options only. on ae a Mi 0889002 00039647 306 Applied Micro Circuits Corporation 11-32 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333