DATA SHEET LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS- ICS8535-31 TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535-31 is a low skew, high performance e 4 differential 3.3V LVPECL outputs tte SSN Crystal Oscillator eNOS 108 * Selectable LVCMOS/LVTTL CLK or crystal inputs E HiPerClockS family of High Performance Clock CLK can accept the following input levels: LVCMOS, LVTTL Solutions from ICS. The ICS8535-31 has select- able single ended clock or crystal inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and e Output skew: 30ps (maximum) translate them to 3.3V LVPECL levels. The output enable is internally synchronized to eliminate runt pulses on the out- puts during asynchronous assertion/deassertion of the clock Propagation delay: 1.65ns (maximum) enable pin. e Maximum output frequency: 266MHz e Part-to-part skew: 200ps (maximum) e Additive phase jitter, RMS: 0.057ps (typical) Guaranteed output and part-to-part skew characteristics make the ICS8535-31 ideal for those applications demand- ing well defined performance and repeatability. e 3.3V operating supply 0C to 70C ambient operating temperature Lead-Free package fully ROHS compliant Industrial Temperature information available upon request Replaces the ICS8535-11 Biock DiaGRAM Pin ASSIGNMENT Pullup CLK_EN a D ve 1 200 ao Q CLK_ENTH2 = 19 nao LE CLK_SELO3 1801 vec cLk 4 170 CLK Pulldown ne 5 ieH oot 00 XTALINOJ6 150.1 qe xTaAL_ouTOW7,s 1400 naga XTAL_IN- nao nos 13f) vec [_] at ne 9 1200 a3 xTAL_ouT- nt Voc 10 11 nas CLK_SEL Pulldown 7 Q2 > ICS8535-31 na 20-Lead TSSOP Q3 6.5mm x 4.4mm x 0.92mm package body nQ3 G Package Top View IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 1essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. Pin DESCRIPTIONS Number Name Type Description 1 Ver Power Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follows clock 2 CLK_EN Input Pullup | input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. 3 CLK_SEL Input | Pulldown When Low. setocts CLK input, LVCMOS. i IVT interface levels. 4 CLK Input | Pulldown | Clock input. LVCMOS / LVTTL interface levels. 5, 8,9 nc Unused No connect. 6, XTAL_IN, Input Crystal oscillator interface. XTAL_IN is the input. 7 XTAL_OUT XTAL_OUT is the output. 10, 13, 18 Voc Power Positive supply pins. 11, 12 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 16, 17 nQi, Q1 Output Differential clock outputs. LVPECL interface levels. 19, 20 n@o, QO Output Differential clock outputs. LVPECL interface levels. NOTE: Pulfup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TaBLe 2. Pin CHARACTERISTICS Symbol Parameter Test Conditions Minimum | Typical | Maximum | Units Cy Input Capacitance 4 pF Reuttue Input Pullup Resistor 51 kQ Reupown | [Input Pulldown Resistor 51 kQ IDT/1ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 2essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TaB_Le 3A. Controt INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK Disabled; LOW Disabled; HIGH 0 1 XTAL_IN, XTAL_OUT Disabled; LOW Disabled; HIGH 1 0 CLK Enabled Enabled 1 1 XTAL_IN, XTAL_OUT Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B. Disabled Enabled CLK CLK_EN \ x, / nQ0:nQ3 AY coos __ A __A__} ~ X__X Figure 1. CLK_EN Timinc Diacram TaB_e 3B. Ciock INnpuT FUNCTION TABLE Inputs Outputs CLK Q0:Q3 nQ0:nQ3 0 LOW HIGH 1 HIGH LOW IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 3essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER Asso_ute Maximum Ratincs Supply Voltage, V, 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, V, 0.5V toV,,+0.5V Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional Outputs, lo operation of product at these conditions or any conditions be- Continuous Current SOmA yond those listed in the DC Characteristics or AC Character- Surge Current 100mA ges oo. : . 3 istics is not implied. Exposure to absolute maximum rating Package Thermal Impedance, 6, 73.2C/W (0 Ifpm) conditions for extended periods may affect product reliability. Storage Temperature, T,,, -65C to 150C Taste 4A. Power Suppty DC Cuaractenistics, V.,,= 3.3V45%, Ta = 0C To 70C 4 Symbol | Parameter Test Conditions Minimum | Typical | Maximum | Units Voc Power Supply Voltage 3.135 3.3 3.465 Vv lee Power Supply Current 60 mA TasLe 4B. LVCMOS / LVTTL DC Cuarnactenristics, V_,, = 3.3V45%, Ta = 0C to 70C Symbol Parameter Test Conditions Minimum | Typical | Maximum | Units Vi Input High Voltage 2 Voge + 0.3V Vv Vi Input Low Voltage -0.3 0.8 Vv CLK , V, = Vo. = 3-465V 150 A lin Input High Current | CLK_SEL nus r CLK_EN Vin = Veg = 3-465V 5 yA CLK , V,, = OV, V,,. = 3.465V -5 A I Input Low Current | CLK_SEL N o r CLK_EN Vin = OV, V,, = 3.465V -150 yA Tape 4C. LVPECL DC Cnaractenistics, V_,. = 3.3V+5%, Ta = 0C To 70C Symbol | Parameter Test Conditions Minimum | Typical Maximum | Units Vou Output High Voltage; NOTE 1 Voc 7 1-4 Voc - 0-9 Vv Vo. Output Low Voltage; NOTE 1 Vog 2.0 Vog 71-7 Vv Vewing | Peak-to-Peak Output Voltage Swing 0.6 1.0 Vv NOTE 1: Outputs terminated with 500 to V,, - 2V. IDT / ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TaBLe 5. Crystal CHARACTERISTICS Parameter Test Conditions Minimum | Typical Maximum] Units Mode of Oscillation Fundamental Frequency 12 40 MHz Equivalent Series Resistance (ESR) 50 Q Shunt Capacitance 7 pF Drive Level 1 mw Tape 6. AC CuaracteristIcs, V,,. = 3.3V+5%, Ta = 0C To 70C Symbol | Parameter Test Conditions Minimum | Typical | Maximum | Units farax Output Frequency 266 MHz 1 a Propagation Delay; NOTE 1 1.45 1.65 ns a: . 155.52MHz, ft Teter to Adctve Phas iter Secon | Integration Range: 0.057 ps tsk(o) Output Skew; NOTE 2, 4 30 ps tsk(pp) | Part-to-Part Skew; NOTE 3, 4 200 ps t/t, Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 46 54 % All parameters measured at f < 266MHz unless noted otherwise. NOTE 1: Measured from the V_,/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 5essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ApopitivE PHASE JITTER The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we geta better understanding of its effects on the desired application over the entire time record of the signal. Itis mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Puase Noise dBe/Hz Additive Phase Jitter, RMS @ 155.52MHz (12kHz to 20MHz) =0.057ps typical 1k 10k 100k 1M 10M 100M OrrseT From CarricR Frequency (Hz) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 6 ICS8535-31essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION -1.3V + 0.165V 3.3V Output Loap AC Test Circuit I >! tsk(o) Output SKEw | Voc CLK ; 2 l nQO:nQ3 l Q0:Q3 x xX > <b PROPAGATION DELAY I f 80% 80% N { 1 ; Vswine Clock 20%/ \ K20% | Outputs ty boy <tr te le Output Rise/Face Time nQO:nQ3 Q0:Q3 7 Pulse Width tperion >! t ode = aw teerion Output Duty Cycie/PuLtse WiptH/PEeriop IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION TERMINATION FOR LVPECL Outputs The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive Figure 2A. LVPECL Output TERMINATION 500 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 2B. LVPECL Output TERMINATION CRYSTAL INPUT INTERFACE The ICS8535-31 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using an 18pF parallel reso- nant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel reso- nant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts. LL C1 TL ie xi Go 18pF Parallel Crystal LL C2 22p XTAL_IN XTAL_OUT Figure 3. Crystat Input INTERFACE IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER 8 ICS8535-31essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER Power CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8535-31. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the |CS8535-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V_,.= 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. *| = 3.465V * 60mA = 207.9mW CC_MAX EE_MAX e Power (outputs),,,,, = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW e Power (core)... = V, Total Power ,,,, (3.465V, with all outputs switching) = 207.9mW + 120mW = 327.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = ,, * Pd_total + T, Tj = Junction Temperature 6, = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T, = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance 6,, must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.328W * 66.6C/W = 92C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TaBLe 7. THERMAL RESISTANCE @,, FOR 20-PiIn TSSOP, Forcep ConvecTION 6, by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 9essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Q1 Figure 4. LVPECL Driver Circuit AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Q load, and a termination voltage of V_ - 2V. cc For logic high, V,,. = Vou Max = Voc max -0.9V (V -V )=0.9V CC_MAX OH_MAX Forlogic low, V,. = Vo wax = Voc wax 1.7V (V -V )=1.7V CC_MAX OL_MAX Pd_H is power dissipation when the output drives high. Pd_Lis the power dissipation when the output drives low. Pd_H = [(V -(V )= OH_MAX CC_MAX - 2V)V/R 1 * (V, [(2V - 0.9V)/50Q] * 0.9V = 19.8mW CC_MAX OH_MAX V )=12V- VV )R1* WV, -V MAX OH_MAX CC_MAX OH_MAX Pd_L=[(V -(V )= OL_MAX CC_MAX [(2V - 1.7V)/50Q] * 1.7V = 10.2mW - 2v)VR 1 * (V -V CC_MAX OL_MAX )= [eV - Vio -V RI *(V -V MAX OL_MAX CC_MAX OL_MAX Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 10essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TaBLe 8. 9 avs: Air FLow Tas_e For 20 Leap TSSOP 8, by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR CouNT The transistor count for |CS8535-31 is: 428 IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 11essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER PackaGeE OutTLine - G Surrix For 20 Leap TSSOP 1GpeD A! = , lL. _ seane b PLANE joj aaa] C | TaBLe 9. PackaGe DIMENSIONS SYMBOL Millimeters MIN MAX N 20 -- 1.20 Al 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC 0.45 0.75 a 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 12essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TaBLe 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging | Temperature ICS8535AG-31 ICS8535AG-31 20 lead TSSOP tube 0C to 70C ICS8535AG-31T ICS8535AG-31 20 lead TSSOP 2500 tape & reel 0C to 70C ICS8535AG-31LF ICS8535AG31L 20 lead "Lead-Free" TSSOP tube 0C to 70C ICS8535AG-31LFT ICS8535AG31L 20 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Parts that are ordered with an LF suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT/ ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 13essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page Description of Change Date 1 Features Section - corrected Part-to-Part Skew bullet from 100ps max. to B 200ps max. 4/29/05 T6 5 AC Characteristics Table - corrected Part-to-Part Skew from 100ps max. to 200ps max. IDT/ICS LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ICS8535-31 14essTsi LA LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support clockhelp@idt.com 408-284-8200 @)IDT www.|IDT.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 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