an Advance Data Sheet, Rev. 5 microelectronics group November 1997 Lucent Technologies Bell Labs Innovations USS-820 USB Device Controller Features Description u Full compliance with the Universal Serial Bus Specification Revision 1.0 for bus-powered devices = Supports control, interrupt, bulk, and isochronous endpoints = USB device controller with protocol control and administration for up to 16 USB endpoints a On-chip PLL allows operation at 12 Mbits/s s On-chip crystal oscillator a Integrated full-speed USB transceivers a 5 V tolerant I/O buffers allow operation in3 V or5V system environment a Implemented in Lucent Technologies Microelec- tronics Groups 0.35 um, 3 V standard-cell library = 44-pin MQFP Applications w Suitable for peripherals with embedded micropro- cessors a Glueless interface to microprocessor buses Support of multifuriction USB implementations, such as printer/scanner and integrated multimedia applications a Suitable for a broad range of device class peripher- als in the USB standard USS-820 is a USB device controller that provides a programmable bridge between the USB and a local microprocessor bus. It allows PC peripherals to upgrade to USB connectivity without major redesign effort. It is programmable through a simple read/write register interface that is compatible with industry- standard USB microcontrollers. USS-820 is designed in 100% compliance with the USB industry standard, allowing device-side USB products to be reliably installed using low-cost, off-the-shelf cables and con- nectors. The integrated USB transceiver supports 12 Mbits/s full-speed operation. FIFO options support all four transfer types: control, interrupt, bulk, and isochro- nous, as described in USB Specification Revision 7.0, with a wide range of packet sizes. Its double sets of FIFO allow back-to-back transfer to reduce latency. FIFO sizes are programmable through control regis- ter settings. The sizes supported are 16 bytes and 64 bytes for nonisochronous pipes and 64 bytes, 256 bytes, and 512 bytes for isochronous pipes. This covers a wide range of data rates, data types, and combinations of applications. USS-820s FIFO con- trol manager (FCM) handles the data flow between the FIFOs and the device controller. It handles flow control and error handling/fault recovery to monitor transaction status and to relay control events via interrupt vectors. The USS-820 is available in a 44-pin MQFP. USS- 820 supports a maximum of eight bidirectional end- points with 16 FIFOs (eight for transmit and eight for receive) associated with them. The FIFOs are on- chip, and sizes are programmable up to a total of 1 Kbyte. The USS-820 can be clocked either by connecting a 42 MHz crystal to the XTAL1 and XTAL2 pins, or by using a 12 MHz external oscillator. The internal 12 MHz clock period, which is a function of either of these clock sources, is referred to as the system clock period (tCLK) throughout this data sheet. Note: Advisories are issued as needed to update product information. When using this data sheet for design purpeses, please contact your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.USS-820 Advance Data Sheet, Rev. 5 USB Device Controller November 1997 Table of Contents Contents Page FOAtUreS ooo... eee cece cee seeeeeecenseeenaaeecaneenesasaepessaaeesassaeecesnenaecsneeessseaeaessasssaesaesecauasescessauaeeceeessuacassueeecenseeseneeavenes 1 APPliCations ooo... ee cee ese eeseeeseereeceeeee ase suaaensseseaeevsssenesseeseceessaceseeresesecaeesecaeeseesuensesssseseeeaesaeaaeessueccssserseesenpecsanenees 1 DO@SCTIDTION .........cccceceeeceeeseeceeneeeesnecesenenenecscsanceeeceessnceeeeeeescesuaueeesesaessaeceeeaeeseessaseeeseeeseeasesseesusceusnsnssssetersesscsrserenseaneees 1 Serial Interface Engine 20.2... cece seeeseneceessesesseceeseeeceeerenseseeesseesensescsassuessesseeecsssesanenasececeesaaeaeesesaueenseseesaaneseesensees 3 Protocol LAYER oo... cee cece cece seen eeenaneeeeseeeensneeeenaenecessaaeeetedaeeraeeeseesceesqenesesssseenessssuneseeseneeesccsaaeeeesssesestsesensaess 3 FEFO oie. cccceseecseneeceneecsnceescececsceseaseecencenescecessaeaecseacersneaceceseacenssaaseasenaeeecsauesecesusaecessaesseceseatnesecesaeeceesseeseetesensees 3 FIFO ACCESS oo... ecsecsccerecerencerssacesessneeeccueececeaeeaeessacesessaeeessaeecsceneaessrsaeeecsneeseaeneesesauseaeeecesseeauensenesesaescauaeaees 3 TRANSMIt FIFO oo... ceccecsccececeeseecesseeaeeesncessnececscateeeecuseesessesseauesssaaseeesaaeeesvessssaesaeesessssuaaeeneceseaeassaescaeseeseseeeces 4 RECEIVE FIFO oo. eeesecceeserssceeessatecensesessuneeseaeeesecseseessseeeaesasesssnneeteseeeeseseseseeasscesacansseeesssseguesesceseneeecsnaeees 5 Pir INFOPMALION 22... eee eee eececeeeeeececoneneeeeeesesaaneecesenanececenessenseceneesssaeetessesaanueeaesasaenseseseeecacsussueaaeseceeesesesuaaseeseeesseeeeeesas 6 Register Timing Characteristics 0.0... cece eceseeseeneesceessccesereessneceanensseesesseseseessaneaesseeceuceseneneeseesereeeseetseneeseeeeees 8 Register Interface oo... eee cece seeeeeseeeeaaeesseseanecsaeeeesneessnsnenesecacecaaesnaueasesnesscesesseseegaessneeesseneeeasaeeseeeeseeeseneeeeeeeses 10 Firmware Responsibilities for USB SETUP Commands .......0... ec cccccccescceecesceeeeesceeeeecsaseaeessensesesesasecenseatersteeees 31 Other Firmware Responsibilities 200.0... eee ccsereccssceneeesssaeeeceacersececaccseeeesessceeesenaeeeeecseeeeesagcecseeeseaseeesnseesesteeees 32 Suspend and Resume Behavior ..........ecccccscesesesseecessneeenecessaeeeseeseneessaeesecseesaeacsaeeeseeeaseseeescgeuseceeecesseseneeesnreseseeesaees 33 Application Notes ............:cccccccssecesccescecreneeecenseeseeensscnsaaeeessenaeeessaeensnaceeesenseececeacensenaeeeessanenesequuaeearecensesesseneteneeeeeaes 34 Absolute Maximum RattingS 0.0.0.0... cecesescceeecsssnceceersceseeseceesnesenenesesenaaneneesecsaneneesesenenesneaeaaeseeeseseesasaaeeeessaaenteteaeas 35 Electrical Characteristics ............ceessceeceesscnenceeseseneeeeceesessnauaeaceesenneeeercnecsucenenesacecaueeaeeseesusedeqenneeersseseceueneneeasensenes 35 AC Characteristics 00.0... eccceeseeeeecesecccenersecuceeeerssccneseeeeeaesenseeeveccecseaeeseresduceueeseataeseensanaeneaeeeeeeseaeaaeeeseneeneetesees 35 Power Considerations oo... eccccceescecececeesereeeeeceseuneneeeecsncceenecereusceeeaeereceaaaeeesessananeeaeeeeeeeeeeeeuensaaeeteessentetsensaees 35 USB Transceiver Driver CNaracteristics oe. eee ecceseeecceseeonecenerreceaeeeeeeeseneaeeseeeescaucneeeseceseecenseeneteeeeseaateersneas 36 Connection REQUIFEMeMtS .........c eee eeeeccsecccececenereececeseeteseseccnnscaaaeeasecaceeaaeeeceeeoneeeeetecesteeeeceeeseeeesseeeseceeeteneavensanaes 36 USB Transceiver Connection .......ceeccccceesececeeeceseeceececeecenseneceessesceeeeeeeesneeasecenecusuanenanaaeeaeeassensensaeeceesacenteserenes 36 Oscillator Connection Require MentS ..........cccccccececceecceeeceeesneeacneasneceeaceeeeeeeeeeeeceseeenenscesageesecaaseeeseeseneererseseeneas 37 CO TU alam B)rc\ | c= 11 | Rene r neon TEESEE EEE TEEEDEETEODONTEEOESOSTLOO TSS SOSOELEOSSEOSSSOOOTELOSSEOSSSSLODSSOOSOESESSSSOSVESOSSSSOSOSSLSSEGEOESTETSSSOOSSEOTOSEOSSSES 38 AA-Pin MQEP ou. ecccceseescessceseecseeessseeseceesacenanesesaeescesteneeansceuaceeseaeceesaesauecsnseesaeceecneeseseeeseadeseneeseaaessessnaeeeaes 38 2 Lucent Technologies Inc.Advance Data Sheet, Rev. 5 November 1997 USS-820 USB Device Controller Description (continued) lH USS-820 PLL }-{ OSCILLATOR | DPLS +} = DMNS FIFO USB DIGITAL PROTOCOL > Vss -~ XCVR PLL SIE LAYER CONTROL Vop EXTERNAL + MICROPROCESSOR BUS FIFOs 5-4965.a.r4 Figure 1. Block Diagram Serial Interface Engine Table 1. Programmable FIFO Sizes The SIE is the USB protocol interpreter. {t serves as a FFS2[1:0] 00 01 10 communicator between the device controller and the Non-ISO 16 bytes 64 bytes 64 bytes host through the USB lines. The SIE functions include: ISO 64 bytes | 256 bytes | 512 bytes m Package protocol sequencing a SOP (start of packet), EOP (end of packet), RESUME, and RESET signal detection and genera- tion a NRZI data encoding/decoding and bit stuffing a CRC generation and checking for token and data = Serial-to-paraliel and parallel-to-serial data conver- sion Protocol Layer The protocol layer manages the interface between the SIE and FIFO control blocks. It passes all USB OUT and SETUP packets through to the appropriate FIFO. It is the responsibility of firmware to correctly interpret and execute each USB SETUP Command (as docu- mented in the Firmware Responsibilities for USB SETUP Commands section), via the register interface. The protocol layer tracks the setup, data, and status stages of control transfers. FIFO Table 1 shows the programmable FIFO sizes. Lucent Technologies Inc. Each FIFO can be programmed independently, but the total size (TX FIFOs + RX FIFOs) must not exceed 1 Kbyte. FIFO Access The transmit and receive FIFOs are accessed by the application through the register interface (see Tables 19-22 for transmit FIFO registers and Tables 2326 for receive FIFO registers). The transmit FIFO is written to via the TXDAT register, and the receive FIFO is read via the RXDAT register. The par- ticular transmit/receive FIFO is specified by the EPIN- DEX register. Each FIFO is accessed serially, and each RXDAT read increments the receive FIFO read pointer by 1, and each TXDAT write increments the transmit FIFO write pointer by 1. Each FIFO consists of two data sets to provide the capability for simultaneous read/write access. Control of these pairs of data sets is managed by the hardware, and is invisible to the application, although the applica- tion must be aware of the implications. The receive FIFO read access is advanced to the next data set by setting the RXFFRC bit of RXCON. This bit clears itself after the advance is complete. The transmit FIFO write access is advanced to the next data set by writing the byte count to the TXCNTH/L registers.USS-820 USB Device Controller Advance Data Sheet, Rev. 5 November 1997 Description (continued) The USB access to the receive and transmit FIFOs is managed by the hardware, although the control of the data sets can be overridden by the ARM and ATM bits of RXCON and TXCON, respectively. A successful USB transaction causes FIFO access to be advanced to the next data set. A failed USB transaction (e.g., for receive operations, FIFO overrun, data time-out, CRC error, bit stuff error; for transmit operations, FIFO underrun, no ACK from host) causes the FIFO read/ write pointer to be reversed to the beginning of the data set to allow transmission retry for nonisochronous transfers. Transmit FIFO The transmit FIFOs are circulating data buffers that have the following features: = Support up to two separate data sets of variable sizes a Include byte counter register for storing the number of bytes in the data sets w Protect against overwriting data in a full FIFO a Can retransmit the current data set All transmit FIFOs use the same architecture (see Figure 2). The transmit FIFO and its associated logic can manage up to two data sets, data set O (dsO) and data set 1 (ds1). Since two data sets can be used in the FIFO, back-to-back transmissions are supported. The CPU writes to the FIFO location that is specified by the write pointer. After a write, the write pointer auto- matically increments by 1. The read marker points to the first byte of data written to a data set, and the read pointer points to the next FIFO location to be read by the function interface. After a read, the read pointer automatically increments by 1. When a good transmission is completed, the read marker can be advanced to the position of the read pointer to set up for reading the next data sei. When a bad transmission is completed, the read pointer can be reversed to the position of the read marker to enable the function interface to reread the last data set for retransmission. The read marker advance and read pointer reversal can be achieved two ways: explicitly by firmware or automatically by hardware, as indicated by bits in the transmit FIFO control register (TXCON). WRITES TO FIFO WRITE POINTER > CPU ; SIE READS FIFO + READ POINTER DATA SET 1 TXDAT BYTE COUNT | REGISTERS DATA SET 0 TXCNTH TXCNTL [ TO USBINTERFACE > A REVRP ADVRM READ MARKER $-5206.r1 Figure 2. Transmit FIFO Lucent Technologies Inc.Advance Data Sheet, Rev. 5 November 1997 USS-820 USB Device Controller Description (continued) Receive FIFO The receive FIFOs are circulating data buffers that have the following features: m= Support up to two separate data sets of variable sizes a Include byte count register that accesses the number of bytes in data sets a Include flags to signal a full FIFO and an empty FIFO a Can rereceive the last data set Figure 3 shows a receive FIFO. A receive FIFO and its associated logic can manage up to two data sets, data set 0 (DSO) and data set 1 (ds1). Since two data sets can be used in the FIFO, back-to-back transmissions are supported. The receive FIFO is symmetrical to the transmit FIFO in many ways. The SIE writes to the FIFO location speci- fied by the write pointer. After a write, the write pointer automatically increments by 1. The write marker points to the first byte of data written to a data set, and the read pointer points to the next FIFO location to be read by the CPU. After a read, the read pointer automati- cally increments by 1. When a good reception is completed, the write marker can be advanced to the position of the write pointer to set up for writing the next data set. When a bad trans- mission is completed, the write pointer can be reversed to the position of the write marker to enable the SIE to rewrite the last data set after receiving the data again. The write marker advance and write pointer reversal can be achieved two ways: explicitly by firmware or automatically by hardware, as specified by bits in the receive FIFO control register (RXCON). The CPU should not read data from the receive FIFO before all bytes are received and successfully acknowl- edged, because the reception may be bad. To avoid overwriting data in the receive FIFO, the SIE can monitor the FIFO full flag (RXFULL bit in RXFLG). To avoid reading a byte when the FIFO is empty, the CPU can monitor the FIFO empty flag (RXEMP bit in RXFLG). SIE WRITES TO FIFO < WRITE POINTER FROM USB INTERFACE RXDAT I A DATA SET 1 READ POINTER > << WRITE MARKER CPU READS FIFO BYTE COUNT DATA SET 0 REGISTERS RXCNTH RXCNTL 5-5207.14 Figure 3. Receive FIFO Lucent Technologies Inc.