MC100LVELT22 3.3VDual LVTTL/LVCMOS to Differential LVPECL Translator The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal. * * * * * * http://onsemi.com MARKING DIAGRAMS* 8 SO-8 D SUFFIX CASE 751 350 ps Typical Propagation Delay <100 ps Output-to-Output Skew 8 KVT22 ALYW 1 Flow Through Pinouts 1 8 The 100 Series Contains Temperature Compensation LVPECL Operating Range: VCC = 3.0 V to 3.8 V with GND = 0 V When Unused TTL Input is left Open, Q Output will Default High KR22 ALYW TSSOP-8 DT SUFFIX CASE 948R 8 1 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, see Application Note AND8002/D. ORDERING INFORMATION Device MC100LVELT22D MC100LVELT22DR2 MC100LVELT22DT Package Shipping** SO-8 98 Units/Rail SO-8 2500 Units/Reel TSSOP-8 98 Units/Rail MC100LVELT22DTR2 TSSOP-8 2500 Units/Reel **For additional tape and reel information, see Brochure BRD8011/D. Semiconductor Components Industries, LLC, 2003 March, 2003 - Rev. 2 1 Publication Order Number: MC100LVELT22/D MC100LVELT22 Q0 1 8 VCC Q0 7 D0 2 LVTTL/ LVCMOS LVPECL Q1 3 6 D1 Q1 4 5 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram PIN DESCRIPTION PIN FUNCTION Qn, Qn D0, D1 VCC GND LVPECL Differential Outputs LVTTL/LVCMOS Inputs Positive Supply Ground ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V Level 1 UL 94 V-0 @ 0.125 in 164 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVELT22 MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units 7 V 7 V 50 100 mA mA -40 to +85 C VCC Positive Power Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range -65 to +150 C JA Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM SO-8 SO-8 190 130 C/W C/W JC Thermal Resistance (Junction-to-Case) std bd SO-8 41 to 44 5% C/W JA Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM TSSOP-8 TSSOP-8 185 140 C/W C/W JC Thermal Resistance (Junction-to-Case) std bd TSSOP-8 41 to 44 5% C/W Tsol Wave Solder <2 to 3 sec @ 248C 265 C VI VCC 2. Maximum Ratings are those values beyond which device damage may occur. LVPECL DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 3) -40 C Symbol Characteristic Min Typ 25C Max Min 85C Typ Max 28 Min Typ Max Unit 29 mA ICC Power Supply Current 28 VOH Output HIGH Voltage (Note 4) 2275 2420 2275 2420 2275 2420 mV VOL Output LOW Voltage (Note 4) 1490 1680 1490 1680 1490 1680 mV NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. Output parameters vary 1:1 with VCC. VCC can vary 0.15 V. 4. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. LVTTL/LVCMOS INPUT DC CHARACTERISTICS VCC = 3.3 V; TA = -40C to 85C (Note 5) Symbol Characteristic Min Typ Max Unit Condition IIH Input HIGH Current 20 A VIN = 2.7 V IIHH Input HIGH Current 100 A VIN = VCC IIL Input LOW Current -0.2 mA VIN = 0.5 V -1.2 V VIK VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 IIN = -18 mA V 0.8 V 5. VCC can vary 0.15 V. AC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 6) -40 C Symbol Characteristic fmax Maximum Toggle Frequency t PLH Propagation Delay (Note 7) skew Skew t tJITTER t /t r f Min Typ 25C Max Min Max Min Typ Max 350 200 Output-to-Output Part-to-Part 350 600 30 100 400 200 Random Clock Jitter (RMS) Output Rise/Fall Time (20-80%) Typ 85C MHz 350 600 30 100 400 200 350 600 ps 30 100 400 ps 1.6 200 550 6. VCC can vary 0.15 V. 7. Specifications for standard TTL input signal. http://onsemi.com 3 200 Unit ps 500 200 500 ps MC100LVELT22 Q D Receiver Device Driver Device Q D 50 50 VTT VTT = VCC - 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels AN1405 - ECL Clock Distribution Techniques AN1406 - Designing with PECL (ECL at +5.0 V) AN1503 - ECLinPS I/O SPICE Modeling Kit AN1504 - Metastability and the ECLinPS Family AN1560 - Low Voltage ECLinPS SPICE Modeling Kit AN1568 - Interfacing Between LVDS and ECL AN1596 - ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 - Using Wire-OR Ties in ECLinPS Designs AN1672 - The ECL Translator Guide AND8001 - Odd Number Counters Design AND8002 - Marking and Date Codes AND8020 - Termination of ECL Logic Devices AND8090 - AC Characteristics of ECL Devices http://onsemi.com 4 MC100LVELT22 PACKAGE DIMENSIONS SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 A 8 5 0.25 (0.010) S B 1 M Y M 4 K -YG C N X 45 SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 5 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC100LVELT22 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 5 0.25 (0.010) B -U- L 0.15 (0.006) T U M M 4 A -V- F DETAIL E C 0.10 (0.004) -T- SEATING PLANE D -WG DETAIL E DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0 6 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0 6 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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