Data Sheet, V1.4, March 2007
Microcontrollers
XC164CM
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Edition 2007-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
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Infineon Technologies components may be used in life-support devices or systems only with the express written
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Data Sheet, V1.4, March 2007
Microcontrollers
XC164CM
16-Bit Single-Chip Microcontroller
with C166SV2 Core
XC164CM
Derivatives
Data Sheet V1.4, 2007-03
XC164CM
Revision History: V1.4, 2007-03
Previous Version(s):
V1.3, 2006-08
V1.2, 2006-03
V1.1, 2005-11 (intermediate version)
V1.0, 2005-05
Page Subjects (major changes since last revision)
6Design steps of the derivatives differentiated.
53 Power consumption of the derivatives differentiated.
54 Figure 11 adapted.
55 Figure 13 adapted.
65 Packages of the derivatives differentiated.
66 Thermal resistances of the derivatives differentiated.
all “Preliminary” removed
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XC164CM
Derivatives
Table of Contents
Data Sheet 3 V1.4, 2007-03
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6 The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.9 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 37
3.11 High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 38
3.12 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.13 LXBus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.16 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.17 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4.2 On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.3 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table of Contents
XC164CM16-Bit Single-Chip Microcontroller with C166SV2 Core
XC166 Family
Data Sheet 4 V1.4, 2007-03
1 Summary of Features
For a quick overview or reference, the XC164CM’s properties are listed here in a
condensed way.
• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 0/2/4 Kbytes1) On-Chip Data SRAM (DSRAM)
– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 32/64/1281) Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
– 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and
Conversion Time (down to 2.55 μs or 2.15 μs)
– 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– On-Chip Real Time Clock, Driven by the Main Oscillator
1) Depends on the respective derivative. See Table 1 “XC164CM Derivative Synopsis” on Page 6.
XC164CM
Derivatives
Summary of Features
Data Sheet 5 V1.4, 2007-03
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 47 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• On-Chip Debug Support via JTAG Interface
• 64-Pin Green LQFP Package for the -16F derivatives, 0.5 mm (19.7 mil) pitch (RoHS
compliant)
• 64-Pin TQFP Package for the -4F/8F derivatives, 0.5 mm (19.7 mil) pitch (RoHS
compliant)
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the XC164CM please refer to your responsible sales
representative or your local distributor.
This document describes several derivatives of the XC164CM group. Table 1
enumerates these derivatives and summarizes the differences. As this document refers
to all of these derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC164CM throughout this
document.
XC164CM
Derivatives
Summary of Features
Data Sheet 6 V1.4, 2007-03
Table 1 XC164CM Derivative Synopsis
Derivative1)
1) This Data Sheet is valid for:
devices starting with and including design step BA for the -16F derivatives, and for
devices starting with and including design step AA for -4F/8F derivatives.
Temp.
Range
Program
Memory
On-Chip RAM Interfaces
SAK-XC164CM-16F40F
SAK-XC164CM-16F20F
-40 to
125 °C
128 Kbytes
Flash
2 Kbytes DPRAM,
4 Kbytes DSRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
SAF-XC164CM-16F40F
SAF-XC164CM-16F20F
-40 to
85 °C
128 Kbytes
Flash
2 Kbytes DPRAM,
4 Kbytes DSRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
SAK-XC164CM-8F40F
SAK-XC164CM-8F20F
-40 to
125 °C
64 Kbytes
Flash
2 Kbytes DPRAM,
2 Kbytes DSRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
SAF-XC164CM-8F40F
SAF-XC164CM-8F20F
-40 to
85 °C
64 Kbytes
Flash
2 Kbytes DPRAM,
2 Kbytes DSRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
SAK-XC164CM-4F40F
SAK-XC164CM-4F20F
-40 to
125 °C
32 Kbytes
Flash
2 Kbytes DPRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
SAF-XC164CM-4F40F
SAF-XC164CM-4F20F
-40 to
85 °C
32 Kbytes
Flash
2 Kbytes DPRAM,
2 Kbytes PSRAM
ASC0, ASC1,
SSC0, SSC1,
CAN0, CAN1
XC164CM
Derivatives
General Device Information
Data Sheet 7 V1.4, 2007-03
2 General Device Information
The XC164CM derivatives are high-performance members of the Infineon
XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend
the functionality and performance of the C166 Family in terms of instructions (MAC unit),
peripherals, and speed. They combine high CPU performance (up to 40 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
They also provide clock generation via PLL and various on-chip memory modules such
as program Flash, program RAM, and data RAM.
Figure 1 Logic Symbol
MCA05554_XC164CM
XC164CM
XTAL1
XTAL2
NMI
RSTIN
Port 5
14 bit
PORT1
14 bit
Port 3
13 bit
Port 9
6 bit
VAGND
VAREF VDDI/P
VSS
TRST
XC164CM
Derivatives
General Device Information
Data Sheet 8 V1.4, 2007-03
2.1 Pin Configuration and Definition
The pins of the XC164CM are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E* marks pins to be used as alternate external interrupt
inputs.
Figure 2 Pin Configuration (top view)
mc_xc164cm_pinout.vsd
P1L.0/CC60
49505152535455565758596061626364
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32313029282726252423222120191817
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
AR EF
P5.0/AN0
V
SS
P5. 6/A N6
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
P3.1/T6OUT/RxD1/TCK/E*
P3.2/CAPIN/TDI
P3.3/T3OUT/TDO
P3.4/T3EUD/TMS
P3.8/MRST0
P3.9/MTSR0
P3.10/TxD0/E*
P3.11/RxD0/E*
P3.13/SCLK0/E*
V
DDP
V
SS
P3.15/CLKOUT/FOUT
P9.0/CC16IO/CAN2_RxD/E
*
P1H.0/CC6POS0/EX0IN/CC23IO
P1H.1/CC6POS1/EX1IN/MRST1
P1H.2/CC6POS2/EX2IN/MTRS1
P1H.3/EX3IN/T7IN/SCLK1
P3.7/T2IN/BRKIN
P1L.1/COUT60
P1L.2/CC61
P1H.4/CC24IO/EX4IN
P1H.5/CC
25IO/EX5IN
P1L.7/CTRAP/CC22IO
V
DDP
V
DDI
V
SS
TRST
RSTIN
NMI
XTA L 1
XTA L 2
V
DDP
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5. 7/A N7
V
AGND
V
SS
V
DDI
V
DDP
P3.5/T4IN/TxD1/BRKOUT
P3.6/T3IN
P9.1/CC17IO/CAN2_TxD
P9.2/CC18IO/CAN1_RxD/E
*
P9.3/CC19IO/CAN1_TxD
P9.4/CC20IO
P9.5/CC21IO
P1L.3/COUT61
P1L.4/CC62
P1L.5/COUT62
P1L.6/COUT63
XC164CM
XC164CM
Derivatives
General Device Information
Data Sheet 9 V1.4, 2007-03
Table 2 Pin Definitions and Functions
Sym-
bol
Pin
Num.
Input
Outp.
Function
RSTIN 63 I Reset Input with Schmitt-Trigger characteristics. A low-level
at this pin while the oscillator is running resets the XC164CM.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
hardware configuration signals settle.
External circuitry must guarantee low-level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
NMI 64 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164CM into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Port 9
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
43-48
43
44
45
46
47
48
IO
I/O
I
I
I/O
O
I/O
I
I
I/O
O
I/O
I/O
Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance state)
or output (configurable as push/pull or open drain driver). The
input threshold of Port 9 is selectable (standard or special).
The following Port 9 pins also serve for alternate functions:
CC16IO: (CAPCOM2) CC16 Capture Inp./Compare Outp.,
CAN2_RxD: (CAN Node 2) Receive Data Input1),
EX5IN: (Fast External Interrupt 5) Input (alternate pin A)
CC17IO: (CAPCOM2) CC17 Capture Inp./Compare Outp.,
CAN2_TxD: (CAN Node 2) Transmit Data Output,
CC18IO: (CAPCOM2) CC18 Capture Inp./Compare Outp.,
CAN1_RxD: (CAN Node 1) Receive Data Input1),
EX4IN: (Fast External Interrupt 4) Input (alternate pin A)
CC19IO: (CAPCOM2) CC19 Capture Inp./Compare Outp.,
CAN1_TxD: (CAN Node 1) Transmit Data Output,
CC20IO: (CAPCOM2) CC20 Capture Inp./Compare Outp.
CC21IO: (CAPCOM2) CC21 Capture Inp./Compare Outp.
Note: At the end of an external reset P9.4 and P9.5 also may
input startup configuration values.
XC164CM
Derivatives
General Device Information
Data Sheet 10 V1.4, 2007-03
Port 5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15
9-18,
21-24
9
10
11
12
13
14
15
16
17
18
21
22
23
24
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 5 is a 14-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN10 (T6EUD): GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11 (T5EUD): GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN6
AN7
AN12 (T6IN): GPT2 Timer T6 Count/Gate Input
AN13 (T5IN): GPT2 Timer T5 Count/Gate Input
AN14 (T4EUD): GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15 (T2EUD): GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
TRST 62 I Test-System Reset Input. For normal system operation, pin
TRST should be held low. A high level at this pin at the rising
edge of RSTIN enables the hardware configuration and
activates the XC164CM’s debug system. In this case, pin
TRST must be driven low once to reset the debug system.
Table 2 Pin Definitions and Functions (cont’d)
Sym-
bol
Pin
Num.
Input
Outp.
Function
XC164CM
Derivatives
General Device Information
Data Sheet 11 V1.4, 2007-03
Port 3
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.13
P3.15
28-39,
42
28
29
30
31
32
33
34
35
36
37
38
39
42
IO
O
I/O
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I/O
I/O
O
I
I/O
I
I/O
I
O
O
Port 3 is a 13-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance state)
or output (configurable as push/pull or open drain driver). The
input threshold of Port 3 is selectable (standard or
special).The following Port 3 pins also serve for alternate
functions:
T6OUT: [GPT2] Timer T6 Toggle Latch Output,
RxD1: [ASC1] Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN: [Fast External Interrupt 1] Input (alternate pin A),
TCK: [Debug System] JTAG Clock Input
CAPIN: [GPT2] Register CAPREL Capture Input,
TDI: [Debug System] JTAG Data In
T3OUT: [GPT1] Timer T3 Toggle Latch Output,
TDO: [Debug System] JTAG Data Out
T3EUD: [GPT1] Timer T3 External Up/Down Control Input,
TMS: [Debug System] JTAG Test Mode Selection
T4IN: [GPT1] Timer T4 Count/Gate/Reload/Capture Inp.
TxD1: [ASC0] Clock/Data Output (Async./Sync.),
BRKOUT: [Debug System] Break Out
T3IN: [GPT1] Timer T3 Count/Gate Input
T2IN: [GPT1] Timer T2 Count/Gate/Reload/Capture Inp.
BRKIN: [Debug System] Break In
MRST0: [SSC0] Master-Receive/Slave-Transmit In/Out.
MTSR0: [SSC0] Master-Transmit/Slave-Receive Out/In.
TxD0: [ASC0] Clock/Data Output (Async./Sync.),
EX2IN: [Fast External Interrupt 2] Input (alternate pin B)
RxD0: [ASC0] Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN: [Fast External Interrupt 2] Input (alternate pin A)
SCLK0: [SSC0] Master Clock Output / Slave Clock Input.,
EX3IN: [Fast External Interrupt 3] Input (alternate pin A)
CLKOUT: System Clock Output (= CPU Clock),
FOUT: Programmable Frequency Output
Table 2 Pin Definitions and Functions (cont’d)
Sym-
bol
Pin
Num.
Input
Outp.
Function
XC164CM
Derivatives
General Device Information
Data Sheet 12 V1.4, 2007-03
PORT1
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
P1H.0
P1H.1
P1H.2
P1H.3
P1H.4
P1H.5
1-6,
49-56
49
50
51
52
53
54
55
56
1
2
3
3
5
6
IO
I/O
O
I/O
O
I/O
O
O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
I/O
I
I/O
I
I/O
I
PORT1 consists of one 8-bit and one 6-bit bidirectional I/O
port P1L and P1H. Each pin can be programmed for input
(output driver in high-impedance state) or output.
The following PORT1 pins also serve for alt. functions:
CC60: [CAPCOM6] Input / Output of Channel 0
COUT60: [CAPCOM6] Output of Channel 0
CC61: [CAPCOM6] Input / Output of Channel 1
COUT61: [CAPCOM6] Output of Channel 1
CC62: [CAPCOM6] Input / Output of Channel 2
COUT62: [CAPCOM6] Output of Channel 2
COUT63: Output of 10-bit Compare Channel
CTRAP: [CAPCOM6] Trap Input CTRAP is an input pin with
an internal pull-up resistor. A low level on this pin switches the
CAPCOM6 compare outputs to the logic level defined by
software (if enabled).
CC22IO: [CAPCOM2] CC22 Capture Inp./Compare Outp.
CC6POS0: [CAPCOM6] Position 0 Input,
EX0IN: [Fast External Interrupt 0] Input (default pin),
CC23IO: [CAPCOM2] CC23 Capture Inp./Compare Outp.
CC6POS1: [CAPCOM6] Position 1 Input,
EX1IN: [Fast External Interrupt 1] Input (default pin),
MRST1: [SSC1] Master-Receive/Slave-Transmit In/Out.
CC6POS2: [CAPCOM6] Position 2 Input,
EX2IN: [Fast External Interrupt 2] Input (default pin),
MTSR1: [SSC1] Master-Transmit/Slave-Receive Out/Inp.
T7IN: [CAPCOM2] Timer T7 Count Input,
SCLK1: [SSC1] Master Clock Output / Slave Clock Input,
EX3IN: [Fast External Interrupt 3] Input (default pin),
CC24IO: [CAPCOM2] CC24 Capture Inp./Compare Outp.,
EX4IN: [Fast External Interrupt 4] Input (default pin)
CC25IO: [CAPCOM2] CC25 Capture Inp./Compare Outp.,
EX5IN: [Fast External Interrupt 5] Input (default pin)
Note: At the end of an external reset P1H.4 and P1H.5 also
may input startup configuration values
Table 2 Pin Definitions and Functions (cont’d)
Sym-
bol
Pin
Num.
Input
Outp.
Function
XC164CM
Derivatives
General Device Information
Data Sheet 13 V1.4, 2007-03
XTAL2
XTAL1
61
60
O
I
XTAL2: Output of the oscillator amplifier circuit
XTAL1: Input to the oscillator amplifier and input to the
internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.
Note: Input pin XTAL1 belongs to the core voltage domain.
Therefore, input voltages must be within the range
defined for VDDI.
VAREF 19 – Reference voltage for the A/D converter
VAGND 20 – Reference ground for the A/D converter
VDDI 26, 58 – Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Condition Parameters
VDDP 8, 27,
40, 57
– Digital Pad Supply Voltage (Pin Output Drivers):
+5 V during normal operation and idle mode.
Please refer to the Operating Condition Parameters
VSS 7, 25,
41, 59
–Digital Ground
Connect decoupling capacitors to adjacent VDD/VSS pin pairs
as close as possible to the pins.
All VSS pins must be connected to the ground-line or ground-
plane.
1) The CAN interface lines are assigned to port P9 under software control.
Table 2 Pin Definitions and Functions (cont’d)
Sym-
bol
Pin
Num.
Input
Outp.
Function
XC164CM
Derivatives
Functional Description
Data Sheet 14 V1.4, 2007-03
3 Functional Description
The architecture of the XC164CM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164CM.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164CM.
Figure 3 Block Diagram
Interrupt Bus
XTAL
Osc / PLL
Clock Generation
RTC WDT
GPT
T2
T3
T4
T5
T6
SSC0
BRGen
(SPI)
ASC1
BRGen
(USAR T)
ADC
8/10-Bit
14
C hannels
CC2
T7
T8
ProgMem
14
Port 5
PSRAM
2 Kbytes
DPRAM
2 Kbytes
DSRAM
0/2/4 Kbytes
C166SV2-Core
PMU
DMU
CPU
ASC0
BRGen
(USAR T)
SSC1
BRGen
(SPI)
Twin
CAN
A B
PORT1Port 3Port 9
14
13
6
Interrupt & PEC
Peripheral Data Bus
OCDS
Debug Support
CC6
T12
T13
reduced
EBC
LXBus
Control
32/64/128 Kbytes
mc_xc164cm_block.vsd
LXBus
Flash
XC164CM
Derivatives
Functional Description
Data Sheet 15 V1.4, 2007-03
3.1 Memory Subsystem and Organization
The memory space of the XC164CM is configured in a von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed byte wise or word wise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, or data is read from or written to peripherals on the LXBus (such as
TwinCAN). The system bus allows concurrent two-way communication for maximum
transfer performance.
32/64/128 Kbytes of on-chip Flash memory1) store code or constant data. The on-chip
Flash memory is organized as four 8-Kbyte sectors and up to three 32-Kbyte sectors.
Each sector can be separately write protected2), erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A password sequence
temporarily unlocks protected areas. The Flash module combines very fast 64-bit one-
cycle read accesses with protected and efficient writing algorithms for programming and
erasing. Thus, program execution out of the internal Flash results in maximum
performance. Dynamic error correction provides extremely high read data security for all
read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
0/2/4 Kbytes1) of on-chip Data SRAM (DSRAM) are provided as a storage for general
user data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses. DSRAM is not available in the XC164CM-4F derivatives.
1) Depends on the respective derivative. See Table 1 “XC164CM Derivative Synopsis” on Page 6.
2) Each two 8-Kbyte sectors are combined for write-protection purposes.
XC164CM
Derivatives
Functional Description
Data Sheet 16 V1.4, 2007-03
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank
can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RH0, …, RL7, RH7)
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word wide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
Table 3 XC164CM Memory Map
Address Area Start Loc. End Loc. Area Size1)
1) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
Notes
Flash register space FF’F000HFF’FFFFH4 Kbytes 2)
Reserved (Acc. trap) F8’0000HFF’FFFFH508 Kbytes –
Reserved for PSRAM E0’0800HF7’FFFFH< 1.5 Mbytes Minus PSRAM
Program SRAM E0’0000HE0’07FFH2 Kbytes –
Reserved for pr. mem. C2’0000HDF’FFFFH< 2 Mbytes Minus Flash
Program Flash C0’0000HC1’FFFFH128 Kbytes XC164CM-16F
C0’0000HC0’FFFFH64 Kbytes XC164CM-8F
C0’0000HC0’7FFFH32 Kbytes XC164CM-4F
Reserved 20’0800HBF’FFFFH< 10 Mbytes Minus TwinCAN
TwinCAN registers 20’0000H20’07FFH2 Kbytes Accessed via EBC
Reserved 01’0000H1F’FFFFH< 2 Mbytes Minus segment 0
SFR area 00’FE00H00’FFFFH0.5 Kbyte –
Dual-Port RAM 00’F600H00’FDFFH2 Kbytes –
Reserved for DPRAM 00’F200H00’F5FFH1 Kbyte –
ESFR area 00’F000H00’F1FFH0.5 Kbyte –
XSFR area 00’E000H00’EFFFH4 Kbytes –
Reserved 00’D000H00’DFFFH6 Kbytes –
Data SRAM 00’C000H00’CFFFH4 Kbytes 3)
Reserved for DSRAM 00’8000H00’BFFFH16 Kbytes –
Reserved 00’0000H00’7FFFH32 Kbytes –
XC164CM
Derivatives
Functional Description
Data Sheet 18 V1.4, 2007-03
3.2 Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4 CPU Block Diagram
Based on these hardware provisions, most of the XC164CM’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
DPRAM
CPU
IPIP
RF
R0
R1
GPRs
R14
R15
R0
R1
GPRs
R14
R15
IFU
Injection/
Exception
Handler
ADU
MAC
mca04917_x.vsd
CPUCON1
CPUCON2
CSP IP
Return
Stack
FIFO
Branch
Unit
Prefetch
Unit VECSEG
TFR
+/-
IDX0
IDX1
QX0
QX1
QR0
QR1
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
MRW
MCW
MSW
MAL
+/-
MAH
Multiply
Unit
ALU
Division Unit
M ultiply Unit
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDC
PSW
MDH
ZEROS
MDL
ONES
R0
R1
GPRs
R14
R15
CP
WB
Buffer
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
R0
R1
GPRs
R14
R15
PMU
DMU
DSRAM
EBC
Peripherals
PSRAM
Flash/ROM
XC164CM
Derivatives
Functional Description
Data Sheet 19 V1.4, 2007-03
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. Also multiplication and most MAC
instructions execute in one single cycle. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: for example, a 32-/16-bit
division is started within 4 cycles, while the remaining 15 cycles are executed in the
background. Another pipeline optimization, the branch target prediction, allows
eliminating the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 word
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank to be accessed by the CPU at any time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC164CM instruction set which
includes the following instruction classes:
• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
XC164CM
Derivatives
Functional Description
Data Sheet 20 V1.4, 2007-03
3.3 Interrupt System
With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC164CM is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC164CM supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC164CM has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bit field exists for each of the possible interrupt nodes. Via
its related register, each node can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible XC164CM interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
XC164CM
Derivatives
Functional Description
Data Sheet 21 V1.4, 2007-03
Table 4 XC164CM Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
EX0IN CC1_CC8IC xx’0060H18H / 24D
EX1IN CC1_CC9IC xx’0064H19H / 25D
EX2IN CC1_CC10IC xx’0068H1AH / 26D
EX3IN CC1_CC11IC xx’006CH1BH / 27D
EX4IN CC1_CC12IC xx’0070H1CH / 28D
EX5IN CC1_CC13IC xx’0074H1DH / 29D
CAPCOM Register 16 CC2_CC16IC xx’00C0H30H / 48D
CAPCOM Register 17 CC2_CC17IC xx’00C4H31H / 49D
CAPCOM Register 18 CC2_CC18IC xx’00C8H32H / 50D
CAPCOM Register 19 CC2_CC19IC xx’00CCH33H / 51D
CAPCOM Register 20 CC2_CC20IC xx’00D0H34H / 52D
CAPCOM Register 21 CC2_CC21IC xx’00D4H35H / 53D
CAPCOM Register 22 CC2_CC22IC xx’00D8H36H / 54D
CAPCOM Register 23 CC2_CC23IC xx’00DCH37H / 55D
CAPCOM Register 24 CC2_CC24IC xx’00E0H38H / 56D
CAPCOM Register 25 CC2_CC25IC xx’00E4H39H / 57D
CAPCOM Register 26 CC2_CC26IC xx’00E8H3AH / 58D
CAPCOM Register 27 CC2_CC27IC xx’00ECH3BH / 59D
CAPCOM Register 28 CC2_CC28IC xx’00F0H3CH / 60D
CAPCOM Register 29 CC2_CC29IC xx’0110H44H / 68D
CAPCOM Register 30 CC2_CC30IC xx’0114H45H / 69D
CAPCOM Register 31 CC2_CC31IC xx’0118H46H / 70D
CAPCOM Timer 7 CC2_T7IC xx’00F4H3DH / 61D
CAPCOM Timer 8 CC2_T8IC xx’00F8H3EH / 62D
GPT1 Timer 2 GPT12E_T2IC xx’0088H22H / 34D
GPT1 Timer 3 GPT12E_T3IC xx’008CH23H / 35D
GPT1 Timer 4 GPT12E_T4IC xx’0090H24H / 36D
GPT2 Timer 5 GPT12E_T5IC xx’0094H25H / 37D
GPT2 Timer 6 GPT12E_T6IC xx’0098H26H / 38D
XC164CM
Derivatives
Functional Description
Data Sheet 22 V1.4, 2007-03
GPT2 CAPREL Register GPT12E_CRIC xx’009CH27H / 39D
A/D Conversion Complete ADC_CIC xx’00A0H28H / 40D
A/D Overrun Error ADC_EIC xx’00A4H29H / 41D
ASC0 Transmit ASC0_TIC xx’00A8H2AH / 42D
ASC0 Transmit Buffer ASC0_TBIC xx’011CH47H / 71D
ASC0 Receive ASC0_RIC xx’00ACH2BH / 43D
ASC0 Error ASC0_EIC xx’00B0H2CH / 44D
ASC0 Autobaud ASC0_ABIC xx’017CH5FH / 95D
SSC0 Transmit SSC0_TIC xx’00B4H2DH / 45D
SSC0 Receive SSC0_RIC xx’00B8H2EH / 46D
SSC0 Error SSC0_EIC xx’00BCH2FH / 47D
PLL/OWD PLLIC xx’010CH43H / 67D
ASC1 Transmit ASC1_TIC xx’0120H48H / 72D
ASC1 Transmit Buffer ASC1_TBIC xx’0178H5EH / 94D
ASC1 Receive ASC1_RIC xx’0124H49H / 73D
ASC1 Error ASC1_EIC xx’0128H4AH / 74D
ASC1 Autobaud ASC1_ABIC xx’0108H42H / 66D
End of PEC Subchannel EOPIC xx’0130H4CH / 76D
CAPCOM6 Timer T12 CCU6_T12IC xx’0134H4DH / 77D
CAPCOM6 Timer T13 CCU6_T13IC xx’0138H4EH / 78D
CAPCOM6 Emergency CCU6_EIC xx’013CH4FH / 79D
CAPCOM6 CCU6_IC xx’0140H50H / 80D
SSC1 Transmit SSC1_TIC xx’0144H51H / 81D
SSC1 Receive SSC1_RIC xx’0148H52H / 82D
SSC1 Error SSC1_EIC xx’014CH53H / 83D
CAN0 CAN_0IC xx’0150H54H / 84D
CAN1 CAN_1IC xx’0154H55H / 85D
CAN2 CAN_2IC xx’0158H56H / 86D
CAN3 CAN_3IC xx’015CH57H / 87D
CAN4 CAN_4IC xx’0164H59H / 89D
Table 4 XC164CM Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
XC164CM
Derivatives
Functional Description
Data Sheet 23 V1.4, 2007-03
CAN5 CAN_5IC xx’0168H5AH / 90D
CAN6 CAN_6IC xx’016CH5BH / 91D
CAN7 CAN_7IC xx’0170H5CH / 92D
RTC RTC_IC xx’0174H5DH / 93D
Unassigned node – xx’0040H10H / 16D
Unassigned node – xx’0044H11H / 17D
Unassigned node – xx’0048H12H / 18D
Unassigned node – xx’004CH13H / 19D
Unassigned node – xx’0050H14H / 20D
Unassigned node – xx’0054H15H / 21D
Unassigned node – xx’0058H16H / 22D
Unassigned node – xx’005CH17H / 23D
Unassigned node – xx’0078H1EH / 30D
Unassigned node – xx’007CH1FH / 31D
Unassigned node – xx’0080H20H / 32D
Unassigned node – xx’0084H21H / 33D
Unassigned node – xx’00FCH3FH / 63D
Unassigned node – xx’0100H40H / 64D
Unassigned node – xx’0104H41H / 65D
Unassigned node – xx’012CH4BH / 75D
Unassigned node – xx’0160H58H / 88D
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Table 4 XC164CM Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
XC164CM
Derivatives
Functional Description
Data Sheet 24 V1.4, 2007-03
The XC164CM also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5 Hardware Trap Summary
Exception Condition Trap
Flag
Trap
Vector
Vector
Location1)
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Trap
Number
Trap
Priority
Reset Functions:
• Hardware Reset
• Software Reset
• W-dog Timer Overflow
–
RESET
RESET
RESET
xx’0000H
xx’0000H
xx’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
• Non-Maskable Interrupt
• Stack Overflow
• Stack Underflow
• Software Break
NMI
STKOF
STKUF
SOFTBRK
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008H
xx’0010H
xx’0018H
xx’0020H
02H
04H
06H
08H
II
II
II
II
Class B Hardware Traps:
• Undefined Opcode
• PMI Access Error
• Protected Instruction
Fault
• Illegal Word Operand
Access
UNDOPC
PACER
PRTFLT
ILLOPA
BTRAP
BTRAP
BTRAP
BTRAP
xx’0028H
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
0AH
I
I
I
I
Reserved – – [2CH - 3CH][0B
H -
0FH]
–
Software Traps
• TRAP Instruction
–– Any
[xx’0000H -
xx’01FCH]
in steps of
4H
Any
[00H -
7FH]
Current
CPU
Priority
XC164CM
Derivatives
Functional Description
Data Sheet 25 V1.4, 2007-03
3.4 On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC164CM. The user software running on the XC164CM can thus
be debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals are realized as alternate
functions on Port 3 pins.
XC164CM
Derivatives
Functional Description
Data Sheet 26 V1.4, 2007-03
3.5 Capture/Compare Unit (CAPCOM2)
The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse
and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, an external
count input for CAPCOM timer T7 allows event scheduling for the capture/compare
registers relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer (T7 or T8,
respectively), and programmed for capture or compare function.
10 registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
Table 6 Compare Modes (CAPCOM2)
Compare Modes Function
Mode 0 Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match;
Several compare events per timer period are possible
Mode 2 Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode Generates single edges or pulses;
Can be used with any compare mode
XC164CM
Derivatives
Functional Description
Data Sheet 27 V1.4, 2007-03
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
XC164CM
Derivatives
Functional Description
Data Sheet 28 V1.4, 2007-03
Figure 5 CAPCOM2 Unit Block Diagram
Sixteen
16-bit
Capture/
Compare
Registers
Mode
Control
(Capture
or
Compare)
T7
Input
Control
T8
Input
Control
MCB05569_2
CCxIRQ
CCxIRQ
CCxIRQ
CAPCOM2 provides channels x = 16 … 31.
(see signals CCxIO and CCxIRQ)
T7IRQ
T8IRQ
CCxIO
CCxIO
CCxIO
T7IN
T6OUF
f
CC
T6OUF
f
CC
Reload Reg.
T7REL
Timer T7
Timer T8
Reload Reg.
T8REL
XC164CM
Derivatives
Functional Description
Data Sheet 29 V1.4, 2007-03
3.6 The Capture/Compare Unit CAPCOM6
The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one independent 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions (deadtime control). The
compare channel can generate a single PWM output signal and is further used to
modulate the capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registers
upon a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled system clock.
Figure 6 CAPCOM6 Block Diagram
For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer T12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).
Control
CC Channel 0
CC60
CC Channel 1
CC61
CC Channel 2
CC62
MCB04109
Prescaler
Offset Register
T12OF
Compare
Timer T12
16-bit
Period Register
T12P
Mode
Select Register
CC6MSEL Trap Register
Port
Control
Logic
Control Register
CTCON
Compare Register
CMP13
Prescaler
Compare
Timer T13
10-bit
Period Register
T13P
Block
Commutation
Control
CC6MCON.H
CC60
COUT60
CC61
COUT61
CC62
COUT62
CTRAP
CC6POS0
CC6POS1
CC6POS2
fCPU
fCPU
The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
COUT63
XC164CM
Derivatives
Functional Description
Data Sheet 30 V1.4, 2007-03
3.7 General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
XC164CM
Derivatives
Functional Description
Data Sheet 31 V1.4, 2007-03
Figure 7 Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
MCA05563
Aux. Timer T2
2
n
:1
T2
Mode
Control
Capture
U/D
Basic Clock
f
GPT
T3CON.BPS1
T3OTL T3OUT
Toggle
Latch
T2IN
T2EUD Reload
Core Timer T3
T3
Mode
Control
T3IN
T3EUD U/D
Interrupt
Request
(T3IRQ)
T4
Mode
Control
U/D
Aux. Timer T4
T4EUD
T4IN Reload
Capture
Interrupt
Request
(T4IRQ)
Interrupt
Request
(T2IRQ)
XC164CM
Derivatives
Functional Description
Data Sheet 32 V1.4, 2007-03
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC164CM to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
XC164CM
Derivatives
Functional Description
Data Sheet 33 V1.4, 2007-03
Figure 8 Block Diagram of GPT2
MCA05564
GPT2 Timer T5
2n:1
T5
Mode
Control
GPT2 CAPREL
T3IN/
T3EUD
CAPREL
Mode
Control
T6
Mode
Control
Reload
Clear
U/D
Capture
Clear
U/D
T5IN
CAPIN
Interrupt
Request
(T5IRQ)
Interrupt
Request
(T6IRQ)
Interrupt
Request
(CRIRQ)
Basic Clock
f
GPT
T6CON.BPS2
T6IN
GPT2 Timer T6 T6OTL T6OUT
T6OUF
Toggle
FF
XC164CM
Derivatives
Functional Description
Data Sheet 34 V1.4, 2007-03
3.8 Real Time Clock
The Real Time Clock (RTC) module of the XC164CM is directly clocked via a separate
clock driver with the prescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is
therefore independent from the selected clock generation mode of the XC164CM.
The RTC basically consists of a chain of divider blocks:
• A selectable 8:1 divider (on - off)
• The reloadable 16-bit timer T14
• The 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
Figure 9 RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
CNT-Register
REL-Register
10 Bits6 Bits6 Bits10 BitsT14
MCB05568
T14-Register
Interrupt Sub Node RTCINT
MUX
8
PRE
RUN CNT
INT3
CNT
INT2
CNT
INT1
CNT
INT0
f
CNT
f
RTC
T14REL 10 Bits6 Bits6 Bits10 Bits
:
XC164CM
Derivatives
Functional Description
Data Sheet 35 V1.4, 2007-03
The RTC module can be used for different purposes:
• System clock to determine the current time and date,
optionally during idle mode, sleep mode, and power down mode
• Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources, e.g. to wake up regularly from idle mode
• 48-bit timer for long term measurements (maximum timespan is > 100 years)
• Alarm interrupt for wake-up on a defined time
XC164CM
Derivatives
Functional Description
Data Sheet 36 V1.4, 2007-03
3.9 A/D Converter
For analog signal measurement, a 10-bit A/D converter with 14 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable (in two modes) and can thus be adjusted to the
external circuitry. The A/D converter can also operate in 8-bit conversion mode, where
the conversion time is further reduced.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converter of the XC164CM supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the prespecified channels are repeatedly sampled and converted. In
addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
The Auto-Power-Down feature of the A/D converter minimizes the power consumption
when no conversion is in progress.
XC164CM
Derivatives
Functional Description
Data Sheet 37 V1.4, 2007-03
3.10 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and half-
duplex synchronous communication. A dedicated baudrate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception, error handling, and baud rate detection 5 separate interrupt
vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Summary of Features
• Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
– Multiprocessor mode for automatic address/data byte detection
– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
– Auto baudrate detection
• Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)
• Buffered transmitter/receiver with FIFO support (8 entries per direction)
• Loop-back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection
XC164CM
Derivatives
Functional Description
Data Sheet 38 V1.4, 2007-03
3.11 High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
• Master or Slave mode operation
• Full-duplex or Half-duplex transfers
• Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
• Loop back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)
• Three pin interface with flexible SSC pin configuration
XC164CM
Derivatives
Functional Description
Data Sheet 39 V1.4, 2007-03
3.12 TwinCAN Module
The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-
structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 9 to interface to an
external bus transceiver. The interface pins are assigned via software.
Figure 10 TwinCAN Module Block Diagram
TwinCAN Module Kernel
MCB05567
TxDCA
RxDCA
TxDCB
RxDCB
CAN
Node A
CAN
Node B
Message
Object
Buffer
Clock
Control
fCAN
Interrupt
Control
Address
Decoder
TwinCAN Control
Port
Control
XC164CM
Derivatives
Functional Description
Data Sheet 40 V1.4, 2007-03
Summary of Features
• CAN functionality according to CAN specification V2.0 B active
• Data transfer rate up to 1 Mbit/s
• Flexible and powerful message transfer control and error handling capabilities
• Full-CAN functionality and Basic CAN functionality for each message object
• 32 flexible message objects
– Assignment to one of the two CAN nodes
– Configuration as transmit object or receive object
– Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm
– Handling of frames with 11-bit or 29-bit identifiers
– Individual programmable acceptance mask register for filtering for each object
– Monitoring via a frame counter
– Configuration for Remote Monitoring Mode
• Up to eight individually programmable interrupt nodes can be used
• CAN Analyzer Mode for bus monitoring is implemented
3.13 LXBus Controller (EBC)
The EBC only controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
XC164CM
Derivatives
Functional Description
Data Sheet 41 V1.4, 2007-03
3.14 Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 μs and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
XC164CM
Derivatives
Functional Description
Data Sheet 42 V1.4, 2007-03
3.15 Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC164CM with high flexibility. The master clock fMC
is the reference clock signal, and is used for TwinCAN and is output to the external
system. The CPU clock fCPU and the system clock fSYS are derived from the master clock
either directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section 4.4.1.
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
XC164CM
Derivatives
Functional Description
Data Sheet 43 V1.4, 2007-03
3.16 Parallel Ports
The XC164CM provides up to 47 I/O lines which are organized into three input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
Table 7 Summary of the XC164CM’s Parallel Ports
Port Control Alternate Functions
PORT1 Pad drivers Capture inputs or compare outputs,
Serial interface lines
Port 3 Pad drivers,
Open drain,
Input threshold
Timer control signals, serial interface lines,
System clock output CLKOUT (or FOUT)
Port 5 – Analog input channels to the A/D converter,
Timer control signals
Port 9 Pad drivers,
Open drain,
Input threshold
Capture inputs or compare outputs
CAN interface lines1)
1) Can be assigned by software.
XC164CM
Derivatives
Functional Description
Data Sheet 44 V1.4, 2007-03
3.17 Power Management
The XC164CM provides several means to control the power it consumes either at a
given time or averaged over a certain timespan. Three mechanisms can be used (partly
in parallel):
•Power Saving Modes switch the XC164CM into a special operating mode (control
via instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
•Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC164CM’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.
•Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3). Each peripheral can separately be disabled/enabled.
The on-chip RTC supports intermittent operation of the XC164CM by generating cyclic
wake-up signals. This offers full performance to quickly react on action requests while
the intermittent sleep phases greatly reduce the average power consumption of the
system.
XC164CM
Derivatives
Functional Description
Data Sheet 45 V1.4, 2007-03
3.18 Instruction Set Summary
Table 8 lists the instructions of the XC164CM in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 8 Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise exclusive OR, (word/byte operands) 2 / 4
BCLR/BSET Clear/Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
2
SHL/SHR Shift left/right direct word GPR 2
XC164CM
Derivatives
Functional Description
Data Sheet 46 V1.4, 2007-03
ROL/ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS/Z Move byte operand to word op. with sign/zero extension 2 / 4
JMPA/I/R Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
JB(C) Jump relative if direct bit is set (and clear bit) 4
JNB(S) Jump relative if direct bit is not set (and set bit) 4
CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine
4
TRAP Call interrupt service routine via immediate trap number 2
PUSH/POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update
register with word operand
4
RET(P) Return from intra-segment subroutine
(and pop direct word register from system stack)
2
RETS Return from inter-segment subroutine 2
RETI Return from interrupt service subroutine 2
SBRK Software Break 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT/ENWDT Disable/Enable Watchdog Timer 4
EINIT End-of-Initialization Register Lock 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
Table 8 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XC164CM
Derivatives
Functional Description
Data Sheet 47 V1.4, 2007-03
NOP Null operation 2
CoMUL/CoMAC Multiply (and accumulate) 4
CoADD/CoSUB Add/Subtract 4
Co(A)SHR (Arithmetic) Shift right 4
CoSHL Shift left 4
CoLOAD/STORE Load accumulator/Store MAC register 4
CoCMP Compare 4
CoMAX/MIN Maximum/Minimum 4
CoABS/CoRND Absolute value/Round accumulator 4
CoMOV Data move 4
CoNEG/NOP Negate accumulator/Null operation 4
Table 8 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XC164CM
Derivatives
Electrical Parameters
Data Sheet 48 V1.4, 2007-03
4 Electrical Parameters
The operating range for the XC164CM is defined by its electrical parameters. For proper
operation the indicated limitations must be respected when designing a system.
4.1 General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 9 Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Notes
Min. Max.
Storage temperature TST -65 150 °C1)
1) Moisture Sensitivity Level (MSL) 3, conforming to Jedec J-STD-020C for 260 °C.
Junction temperature TJ-40 150 °C Under bias
Voltage on VDDI pins with
respect to ground (VSS)
VDDI -0.5 3.25 V –
Voltage on VDDP pins with
respect to ground (VSS)
VDDP -0.5 6.2 V –
Voltage on any pin with
respect to ground (VSS)
VIN -0.5 VDDP +
0.5
V2)
2) Input pin XTAL1 belongs to the core voltage domain. Therefore, input voltages must be within the range
defined for VDDI.
Input current on any pin
during overload condition
–-1010mA–
Absolute sum of all input
currents during overload
condition
– – |100| mA –
XC164CM
Derivatives
Electrical Parameters
Data Sheet 49 V1.4, 2007-03
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC164CM. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Table 10 Operating Condition Parameters
Parameter Symbol Limit Values Unit Notes
Min. Max.
Digital supply voltage for
the core
VDDI 2.35 2.7 V Active mode,
fCPU = fCPUmax1)
1) fCPUmax = 40 MHz for devices marked … 40F, fCPUmax = 20 MHz for devices marked … 20F.
Digital supply voltage for
IO pads
VDDP 4.4 5.5 V Active mode2)3)
2) External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have
reached the operating range.
3) The specified voltage range is allowed for operation. The range limits may be reached under extreme
operating conditions. However, specified parameters, such as leakage currents, refer to the standard
operating voltage range of VDDP = 4.75 V to 5.25 V.
Supply Voltage Difference ΔVDD -0.5 – V VDDP - VDDI4)
4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,
and power-save modes.
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV -5 5 mA Per IO pin5)6)
-2 5 mA Per analog input
pin5)6)
Overload current coupling
factor for analog inputs7) KOVA –1.0 × 10-4 –IOV > 0
–1.5 × 10-3 –IOV < 0
Overload current coupling
factor for digital I/O pins7) KOVD –5.0 × 10-3 –IOV > 0
–1.0 × 10-2 –IOV < 0
Absolute sum of overload
currents
Σ|IOV|– 50 mA
6)
External Load
Capacitance
CL– 50 pF Pin drivers in
default mode8)
Ambient temperature TA070°C SAB-XC164…
-40 85 °C SAF-XC164…
-40 125 °C SAK-XC164…
XC164CM
Derivatives
Electrical Parameters
Data Sheet 50 V1.4, 2007-03
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the
XC164CM and partly its demands on the system. To aid in interpreting the parameters
right, when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC164CM will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC164CM.
5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of
input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1.
6) Not subject to production test - verified by design/characterization.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
XC164CM
Derivatives
Electrical Parameters
Data Sheet 51 V1.4, 2007-03
4.2 DC Parameters
These parameters are static or average values, which may be exceeded during
switching transitions (e.g. output current).
Table 11 DC Characteristics (Operating Conditions apply)1)
Parameter Symbol Limit Values Unit Test Condition
Min. Max.
Input low voltage TTL
(all except XTAL1)
VIL SR -0.5 0.2 × VDDP
- 0.1
V–
Input low voltage
XTAL12) VILC SR -0.5 0.3 × VDDI V–
Input low voltage
(Special Threshold)
VILS SR -0.5 0.45 ×
VDDP
V3)
Input high voltage TTL
(all except XTAL1)
VIH SR 0.2 × VDDP
+ 0.9
VDDP + 0.5 V –
Input high voltage
XTAL12) VIHC SR 0.7 × VDDI VDDI + 0.5 V –
Input high voltage
(Special Threshold)
VIHS SR 0.8 × VDDP
- 0.2
VDDP + 0.5 V 3)
Input Hysteresis
(Special Threshold)
HYS 0.04 ×
VDDP
–VVDDP in [V],
Series resis-
tance = 0 Ω3)
Output low voltage VOL CC – 1.0 V IOL ≤ IOLmax4)
–0.45VIOL ≤ IOLnom4)5)
Output high voltage6) VOH CC VDDP - 1.0 – V IOH ≥ IOHmax4)
VDDP -
0.45
–VIOH ≥ IOHnom4)5)
Input leakage current
(Port 5)7) IOZ1 CC – ±300 nA 0 V < VIN < VDDP,
TA ≤ 125 °C
±200 nA 0 V < VIN < VDDP,
TA ≤ 85 °C12)
Input leakage current
(all other8))7) IOZ2 CC – ±500 nA 0.45 V < VIN <
VDDP
Configuration pull-up
current9) ICPUH10) –-10μAVIN = VIHmin
ICPUL11) -100 – μAVIN = VILmax
XC164CM
Derivatives
Electrical Parameters
Data Sheet 52 V1.4, 2007-03
XTAL1 input current IIL CC – ±20 μA0 V < VIN < VDDI
Pin capacitance12)
(digital inputs/outputs)
CIO CC – 10 pF –
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV.
2) If XTAL1 is driven by a crystal, reaching an amplitude (peak to peak) of 0.4 × VDDI is sufficient.
3) This parameter is tested for P3, P9.
4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL → VSS,
VOH → VDDP). However, only the levels for nominal output currents are guaranteed.
6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
7) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
8) The driver of P3.15 is designed for faster switching, because this pin can deliver the system clock (CLKOUT).
The maximum leakage current for P3.15 is, therefore, increased to 1 μA.
9) During a hardware reset this specification is valid for configuration on P1H.4, P1H.5, P9.4 and P9.5.
After a hardware reset this specification is valid for NMI.
10) The maximum current may be drawn while the respective signal line remains inactive.
11) The minimum current must be drawn to drive the respective signal line active.
12) Not subject to production test - verified by design/characterization.
Table 12 Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
(IOLmax, -IOHmax)1)
1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH) must
remain below 50 mA.
Nominal Output Current
(IOLnom, -IOHnom)
Strong driver 10 mA 2.5 mA
Medium driver 4.0 mA 1.0 mA
Weak driver 0.5 mA 0.1 mA
Table 11 DC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter Symbol Limit Values Unit Test Condition
Min. Max.
XC164CM
Derivatives
Electrical Parameters
Data Sheet 53 V1.4, 2007-03
Table 13 Power Consumption XC164CM (Operating Conditions apply)
Parameter Sym-
bol
Limit Values Unit Test Condition
Min. Max.
Power supply current (active)
with all peripherals active
IDDI – 15 +
2.6 × fCPU
mA fCPU in [MHz]1)2),
-16F derivatives
1) During Flash programming or erase operations the supply current is increased by max. 5 mA.
2) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 11.
These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and
all inputs at VIL or VIH.
– 10 +
2.6 × fCPU
mA fCPU in [MHz]1)2),
-4F/8F derivatives
Pad supply current IDDP –5 mA
3)
3) The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A small
amount of current is consumed even though no outputs are driven, because the drivers’ input stages are
switched and also the Flash module draws some power from the VDDP supply.
Idle mode supply current with
all peripherals active
IIDX –15 +
1.2 × fCPU
mA fCPU in [MHz]2),
-16F derivatives
–10 +
1.2 × fCPU
mA fCPU in [MHz]2),
-4F/8F derivatives
Sleep and Power down mode
supply current caused by
leakage4)
4) The total supply current in Sleep and Power down mode is the sum of the temperature dependent leakage
current and the frequency dependent current for RTC and main oscillator.
IPDL5)
5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the
junction temperature (see Figure 13). The junction temperature TJ is the same as the ambient temperature TA
if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.
– 84,000
× e-α
mA VDDI = VDDImax6)
TJ in [°C]
α = 4380 / (273 + TJ)
-16F derivatives
6) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including
pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for TJ ≥ 25 °C.
– 128,000
× e-α
mA α = 4670 / (273 + TJ)
-4F/8F derivatives
Sleep and Power down mode
supply current caused by
leakage and the RTC running,
clocked by the main oscillator4)
IPDM7)
7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see
Figure 12). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The
given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
– 0.6 +
0.02 × fOSC
+ IPDL
mA VDDI = VDDImax
fOSC in [MHz]
XC164CM
Derivatives
Electrical Parameters
Data Sheet 54 V1.4, 2007-03
Figure 11 Supply/Idle Current as a Function of Operating Frequency
I [mA]
fCPU [MHz]
10 20 30 40
IDDImax
IDDItyp
IIDXmax
IIDXtyp
20
40
60
80
100
120
140
-4F/8F
-16F
-16F
-4F/8F
-16F
-4F/8F
-16F
-4F/8F
XC164CM
Derivatives
Electrical Parameters
Data Sheet 55 V1.4, 2007-03
Figure 12 Sleep and Power Down Supply Current due to RTC and Oscillator
Running, as a Function of Oscillator Frequency
Figure 13 Sleep and Power Down Leakage Supply Current as a Function of
Temperature
I [mA]
fOSC [MHz]
4 8 12 16
IPDMmax
IPDMtyp
1.0
2.0
3.0
[mA]
TJ [°C]
050 100 150
IPDL
0.5
1.0
1.5
-50
-16F
-4F/8F
XC164CM
Derivatives
Electrical Parameters
Data Sheet 56 V1.4, 2007-03
4.3 Analog/Digital Converter Parameters
These parameters describe how the optimum ADC performance can be reached.
Table 14 A/D Converter Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test
Condition
Min. Max.
Analog reference supply VAREF SR 4.5 VDDP
+ 0.1
V1)
1) TUE is tested at VAREF = VDDP + 0.1 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range.
If the analog reference supply voltage drops below 4.5 V (i.e. VAREF ≥ 4.0 V) or exceeds the power supply
voltage by up to 0.2 V (i.e. VAREF = VDDP + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not
subject to production test.
The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the respective period of
time. During the reset calibration sequence the maximum TUE may be ±4 LSB.
Analog reference ground VAGND SR VSS - 0.1 VSS + 0.1 V –
Analog input voltage range VAIN SR VAGND VAREF V2)
Basic clock frequency fBC 0.5 20 MHz 3)
Conversion time for 10-bit
result4) tC10P CC 52 × tBC + tS + 6 × tSYS – Post-calibr. on
tC10 CC 40 × tBC + tS + 6 × tSYS – Post-calibr. off
Conversion time for 8-bit
result4) tC8P CC 44 × tBC + tS + 6 × tSYS – Post-calibr. on
tC8 CC 32 × tBC + tS + 6 × tSYS – Post-calibr. off
Calibration time after reset tCAL CC 484 11,696 tBC 5)
Total unadjusted error TUE CC – ±2LSB
1)
Total capacitance
of an analog input
CAINT CC – 15 pF 6)
Switched capacitance
of an analog input
CAINS CC – 10 pF 6)
Resistance of
the analog input path
RAIN CC – 2 kΩ6)
Total capacitance
of the reference input
CAREFT CC – 20 pF 6)
Switched capacitance
of the reference input
CAREFS CC – 15 pF 6)
Resistance of
the reference input path
RAREF CC – 1 kΩ6)
XC164CM
Derivatives
Electrical Parameters
Data Sheet 57 V1.4, 2007-03
Figure 14 Equivalent Circuitry for Analog Inputs
2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
3) The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting.
4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result (tSYS = 1/fSYS).
Values for the basic clock tBC depend on programming and can be taken from Table 15.
When the post-calibration is switched off, the conversion time is reduced by 12 × tBC.
5) The actual duration of the reset calibration depends on the noise on the reference signal. Conversions
executed during the reset calibration increase the calibration time. The TUE for those conversions may be
increased.
6) Not subject to production test - verified by design/characterization.
The given parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal
supply voltage the following typical values can be used:
CAINTtyp = 12 pF, CAINStyp = 7 pF, RAINtyp = 1.5 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 13 pF, RAREFtyp = 0.7 kΩ.
A/D Converter
MCS05570
R
Source
V
AIN
C
Ext
C
AINT
C
AINS
-
R
AIN, On
C
AINS
XC164CM
Derivatives
Electrical Parameters
Data Sheet 58 V1.4, 2007-03
Sample time and conversion time of the XC164CM’s A/D Converter are programmable.
In compatibility mode, the above timing can be calculated using Table 15.
The limit values for fBC must not be exceeded when selecting ADCTC.
Converter Timing Example:
Table 15 A/D Converter Computation Table1)
1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock
can be selected.
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock fBC
ADCON.13|12
(ADSTC)
Sample Time
tS
00 fSYS / 4 00 tBC × 8
01 fSYS / 2 01 tBC × 16
10 fSYS / 16 10 tBC × 32
11 fSYS / 8 11 tBC × 64
Assumptions: fSYS = 40 MHz (i.e. tSYS = 25 ns), ADCTC = ‘01’, ADSTC = ‘00’
Basic clock fBC = fSYS / 2 = 20 MHz, i.e. tBC = 50 ns
Sample time tS= tBC × 8 = 400 ns
Conversion 10-bit:
With post-calibr. tC10P = 52 × tBC + tS + 6 × tSYS = (2600 + 400 + 150) ns = 3.15 μs
Post-calibr. off tC10 = 40 × tBC + tS + 6 × tSYS = (2000 + 400 + 150) ns = 2.55 μs
Conversion 8-bit:
With post-calibr. tC8P = 44 × tBC + tS + 6 × tSYS = (2200 + 400 + 150) ns = 2.75 μs
Post-calibr. off tC8 = 32 × tBC + tS + 6 × tSYS = (1600 + 400 + 150) ns = 2.15 μs
XC164CM
Derivatives
Electrical Parameters
Data Sheet 59 V1.4, 2007-03
4.4 AC Parameters
These parameters describe the dynamic behavior of the XC164CM.
4.4.1 Definition of Internal Timing
The internal operation of the XC164CM is controlled by the internal master clock fMC.
The master clock signal fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate fMC.
This influence must be regarded when calculating the timings for the XC164CM.
Figure 15 Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
MCT05555
Phase Locked Loop Operation (1:N)
f
OSC
Direct Clock Drive (1:1)
Prescaler Operation (N:1)
f
MC
f
OSC
f
MC
f
OSC
f
MC
TCM
TCM
TCM
XC164CM
Derivatives
Electrical Parameters
Data Sheet 60 V1.4, 2007-03
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the
same frequency as the master clock (fCPU = fMC) or can be the master clock divided by
two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal fSYS which has the same
frequency as the CPU clock signal fCPU.
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
fMC = fOSC / ((PLLIDIV + 1) × (PLLODIV + 1)).
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of fMC
directly follows the frequency of fOSC so the high and low time of fMC is defined by the duty
cycle of the input clock fOSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
fMC = fOSC / ((3 + 1) × (14 + 1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it
is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 16).
XC164CM
Derivatives
Electrical Parameters
Data Sheet 61 V1.4, 2007-03
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore,
the number of VCO cycles can be represented as K ×N, where N is the number of
consecutive fMC cycles (TCM).
For a period of N × TCM the accumulated PLL jitter is defined by the deviation DN:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Figure 16 Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
MCD05566
N
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
DN
051015 20 25
ns K = 15
K = 12
K = 10
K = 8
K = 6 K = 5
1
10 MHz
20 MHz
40 MHz
XC164CM
Derivatives
Electrical Parameters
Data Sheet 62 V1.4, 2007-03
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Table 16 VCO Bands for PLL Operation1)
1) Not subject to production test - verified by design/characterization.
PLLCON.PLLVB VCO Frequency Range Base Frequency Range
00 100 … 150 MHz 20 … 80 MHz
01 150 … 200 MHz 40 … 130 MHz
10 200 … 250 MHz 60 … 180 MHz
11 Reserved
XC164CM
Derivatives
Electrical Parameters
Data Sheet 63 V1.4, 2007-03
4.4.2 On-chip Flash Operation
The XC164CM’s Flash module delivers data within a fixed access time (see Table 17).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time tACC of the Flash array. The required Flash waitstates depend on the actual system
frequency.
The Flash access waitstates only affect non-sequential accesses. Due to prefetching
mechanisms, the performance for sequential accesses (depending on the software
structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average performance by
5% … 15%.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18 indicates the interrelation of waitstates and system frequency.
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for XC164CM-xF20F devices).
Table 17 Flash Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit
Min. Typ. Max.
Flash module access time tACC CC––50
1)
1) The actual access time is influenced by the system frequency, see Table 18.
ns
Programming time per 128-byte block tPR CC – 22)
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
5ms
Erase time per sector tER CC – 2002) 500 ms
Table 18 Flash Access Waitstates
Required Waitstates Frequency Range
0 WS (WSFLASH = 00B)fCPU ≤ 20 MHz
1 WS (WSFLASH = 01B)fCPU ≤ 40 MHz
XC164CM
Derivatives
Electrical Parameters
Data Sheet 64 V1.4, 2007-03
4.4.3 External Clock Drive XTAL1
These parameters define the external clock supply for the XC164CM.
Figure 17 External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).
Table 19 External Clock Drive Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit
Min. Max.
Oscillator period tOSC SR 25 2501)
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
ns
High time2)
2) The clock input signal must reach the defined levels VILC and VIHC.
t1SR6–ns
Low time2) t2SR6–ns
Rise time2) t3SR–8ns
Fall time2) t4SR–8ns
MCT05572
t
1
t
2
t
OSC
t
3
t
4
0.5
V
DDI
V
ILC
V
IHC
XC164CM
Derivatives
Package and Reliability
Data Sheet 65 V1.4, 2007-03
5 Package and Reliability
In addition to the electrical parameters, the following information ensures proper
integration of the XC164CM into the target system.
5.1 Packaging
These parameters describe the housing rather than the silicon.
Package Outlines
Figure 18 PG-LQFP-64-4 (Plastic Green Low profile Quad Flat Package),
valid for the -16F derivatives
XC164CM
Derivatives
Package and Reliability
Data Sheet 66 V1.4, 2007-03
Figure 19 PG-TQFP-64-8 (Plastic Thin Quad Flat Package),
valid for the -4F/8F derivatives
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products
Dimensions in mm.
Table 20 Package Parameters
Parameter Symbol Limit Values Unit Notes
Min. Max.
PG-LQFP-64-4
Thermal resistance
junction to case
RΘJC –8K/W–
Thermal resistance
junction to leads
RΘJL –23K/W–
PG-TQFP-64-8
Thermal resistance
junction to case
RΘJC –9K/W–
Thermal resistance
junction to leads
RΘJL –19K/W–
1) Does not include plastic or metal protrusion of 0.25 max. per side
4x
64 1
Index Marking
0.08
D
A
101)
12
-0.03
+0.07
0.2
0.5
7.5
A-B D 64xC
0.2
0.2
B
A-B
A-B D
D
H
0.1
C
M
±0.05
1.4
1.6 MAX.
0.08
±0.05
±0.15
4x
H
0.6
7˚ MAX.
0.15
+0.03
-0.06
12
10
1)
2)
2) Does not include dambar protrusion of 0.08 max. per side
XC164CM
Derivatives
Package and Reliability
Data Sheet 67 V1.4, 2007-03
5.2 Flash Memory Parameters
The data retention time of the XC164CM’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 21 Flash Parameters
Parameter Symbol Limit Values Unit Notes
Min. Max.
Data retention time tRET 15 – years 103 erase/program
cycles
Flash Erase Endurance NER 20 × 103– cycles Data retention time
5years
