© Semiconductor Components Industries, LLC, 2015
February, 2017 − Rev. 4 1Publication Order Number:
KAI−0340/D
KAI-0340
640 (H) x 480 (V) Interline
CCD Image Sensor
Description
The KAI−0340 image sensor is a 640 (H) × 480 (V) resolution, 1/3″
optical format, progressive scan interline CCD. This image sensor is
offered i n 2 versions: the KAI−0340−Dual supports 210 full resolution
frame-per-second readout while the KAI−0340−Single supports 110
frame-per-second readout. Frame rates as high as 2,000 Hz
(KAI−0340−Single) and 3,400 Hz (KAI−0340−Dual) can be achieved
by combining the Fast Horizontal Line Dump with custom clocking
modes. Designed for demanding imaging applications, the KAI−0340
provides electronic shuttering, peak QE (quantum efficiency) of 55%,
extremely low noise and low dark current. These features give this
sensor exceptional sensitivity and make it ideal for machine vision,
scientific, surveillance, and other computer input applications.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CDD; Progressive Scan
Total Number of Pixels 696 (H) × 492 (V)
Number of Effective Pixels 648 (H) × 484 (V)
Number of Active Pixels 640 (H) × 480 (V)
Pixel Size 7.4 mm(H) × 7.4 mm (V)
Active Image Size 4.736 mm (H) × 3.552 mm (V),
5.920 mm (Diagonal),
1/3″ Optical Format
Aspect Ratio 4:3
Number of Outputs 1 or 2
Charge Capacity 40 MHz − 20,000 e−
20 MHz − 40,000 e−
Output Sensitivity 30 mV/e−
Photometric Sensitivity
KAI−0340−ABB
KAI−0340−CBA (RGB)
KAI−0340−FBA (RGB)
3.61 V/lux−sec
0.66 (R), 1.51 (G), 1.14 (B) V/lux−sec
0.92 (R), 1.80 (G), 1.22 (B) V/lux−sec
Readout Noise 40 MHz − 16 e−
20 MHz − 14 e−
Dynamic Range 40 MHz − 62 dB
20 MHz − 69 dB
Dark Current
Photodiode
VCCD < 200 eps
< 1,000 eps
Maximum Pixel Clock Speed 40 MHz
Maximum Frame Rate
KAI−0340−Dual
KAI−0340−Single 210 fps
110 fps
Package Type 22-Pin CERDIP (0.050″ Pin Spacing)
Cover Glass Clear/Quartz Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
Features
•High Sensitivity
•High Dynamic Range
•Low Noise Architecture
•High Frame Rate
•Electronic Shutter
Applications
•Intelligent Transportation Systems
•Machine Vision
•Scientific
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Figure 1. KAI−0340 Interline
CCD Image Sensor
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
KAI−0340
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2
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−0340 IMAGE SENSOR
Part Number Description Marking Code
KAI−0340−AAA−CP−AA−Single Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Standard Grade, Single Output KAI−0340S
KAI−0340−AAA−CP−AE−Single Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−AAA−CP−AA−Dual Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Standard Grade, Dual Output KAI−0340D
KAI−0340−AAA−CP−AE−Dual Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Engineering Grade, Dual Output
KAI−0340−AAA−CF−AA−Single Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass, No Coatings, Standard Grade, Single Output KAI−0340S
KAI−0340−AAA−CF−AE−Single Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−AAA−CF−AA−Dual Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass, No Coatings, Standard Grade, Dual Output KAI−0340D
KAI−0340−AAA−CF−AE−Dual Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass, No Coatings, Engineering Grade, Dual Output
KAI−0340−ABB−CP−AA−Single Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Standard Grade, Single Output KAI−0340ABBS
KAI−0340−ABB−CP−AE−Single Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−ABB−CP−AA−Dual Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Standard Grade, Dual Output KAI−0340ABBD
KAI−0340−ABB−CP−AE−Dual Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, No Coatings, Engineering Grade, Dual Output
KAI−0340−ABB−CB−AA−Single Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Single Output KAI−0340ABBS
KAI−0340−ABB−CB−A2−Single Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Grade 2, Single Output
KAI−0340−ABB−CB−AE−Single Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−ABB−CB−AA−Dual Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Dual Output KAI−0340ABBD
KAI−0340−ABB−CB−AE−Dual Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Dual Output
KAI−0340−FBA−CB−AA−Single Color Gen2 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Single Output KAI0340FBAS
KAI−0340−FBA−CB−AE−Single Color Gen2 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−FBA−CB−AA−Dual Color Gen2 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Dual Output KAI0340FBAD
KAI−0340−FBA−CB−AE−Dual Color Gen2 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Dual Output
KAI−0340−CBA−CB−AA−Single* Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Single Output KAI−0340SCM
KAI−0340−CBA−CB−AE−Single* Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Single Output
KAI−0340−CBA−CB−AA−Dual* Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Standard Grade, Dual Output KAI−0340DCM
KAI−0340−CBA−CB−AE−Dual* Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass, No Coatings, Engineering Grade, Dual Output
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAI−0340−10−40−A−EVK Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−0340
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Sensor Architecture
Dual
Output
or
Video L Video R
12 24 4640 4 24 12
Single
12 24 4 320 320 4 24 12
GG
R
B
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
24 Dark Columns
4 Buffer Columns
24 Dark Columns
4 Buffer Columns
12 Dummy Pixels
12 Dummy Pixels
Pixel 1,1
KAI−0340
640 (H) × 480 (V)
Active Pixels
1/3″ VGA
There are 4 light-shielded rows followed by 488
photoactive rows. The first 4 and the last 4 photoactive rows
are buffer rows giving a total of 480 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
12 empty pixels of each line do not receive charge from the
vertical shift register. The next 24 pixels receive charge from
the left light-shielded edge followed by 648 photosensitive
pixels and finally 24 more light-shielded pixels from the
right edge of the sensor. The first and last 4 photosensitive
pixels are buffer pixels giving a total of 640 pixels of image
data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out V ideo L and the right half of the image is clocked
out Video R. Each row consists of 12 empty pixels followed
by 24 light-shielded pixels followed by 324 photosensitive
pixels. When reconstructing the image, data from Video R
will have to be reversed in a line buf fer and appended to the
Video L data.
There are no dark reference rows at the top and 4 dark rows
at the bottom of the image sensor. The 4 dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 24 dark columns on the left or right side of the
image sensor as a dark reference.
Of the 24 dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
Only use the center 22 columns of the 24 column dark
reference.
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ESD Protection
Figure 3. ESD Protection
RL H1S H1BL H2BL
RR H2S H1BR H2BR
D1
D2 D2 D2 D2
D2D2D2D2
VSUB
ESD
The ESD protection on the KAI−0340 is implemented
using bipolar transistors. The substrate (SUB) forms the
common collector of all the ESD protection transistors. The
ESD pin is the common base of all the ESD protection
transistors. Each protected pin is connected to a separate
emitter as shown in Figure 3.
The ESD circuit turns on if the base-emitter junction
voltage exceeds 17 V. Care must be taken while operating
the image sensor, especially during the power on sequence,
to not forward bias the base-emitter or base-collector
junctions. I f i t i s possible for the camera power up sequence
to forward bias these junctions then diodes D1 and D2
should be added to protect the image sensor. Put one diode
D1 between the ESD and VSUB pins. Put one diode D2 on
each pin that may forward bias the base-emitter junction.
The diodes will prevent large currents from flowing through
the image sensor. Note that external diodes D1 and D2 are
optional and are only needed if it is possible to forward bias
any of the junctions.
Note that diodes D1 and D2 are added external to the
KAI−0340.
KAI−0340
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Pin Description and Device Orientation
Figure 4. Pin Description (Top View)
VOUTL VDDL
Pixel 1,1
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
18
19
20
21
22
RL FDC
H2BL ESD
H1BL V1C
H1S V1
GND V2
H2S V2C
H1BR GND
H2BR SUB
RR FD
VOUTR VDDR
Table 4. PIN DESCRIPTION
Pin No. Symbol Description
1 VOUTL Video Output, Left
2 RL Reset Gate, Left
3 H2BL Horizontal Clock, Phase 2, Barrier, Left
4 H1BL Horizontal Clock, Phase 1, Barrier, Right
5 H1S Horizontal Clock, Phase 1, Storage
6 GND Ground
7 H2S Horizontal Clock, Phase 2, Storage
8 H1BR Horizontal Clock, Phase 1, Barrier, Right
9 H2BR Horizontal Clock, Phase 2, Barrier, Right
10 RR Reset Gate, Right
11 VOUTR Video Output, Right
12 VDDR VDD, Right
13 FD Fast Line Dump Gate, Left and Right Columns
14 SUB Substrate
15 GND Ground
16 V2C Vertical Clock, Phase 2, Center Rows
17 V2 Vertical Clock, Phase 2, Top and Bottom Rows
18 V1 Vertical Clock, Phase 1, Top and Bottom Rows
19 V1C Vertical Clock, Phase 1, Center Rows
20 ESD ESD
21 FDC Fast Line Dump Gate, Center Columns
22 VDDL VDD, Left
1. The pins are on a 0.050″ spacing
2. If the vertical windowing option is not to be used, then the V1 and V1C pins should be driven from one clock driver. The V2 and V2C pins
should also be driven from one clock driver.
3. If the fast dump windowing option is not to be used, then the FD and FDC pins should be driven from the same clock driver.
4. The VOUTR pin is not enabled in the KAI−0340−Single version.
KAI−0340
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IMAGING PERFORMANCE
Table 5. IMAGING PERFORMANCE OPERATIONAL CONDITIONS
(Unless otherwise noted, Imaging Performance Specifications are measured using the following conditions.)
Description Condition
Frame Time (Note 5) 53 ms
Horizontal Clock Frequency 10 MHz
Light Source (Notes 6, 7) Continuous Red, Green and Blue Illumination Centered at 450, 530 and 650 nm
Operation Nominal Operating Voltages and Timing
5. Electronic shutter is not used. Integration time equals frame time.
6. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115.
7. For monochrome sensor, only green LED used.
Table 6. IMAGING PERFORMANCE SPECIFICATIONS
Description Symbol Min. Nom. Max. Unit Sampling
Plan
Temperature
Tested at
(5C)
ALL CONFIGURATIONS
Photodiode CCD Dark Current IPD 0 40 200 e/p/s Die 27, 40
Vertical CCD Dark Current IVD 0 400 1,000 e/p/s Die 27, 40
Dark Current Doubling Temperature N/A 7 N/A °C Design
Horizontal CCD Charge Capacity HNe 80 N/A N/A ke−Design
Vertical CCD Charge Capacity VNe 50 N/A N/A ke−Design
Horizontal CCD Charge Transfer
Efficiency HCTE 0.99999 N/A N/A Design
Vertical CCD Charge Transfer
Efficiency VCTE 0.99999 N/A N/A Design
Image Lag Lag 0 < 10 50 e−Design
Anti-Blooming Factor XAB 100 300 N/A Design
Vertical Smear Smr N/A 80 75 dB Design
Output Amplifier DC Offset (Note 8) VODC 6 N/A 12 V Die
Output Amplifier Impedance (Note 9) ROUT 100 150 200 WDie
Output Amplifier Bandwidth f−3dB N/A 140 N/A MHz Design
Output Amplifier Sensitivity DV/DNN/A 30 N/A mV/e Design
MONOCHROME CONFIGURATIONS
Global Uniformity 0.0 1.5 3.0 % rms Die 27, 40
Global Peak to Peak Uniformity PRNU 0.0 5.0 10.0 %pp Die 27, 40
Center Uniformity 0.0 0.6 1.0 % rms Die 27, 40
Photometric Sensitivity
KAI−0340M (Note 11) N/A 3.61 N/A V/lux-sec Design
COLOR CONFIGURATIONS
Global Uniformity (Note 10) 0.0 2.0 5.0 % rms Die 27, 40
Global Peak to Peak Uniformity
(Note 10) PRNU 0.0 5.0 10.0 %pp Die 27, 40
Center Uniformity (Note 10) 0.0 1.0 2.0 % rms Die 27, 40
Photometric Sensitivity Gen2
Blue (B) Pixels (Note 11) N/A 1.22 N/A V/lux-sec Design
Photometric Sensitivity Gen2
Green (G) Pixels (Note 11) N/A 1.80 N/A V/lux-sec Design
KAI−0340
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Table 6. IMAGING PERFORMANCE SPECIFICATIONS (continued)
Description
Temperature
Tested at
(5C)
Sampling
Plan
UnitMax.Nom.Min.Symbol
COLOR CONFIGURATIONS
Photometric Sensitivity Gen2
Red (R) Pixels (Note 11) N/A 0.92 N/A V/lux-sec Design
Photometric Sensitivity Gen1
Blue (B) Pixels (Notes 11, 12) N/A 1.14 N/A V/lux-sec Design
Photometric Sensitivity Gen1
Green (G) Pixels (Notes 11, 12) N/A 1.51 N/A V/lux-sec Design
Photometric Sensitivity Gen1
Red (R) Pixels (Notes 11, 12) N/A 0.66 N/A V/lux-sec Design
8. Measured at sensor output with constant current load of IOUT = −5 mA and during the floating diffusion reset interval (R high).
9. Last stage only. CLOAD = 10 pF. Then f−3dB = (1 / (2n ⋅ ROUT ⋅ CLOAD)).
10.Per color.
11.Calculated using quantum efficiency, output amplifier sensitivity, 3200K Plankian source and a CM500S IR-cut filter.
12.This color filter set configuration (Gen1) is not recommended for new designs.
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TYPICAL PERFORMANCE CUR VES
Quantum Efficiency
Monochrome with Microlens
Figure 5. Monochrome with Microlens Quantum Efficiency
0.00
0.10
0.20
0.30
0.40
0.50
0.60
300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
Absolute Quantum Efficiency
Measured with
Clear Cover Glass
Monochrome without Microlens
Figure 6. Monochrome without Microlens Quantum Efficiency
0.00
0.02
0.04
0.06
0.08
0.10
0.12
240 340 440 540 640 740 840 940
Wavelength (nm)
Absolute Quantum Efficiency
Measured without
Cover Glass
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Color (Bayer RGB) with Microlens
Figure 7. Color (Bayer RGB) with Microlens Quantum Efficiency
0.00
0.10
0.20
0.30
0.40
0.50
300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
Absolute Quantum Efficiency
Measured with
Clear Cover Glass
Gen1 Red
Gen1 Green
Gen1 Blue
Gen2 Red
Gen2 Green
Gen2 Blue
Angular Quantum Efficiency
Monochrome with Microlens
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Figure 8. Angular Quantum Efficiency
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Angle (degrees)
Relative Quantum Efficiency (%)
Horizontal
Vertical
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Frame Rates
Frames rates are for continuous mode operation.
Table 7. FRAME RATES
Description KAI−0340−Single and KAI−0340−Dual
Single Output (fps) KAI−0340−Dual Only
Dual Output (fps)
640 × 480 112 214
228 × 480 306 581
640 × 164 325 618
228 × 164 877 1,637
228 × 55 2,000 3,400
640 x 480 Full Field Single Output
640 x 480 Full Field Dual Outputs
228(H) x 480(V) Center Columns One Output
228(H) x 480(V) Center Columns Dual Outputs
640(H) x 164(V) Center Rows One Output
640(H) x 164(V) Center Rows Dual Outputs
228(H) x 164(V) Center Rows and Columns One Output
228(H) x 164(V) Center Rows and Columns Dual Outputs
Figure 10. Frame Rates
112
214
306
581
325
618
877
1637
0
200
400
600
800
1000
1200
1400
1600
1800
0 5 10 15 20 25 30 35 40
HCCD Clock Frequency (MHz)
Frame Per Second
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DEFECT DEFINITIONS
Table 8. DEFECT DEFINITIONS
Description Definition Maximum Temperature(s)
Tested at (5C)
MONOCHROME (EXCLUDING KAI−0340−ABB−CB−A2−SINGLE)
Major Dark Field Defective Pixel Defect ≥ 16 mV 227, 40
Major Bright Field Defective Pixel Defect ≥ 11% 027, 40
Minor Dark Field Defective Pixel Defect ≥ 4mV 100 27, 40
Dead Pixel Defect ≥ 80% 027, 40
Saturated Pixel Defect ≥ 30 mV 027, 40
Cluster Defect A Group of 2 to 10 Contiguous Major Defective Pixels 027, 40
Column Defect A Group of more than 10 Contiguous Major Defective
Pixels along a Single Column 027, 40
MONOCHROME (KAI−0340−ABB−CB−A2−SINGLE ONLY)
Major Dark Field Defective Pixel Defect ≥ 16 mV 227, 40
Major Bright Field Defective Pixel Defect ≥ 11% 10 27, 40
Minor Dark Field Defective Pixel Defect ≥ 4mV 100 27, 40
Dead Pixel Defect ≥ 80% 027, 40
Saturated Pixel Defect ≥ 30 mV 027, 40
Cluster Defect A Group of 2 to 10 Contiguous Major Defective Pixels 027, 40
Column Defect A Group of more than 10 Contiguous Major Defective
Pixels along a Single Column 027, 40
COLOR VERSIONS
Major Dark Field Defective Pixel Defect ≥ 16 mV 227, 40
Major Bright Field Defective Pixel Defect ≥ 11% 227, 40
Minor Dark Field Defective Pixel Defect ≥ 4mV 100 27, 40
Dead Pixel Defect ≥ 80% 027, 40
Saturated Pixel Defect ≥ 30 mV 027, 40
Cluster Defect A Group of 2 to 10 Contiguous Major Defective Pixels 027, 40
Column Defect A Group of more than 10 Contiguous Major Defective
Pixels along a Single Column 027, 40
Defect Map
No defect maps are available for the KAI−0340 image sensor.
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TEST DEFINITIONS
Test Regions of Interest
Active Area ROI: Pixel (1, 1) to Pixel (640, 480)
Center 100 by 100 ROI: Pixel (270, 190) to Pixel (369, 289)
Only the active pixels are used for performance and defect tests.
Test Sub-Regions of Interest
Figure 11. Test Sub-Regions of Interest
Pixel
(1,1)
Pixel
(640,480)
12345
6 7 8 9 10
11 12 13 14 15
16 17 18 19 20
21 22 23 24 25
Over-Clocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 12 for a pictorial representation of the regions.
Figure 12. Overclock Regions of Interest
Pixel 1,1
Vertical Overclock
Horizontal Overclock
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Tests
Global Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 42 0 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 600 mV. Global non-uniformity is
defined as
Global Non−Uniformity +100 @ǒActive Area Standard Deviation
Active Area Signal Ǔ
Active Area Signal = Active Area Average − H. Overclock Average
Units : % rms
Global Peak-to-Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 42 0 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 600 mV. The sensor is partitioned
into 25 sub-regions of interest, each of which is 128 by 96
pixels in size. The average signal level of each of the 25
sub-regions of interest (ROI) is calculated. The signal level
of each of the sub regions of interest is calculated using the
following formula:
A[i] +(ROI Average *Horizontal Overclock Average)
Where i = 1 to 25. During this calculation on the 25
sub-regions of interest, the maximum and minimum average
signal levels are found. The global peak-to-peak
non-uniformity is then calculated as:
Global Non−Uniformity +100 @ǒA[i] Max. Signal *A[i] Min. Signal
Active Area Signal Ǔ
Active Area Signal = Active Area Average − H. Overclock Average
Units : % pp
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 42 0 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 600 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels (See Test Regions of Interest) of the
sensor. Center non-uniformity is defined as:
Center ROI Non−Uniformity +100 @ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Center ROI Signal = Center ROI Average − H. Overclock Average
Units : % rms
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 25 sub-regions of interest,
each of which is 128 by 96 pixels in size. In each region of
interest, the median value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in “Defect Definitions”
section.
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 42 0 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity o f the sensor is 600 mV. The average signal level of
all active pixels is found. The bright and dark thresholds are
set as:
Dark Defect Threshold = Active Area Signal @Threshold
Bright Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 25 sub-regions of
interest, each of which is 128 by 96 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
•Average value of all active pixels is found to be 420 mV.
•Dark defect threshold: 420 mV ⋅ 11% = 46 mV
•Bright defect threshold: 420 mV ⋅ 11% = 46 mV
•Region of interest #1 selected. This region of interest is
pixels 1,1 to pixels 128,96.
♦Median of this region of interest is found to be
420 mV.
♦Any pixel in this region of interest that is
≥(420 + 46 mV) 466 mV in intensity will be marked
defective.
♦Any pixel in this region of interest that is
≤(420 − 46 mV) 374 mV in intensity will be marked
defective.
•All remaining 24 sub-regions of interest are analyzed
for defective pixels in the same manner.
For the color sensor, the threshold for each color channel
is determined independently.
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OPERATION
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the
device will be degraded and may be damaged.
Table 9. ABSOLUTE MAXIMUM RATINGS
Description Symbol Min. Max. Unit
Operating Temperature (Note 13) T−50 70 °C
Humidity (Note 14) RH 5 90 %
Output Bias Current (Note 15) IOUT 0.0 10 mA
Off−chip Load (Note 16) CLN/A 10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
13.Noise performance will degrade at higher temperatures.
14.T = 25°C. Excessive humidity will degrade MTTF.
15.Each output. See Figure 13. Note that the current bias affects the amplifier bandwidth.
16.With total output load capacitance of CL = 10 pF between the outputs and AC ground.
Table 10. ABSOLUTE VOLTAGE RATINGS BETWEEN PINS
Description Min. Max. Unit
RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR to ESD 0 17 V
Pin to Pin with ESD Protection (Note 17) −17 17 V
VDDL, VDDR to GND 0 25 V
17.Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, and H2BR.
Table 11. DC OPERATING CONDITIONS
Description Symbol Min. Nom. Max. Unit Maximum
DC Current
Output Amplifier Supply (Notes 18, 21) VDD 14.75 15.0 15.25 V 2.5 mA
Ground GND 0.0 0.0 0.0 V
Substrate (Notes 19, 23) SUB 8.0 VAB 15.0 V
ESD Protection (Note 20) ESD −9.25 −9.0 −8.75 V 2.0 mA
Output Bias Current (Note 22) IOUT 0.0 5.0 10.0 mA
18.The maximum DC current is for one output unloaded and is shown as IRD + ISS in Figure 13. This is the maximum current that the first two
stages of one output amplifier plus the reset drain bias circuit will draw. This value is with VOUT disconnected.
19.The operating value of the substrate voltage, V AB, will be marked on the shipping container for each device. The shipping container will be
marked with two VAB voltages. One VAB will be for a 600 mV charge capacity and the other VAB will be for a 1,200 mV charge capacity.
The 600 mV charge capacity is for operation of the horizontal clock at frequencies greater than 20 MHz. The 1,200 mV charge capacity VAB
value may be used for horizontal clock frequencies at or below 20 MHz.
20.VESD must be more negative than H1L, H2L and RL during sensors operation AND during camera power turn on.
21.Both VDDL and VDDR must both be supplied.
22.One output.
23.Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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Figure 13. Output Amplifier
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Floating
Diffusion
ISS
IDD
IOUT
VOUT
VDD
IRD
Reset
Drain
RD
R
AC Operating Conditions
Table 12. CLOCK LEVELS
Description Symbol Min. Nom. Max. Unit
Vertical CCD Clock High V2H 9.5 10.0 10.5 V
Vertical CCD Clocks Midlevel V1M, V2M −0.2 0.0 0.2 V
Vertical CCD Clocks Low V1L, V2L −9.5 −9.0 −8.5 V
Horizontal CCD Clocks High (Note 24) H1H, H2H −0.5 0.0 0.5 V
Horizontal CCD Clocks Low (Note 24) H1L, H2L −5.5 −5.0 −4.5 V
Reset Clock High (Note 25) RH 1.5 2.0 2.5 V
Reset Clock Low (Note 25) RL −3.5 −3.0 −2.5 V
Electronic Shutter Voltage (Note 26) VES 44 48 52 V
Fast Dump High FDH 4.0 5.0 5.5 V
Fast Dump Low FDL −9.5 −9.0 −8.5 V
24.The amplitude of the horizontal clock must be at least 4.5 V.
25.The amplitude of the reset clock must be at least 4.5 V.
26.Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
The Figure 14 shows the DC bias (SUB) and AC clock
(VES) applied to the SUB pin. Both the DC bias and AC
clock are referenced to ground.
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TIMING
Timing Requirements
Table 14. TIMING REQUIREMENTS
Description Symbol Min. Unit
HCCD Delay tHD 200 ns
VCCD Transfer Time tVCCD 200 ns
Photodiode Transfer Time tV3rd 300 ns
VCCD Pedestal Time t3P 15 ms
VCCD Delay t3D 5ms
VCCD Frame Delay t3L 15 ms
VCCD Line End Delay tEL 25 ns
HCCD Clock Period (Note 27) tH25 ns
Reset Pulse Time tR2.5 ns
Shutter Pulse Time tS1.0 ms
Shutter Pulse Delay tSD 1.0 ms
Fast Line Dump Delay tFD 75 ns
VCCD Clock Overlap tOV 50 %
27.For operation at the minimum HCCD clock period (40 MHz), the substrate voltage must be set to limit the signal at the output to 600 mV.
28.Each clock pulse width is defined for tWH or tWL.
Low 0%
10%
High 100%
90%
50%
tRtF
tWH
tOV tWL
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Timing Sequence B: Vertical CCD Line Shift and Horizontal CCD Readout of One Line
Figure 16. Timing Sequence B
V1, V1C
V2, V2C
H1
H2
V1M
V1L
V2H
V2M
V2L
H1H
H1L
H2L
H2H
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
RL, RR
RH
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
RL
tEL
tHD
tVCCD
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Timing Sequence D: No Vertical CCD Line Transfer, Readout of One Horizontal CCD Line
Figure 18. Timing Sequence D
V1, V1C
V2, V2C
H1
H2
V1M
V1L
V2H
V2M
V2L
H1H
H1L
H2L
H2H
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
RL, RR
RH
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
RL
tEL
tHD
tVCCD
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Timing Modes
Sensor Architectur e
Figure 19. Sensor Architecture
696
ÓÓ
ÓÓ
12
4
4
480
4
492
24 4 640 4 24
696
228 234234
114
V2
V1
164
164
164
114
FD FDC FD
V2
V1
V2C
V1C
ÓÓ
ÓÓ
12
When the sensor is operated in single output mode using the left output, the horizontal CCD is 708 pixels long. This assumes
no horizontal over clocking is done.
708
When the sensor is operated in dual output mode, the horizontal CCD is dived into left and right registers. Each half of the
register is 360 pixels long. This assumes no horizontal over clocking is done.
360360
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One Output Full Field
Figure 20. One Output Full Field
Sequence B
Repeat 492
FD = FDL
FDC = FDL
Sequence A
Repeat 1
FD = FDL
FDC = FDL
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
GG
R
B
V2
V1
V2
V1
V2C
V1C
FD = Inactive FDC = Inactive FD = Inactive
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
24 Dark Columns
4 Buffer Columns
24 Dark Columns
4 Buffer Columns
Pixel 1,1
640 (H) y 480 (V)
Active Pixels
12 Dummy Columns
708 HCCD Clock Cycles per Line
492 VCCD Clock Cycles
VCCD Overclocking: Allowed
HCCD Overclocking: Allowed
H1 Timing: Connect to H1S, H1BL, H2BR
H2 Timing: Connect to H2S, H2BL, H1BR
FDH = Active
FDL = Inactive
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Two Outputs Full Field
Figure 21. Two Outputs Full Field
Left Output Right Output
Pixel
1,1
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
GG
R
B
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
GG
R
B
V2
V1
V2
V1
V2C
V1C
FDC = Inactive FDC = Inactive FDC = Inactive
4 Dark Rows
4 Buffer Rows
24 Dark Columns
4 Buffer Columns
320 (H) y 480 (V)
Active Pixels
12 Dummy Columns
360 HCCD Clock Cycles per Line
492 VCCD Clock Cycles
VCCD Overclocking: Allowed
HCCD Overclocking: Allowed
H1 Timing: Connect to H1S, H1BL, H1BR
H2 Timing: Connect to H2S, H2BL, H2BR
FDH = Active
FDL = Inactive
4 Buffer Rows
320 (H) y 480 (V)
Active Pixels
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
24 Dark Columns
4 Buffer Columns
12 Dummy Columns
Sequence B
Repeat 492
FD = FDL
FDC = FDL
Sequence A
Repeat 1
FD = FDL
FDC = FDL
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One Output Center Columns
Figure 22. One Output Center Columns
GG
R
B
Pixel
207,1
V2
V1
V2
V1
V2C
V1C
FD = Active FDC = Inactive FD = Active
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
228 (H) y 480 (V)
Active Pixels
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
18 Overclock Columns
246 HCCD Clock Cycles per Line
492 VCCD Clock Cycles
VCCD Overclocking: Allowed
HCCD Overclocking: Not Allowed
H1 Timing: Connect to H1S, H1BL, H2BR
H2 Timing: Connect to H2S, H2BL, H1BR
FDH = Active
FDL = Inactive
Sequence B
Repeat 492
FD = FDH
FDC = FDL
Sequence A
Repeat 1
FD = FDH
FDC = FDL
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Two Outputs Center Columns
Figure 23. Two Outputs Center Columns
V2
V1
V2
V1
V2C
V1C
FD = Active FDC = Inactive FD = Active
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
120 HCCD Clock Cycles per Line
492 VCCD Clock Cycles
VCCD Overclocking: Allowed
HCCD Overclocking: Not Allowed
H1 Timing: Connect to H1S, H1BL, H1BR
H2 Timing: Connect to H2S, H2BL, H2BR
FDH = Active
FDL = Inactive
Sequence B
Repeat 492
FD = FDH
FDC = FDL
Sequence A
Repeat 1
FD = FDH
FDC = FDL
GG
R
B
Pixel
207,1
Left Output Right Output
GG
R
B
Pixel
321,1
114 (H) y 480 (V)
Active Pixels
114 (H) y 480 (V)
Active Pixels
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
6 Overclock Columns
6 Overclock Columns
4 Dark Rows
4 Buffer Rows
4 Buffer Rows
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One Output Center Rows
Figure 24. One Output Center Rows
V2
V1
V2
V1
V2C
V1C
FDC = Inactive
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
708 HCCD Clock Cycles per Line
163 VCCD Clock Cycles
VCCD Overclocking: Not Allowed
HCCD Overclocking: Allowed
H1 Timing: Connect to H1S, H1BL, H2BR
H2 Timing: Connect to H2S, H2BL, H1BR
FDH = Active
FDL = Inactive
FDC = InactiveFDC = Inactive
Pixel
1,157
GG
R
B
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
24 Dark Columns
24 Dark Columns
4 Buffer Columns
4 Buffer Columns
12 Dummy Columns
4 Overclock Rows
640 (H) y 164 (V)
Active Pixels
Sequence B
Repeat 163
FD = FDL
FDC = FDL
Sequence C
Repeat 1
FD = FDL
FDC = FDL
Sequence D
Repeat 1
FD = FDL
FDC = FDL
Sequence D
Repeat 4
FD = FDL
FDC = FDL
Omit this Step if the
4 Overclock Rows
are Not Needed
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Two Outputs Center Rows
Figure 25. Two Outputs Center Rows
V2
V1
V2
V1
V2C
V1C
FDC = Inactive
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
360 HCCD Clock Cycles per Line
163 VCCD Clock Cycles
VCCD Overclocking: Not Allowed
HCCD Overclocking: Allowed
H1 Timing: Connect to H1S, H1BL, H1BR
H2 Timing: Connect to H2S, H2BL, H2BR
FDH = Active
FDL = Inactive
FDC = InactiveFDC = Inactive
Sequence B
Repeat 163
FD = FDL
FDC = FDL
Sequence C
Repeat 1
FD = FDL
FDC = FDL
Sequence D
Repeat 1
FD = FDL
FDC = FDL
Sequence D
Repeat 4
FD = FDL
FDC = FDL
Omit this Step if the
4 Overclock Rows
are Not Needed
Pixel
1,157
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
Left Output Right Output
Pixel
321,157
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
GG
R
BGG
R
B
320 (H) y 164 (V)
Active Pixels 320 (H) y 164 (V)
Active Pixels
4 Buffer Columns
24 Dark Columns
12 Dummy Columns
4 Overclock Rows 4 Overclock Rows
24 Dark Columns
12 Dummy Columns
4 Buffer Columns
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One Output Center Rows and Columns
Figure 26. One Output Center Rows and Columns
V2
V1
V2
V1
V2C
V1C
FDC = Inactive
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
264 HCCD Clock Cycles per Line
163 VCCD Clock Cycles
VCCD Overclocking: Not Allowed
HCCD Overclocking: Not Allowed
H1 Timing: Connect to H1S, H1BL, H2BR
H2 Timing: Connect to H2S, H2BL, H1BR
FDH = Active
FDL = Inactive
FD = Active
Sequence B
Repeat 163
FD = FDH
FDC = FDL
Sequence C
Repeat 1
FD = FDH
FDC = FDL
Sequence D
Repeat 1
FD = FDH
FDC = FDL
Sequence D
Repeat 4
FD = FDH
FDC = FDL
Omit this Step if the
4 Overclock Rows
are Not Needed
Pixel
207, 157
GG
R
B
228 (H) y 164 (V)
Active Pixels
4 Overclock Rows
18 Overclock Columns
FD = Active
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Two Outputs Center Rows and Columns
Figure 27. Two Outputs Center Rows and Columns
V2
V1
V2
V1
V2C
V1C
FDC = Inactive
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
120 HCCD Clock Cycles per Line
163 VCCD Clock Cycles
VCCD Overclocking: Not Allowed
HCCD Overclocking: Not Allowed
H1 Timing: Connect to H1S, H1BL, H1BR
H2 Timing: Connect to H2S, H2BL, H2BR
FDH = Active
FDL = Inactive
FD = Active
Sequence B
Repeat 163
FD = FDH
FDC = FDL
Sequence C
Repeat 1
FD = FDH
FDC = FDL
Sequence D
Repeat 1
FD = FDH
FDC = FDL
Sequence D
Repeat 4
FD = FDH
FDC = FDL
Omit this Step if the
4 Overclock Rows
are Not Needed
FD = Active
Pixel
207,157
GG
R
BPixel
321,157
GG
R
B
Left Output Right Output
114 (H) y 164 (V)
Active Pixels
114 (H) y 164 (V)
Active Pixels
4 Overclock Rows4 Overclock Rows
6 Overclock Columns
6 Overclock Columns
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Timing Details
Pixel Timing
Figure 28. Pixel Timing Detail
H1
H2
RL, RR
H1H, H2H
H1L, H2L
RH
RL
tR
Vertical Clock Phase 1 − Line Timing Detail
The following timing detail applies if any of the center
row timing modes are selected. If the center row timing
modes are not to be used, then the V1 and V1C pins should
be tied together and driven from one clock driver.
During the line timing, the V1 and V1C rise and fall times
need to be identical. Since the V1 capacitance is
approximately twice the V1C capacitance, the clock driver
circuits must be adjusted to ensure equal rise and fall times.
The figure below is an example of unacceptable V1 and
V1C clock waveforms.
Incorrect
V1
V1C
The figures below are examples of acceptable V1 and
V1C clock waveforms.
Correct
V1
V1C
V1
V1C
Correct
tVCCD
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Vertical Clock Phase 2 − Line Timing Detail
The following timing detail applies if any of the center
row timing modes are selected. If the center row timing
modes are not to be used, then the V2 and V2C pins should
be tied together and driven from one clock driver.
During the line timing, the V2 and V2C rise and fall times
need to be identical. Since the V2 capacitance is
approximately twice the V2C capacitance, the clock driver
circuits must be adjusted to ensure equal rise and fall times.
The figure below is an example of unacceptable V2 and
V2C clock waveforms.
Incorrect
V2
V2C
The figures below are examples of acceptable V2 and
V2C clock waveforms.
Correct
V2
V2C
V2
V2C
Correct
tVCCD
Vertical Clock Phases 1 and 2 − Line Timing Detail
The following line timing detail applies to all modes. The
V1 and V1C clocks must be symmetrical to the V2 and V2C clocks. The figure below is an example of unacceptable V1,
V1C, V2 and V2C clock waveforms.
Incorrect
V1, V1C
V2, V2C
The figures below are of acceptable V1, V1C, V2 and
V2C clock waveforms.
Correct
Correct
tVCCD
V1, V1C
V2, V2C
V1, V1C
V2, V2C
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Vertical Clock Phase 1 − Frame Timing Detail
The following timing detail applies if any of the center
row timing modes are selected. If the center row timing
modes are not to be used, then the V1 and V1C pins should
be tied together and driven from one clock driver.
During the frame timing, the V1 and V1C rise and fall
times need to be identical. Since the V1 capacitance is
approximately twice the V1C capacitance, the clock driver
circuits must be adjusted to ensure equal rise and fall times.
The figure below is an example of unacceptable V1 and
V1C clock waveforms.
Incorrect
V1
V1C
The figures below are examples of acceptable V1 and
V1C clock waveforms
Correct
V1
V1C
V1
V1C
Correct
tVCCD
Vertical Clock Phase 2 − Frame Timing Detail
The following timing detail applies if any of the center
row timing modes are selected. If the center row timing
modes are not to be used, then the V2 and V2C pins should
be tied together and driven from one clock driver.
During the frame timing, the V2 and V2C rise and fall
times need to be identical. Since the V2 capacitance is
approximately twice the V2C capacitance, the clock driver
circuits must be adjusted to ensure equal rise and fall times.
The figure below is an example of unacceptable V2 and
V2C clock waveforms during the frame timing.
Incorrect
V2
V2C
tV3rd
The figures below are examples of acceptable V2 and
V2C clock waveforms during the frame timing.
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35
V2
V2C
Correct
V2
V2C
Correct
Vertical Clock Phases 1 and 2 − Frame Timing Detail
The following frame timing detail applies to all modes.
The V1 and V1C clocks must be symmetrical to the V2 and
V2C clocks. Also, during the tV3rd timing, the V1 and V2
waveform edges should be aligned to occur at the same time.
The figure below is an example of unacceptable V1, V1C,
V2 and V2C clock waveforms.
Incorrect
tV3rd
V1, V1C
V2, V2C
The figures below are of acceptable V1, V1C, V2 and
V2C clock waveforms.
V1, V1C
V2, V2C
Correct
V1, V1C
V2, V2C
Correct
50%
50%
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Electronic Shutter Timing
Figure 29. Electronic Shutter Timing
tEL
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
V1, V1C
V2, V2C
H1
H2
SUB
VAB
V1M
V1L
V2M
V2L
H1H
H1L
H2L
H2H
VES
tStSD tVCCD tHD
Electronic Shutter − Integration Time Definition
Figure 30. Integration Time Definition
SUB
V2, V2C
V2H
V2M
V2L
VES
VAB
Integration Time
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Fast Line Dump Timing
The figure below shows an example of dumping three
lines for all rows.
Figure 31. Fast Line Dump Timing
tFD tVCCD tFD
V2, V2C
V1, V1C
FD, FDC
H1
H2
tVCCD
Example HCCD Clock Driver
The HCCD clock inputs should be driven by buffers
capable of driving a capacitance of 40 pF and having a full
voltage swing of at least 4.7 V. A 74AC04 or equivalent is
recommended t o drive the HCCD. The HCCD requires a 0.0
to 5.0 V clock. This clock level can be obtained by
capacitive coupling and a diode to clamp the high level to
ground. Resistors R2 and R6 are used to dampen the signal
to prevent overshoots. The values of resistors R2 and R6
shown in the schematics below are only suggestions.
The actual value required should be selected for each
camera design.
Single Output Only:
Figure 32. Single Output Only
74AC04
H1 H1S (5)
H1BL (4)
H2BR (9)
74AC04
74AC04
U1A
U1B
U1C
74AC04
H2 H2S (7)
H2BL (3)
H1BR (8)
74AC04
74AC04
U1D
U1E
U1F
C1
0.1 mFR2
3 W
C2
0.1 mFR6
3 W
R1
300 kW
R5
300 kW
D2
D1
0
0
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Dual Output Only:
Figure 33. Dual Output Only
74AC04
H1 H1S (5)
H1BL (4)
H1BR (8)
74AC04
74AC04
U1A
U1B
U1C
74AC04
H2 H2S (7)
H2BL (3)
H2BR (9)
74AC04
74AC04
U1D
U1E
U1F
C1
0.1 mFR2
3 W
C2
0.1 mFR6
3 W
R1
300 kW
R5
300 kW
D2
D1
0
0
Selectable Single or Dual Output:
Figure 34. Selectable Single or Dual Output
C1
0.1 mFR2
3 W
R1
300 kW
D1
0
74AC04
H1 H1S (5)
H1BL (4)
H1BR (8)
74AC04
74AC04
U1A
U1B
U1C
H1BR
74AC04
H2 H2S (7)
H2BL (3)
H2BR (9)
74AC04
74AC04
U1D
U1E
U1FH2BR
D3 R9
300 kW
R4
3 W
C3
0.1 mF
C2
0.1 mFR6
3 W
R5
300 kW
D2
D4
R8
3 W
C4
0.1 mF
R10
300 kW
The inputs to the above circuits, H1 and H2, are 5 V logic
from the timing generator (a programmable gate array for
example). If the camera is to have selectable single or dual
output modes of operation, then the timing logic needs to
generate two extra signals for the H1BR and H2BR timing.
For single output mode program the timing such that
H1BR = H2 and H2BR = H1. For dual output mode
program the timing such that H1BR = H1 and H2BR = H2.
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39
STORAGE AND HANDLING
Table 15. CLIMATIC REQUIREMENTS
Description Symbol Minimum Maximum Unit
Temperature (Note 29) TST −55 80 °C
Humidity (Note 30) RH 5 90 %
29.Long-term exposure toward the maximum temperature will accelerate color filter degradation.
30.T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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MECHANICAL INFORMATION
Completed Assembly
Figure 35. Completed Assembly
31.See Available Part Configurations in Ordering Section for a description of the marking code.
32.Lid shall not extend beyond ceramic edge.
33.Light shield shown for reference only. Quartz version is smaller.
34.Units: IN [mm].
Notes:
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Glass Transmission
Clear Cover Glass
Figure 39. Clear Cover Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Wavelength (nm)
Transmission (%)
Quartz Cover Glass
Figure 40. Quartz Cover Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
190 290 390 490 590 690 790 890
Wavelength (nm)
Transmission (%)
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45
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