PC87570 General Description The PC87570 is a highly integrated embedded RISC based controller optimized for power management, keyboard, Real Time Clock (RTC) and system control in portable Personal Computers (PC) applications. The PC87570 incorporates Nationals GR16A high perfor- mance 16-bit RISC processor core, on-chip memories and system support functions such as: A/D, D/A, internal key- board scanning, PS/2 devices interface, Interrupt Control Unit (ICU), general purpose timers, Pulse Width Modulator Timers (PWM), system tick timers and a WATCHDOG counter, frequency-multiplier-based high frequency clock generator, power management support, ACCESS bus com- patible interface, Real Time Glock (RTC) and general pur- pose I/O ports. The PG87570's highly efficient architecture, combined with its on-chip peripherals, supporting functions and low power consumption, provides a highly integrated solution for por- table notebook PCs, sub-notebook PCs and other portable devices. Features + w CR16A 16-bit embedded RISC processor core w Internal Memory: 2 Kbytes of on-chip ROM 1024 bytes of on-chip RAM All memories can hold both code and data @ External Memory: Up to 56 Kbyte of External memory for code and data Field upgrade supported with Flash or SRAM devices Support for host controlled cade down load and update Support for sharing the BIOS memory with the PC hast @ Interrupt Control Unit: 16 maskable interrupts sources 4 general purpose External Interrupt inputs Programmable trigger mode (high or low level, falling or rising edge) Enable and pending indication tor each interrupt Non Maskable Interrupt input @ Direct Interface to external PS/2 devices: Supports three independent devices (KBC, Mouse and additional pointing device) Supports byte level handling via hardware accelerator WATCHDGG is a trademark of National Semiconductor Corporation. TRI-STATE is a registered trademark of National Semiconductor Corporation PS/2 is a registered trademark of International Business Machines Corp. ACCESS. bus is a registered trademark of Digital Equipment Corporation I?c is a registered trademark of Phillips ADVANCED INFORMATION AD vetionat Semiconductor February 1997 Keyboard and Power Management Controller @ Host Intertace: Two host intertace channels, typically used for Keyboard Control (KBC) and Power Management 8042 KBC standard Interface (Legacy addresses 60,, 64,) IR@1 and IR@Q12 support Fast Gate A20 and Fast host Reset, via firmware PM interface port (62,, 66.) PM port IR@Q11 Address selection via on chip programmable address decoder w@ Real Time Clock (RTC): DS1287, MC146818 and PC87911 compatible 242 bytes of battery backed-up CMOS RAM in two banks Calendar in days, day of the week, months, years and century with automatic leap-year adjustment Time of day in seconds, minutes and hours: - 12 or 24 hour format Optional daylight savings adjustment BCD or binary format for time keeping Three individually maskable interrupt event flags: Periodic rates from 122 us to 500 ms Time-of-day alarm once per second to once per day Separate backup battery pin Double butfer time registers Advanced Power Control - Alarm wake-up Hardware wake-up events Software off events The CMOS RAM and the RTC registers can be accessed by the CR16A firmware @ Host Interface Configuration: Mother board Plug-and-Play configuration Configuration enable key (32 elements long) Programmable address per device Enable bit per device Configuration lock bit per device Host Power Supply state detector, blocks inputs while the supply is low @ Four on-chip timers: 16-bit programmable time base counter, with 30 ps resolution and 5-bit prescaler, for system tick and periodic wake-up tasks 8-bit WATCHDOG timer 16-bit timer with 30 ps resolution 16-bit general purpose timer with PWM and Capture capabilities 1997 National Semicenducter Corporation ds012932 PrintDate=1997/02/08 PrintTime=09:52:22 ds012932 Rev. No. 4 htipiwaw.national.com Final J9]|01]U05 JUsWeBeUuRW J8aM0g pue pieogAey 0/G/89dFeatures (continued) we A/D converter: Eight 8-bit A/D channels 16 us conversion/channel Internal or external voltage reference @ D/A converter: 8-bit resolution 4 channels Rail-to-Rail output range = ACCESS. bus Interface: Intel SMBus and Phillips 1C compatible = Clock Generation Single 32.768 kHz crystal High Frequency clock generator: Using on-chip Frequency Multiplier Software controlled frequency generation @ Support for Microsoft Advanced Power Management (APM) specifications revision 1.2, February 1996. Generates the System Management Interrupt (SMI) on an I/O pin Power Management: 3.3 and 5V operation with support for mixed voltage systems 4 power states Active (TBD) Active while executing WAIT (TBD) Idle mode (10 pA) Power Off mode - RTC only (1.5 A from VBAT) Power mode switch by software and/or hardware control Automatic wakeup on system events Up to 76 General Purpose I/O ports: Bits individually configured as input or output Internal pull-up resistors Special ports for internal keyboard scan - 16-open collector outputs - 8 Schmidt inputs with intemal pull-up - Automatic wakeup on key-press Special input for On/Off Switch Control Support for off-chip implementation of additional I/O ports Active mode operating frequency 4-10 MHz 160-pin POFP and 176-pin TQFP Block Diagram | RAM CRI6A Core Core Rus Bus Acapter Peripheral Bus Unit Host RTC <B and PY l Config +APC Hest | /F AfO I fA ICU Timers and WATCHDOG Powar PWM dest SIB Bus Management | Resel and Configuratior I 3us/IF Contreller ACCESS. bus 513 Bus 3x PS/? type HF and LF KBC and {0 Parts and Clock Mouse /F Int, KB Scan Generator External Host Bus Memory {ISA Compatible) Interface tt dsoizea24 http Aawaww.national.com PrintDate=1997/02/08 PrintTime=09:52:24 ds012932 Rev. No. 4 FinalSystem Connection Diagram EXTERNAL EXTERKAL AUXILIARY KEYBOARE MOUSE PS/2 NTERFACE ITERFACE INTERFACE a a ad mn "Y "YF TY oe Ts we ate atk a =a at gS a oa oo aa ee eR 32.768 kH Re , External . Zz wterna pl 32 wRO-1 + CRYSTAL py S2KX132/CLKIN Ro-1 , vemory or a SELO + cLock < SERRE AC16:18), Af0:155 > SRAM or DC8:15) ft > FLASH D{O:7) be > _ Ly fa 2 . Su > Expansion : HAE - = $$_} HALO:18) 5 ao _ > Ho(0-7) KESCL-(0:15) > internal a | HIOR KBSIN(0:73 pt KEYBOARD 2 IW a lad HIOCHRDY PAtO:63 [A > ca | HM EMR PB(O:7) Ht > 2 * _ pc(o:7) [ > a - 5 . POCO:7) iat B | une PC87570 ok : +r Fro @ a] gtr * IROM PG(O:4) [At > SECTIONS TROB PH{O:5) |g > 4 ROW AD(O:7) Ht 4 IRO12 DAtO:3) > 4 CA20 EXINT(O.10, 11, 18) 4 . PFAIL [Me ____ 2 HRSTO ACCESS. bus + SM +J Ta, TB fe > SWIN, RING [A Pol Ly Aves |. ASND [ POWER Yoo ft SUPPLY +] FXBUSEN ASND [ft ] TRS Cenfiguration el EYV(O: 1} npvts ] SHIDM +| Favs ae $+} HEN Veat KH Baztery dsoiam22 3 http:Mwaw. national.com PrintDate=1997/02/08 PrintTime=09:52:25 ds012932 Rev. No. 4 FinalPRB/AT? Pri /a 8/SHEM bo BI D2 DS Da DS 06 OF Pros OB PFI /DS PF2/D10 PRS/ 911 Fa fD12 prs/D13 2Fa/Oid POT /D15 IRQ 12 IRO11 IRQS IRCA PAO /HMEMCS HIOR Hcw Veg 4 Yor 4 PA1/HMEMRD PA? /HMEMWR HMR HPWRON HAG HAI Hae HAS Had HAS HAG HAF HAs Pin Connection Diagrams a Sau = zr ao ba tu oO 19 MeL, aa a -Es-a win = 25 wee ee vA, mow == ma Soraaas ae oa tx = aa Op moose S tot wotancs Fei Wars STAT oe MANS Tom TtToT QOerwnte nN oof We mao ol rrr ri rbiatawaS > oo aoxngar atic t gern tare oe eee eee eae aea eat eoa Lo 120 115 119 105 109 a5 a0 a4 81 121 20 125 75 130 70 185 63 40 PC87570 60 160 PQFP 145 55 180 50 155 45 160 41 1 4 10 13 20 25 30 35 40 PEEP PPP PrP rrr rrr rrr rere POT MBP erwM ZR QEaPERSE AS at eS ey er pes ramysrse Fee GREE EE a EE EST SPSS SASS BS Sez ee zee eT Tee Brats rrrrts wa ee BHAA eRe 2 =2ze>Rs SS 8 SEU Seer eaRe re tie 7 eeoeE FIGURE 1. 160-Pin-Package Connection Diagram POS/ADS 204 /AD4 2p3/AD3 2p2/Ab2 2p fad 200/400 Vine 2FAIL 287 /SWIN BB /HRSTC 2B5/6420 ?B4/TB/ERINT 19 2B3/TA B2/ SEA B1/SCL 3 PBOSRIKG 206 /PSCLKS 207 /PSDA73 205 /EKINT15 Yop 2 Veg? 204 /EXINT1 203 /EXINTO C2 C1 C0 PSOLK2 PSN AT? 250LK1 25AaT1 <aS QUTO 44S 0UT | 4S9UT2 43S0UT3 S38 0UT4 AIS OUTS SAS OUTS 35 OUT? <3S OUTS 43S OUTS ds012502-3 http Aawaww.national.com PrintDate=1997/02/08 PrintTime=09:52:26 ds012932 Rev. No. 4 FinalPin Connection Diagrams (continued) 2 zie o ao = g 2 -2329 22 = oad SofeGbOoy aa tt = ow aww Oo moa = aes Dlesa a Foss Pers PST As sea e METS aac t tt more MT MN ook Oo AoW rr rrr iaeknwate Poo aadtatteant att ttt atte eee eee ero Khe toe LETTE PTET IEP = 130 125 120 115 110 05 100 95 90 Ps6/A1? f 155 POS/ADS PE1/418/SHEM 85 Pe pua/ana ta P23 /403 a1 i po2/aD2 be m P21/aDt C3 ] 140 P50/aD0 b4 80 [ rer o 4 Mm PrAIL D ps7 /Swiy oF P P36 /HRSTO 2FO/CB 145 PR P25 /GA20 PF1/og 75 fF P34/1B/EXINTIO PF2/010 bee P23/TA FF3/O11 po Pa2/S3a PRa/012 ee PST /SC_ P=5/015 =m 150 50/RNG Pr6/D14 4 70 fF PCS /PSCLES Pr7/015 PC? /PSIAT3 IRa12 PCS/EXINTIS et. PC87570 to>? IRQS J 155 H Ves Iko1 176 TQFP 65 FE PCa /EXINTI PAO /HMEMCS PCS/EXINTO HIoR pc2 How 4 PCI Vsg4 160 PCO pnd 60 f PSCLK2 PAL/HWEMRD P PSDATZ PA2/HMEMWR PSCLKI HMR = be PSDATI HPWRON 4 165 I KasouTO Had 55 F KBSOUTI HAT 4 KBSOUT2 Haz om KESOUTS Was 4 KBSOUT4 Had t 170 KOSOUTS HAs 4 50 F kesoure HA6 1 KBSOUT? H4?7 I P KESOUTS Hsa KBSOUTS iifa = 5 10 15 20 25 30 34 4g PETE PEP PPrtr rr Perr rrr rrereeere eee eed SOLSM SP SU SGA BER ESSER She wee SEES TSG eeresle WT SSSSSSPSSPET TT TTT TT SAS a SEB ae Reese s5h55s Bes 8 "eV OVUElV eee aes a2ee = geeeee dso1 25324 FIGURE 2. 176-Pin-Package Connection Diagram 5 http:Mwaw. national.com PrintDate=1997/02/08 PrintTime=09:52:26 ds012932 Rev. No.4 FinalSignal/Pin Descriptions Signal Type Buffer Description Table 1 lists the signals of the PC87570 in alphabetical order. OD-TTL OD output butfer, TTL input It also shows the pin associated with each signal for the 160- characteristics pin Plastic Quad Flatpack, (PQFP} and tor the 176 pin TQFP PU Weak Pull-up capability option. The Signal-Type column describes the signal type {binary input, output, or bidirectional signal, or an analog sig- PD Weak Pull-down capability nal etc.) and the butfer type for the signal. Qz-TTL TTL input: Output has GMHD1 low The signal types and associated buffer descriptions in this drive, high drive has brie CMDH1 device are as follows: capability, followed by steady-state weak pullup (PU). TABLE 1. Buffer-type Abbreviations CM-PU Output with CM and PU Signal Type Butter Description STRAP Schmid input and internal PD resistor. - (Typically used for strapped input TTL TTL input levels pins) Schmidt CMOS input levels with Hysteresis OSCIN Oscillator input cM CMOS output buffer OSCOUT Oscillator output CMHD1 rues output butfer with High Drive Analog in A/D Analog input signal ype - - - Analog out A/D Analog output signal CMHD2 CMOS output butfer with High Drive - - type 2 Analog I/O A/D Analog input/output signal CM-TTL CMOS output butter, Input TTL Some I/O pins are shared by a number of signals. Where this h i occurs, the Signal/Pin function column lists the additional characteristics signals that are multiplexed to the same pin as the signal be- oD Open Drain output ing described. OD2 Open Drain output with High Drive type 2 TABLE 2. Signal/Pin Description Table Signal Name 160-pin 176-pin Signal Type Signal/Pin Function + 32CLKIN 23 25 TTL 32.768 kHz Oscillator Clock Input. 32KX1 23 25 OSCIN 32.768 kHz Crystal Oscillator Interface. 32KX2 25 27 OSCOUT A(18-0) 122-104 136-114 Output GM Address bits 0 through 18. A18 is multiplexed with PE1 AND SHBM. A17 is multiplexed with PA6. A16 is multiplexed with PA5. A15 is multiplexed with PG1 and CBRD. AD(7-0) 82-75 92, 91, Analog Input A/D converter analog Inputs. 86-81 AD7-0 are multiplexed with PD7-0. BE1,0 118, 117 128, 127 CM Byte Enable bits 0 and 1. BST(2-0) 92, 94 102-104 Output CM Bus Status bits 0 through 2. BST2 is multiplexed with PH2 and TRIS. BST1 is multiplexed with PH1 and ENV1. BSTO is multiplexed with PHO and ENVO. CBRO 119 129 cM Core Bus Read Status on Monitor Bus Cycles. CLK 97 107 Output CM CPU Clock. CLK is multiplexed with PG2. D(7-0) 130-123 144-137 VO CNM-TTL Data bits 0 through 7. D(15-8) 138-131 152-145 VO CN-TTL Data bits 8 through 15. D15-8 are multiplexed with PF7-0 Respectively. DA(3-0) 88-85 98-95 Analog Output D/A converter analog outputs 0-3. ENV(1,0) 93, 94 103, 104 Input STRAP Environment select strap inputs 0 and 1. ENV1 is multiplexed with PH1 AND BST1. ENV0 is multiplexed with PHO AND BSTO. EXINT{0,10,11,15) | 58, 69, 59, 64, 75, 65, Input TTL External Interrupt 0, 10, 11 and 15. 62 68 http Aawaww.national.com PrintDate=1997/02/08 PrintTime=09:52:27 ds012932 Rev. No. 4 FinalSignal/Pin Descriptions (Continued) TABLE 2. Signal/Pin Description Table (Continued) Signal Name 160-pin 176-pin Signal Type Signal/Pin Function FXASTB 11 13 TTL FX Bus Address Strobe input. When enabled by FXBUSEN strap input, allows sampling of the address line on its falling edge. FXBUSEN 148 162 Input STRAP FX bus (PC87560 I/F) enable, strap input. HA(18-0) 10-1, 12-3, Input TTL Host Address lines. 160-152 174-166 Signals HA18-16 are multiplexed with signals PEO, PE4 and PE3 respectively. HAEN 1 13 Input TTL Host Address Enable. HD(7-0) 20-13 22-15 Vo Bi-directional Data bus used to interface the CMHD2-TTL PC87570 to the peripheral data bus of a host. HDEN 101 111 Input STRAP Host Device Enable, strap input. HDEN is multiplexed with RD. HIOCHRDY 12 14 Output OD2 Host If channel Ready. An open drain output that enables extending the host access. HIOR 144 158 Input TTL Host lO Read. Active low input to signal data read by the host processor. HIOW 145 159 Input TTL Host If Write signal which enables a write operation to the PC87570 through DO-D7. HMEMGS 143 157 Input TTL Host BIGS memory chip select. HMEMCS is multiplexed with PAO. HMEMRD 148 162 Input TTL Host memory read. HMEMRD multiplexed with PA1. HMEMWR 149 163 Input TTL Host memory write. HMEMWAR is multiplexed with PA2. HMR 150 164 Input Schmidt Host Master Reset. A rising edge on HMR triggers warm reset. HPWRON 151 165 Input Schmidt Host Power On Indication. HRMS 95 105 Input STRAP Host Reset Mode Select strap input. HRMS is multiplexed with SELO. HR8TS 71 7? Qutput CM Fast Host Reset Output. It is generated by the hardware and firmware. HRSTO is multiplexed with PB6. IR@1 142 156 VO Interrupt Request 1. Signals a keyboard interrupt. CMHD2-TTL ODHD2-TTL IRQS 141 155 Cutput OD2 Interrupt Request 8. Indicates a Real Time Clock (RTC) interrupt. IRQ11 140 154 VO Interrupt Request 11. Indicates an output buffer full CMHD2-TTL in the Power Management port of the host interface. OD2-TTL IRQ12 139 153 VW Interrupt Request 12. Indicates a mouse interrupt. CMHD2-TTL This bit is set when the port input buffer is full with OD2-TTL mouse data. ISE 89 99 Input TTL SE (Non Maskable) Interrupt. Reserved for use by the development system TSE is multiplexed with PH5. KBSIN(7-0) 27-34 29-36 Input Internal Keyboard input scan lines. PU-Schmidt KBSOUT(15-0) 35-40, 37-42, Output OD Internal Keyboard output sean lines. 41-50 47-56 PrintDate=1997/02/08 PrintTime=09:52:28 dsO12932 Rev. No. 4+ http:Mwaw. national.com FinalSignal/Pin Descriptions (continued) TABLE 2. Signal/Pin Description Table (Continued) Signal Name 160-pin 176-pin Signal Type Signal/Pin Function PA(60} 149, 149, 143, 121, 120, 9,8 163, 162, 157, 135, 130, 11, 10 VO CM-PU-TTL Port A, bits 0 through 6. PAZ is multiplexed with HMEMWR. PA is multiplexed with HMEMRD. PAO is multiplexed with HMEMCS. PB(7-0} 72-65 78-71 VO CM-PU-TTL Port B, bits 0 through 7. PB7 is multiplexed with SWIN. PB6 is multiplexed with HRSTO. PBS is multiplexed with GA20. PB4 is multiplexed with TB AND EXINT10. PB3 is multiplexed with TA. PB2 is multiplexed with SDA. PB1 is multiplexed with SCL. PEO is multiplexed with RING. PC(7,6) PC(5-3) PC(2-0) 63, 64, 62, 59, 58, 57-55 69, 70, 68, 65, 64, 63-61 vO CM1-PU-TTL CM-PU-TTL CMHD1-PU-TTL Port G, bits 0 through 7. PG7 is multiplexed with PSDATS3. PC6 is multiplexed with PSCLK3. PCS is multiplexed with EXINT15. PC4 is multiplexed with EXINT11. PC3 is multiplexed with EXINTO. PD(7-0) 82-75 86-81 92-91 Input TTL Port D, bits 0 through 7 PD?7-0 are multiplexed with signals AD7-0, respectively. PE(1,0) 10, 122 12, 136 VO CM-PU-TTL Port E, bits 0 through 1. PF(7-0} 138-131 152-145 VO CN-TTL Port F, bits 0 through 7. PF7-0 are multiplexed with D15-8 respectively. PFAIL 73 79 Input TTL Power Fail Interrupt Request Indication Input. PFS 91 101 Output GM Pipe Flow Status. PFS is multiplexed with PH3. PG(40) 103, 96, 97,119, 100 113, 106, 107, 129, 110 VO CM-TTL Port G, bits 0 through 4. PG4 is multiplexed with WR1. PG3 is multiplexed with SEL1. PG2 is multiplexed with CLK. PG1 is multiplexed with A15 AND CBRD. PGO is multiplexed with SELIO. PH(5-0) g9-94 99-104 VO CN-TTL Port H, bits 0 through 5. PHS is multiplexed with ISE. PH4 is multiplexed with PLI. PH3 is multiplexed with PFS. PH2 is multiplexed with BST2 AND TRIS. PH1 is multiplexed with BST1 AND ENV1. PHO is multiplexed with BSTO AND ENV0. PLI 90 100 Output Pipe Long Instruction. PLI is multiplexed with PH4. PSGLK3-1 64, 54, 52 70, 60, 58 VO Q2-TTL PS/2 channel 1 clock signal. PSCLK3 is multiplexed with PC6. PSDAT3-1 63, 53, 51 69, 59, 57 VO Qz-TTL P/2 channel 1 data signal. PSDATS3 is multiplexed with PC7. RD 101 111 Output GMHD1 Bus Read Conirol bit. May be used as an output enable (OE). RD is multiplexed with HDEN. RING 65 71 Input Schimdt Advanced Power Control (APC) RING detect and wakeup input. RING is multiplexed with PBO. http Aawaww.national.com PrintDate=1997/02/08 PrintTime=09:52:29 dsO012932 Rev. No. 4 FinalSignal/Pin Descriptions (Continued) TABLE 2. Signal/Pin Description Table (Continued) Signal Name 160-pin 176-pin Signal Type Signal/Pin Function SCL 66 72 Vo ACCESS .bus clock signal. @D-PU-Schmidt SCL is multiplexed with PB1. SDA 67 73 VO ACCESS.bus data signal. OD-PU-Schmidt SDA is multiplexed with PB2. SELO 95 105 Qutput CM Extermal Memory Chip Select (Zone 0) SELO is multiplexed with HRMS. SEL1 96 106 Cutput CM Ott chip Base Memory Chip Select (Zone 1) SEL1 is multiplexed with PG3. SELIG 100 110 Cutput CM Expansion Chip Select Zone I/O). SELIO is multiplexed with PGO. SHBM 122 136 Input STRAP Shared memory between BIOS and PC87570 firmware mode strap pin. SHBM is multiplexed with PE1 AND A18. SWIN 72 78 Input Schmidt On/Ott Switch input. SWIN is multiplexed with PB7. TA 68 74 VO CM-TTL Timer pin A. TA is multiplexed with PB3. TB 69 75 Input TTL Timer pin B. TB is multiplexed with PB4 and EXINT10. TRIS 92 102 Input STRAP TRI-STATE Control Strap pin (For ISE clip-on). TRIS is multiplexed with PH2 and BST2. WR(1,0) 103, 102 113, 112 Cutput CM Write control for bytes 0 and 1. WAR1 is multiplexed with PG4. VREF 74 80 Analog I/O A/D Reference Voltage. Used as analog Input for external reference voltage, or as analog output for filtering of internal reference voltage. Avec 83 93 Power Analog Supply. This is the 3.3V or 5V supply to the analog circuits of the A/D, D/A and Battery Manager. Voat 26 28 Power Battery Supply. This is the 2.45.5V battery voltage for the Real Time Clock (RTC) circuitry. Vee 21, 61, 98, 23, 67, Power Power Supply. +5 or +3.3 Volt supply. 147 108, 161 AGND 84 94 Power Analog Ground for the A/D, D/A and Battery Manager. GND 22, 24, 60, 24, 26, 66, Power Ground for on-chip logic, output drivers and battery 99, 146 109, 160 circuits. PrintDate=1997/02/08 PrintTime=09:52:30 ds012932 Rev. No. 4 http:Mwaw. national.com FinalPower and Grounding The PG87570 requires either a 5V 410% or a 3.3V 410% Yeo ?_ Digital Power supply to Vec and 5.5V 2.7V to Ve, pin. The digital ground pins of the PC87570 are marked GND. The battery is Yor Analog Pawer connected between V,,7 and GND. The on-chip analog cir- cuits have separate supply (marked AV...) and ground Vear (marked AGND) signals. These signals must have the same Pos7s70 voltage as the Voc and GND of the digital section. = Battery oNc Digital Ground AGNC Ae Analog Ground ds01 2502-5 FIGURE 3. Power and Ground Connections SUPPLY VOLTAGES TABLE 3. Power Supply Signal No. of Pins Function Moc 1 Analog 5V to 3.3V power supply. Voc 4 Digital 5V or 3.3V power supply. Veet 1 Battery Supply. This is the 2.4-5.5 battery voltage for the Real Time Clock {RTC) circuitry. AGND 1 Analog ground, for A/D and D/A. GND 5 Ground for both on-chip logic, output drivers and battery circuits. SUPPLY CURRENTS T, = 0C to +70C _ Veo = SV 410% Voc = 3.3V 10% . Symbol Parameter Conditions - - Units + Min Typ | Max Min Typ | Max lees Active Supply Current teL~ = 250 ns (Note 1) 30 20 mA teL~ = 100 ns (Note 1) mA lees Active Executing WAIT te_~ = 250 ns (Notes 1 and 10 6.6 mA Supply Current 2) tei~ = 100 ns (Notes 1 and mA 2) lees Idle Mode Supply Idle Mode (Notes 2 and 3) 10 10 pA Current leca VBAT Supply Current Power Off Mode (Notes 2 145 1.5 HA and 3) Note 1: Igur = 0. Ta = 25C. Vee = SV (or Ver = 3.3) Note 2: All input signals are tied to 1 or O (above Vec0.5 or below Vgg+0.5). Note 3: lout = 0. Ta = 25". Voo = S (or Ver = 3.3). operating from a 32.768 kHz crystal http Aawaww.national.com 10 PrintDate=1997/02/08 PrintTime=09:52:31 ds012932 Rev. No.4 Final 10Absolute Maximum Ratings (note 4) It MilitaryAerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature -65C to +150C Temperature Under Bias 0 to +70C All Input or Qutput Voltages, with Respect to GND Note 4: Absolute maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is net intended; operation should be limited to these conditions specified under Electrical Characteristics below. -0.5V to +6.5V 11 http:Mwaw. national.com PrintDate=1997/02/08 PrintTime=09:52:32 ds012932 Rev. No.4 Final 11{retrs PAGE IS IGNORED IN THE DATABOOK PrintDate=1997/02/08 PrintTime=09:52:32 dsO012932 Rev. No. 4 Final 12Physical Dimensions inches (milimeters) PQFP Plastic Quad Flat Package (VUL) NS Package VUL160A 13 http:Mwaw. national.com 13 PrintDate=1997/02/08 PrintTime=09:52:32 ds012932 Rev. No. 4 Final 13+ PQFP Plastic Quad Flat PC87570 Keyboard and Power Management Controller LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are davices or sys- 2. tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury Physical Dimensions inches (millimeters) (Continued) Package (VPC) NS Package VPC176A AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIGNAL SEMI- A critical component in any component ct a lite support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Lid. Japan Ltd. 1111 West Bardin Road Fax: (+49) 0-180-530 65 66 18th Floor, Straight Black, Tel: @1-048-299-2508 Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-045-299-2406 Tel: 1(800) 272-9959 Deutsch Tel: (+49) 0-160-580 65 25 Tsimshatsui, Kowloon Fax: 1(600) 737-7018 English Tel: (449) 0-180-582 78 32 Hong Kang Frangais Tal: (449) 0-180-532 93 56 Tal: (852) 2737-1600 htip Awww. national.com Italiano = Tel: (+49) 0-180-534 16 60 Fax: (852) 2736-9960 National does not assume ary responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications PrintDate=1997/02/08 PrintTime=09:52:33 ds012932 Rev. No.4 Final 14