THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Very High Speed
– 290 MHz Bandwidth (G = 1, –3 dB)
– 310 V/µs Slew Rate
– 37 ns Settling Time (0.1%)
D
Very Low Distortion
– THD = –80 dBc (f = 1 MHz, RL = 150 Ω)
D
110 mA Output Current Drive (Typical)
D
7.5 nV/√Hz Voltage Noise
D
Excellent Video Performance
– 70 MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
D
±5 V to ±15 V Supply Voltage
D
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Packages
D
Evaluation Module Available
description
The THS401 1 and THS4012 are very high speed,
single/dual, voltage feedback amplifiers ideal for
a wide range of applications. The devices offer
very good ac performance with 290-MHz
bandwidth, 310-V/µs slew rate, and 37-ns settling
time (0.1%). These amplifiers have a high output
drive capability of 110 mA and draw only 7.8-mA
supply current per channel. For applications
requiring low distortion, the THS4011/12 operate
with a total harmonic distortion (THD) of –80 dBc
at f = 1 MHz. For video applications, the
THS401 1/12 offer 0.1 dB gain flatness to 70-MHz,
0.006% differential gain error, and 0.01°
differential phase error.
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
CAUTION: THE THS4011 AND THS4012 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
NC
IN–
NC
IN+
NC
THS4012
D AND DGN† PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
–VCC
VCC+
2OUT
2IN–
2IN+
1
2
3
4
8
7
6
5
NULL
IN–
IN+
VCC–
NULL
VCC+
OUT
NC
THS4011
JG, D AND DGN PACKAGE
(TOP VIEW)
NC – No internal connection
Cross Section View Showing
PowerPAD Option (DGN)
†This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
VCC+
NC
OUT
NC
NC
NULL
NC
NULL
NC
V
NC
NC
NC
NC
THS4011
FK PACKAGE
(TOP VIEW)
CC–
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
100k 1M 10M
f – Frequency – Hz
–100
Distortion – dB
–110
2nd Harmonic
VCC = ± 15 V
RL = 150 Ω
G = 2
3rd Harmonic
AVAILABLE OPTIONS
PACKAGED DEVICES
TANUMBER OF
CHANNELS
PLASTIC
SMALL
OUTLINE†
(D)
PLASTIC
MSOP†
(DGN)
CERAMIC
DIP
(JG)
CHIP
CARRIER
(FK)
MSOP
SYMBOL EVALUATION
MODULE
0°C to 1 THS4011CD THS4011CDGN — — TIACM THS4011EVM
70°C2 THS4012CD THS4012CDGN‡— — TIABD THS4012EVM
–40°C to 1 THS4011ID THS4011IDGN — — TIACN —
85°C2 THS4012ID THS4012IDGN‡— — TIABZ —
–55°C to
125°C1 — — THS4011MJG THS4011MFK — —
†The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
‡This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
OUT
86
1
IN–
IN+
2
3
Null
–
+
Figure 1. THS4011 – Single Channel
1OUT
1IN–
1IN+
VCC
2OUT
2IN–
2IN+
–VCC
8
6
1
2
3
57
4
–
+
–
+
Figure 2. THS4012 – Dual Channel
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA, THS401xC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS401xI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS4011M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds, D, DGN package 300°C. . . . . . . . . . . . . . .
Lead temperature, 1,6 mm (1/16 inch) from case for 60 seconds, JG package 300°C. . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
DISSIPATION RATING TABLE
PACKAGE
θ
JA
θ
JC
T
A
= 25°C
PACKAGE
JA
(°C/W)
JC
(°C/W)
A
POWER RATING
D 167†38.3 740 mW
DGN‡58.4 4.7 2.14 W
JG 119 28 1050 mW
FK 87.7 20 1375 mW
†This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
‡This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to
Application Information
section of this data sheet.
recommended operating conditions
MIN NOM MAX UNIT
Su
pp
ly voltage VCC
Split supply ±4.5 ±16
V
S
u
ppl
y v
oltage
,
V
CC Single supply 9 32
V
C suffix 0 70
Operating free-air temperature, TAI suffix –40 85 °C
M suffix –55 125
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
PARAMETER TEST CONDITIONS
†
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
Unity gain bandwidth ( 3 dB)
Gain = 1
VCC = ±15 V 290
MHz
Unit
y-
gain
band
w
idth
(
–
3
dB)
Gain
=
1
VCC = ±5 V 270
MH
z
BW
Bandwidth for 0 1 dB flatness
Gain = 1
VCC = ±15 V 70
MHz
BW
Band
w
idth
for
0
.
1
dB
flatness
Gain
=
1
VCC = ±5 V 35
MH
z
Full
p
ower bandwidth (see Note 2)
VCC = ±15 V, RL = 150 ΩVO(PP) = 20 V, 4.9
MHz
F
u
ll
po
w
er
band
w
idth
(see
Note
2)
VCC = ±5 V, RL = 150 Ω, VO(PP) = 5 V, 16
MH
z
SR
Slew rate
Gain = 1 RL= 150 Ω
VCC = ±15 V 310
V/µs
SR
Sle
w
rate
Gain
= –
1
,
R
L =
150
Ω
VCC = ±5 V 260
V/
µ
s
Settling time to 0 1%
VI= 2 5 V to 2 5 V Gain = 1
VCC = ±15 V 37
ns
t
Settling
time
to
0
.
1%
V
I = –
2
.
5
V
to
2
.
5
V
,
Gain
= –
1
VCC = ±5 V 35
ns
t
s
Settling time to 0 01%
VI= 2 5 V to 2 5 V Gain = 1
VCC = ±15 V 90
ns
Settling
time
to
0
.
01%
V
I = –
2
.
5
V
to
2
.
5
V
,
Gain
= –
1
VCC = ±5 V 70
ns
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
noise/distortion performance
PARAMETER TEST CONDITIONS
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
THD Total harmonic distortion VCC = ±15 V,
VO(PP) = 2 V fc = 1 MHz, –80 dBc
VnInput voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
Differential gain error
Gain = 2,
RL150 Ω
VCC = ±15 V 0.01%
Differential
gain
error
R
L =
150
Ω
,
NTSC VCC = ±5 V 0.01%
Differential
p
hase error
Gain = 2,
RL150 Ω
VCC = ±15 V 0.01°
Differential
phase
error
R
L =
150
Ω
,
NTSC VCC = ±5 V 0.001°
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
dc performance
PARAMETER TEST CONDITIONS
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
VCC = ±15 V,
VO±10 V
TA = 25°C 10 25
V/mV
O
p
en loo
p
gain
V
O =
±10
V
,
RL = 1 kΩTA = full range 8
V/mV
Open
loop
gain
VCC = ±5 V,
VO±25V
TA = 25°C 7 12
V/mV
V
O =
±2
.
5
V
,
RL = 250 ΩTA = full range 5
V/mV
VIO
In
p
ut offset voltage
VCC =±5Vor±15 V
TA = 25°C 1 6
mV
V
IO
Inp
u
t
offset
v
oltage
V
CC =
±5
V
or
±15
V
TA = full range 8
mV
Input offset voltage drift 15 µV/°C
IIB
In
p
ut bias current
VCC =±5Vor±15 V
TA = 25°C 2 6
µA
I
IB
Inp
u
t
bias
c
u
rrent
V
CC =
±5
V
or
±15
V
TA = full range 8µ
A
IIO
In
p
ut offset current
VCC =±5Vor±15 V
TA = 25°C 25 250
nA
I
IO
Inp
u
t
offset
c
u
rrent
V
CC =
±5
V
or
±15
V
TA = full range 400
nA
Offset current drift VCC = ±5 V or ±15 V 0.3 nA/°C
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
input characteristics
PARAMETER TEST CONDITIONS
†
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
VICR
Common mode in
p
ut voltage range
VCC = ±15 V ±13 ±14.1
V
V
ICR
Common
-
mode
inp
u
t
v
oltage
range
VCC = ±5 V ±3.8 ±4.3
V
V
CC
= ±15 V, TA = 25°C 82 110 dB
CMRR
Common mode rejection ratio
CC ,
VIC = ±12 V TA = full range 77 dB
CMRR
Common
-
mode
rejection
ratio
V
CC
= ±5 V, TA = 25°C 90 95
dB
CC ,
VIC = ±2.5 V TA = full range 83
dB
RIInput resistance 2 MΩ
CIInput capacitance 1.2 pF
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
output characteristics
PARAMETER TEST CONDITIONS
†
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
VCC = ±15 V
RL=1kΩ
±13 ±13.5
VO
Out
p
ut voltage swing
VCC = ±5 V
R
L =
1
kΩ
±3.4 ±3.7
V
V
O
O
u
tp
u
t
v
oltage
s
w
ing
VCC = ±15 V RL = 250 Ω±12 ±13
V
VCC = ±5 V RL = 150 Ω±3±3.4
IO
Out
p
ut current
RL=20Ω
VCC = ±15 V 70 110
mA
I
O
O
u
tp
u
t
c
u
rrent
R
L =
20
Ω
,VCC = ±5 V 50 75
mA
IOS Short-circuit output current VCC = ±15 V 150 mA
ROOutput resistance Open loop 12 Ω
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
power supply
PARAMETER TEST CONDITIONS
†
THS4011C/I,
THS4012C/I UNIT
MIN TYP MAX
VCC
Su
pp
ly voltage
Dual supply ±4.5 ±16.5
V
V
CC
S
u
ppl
y v
oltage
Single supply 9 33
V
VCC =±15 V
TA = 25°C 7.8 9.5
ICC
Su
pp
ly current (each am
p
lifier)
V
CC =
±15
V
TA = full range 11
mA
I
CC
S
u
ppl
y
c
u
rrent
(each
amplifier)
VCC =±5V
TA = 25°C 6.9 8.5
mA
V
CC =
±5
V
TA = full range 10
PSRR
Power su
pp
ly rejection ratio
VCC =±5Vto±15 V
TA = 25°C 75 83
dB
PSRR
Po
w
er
s
u
ppl
y
rejection
ratio
V
CC =
±5
V
to
±15
V
TA = full range 68
dB
†Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
PARAMETER
TEST CONDITIONS†
THS4011M
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX
UNIT
Unity-gain bandwidth Closed loop, RL = 1 kΩVCC = ±15 V *160 200 MHz
VCC = ±15 V 70
BW
Bandwidth for 0.1 dB flatness Gain = 1 VCC = ±5 V 35 MHz
BW
VCC = ±2.5 V 30
Full
p
ower bandwidth (see Note 1)
VCC = ±15 V, RL = 150 Ω, VO(PP) = 20 V 2.5
MHz
F
u
ll
po
w
er
band
w
idth
(see
Note
1)
VCC = ±5 V, RL = 150 Ω, VO(PP) = 20 V 8
MH
z
SR Slew rate VCC = ±15 V, RL = 1 kΩ*300 400 V/µs
Settling time to 0 1%
VI= 2 5 V to 2 5 V Gain = 1
VCC = ±15 V 37
ns
t
Settling
time
to
0
.
1%
V
I = –
2
.
5
V
to
2
.
5
V
,
Gain
= –
1
VCC = ±5 V 35
ns
t
s
Settling time to 0 01%
VI= 2 5 V to 2 5 V Gain = 1
VCC = ±15 V 90
ns
Settling
time
to
0
.
01%
V
I = –
2
.
5
V
to
2
.
5
V
,
Gain
= –
1
VCC = ±5 V 70
ns
†Full range = –55°C to 125°C for the M suffix.
*This parameter is not tested.
NOTE 1: Full pwer bandwidth = slew rate/2π V(PP).
noise/distortion performance
PARAMETER
THS4011M
UNIT
PARAMETER
MIN TYP MAX
UNIT
THD Total harmonic distortion VCC = ±15 V, fc = 1 MHz,
VO(PP) = 1 V –80 dBc
VnInput voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
Differential gain error
Gain = 2,
RL150 Ω
VCC = ±15 V 0.006
%
Differential
gain
error
R
L =
150
Ω
,
NTSC VCC = ±5 V 0.001
%
Differential
p
hase error
Gain = 2,
RL= 150 Ω
VCC = ±15 V 0.01°
Differential
phase
error
RL
=
150
Ω
,
NTSC VCC = ±5 V 0.002°
†Full range = –55°C to 125°C for the M suffix.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
dc performance
PARAMETER
THS4011M
UNIT
PARAMETER
MIN TYP MAX
UNIT
O
p
en loo
p
gain
VCC = ±15 V, VO = ±10 V,
RL = 1 kΩTA = full range 6 14 V/mV
Open
loop
gain
VCC = ±5 V, VO = ±2.5 V,
RL = 1 kΩTA = full range 5 10 V/mV
VIO
In
p
ut offset voltage
VCC =±5Vor±15 V
TA = 25°C 2 6
mV
V
IO
Inp
u
t
offset
v
oltage
V
CC =
±5
V
or
±15
V
TA = full range 2 8
mV
Input offset voltage drift VCC = ±5 V or ±15 V 15 µV/°C
IIB
In
p
ut bias current
VCC =±5Vor±15 V
TA = 25°C 2 6
µA
I
IB
Inp
u
t
bias
c
u
rrent
V
CC =
±5
V
or
±15
V
TA = full range 4 8 µ
A
IIO Input offset current VCC = ±5 V or ±15 V 25 250 nA
Offset current drift VCC = ±5 V or ±15 V TA = 25°C 0.3 nA/°C
†Full range = –55°C to 125°C for the M suffix.
input characteristics
PARAMETER
TEST CONDITIONS†
THS4011M
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX
UNIT
VICR
Common mode in
p
ut voltage range
VCC = ±15 V ±13 ±14.1
V
V
ICR
Common
-
mode
inp
u
t
v
oltage
range
VCC = ±5 V ±3.8 ±4.3
V
CMRR
Common mode rejection ratio
VCC = ±15 V, VIC = ±12 V 75 90
dB
CMRR
Common
-
mode
rejection
ratio
VCC = ±5 V, VIC = ±2.5 V 84 95
dB
RIInput resistance 2 MΩ
CIInput capacitance 1.2 pF
†Full range = –55°C to 125°C for the M suffix.
output characteristics
PARAMETER
TEST CONDITIONS†
THS4011M
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V
RL=1kΩ
±13 ±13.5
VO
Out
p
ut voltage swing
VCC = ±5 V
R
L =
1
kΩ
±3.4 ±3.7
V
V
O
O
u
tp
u
t
v
oltage
s
w
ing
VCC = ±15 V RL = 250 Ω±12 ±13
V
VCC = ±5 V RL = 150 Ω±3±3.4
IO
Out
p
ut current
VCC = ±15 V
RL=20Ω
70 115
mA
I
O
O
u
tp
u
t
c
u
rrent
VCC = ±5 V
R
L =
20
Ω
50 75
mA
IOS Short-circuit output current VCC = ±15 V TA = 25°C 150 mA
ROOutput resistance Open loop 12 Ω
†Full range = –55°C to 125°C for the M suffix.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
power supply
PARAMETER
TEST CONDITIONS†
THS4011M
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX
UNIT
VCC
Su
pp
ly voltage
Dual supply ±4.5 ±16.5
V
V
CC
S
u
ppl
y v
oltage
Single supply 9 33
V
VCC =±15 V
TA = 25°C 7.8 9.5
ICC
Quiescent current
V
CC =
±15
V
TA = full range 11
mA
I
CC
Q
u
iescent
c
u
rrent
VCC =±5V
TA = 25°C 6.9 8.5
mA
V
CC =
±5
V
TA = full range 10
PSRR
Power su
pp
ly rejection ratio
VCC =±5Vto±15 V
TA = 25°C 80 86
dB
PSRR
Po
w
er
s
u
ppl
y
rejection
ratio
V
CC =
±5
V
to
±15
V
TA = full range 78 83
dB
†Full range = –55°C to 125°C for the M suffix.
PARAMETER MEASUREMENT INFORMATION
_
+
1.5 kΩ
50 Ω150 Ω
VO1
VI1
1.5 kΩ
CH1
_
+
50 Ω
150 Ω
VO2 VI2
CH2
1.5 kΩ1.5 kΩ
Figure 3. THS4012 Crosstalk Test Circuit
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
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TYPICAL CHARACTERISTICS
Figure 4
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
1.2
1
0.8
0.6
0.4
0.2
–40 –20 0 20 40 60
TA – Free-AIR Temperature –
_
C
V
0
IO – Input Offset Voltage – mV
80 100
1.4 VCC = ±15 V
Figure 5
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
Iib – Input Bias Current – uA
3
2.5
2
1.5
1
0
–40 –20 0 20 40 60 80 100
TA – Free-Air Temperature –
_
C
VCC = ±15 V or ±5 V
0.5
Figure 6
OUPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
12
10
8
6
4
57 9111315
|V V
2
– Output Voltage Swing –
±VCC – Supply Voltage – V
O|
TA = 25° C
RL = 150 Ω
RL = 1 kΩ
Figure 7
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
Maximum Output Voltage Swing –
12.5
12
4.5
4
3.5
2.5
–40 –20 0 20 40 60 80 100
TA – Free-Air Temperature –
_
C
3
13.5
13
±V
14
VCC = ± 5 V
RL = 150 Ω
VCC = ± 5 V
RL = 1 kΩ
VCC = ± 15 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
Figure 8
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
13
11
9
7
5
57 9111315
3
±VCC – Supply Voltage – V
TA = 25° C
Input Common-Mode Range – V
VIC –
Figure 9
PSRR
vs
FREQUENCY
100
80
60
40
20
1k 10k 100k 1M
0
PSRR – Power-Supply Rejection Ratio – dB
f – Frequency – Hz10M 100M
VCC = ±15 V or ±5 V
90
70
50
30
10
Figure 10
CMRR
vs
FREQUENCY
120
100
80
60
40
20
1k 10k 100k 1M
0
CMRR – Common-Mode Rejection Ratio – dB
f – Frequency – Hz10M 100M
VCC ±5V
VCC ±15V
Figure 11
CROSSTALK
vs
FREQUENCY
–40
–60
100k 10M 100M
–90
Crosstalk – dB
f – Frequency – Hz
1M
–80
–50
–70 VI = CH1
VO = CH2
1G
VI = CH2
VO = CH1
0
–30
–20
–10 VCC ±15V
Figure 12
OPEN-LOOP GAIN RESPONSE
80
1k 100K 1M
–20
Open0Loop Gain – dB
f – Frequency – Hz
10K
0
60
20
40
100
10M 100M 1G
VCC ±5V
VCC ±15V
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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TYPICAL CHARACTERISTICS
Figure 13
DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
100k 1M 10M
f – Frequency – Hz
–100
Distortion – dB
–110
2nd Harmonic
VCC = ± 15 V
RL = 1 kΩ
G = 2
3rd Harmonic
Figure 14
DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
100k 1M 10M
f – Frequency – Hz
–100
Distortion – dB
–110
2nd Harmonic
VCC = ± 5 V
RL = 1 kΩ
G = 2
3rd Harmonic
Figure 15
DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
100k 1M 10M
f – Frequency – Hz
–100
Distortion – dB
–110
2nd Harmonic
VCC = ± 15 V
RL = 150 Ω
G = 2
3rd Harmonic
Figure 16
DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
100k 1M 10M
f – Frequency – Hz
–100
Distortion – dB
–110
2nd Harmonic
VCC = ± 5 V
RL = 150 Ω
G = 2
3rd Harmonic
Figure 17
OUTPUT AMPLITUDE
vs
FREQUENCY
Output Amplitude – dB
5
0
–5
–10
–15
0
100k 1M 10M 100M 1G
f – Frequency – Hz
–20
–25
Rf = 270 Ω
VCC = ± 15 V
RL = 150 Ω
G = 1
Rf = 100 Ω
Figure 18
OUTPUT AMPLITUDE
vs
FREQUENCY
Output Amplitude – dB
5
0
–5
–10
–15
100k 1M 10M 100M 1G
f – Frequency – Hz
–20
Rf = 270 Ω
VCC = ± 5 V
RL = 150 Ω
G = 1
Rf = 100 Ω
Figure 19
NOISE SPECTRAL DENSITY
vs
FREQUENCY
100
10 100 1k
f – Frequency – Hz
10
10k
1100k
Noise Spectral Density
VCC = ±15 V or ±5 V
Figure 20
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.2°
0.15°
0.1°
1234
Number of 150-Ω Loads
0.05°
Differential Phase
0°
0.35°
0.3°
0.25°
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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TYPICAL CHARACTERISTICS
Figure 21
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.25°
0.2°
0.15°
0.1°
1234
Number of 150-Ω Loads
0.05°
Differential Phase
0°
Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
0.4°
0.35°
0.3°
VCC = ± 15 V
VCC = ± 5 V
Figure 22
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.03
0.02
1234
Number of 150-Ω Loads
0.01
Differential Gain – %
0
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ±100 IRE Ramp
VCC = ± 5 V
VCC = ± 15 V
0.04
0.05
Figure 23
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.03
0.02
1234
Number of 150-Ω Loads
0.01
Differential Gain – %
0
0.04
0.05
0.06 Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
theory of operation
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
IN– (2)
IN+ (3)
NULL (1) NULL (8)
(6) OUT
(4) VCC–
(7) VCC+
Figure 24. THS4011 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
•en = Amplifier internal voltage noise (nV/√Hz)
•IN+ = Noninverting current noise (pA/√Hz)
•IN– = Inverting current noise (pA/√Hz)
•eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
_
+
RF
RS
RG
eRg
eRf
eRs en
IN+
Noiseless
IN–
eni eno
Figure 25. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
eni
+ǒ
en
Ǔ
2
)ǒ
IN
)
RS
Ǔ
2
)ǒ
IN–
ǒ
RF
ø
RG
ǓǓ
2
)
4kTR
s
)
4kT
ǒ
RF
ø
RG
Ǔ
Ǹ
Where: k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
eno
+
eni AV
+
eni
ǒ
1
)
RF
RG
Ǔ
(noninverting case)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the
Noise Analysis
section in
Operational Amplifier
Circuits Applications Report
(literature number SLVA043).
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF
+
10log
ȧ
ȧ
ȱ
Ȳ
e2
ni
ǒ
eRs
Ǔ
2
ȧ
ȧ
ȳ
ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
NF
+
10log
ȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1
)
ȧ
ȡ
Ȣǒ
en
Ǔ
2
)ǒ
IN
)
RS
Ǔ
2
ȧ
ȣ
Ȥ
4kTR
S
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
Figure 26 shows the noise figure graph for the THS401x.
20
5
010 100
Noise Figure – dB
25
NOISE FIGURE
vs
SOURCE RESISTANCE
30
1 k 100 k
15
10
Source Resistance – Ω
f = 10 kHz
TA = 25°C
10 k
Figure 26. Noise Figure vs Source Resistance
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS401x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
+
_
THS401x
CLOAD
1.3 kΩ
Input
Output
1.3 kΩ
20 Ω
Figure 27. Driving a Capacitive Load
offset nulling
The THS401x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply . This
is shown in Figure 28.
_
+
THS4011
VCC–
VCC+
0.1 µF
0.1 µF
10 kΩ
Figure 28. Offset Nulling Schematic
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO
+
VIO
ǒ
1
)ǒ
RF
RG
ǓǓ"
IIB
)
RS
ǒ
1
)ǒ
RF
RG
ǓǓ"
IIB– RF
+
–
VI+
RG
RS
RF
IIB–
VO
IIB+
Figure 29. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS401x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should
be used as shown in Figure 30. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
_
+
THS401x
100 Ω
Input
Output
Figure 30. Noninverting, Unity Gain Schematic
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer
(see Figure 31).
VIVO
C1
+
–
RGRF
R1
f–3dB
+
1
2
p
R1C1
VO
VI
+ǒ
1
)
RF
RG
Ǔǒ
1
1
)
sR1C1
Ǔ
Figure 31. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 – )
RGRF
_
+f–3dB
+
1
2
p
RC
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS401x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS401x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 34. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 34. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier .
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS401xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4
_
C/W . For comparison, the non-PowerPAD version of
the THS401x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 35 and
is calculated by the following formula:
PD
+ǒ
TMAX–TA
q
JA
Ǔ
Where: PD= Maximum power dissipation of THS401x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θJA = 98°C/W
TJ = 150°C
SOIC Package
Low-K Test PCB
θJA = 167°C/W
2
1.5
1
0
–40 –20 0 20 40
Maximum Power Dissipation – W
2.5
3
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
60 80 100
0.5
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and PCB size = 3”×3”
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced Package.
This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, there is
generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is
severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how
the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But,
the device should always be soldered to a copper plane to fully use the heat dissipation properties of the
PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As
more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability
increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier
package (THS4012), the sum of the RMS output currents and voltages should be used to choose the proper
package.
Figure 36
Package With
θJA < = 120°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ± 5 V
Tj = 150°C
TA = 50°C
100
80
40
0012 3
– Maximum RMS Output Current – mA
140
180
200
45
160
120
60
20
| VO | – RMS Output Voltage – V
IO
||
Maximum Output
Current Limit Line
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating
Area
Figure 37
100
10 0369
1000
12 15
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
SO-8 Package
θJA = 98°C/W
High-K Test PCB
TJ = 150°C
TA = 50°C
| VO | – RMS Output Voltage – V
– Maximum RMS Output Current – mA
IO
||
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating
Area
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Figure 38
Package With
θJA ≤ 60°C/W
SO-8 Package
θJA = 98°C/W
High-K Test PCB
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
100
80
40
0012 3
– Maximum RMS Output Current – mA
140
180
200
45
160
120
60
20
| VO | – RMS Output Voltage – V
IO
||
Maximum Output
Current Limit Line
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating Area
Figure 39
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
| VO | – RMS Output Voltage – V
– Maximum RMS Output Current – mA
IO
||
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
DGN Package
θJA = 58.4°C/W
Safe Operating Area
SO-8 Package
θJA = 98°C/W
High-K Test PCB
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier . A schematic of the THS401 1 evaluation board is shown in Figure 40. The circuitry
has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For
more information, please refer to the
THS4011 EVM User’s Guide
(literature number SLOU028) or the
THS4012
EVM User’s Guide
(literature number SLOU041) To order the evaluation board contact your local TI sales office
or distributor.
_
+
THS4011
VCC–
VCC+
C3
6.8 µF
C4
0.1 µF
C1
6.8 µF
C2
0.1 µF
R1
1 kΩ
R5
1 kΩ
R3
49.9 Ω
R2
49.9 Ω
R4
49.9 Ω
IN–
IN+
NULL
OUT
NULL
+
+
Figure 40. THS4011 Evaluation Board
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/A 04/98
4,98
0,25
5
3,05 4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65 M
0,25
0°–6°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUAR Y 2000
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,20)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
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