1
®HFA1130
850MHz, Output Limiting, Low Distortion
Current Feedback Operational Amplifier
The HFA1130 is a high speed wideband current feedback
amplifier featuring programmable output limits. Built with
Intersil’s proprietary complementary bipolar UHF-1 process,
it is the fastest monolithic amplifier available from any
semiconductor manufacturer.
This amplifier is the ideal choice for high frequency
applications requiring output limiting, especially those needing
ultra fast overdrive recovery times. The output limiting function
allows the designer to set the maximum positive and negative
output levels, thereby protecting later stages from damage or
input saturation. The sub-nanosecond overdrive recovery time
quickly returns the amplifier to linear operation, following an
overdrive condition.
The HFA1130 offers significant performance improvements
over the CLC500/501/502.
The Op Amps with Fastest Edges
Features
• User Programmable Output Voltage Limits
• Low Distortion (30MHz, HD2) . . . . . . . . . . . . . . . . -56dBc
• -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 850MHz
• Very Fast Slew Rate. . . . . . . . . . . . . . . . . . . . . . 2300V/µs
• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . . 11ns
• Excellent Gain Flatness
- (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.14dB
- (50MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04dB
- (30MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01dB
• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . 60mA
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Residue Amplifier
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Flash A/D Driver
• Medical Imaging Systems
• Related Literature
- AN9420, Current Feedback Theory
- AN9202, HFA11XX Evaluation Fixture
Pinout
HFA1130 (SOIC)
TOP VIEW
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
HFA1130IB
(H1130I)
-40 to 85 8 Ld SOIC M8.15
HFA1130IBZ (Note)
(H1130IBZ)
-40 to 85 8 Ld SOIC (Pb-free) M8.15
HFA1130IBZ-T (Note)
(H1130IBZ)
-40 to 85 8 Ld SOIC (Pb-free) M8.15
HFA11XXEVAL DIP Evaluation Board for High-Speed Op
Amps
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
INPUT
220MHz
SIGNAL
OUTPUT
(AV = 2)
HFA1130
OP AMP
0ns 25ns
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
VH
V+
OUT
VL
-
+
Data Sheet July 15, 2005 FN3369.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN3369.4
July 15, 2005
Absolute Maximum Ratings TA = 25°C Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . -65°C to TA to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified
PARAMETER
TEST
CONDITIONS
(NOTE 2)
TEST
LEVEL
TEMP.
(°C) MIN TYP MAX UNITS
INPUT CHARACTERISTICS
Input Offset Voltage (Note 3) A 25 - 2 6 mV
AFull - - 10 mV
Input Offset Voltage Drift C Full - 10 - µV/°C
VIO CMRR ∆VCM = ±2V A 25 40 46 - dB
AFull 38 - - dB
VIO PSRR ∆VS = ±1.25V A 25 45 50 - dB
AFull 42 - - dB
Non-Inverting Input Bias Current
(Note 3)
+IN = 0V A 25 - 25 40 µA
AFull - - 65 µA
+IBIAS Drift C Full - 40 - nA/°C
+IBIAS CMS ∆VCM = ±2V A 25 - 20 40 µA/V
AFull - - 50 µA/V
Inverting Input Bias Current (Note 3) -IN = 0V A 25 - 12 50 µA
AFull - - 60 µA
-IBIAS Drift C Full - 40 - nA/°C
-IBIAS CMS ∆VCM = ±2V A 25 - 1 7 µA/V
AFull - - 10 µA/V
-IBIAS PSS ∆VS = ±1.25V A 25 - 6 15 µA/V
AFull - - 27 µA/V
Non-Inverting Input Resistance A 25 25 50 - kΩ
Inverting Input Resistance C 25 - 20 30 Ω
Input Capacitance (Either Input) B 25 - 2 - pF
Input Common Mode Range C Full ±2.5 ±3.0 - V
Input Noise Voltage (Note 3) 100kHz B 25 - 4 - nV/√Hz
+Input Noise Current (Note 3) 100kHz B 25 - 18 - pA/√Hz
-Input Noise Current (Note 3) 100kHz B 25 - 21 - pA/√Hz
TRANSFER CHARACTERISTICS AV = +2, Unless Otherwise Specified
Open Loop Transimpedance (Note 3) B 25 - 300 - kΩ
HFA1130
3FN3369.4
July 15, 2005
-3dB Bandwidth (Note 3) VOUT = 0.2VP-P
,
AV = +1
B 25 530 850 - MHz
-3dB Bandwidth VOUT = 0.2VP-P
,
AV = +2, RF = 360Ω
B25 - 670 - MHz
Full Power Bandwidth 4VP-P
, AV = -1 B Full - 300 - MHz
Gain Flatness (Note 3) To 100MHz B 25 - ±0.14 - dB
Gain Flatness To 50MHz B 25 - ±0.04 - dB
Gain Flatness To 30MHz B 25 - ±0.01 - dB
Linear Phase Deviation (Note 3) DC to 100MHz B 25 - 0.6 - Degrees
Differential Gain NTSC, RL = 75ΩB 25 - 0.03 - %
Differential Phase NTSC, RL = 75ΩB 25 - 0.05 - Degrees
Minimum Stable Gain A Full 1 - - V/V
OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Specified
Output Voltage (Note 3) AV = -1 A 25 ±3.0 ±3.3 - V
AFull±2.5 ±3.0 - V
Output Current RL = 50Ω, AV = -1 A 25, 85 50 60 - mA
A -40 35 50 - mA
DC Closed Loop Output Impedance
(Note 3)
B 25 - 0.07 - Ω
2nd Harmonic Distortion (Note 3) 30MHz, VOUT = 2VP-P B25 - -56 - dBc
3rd Harmonic Distortion (Note 3) 30MHz, VOUT = 2VP-P B25 - -80 - dBc
3rd Order Intercept (Note 3) 100MHz B 25 20 30 - dBm
1dB Compression 100MHz B 25 15 20 - dBm
TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified
Rise Time VOUT = 2.0V Step B 25 - 900 - ps
Overshoot (Note 3) VOUT = 2.0V Step B 25 - 10 - %
Slew Rate AV = +1,
VOUT = 5VP-P
B 25 - 1400 - V/µs
AV = +2,
VOUT = 5VP-P
B 25 1850 2300 - V/µs
0.1% Settling Time (Note 3) VOUT = 2V to 0V B 25 - 11 - ns
0.2% Settling Time (Note 3) VOUT = 2V to 0V B 25 - 7 - ns
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range B Full ±4.5 - ±5.5 V
Supply Current (Note 3) A 25 - 21 26 mA
AFull - - 33 mA
LIMITING CHARACTERISTICS AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified
Clamp Accuracy VIN = ±2V, AV = -1 A 25 - 60 ±125 mV
Clamped Overshoot VIN = ±1V,
Input tR/tF = 2ns
B25 - 4 - %
Overdrive Recovery Time VIN = ±1V B 25 - 0.75 1.5 ns
Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
PARAMETER
TEST
CONDITIONS
(NOTE 2)
TEST
LEVEL
TEMP.
(°C) MIN TYP MAX UNITS
HFA1130
4FN3369.4
July 15, 2005
Application Information
Optimum Feedback Resistor (RF)
The enclosed plots of inverting and non-inverting frequency
response detail the performance of the HFA1130 in various
gains. Although the bandwidth dependency on ACL isn’t as
severe as that of a voltage feedback amplifier, there is an
appreciable decrease in bandwidth at higher gains. This
decrease can be minimized by taking advantage of the current
feedback amplifier’s unique relationship between bandwidth
and RF. All current feedback amplifiers require a feedback
resistor, even for unity gain applications, and the RF, in
conjunction with the internal compensation capacitor, sets the
dominant pole of the frequency response. Thus, the
amplifier’s bandwidth is inversely proportional to RF. The
HFA1130 design is optimized for a 510Ω RF, at a gain of +1.
Decreasing RF in a unity gain application decreases stability,
resulting in excessive peaking and overshoot (Note:
Capacitive feedback causes the same problems due to the
feedback impedance decrease at higher frequencies). At
higher gains the amplifier is more stable, so RF can be
decreased in a trade-off of stability for bandwidth. The table
below lists recommended RF values for various gains, and the
expected bandwidth.
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (pins 8 and
5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces -IN
to track +IN, and sets up a slewing current of (V-IN -V
OUT)/RF.
This current is mirrored onto the high impedance node (Z) by
QX3-QX4, where it is converted to a voltage and fed to the output
via another unity gain buffer. If no clamping is utilized, the high
impedance node may swing within the limits defined by QP4 and
QN4. Note that when the output reaches it’s quiescent value, the
current flowing through -IN is reduced to only that small current
(-IBIAS) required to keep the output at the final voltage.
Tracing the path from VH to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
Negative Clamp Range B 25 - -5.0 to +2.0 - V
Positive Clamp Range B 25 - -2.0 to +5.0 - V
Clamp Input Bias Current A 25 - 50 200 µA
Clamp Input Bandwidth VH or VL = 100mVP-P B25 - 500 - MHz
NOTES:
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
3. See Typical Performance Curves for more information.
Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
PARAMETER
TEST
CONDITIONS
(NOTE 2)
TEST
LEVEL
TEMP.
(°C) MIN TYP MAX UNITS
ACL RF (Ω)BW (MHz)
+1 510 850
-1 430 580
+2 360 670
+5 150 520
+10 180 240
+19 270 125
+1
+IN V-
V+
QP1
QN1
V-
QN3
QP3 QP4
QN2
QP2
QN4 QP5
QN5
Z
V+
-IN VOUT
ICLAMP
RF
(EXTERNAL)
QP6
QN6
VH
R1
50K
(30K
FOR VL)
200Ω
FIGURE 1. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
HFA1130
5FN3369.4
July 15, 2005
reaches a voltage equal to QP5’s base + 2VBE (QP5 and
QN5). Thus, QP5 clamps node Z whenever Z reaches VH.
R1 provides a pull-up network to ensure functionality with the
clamp inputs floating. A similar description applies to the
symmetrical low clamp circuitry controlled by VL.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the
output to the quiescent voltage defined by the input. QP5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as (V-IN - VOUT)/RF. As
an example, a unity gain circuit with VIN = 2V, VH = 1V, and
RF = 510Ω would have ICLAMP = (2-1)/510Ω = 1.96mA.
Note that ICC will increase by ICLAMP when the output is
clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to VH or VL. Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which is
found in the device specifications. Clamp accuracy is a function
of the clamping conditions. Referring again to Figure 1, it can
be seen that one component of clamp accuracy is the VBE
mismatch between the QX6 transistors, and the QX5
transistors. If the transistors always ran at the same current
level there would be no VBE mismatch, and no contribution to
the inaccuracy. The QX6 transistors are biased at a constant
current, but as described earlier, the current through QX5 is
equivalent to ICLAMP. VBE increases as ICLAMP increases,
causing the clamped output voltage to increase as well. ICLAMP
is a function of the overdrive level (V-IN -VOUTCLAMPED) and
RF, so clamp accuracy degrades as the overdrive increases, or
as RF decreases. As an example, the specified accuracy of
±60mV for a 2X overdrive with RF= 510Ω degrades to ±220mV
for RF= 240Ω at the same overdrive, or to ±250mV for a 3X
overdrive with RF = 510Ω.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve in the data sheet
illustrates the impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both VH and VL have usable
ranges that cross 0V. While VH must be more positive than VL,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HFA1130 could
be limited to ECL output levels by setting VH= -0.8V and
VL= -1.8V. VH and VL may be connected to the same voltage
(GND for instance) but the result won’t be in a DC output
voltage from an AC input signal. A 150 - 200mV AC signal will
still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMP/A
VCL) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1130’s
subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed.
Note: The propagation delay illustrated is dominated by the
fixturing. The delta shown is accurate, but the true HFA1130
propagation delay is 500ps.
Use of Die in Hybrid Applications
This amplifier is designed with compensation to negate the
package parasitics that typically lead to instabilities. As a
result, the use of die in hybrid applications results in
overcompensated performance due to lower parasitic
capacitances. Reducing RF below the recommended values
for packaged units will solve the problem. For AV = +2 the
recommended starting point is 300Ω, while unity gain
applications should try 400Ω.
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown below.
HFA1130
6FN3369.4
July 15, 2005
Evaluation Board
An evaluation board is available for the HFA1130, (Part
Number HFA11XXEVAL). Please contact your local sales
office for information.
Note: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part
Number 08-350000-10.
The layout and schematic of the board are shown here:
1
2
3
4
8
7
6
5
+5V
10µF0.1µF
VH
50Ω
GND
GND
500Ω
500Ω
-5V
0.1µF10µF
50Ω
IN OUT
VL
FIGURE 2. BOARD SCHEMATIC
VH
+IN
VLV+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified
FIGURE 3. SMALL SIGNAL PULSE RESPONSE FIGURE 4. LARGE SIGNAL PULSE RESPONSE
120
TIME (5ns/DIV.)
90
60
30
0
-30
-60
-90
-120
OUTPUT VOLTAGE (mV)
AV = +2
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
1.2
0.9
0.6
0.3
0
-0.3
-0.6
-0.9
-1.2
AV = +2
HFA1130
7FN3369.4
July 15, 2005
FIGURE 5. UNCLAMPED PERFORMANCE FIGURE 6. CLAMPED PERFORMANCE
FIGURE 7. NON-INVERTING FREQUENCY RESPONSE FIGURE 8. INVERTING FREQUENCY RESPONSE
FIGURE 9. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FIGURE 10. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified (Continued)
IN
0V TO 0.5 V
OUT
0V TO 1V
TIME (10ns/DIV.)
AV = +2, VH = 2V, VL = -2V
IN
0V TO 1V
OUT
0V TO 1V
TIME (10ns/DIV.)
AV = +2, VH = 1V, VL = -1V, 2X OVERDRIVE
FREQUENCY (MHz)
0
-3
-6
-9
-12
NORMALIZED GAIN (dB)
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
PHASE
GAIN
AV = +11
AV = +1
AV = +6
AV = +11
AV = +1
AV = +6
AV = +2
AV = +2
VOUT = 200mVP-P
FREQUENCY (MHz)
PHASE
GAIN
0
-3
-6
-9
-12
NORMALIZED GAIN (dB)
0.3 1 10 100 1K
180
90
0
-90
-180
PHASE (DEGREES)
AV = -5
AV = -1
AV = -10
AV = -20
AV = -20
AV = -10
AV = -5
AV = -1
VOUT = 200mVP-P
FREQUENCY (MHz)
6
3
0
-3
-6
GAIN (dB)
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
PHASE
GAIN
RL = 1kΩ
RL = 1kΩ
RL = 100Ω
RL = 50Ω
RL = 100Ω
RL = 50Ω
RL = 100Ω
RL = 1kΩ
AV = +1, VOUT = 200mVP-P
FREQUENCY (MHz)
PHASE
GAIN
3
0
-3
-6
NORMALIZED GAIN (dB)
0.3 1 10 100 1K
0
-90
-180
-270
-360
PHASE (DEGREES)
RL = 100Ω
RL = 1kΩ
RL = 50Ω
RL = 100ΩRL = 1kΩ
RL = 50Ω
RL = 100Ω
RL = 1kΩ
AV = +2, VOUT = 200mVP-P
HFA1130
8FN3369.4
July 15, 2005
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE
FIGURE 15. GAIN FLATNESS FIGURE 16. DEVIATION FROM LINEAR PHASE
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified (Continued)
FREQUENCY (MHz)
20
10
0
-10
-20
GAIN (dB)
0.3 1 10 100 1K
-30
0.500VP-P
0.920VP-P
1.63VP-P
0.160VP-P
AV = +1
FREQUENCY (MHz)
20
10
0
-10
-20
NORMALIZED GAIN (dB)
0.3 1 10 100 1K
-30
1.00VP-P
1.84VP-P
3.26VP-P
0.32VP-P
AV = +2
FREQUENCY (MHz)
20
10
0
-10
-20
NORMALIZED GAIN (dB)
0.3 1 10 100 1K
-30
0.96VP-P
3.89VP-P
TO
AV = +6
TEMPERATURE (°C)
950
900
850
800
750
BANDWIDTH (MHz)
-50 -25 0 75 125
700
25 50 100
AV = +1
FREQUENCY (MHz)
0
-0.05
-0.10
GAIN (dB)
1 10 100
-0.15
-0.20
AV = +2 +2.0
+1.5
+1.0
+0.5
0
-0.5
-1.0
-1.5
-2.0
0 15 30 45 60 75 90 105 120 135 150
FREQUENCY (MHz)
DEVIATION (DEGREES)
AV = +2
HFA1130
9FN3369.4
July 15, 2005
FIGURE 17. OPEN LOOP TRANSIMPEDANCE FIGURE 18. SETTLING RESPONSE
FIGURE 19. CLOSED LOOP OUTPUT RESISTANCE FIGURE 20. 3rd ORDER INTERMODULATION INTERCEPT
FIGURE 21. 2nd HARMONIC DISTORTION vs POUT FIGURE 22. 3rd HARMONIC DISTORTION vs POUT
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified (Continued)
250
25
2.5
0.25
0.01 0.1 1 10 100 500
180
135
90
45
0
PHASE (DEGREES)
GAIN (kΩ)
FREQUENCY (MHz)
AV = -1
GAIN
PHASE
TIME (ns)
0.6
0.4
0.2
0
SETTLING ERROR (%)
-4 1 6 21 31
-0.2
11 16 26 36 41 46
-0.4
-0.6
AV = +2, VOUT = 2V
OUTPUT RESISTANCE (Ω)
1000
100
10
1
0.1
0.3 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)
40
35
30
25
20
INTERCEPT POINT (dBm)
0 100 200
15
300 400
10
5
0
2-TONE
OUTPUT POWER (dBm)
-30
-35
-40
-45
-50
DISTORTION (dBc)
-5 3
-55
-60
-65
-70 -3 -1 1 5 7 9 11 13 15
100MHz
50MHz
30MHz
OUTPUT POWER (dBm)
-30
-40
-50
-60
-70
DISTORTION (dBc)
-5 3
-80
-90
-100
-110 -3 -1 1 5 7 9 11 13 15
100MHz
50MHz
30MHz
HFA1130
10 FN3369.4
July 15, 2005
FIGURE 23. OVERSHOOT vs INPUT RISE TIME FIGURE 24. OVERSHOOT vs INPUT RISE TIME
FIGURE 25. OVERSHOOT vs FEEDBACK RESISTOR FIGURE 26. SUPPLY CURRENT vs TEMPERATURE
FIGURE 27. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 28. VIO AND BIAS CURRENTS vs TEMPERATURE
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified (Continued)
INPUT RISE TIME (ps)
38
36
34
32
30
OVERSHOOT (%)
100 500
28
26
24
22
200 300 400 600 700 800 900 1000
VOUT = 1VP-P
VOUT = 2VP-P
VOUT = 0.5VP-P
20
18
16
14
12
10
8
6
AV = +1
INPUT RISE TIME (ps)
35
30
25
20
15
OVERSHOOT (%)
100 500
10
5
0
200 300 400 600 700 800 900 1000
RF = 360Ω
VOUT = 2VP-P
RF = 510Ω
VOUT = 0.5VP-P
RF = 510Ω
VOUT = 1VP-P
RF = 360Ω
VOUT = 1VP-P
RF = 360Ω
VOUT = 0.5VP-P
RF = 510Ω
VOUT = 2VP-P
AV = +2
FEEDBACK RESISTOR (Ω)
36
34
32
30
OVERSHOOT (%)
360 520
28
26
24
22
400 440 480 560 600 640 680
20
18
16
14
12
10
8
6
4
AV = +2, tR = 200ps, VOUT = 2VP-P
TEMPERATURE (°C)
25
24
23
22
21
SUPPLY CURRENT (mA)
-60 20
20
19
18
-40 -20 0 40 60 80 100 120
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
22
17
15
13
11
SUPPLY CURRENT (mA)
59
9
7
5
678 10
21
20
19
6
8
10
12
14
16
18
TEMPERATURE (°C)
45
42
39
36
33
BIAS CURRENTS (µA)
-60 20
30
27
24
-40 -20 0 40 60 80 100 120
21
18
15
12
9
6
3
0
2.8
2.7
2.6
2.5
2.4
INPUT OFFSET VOLTAGE (mV)
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
+IBIAS
VIO
-IBIAS
HFA1130
11 FN3369.4
July 15, 2005
FIGURE 29. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 30. INPUT NOISE vs FREQUENCY
FIGURE 31. NON-LINEARITY NEAR CLAMP VOLTAGE
Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, TA = 25°C, RL = 100Ω, Unless Otherw ise Specified (Continued)
TEMPERATURE (°C)
3.7
3.6
3.5
3.4
OUTPUT VOLTAGE (V)
-60 20
3.3
3.2
3.1
3.0
-40 -20 0 40 60 80 100
2.9
2.8
2.7
2.6
2.5
120
| - VOUT |
+VOUT
(AV = -1, RL = 50Ω)
300
275
250
225
200
175
150
125
100
75
50
25
0
30
25
20
15
10
5
0
100 1K 10K 100K
FREQUENCY (Hz)
NOISE VOLTAGE (nV/√Hz)
NOISE CURRENT (pA/√Hz)
ENI
INI-
INI+
20
15
10
5
0
-5
-10
-15
-20
VOUT - (AV VIN) (mV)
-3 -2 -1 0 1 2 3
AV VIN (V)
VL = -3V VL = -1V
VL = -2V
VH = 3VVH = 1V VH = 2V
AV = -1, RL = 100Ω
HFA1130
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3369.4
July 15, 2005
Die Characteristics
Metallization Mask Layout
HFA1130
DIE DIMENSIONS:
63 mils x 44 mils x 19 mils
1600µm x 1130µm
METALLIZATION:
Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: ALCu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PASSIVATION:
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
TRANSISTOR COUNT:
52
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
+IN
V-
VL
BAL
OUT
-IN
BAL
VH
V+
HFA1130
