OTHER
• Listed on SMD #5962-92153. Available as
MIL-PRF-38535 QML Class Q and Class V
• Read/Write Cycle Times
≤ 30 ns (Typical)
≤ 40 ns (-55 to 125°C)
• Standby Current of 20 µA (typical)
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V ± 10% Power Supply
• Packaging Options
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- 28-Lead Flat Pack (0.530 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
RADIATION
• Fabricated with RICMOS™ IV Bulk
0.8 µm Process (Leff = 0.65 µm)
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Soft Error Rate of <1x10-10 upsets/bit-day
• Dose Rate Survivability through 1x1012 rad(Si)/s
• Latchup Free
32K x 8 STATIC RAM HC6856
Military & Space Products
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 x 8-bit static random access memory
with industry-standard functionality. It is fabricated with
Honeywell’s radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V ± 10% power supply.
The RAM is available with either TTL or CMOS compatible
I/O. Power consumption is typically less than 50 mW/MHz
in operation, and less than 5 mW/MHz in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 20 ns.
Honeywell’s enhanced RICMOS™IV (Radiation Insensitive
CMOS) technology is radiation hardened through the use of
advanced and proprietary design, layout, and process hard-
ening techniques. The RICMOS™ IV process is a 5-volt,
twin-well CMOS technology with a 170 Å gate oxide and a
minimum drawn feature size of 0.8 µm (0.65 µm effective
gate length—Leff). Additional features include a three layer
interconnect metalization and a lightly doped drain (LDD)
structure for improved short channel reliability. High resis-
tivity cross-coupled polysilicon resistors have been incorpo-
rated for single event upset hardening.
FEATURES
HC6856
2
FUNCTIONAL DIAGRAM
NCS CE NWE NOE MODE DQ
L H H L Read Data Out
L H L X Write Data In
H X XX XX Deselected High Z
X L XX XX Disabled High Z
TRUTH TABLE
NCS
A:0-8,12-13
CE
NWE
NOE
CS • CE
WE • CS • CE
NWE • CS • CE • OE
Column Decoder
Data Input/Output
Row
Decoder 32,768 x 8
Memory
Array
A:9-11,14
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
4
DQ:0-7
(0 = high Z)
•
•
•
• • •
8
8
11
SIGNAL DEFINITIONS
A: 0-14 Address input pins (A) which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces
the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all
the input buffers. If this signal is not used it must be connected to VSS.
NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level it allows normal read operation.
NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers.
If this signal is not used it must be connected to VDD.
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
HC6856
3
Pulse width≤1µs
Total Dose ≥1x106rad(SiO2)
Transient Dose Rate Upset (3) ≥1x109rad(Si)/s
Transient Dose Rate Survivability ≥1x1012 rad(Si)/s
Soft Error Rate: Level A <1x10-9 (4)
Level Z <1x10-10
Neutron Fluence ≥1x1014 N/cm2
TA=25°C
Parameter Limits (2)
Pulse width≤50 ns, X-ray,
VDD=6.6 V, TA=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
(3) Suggested stiffening capacitance specifications for optimum expected dose rate upset performance is stated above in the text.
(4) SER <1x10-10 u/b-d from -55 to 80°C.
Adams 10%
worst case environment
Test Conditions
RADIATION HARDNESS RATINGS (1)
Total Ionizing Radiation Dose
The RAM will meet all stated functional and electrical speci-
fications over the entire operating temperature range after
the specified total ionizing radiation dose. All electrical and
timing performance parameters will remain within specifica-
tions after rebound at VDD = 5.5 V and T =125°C extrapo-
lated to ten years of operation. Total dose hardness is
assured by wafer level testing of process monitor transistors
and RAM product using 10 keV X-ray radiation. Transistor
gate threshold shift correlations have been made between
10 keV X-rays applied at a dose rate of 1x10
5
rad(SiO
2
)/min
at T = 25°C and gamma rays (Cobalt 60 source) to ensure
that wafer level X-ray testing is consistent with standard
military radiation test environments.
Transient Pulse Ionizing Radiation
The RAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient ionizing
radiation pulse of ≤1µs duration up to 1x109 rad(Si)/s, when
applied under recommended operating conditions. To en-
sure validity of all specified performance parameters be-
fore, during, and after radiation (timing degradation during
transient pulse radiation is ≤10%), it is suggested that a
minimum of 0.8 µF per part of stiffening capacitance be
placed between the package (chip) VDD and VSS, with a
maximum inductance between the package (chip) and
stiffening capacitance of 0.7 nH per part. If there are no
operate-through or valid stored data requirements, the
capacitance specification can be reduced to a minimum of
0.1 µF per part.
The RAM will meet any functional or electrical specification
after exposure to a radiation pulse of ≤ 50 ns duration up to
1x1012 rad(Si)/s,when applied under recommended oper-
ating conditions. Note that the current conducted during the
pulse by the RAM inputs, outputs, and power supply may
significantly exceed the normal operating levels. The appli-
cation design must accommodate these effects.
Neutron Radiation
The RAM will meet any functional or timing specification
after a total neutron fluence of up to 1x1014 cm-2 applied
under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
The RAM is capable of soft error rate (SER) performance
of <1x10-10 upsets/bit-day, under recommended operating
conditions. This hardness level is defined by the Adams
10% worst case cosmic ray environment.
Latchup
The RAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the RICMOS™ p-epi
on p+ substrate process and use of proven design tech-
niques, such as double guardbanding, ensure latchup
immunity.
1 MeV equivalent energy,
Unbiased, TA=25°C
Units
upsets/bit-day
RADIATION CHARACTERISTICS
HC6856
4
VDD Positive Supply Voltage (2) -0.5 7.0 V
VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V
TSTORE Storage Temperature (Zero Bias) -65 150 °C
TSOLDER Soldering Temperature • Time 270•5 °C•s
PD Total Package Power Dissipation (3) 2.5 W
IOUT DC or Average Output Current 25 mA
VPROT ESD Input Protection Voltage (4) 2000 V
ΘJC Thermal Resistance (Jct-to-Case) 28 FP/36 FP 2 °C/W
28 DIP 10 °C/W
TJ Junction Temperature 175 °C
Parameter
Symbol Rating Units
Min Max
ABSOLUTE MAXIMUM RATINGS (1)
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
Symbol Test Conditions
Min Max
Worst Case
Parameter (2) Typical
(1) Units
NCS=VDD=VDR
VI=VDR or VSS
VDR Data Retention Voltage (3) 2.0 2.5 V
IDR Data Retention Current 150 400 µA
NCS=VDR
VI=VDR or VSS
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
DATA RETENTION CHARACTERISTICS
CI Input Capacitance 4 6 pF VI=VDD or VSS, f=1 MHz
CO Output Capacitance 6.5 8 pF VIO=VDD or VSS, f=1 MHz
Parameter Max
Symbol Typical Test Conditions
Worst Case Units
(1) This parameter is tested during initial design characterization only.
CAPACITANCE (1)
Symbol
VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V
TA Ambient Temperature -55 25 125 °C
VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V
Typ Units
Description
Parameter
RECOMMENDED OPERATING CONDITIONS
Min Max
HC6856
5
IDDSB1 Static Supply Current 0.02 1.2 mA
IDDSB2 Static Supply Current with Chip Disabled 0.02 1.2 mA
IDDOPW Dynamic Supply Current, Selected (Write) 5.5 7.5 mA
IDDOPR Dynamic Supply Current, Selected (Read) 4.5 6.5 mA
II Input Leakage Current ±0.05 -5 +5 µA
IOZ Output Leakage Current ±0.1 -10 10 µA
VIL Low-Level InputVoltage
VIH High-Level Input Voltage
Units Test Conditions (3)
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) Input high = VIH ≥ VDD-0.3V, input low =VIL ≤ 0.3V
(4) Guaranteed but not tested.
(5) All inputs switching. DC average current.
VOL Low-Level Output Voltage
VOH High-Level Output Voltage
DC ELECTRICAL CHARACTERISTICS
CMOS 1.9 0.3xVDD VVDD=4.5V
TTL 1.3 0.8 V VDD=4.5V
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
VIH=VDD IO=0
VIL=VSS Inputs Stable
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
Min Max
Worst Case (2)
Symbol Parameter
CE=VSS or NCS=VDD
IO=0, VSS≤ VI≤VDD (4)
CMOS 3.0 0.7xVDD VVDD=5.5V
TTL 1.7 2.2 V VDD=5.5V
0.2 0.4 V VDD=4.5V, IOL=10 mA
0.05 V VDD=4.5V, IOL=200 µA
4.8 4.2 V VDD=4.5V, IOH=-5 mA
VDD-0.05 VVDD=4.5V, IOH=-200 µA
Typical
(1)
VSS≤VI≤VDD
VSS≤VIO≤VDD
Output=high Z
DUT
output Valid low
output
Vref1
CL>50 pF*
249Ω
Tester Equivalent Load Circuit
2.9 V Valid high
output
Vref2
-
+
-
+
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
HC6856
6
TAVAVR Address Read Cycle Time 18 40 ns
TAVQV Address Access Time 18 40 ns
TAXQX Address Change to Output Invalid Time 15 5 ns
TSLQV Chip Select Access Time 20 40 ns
TSLQX Chip Select Output Enable Time 20 16 ns
TSHQZ Chip Select Output Disable Time 6 10 ns
TEHQV Chip Enable Access Time 20 40 ns
TEHQX Chip Enable Output Enable Time 20 16 ns
TELQZ Chip Enable Output Disable Time 6 10 ns
TGLQV Output Enable Access Time 4 10 ns
TGLQX Output Enable Output Enable Time 3 0 ns
TGHQZ Output Enable Output Disable Time 4 10 ns
READ CYCLE AC TIMING CHARACTERISTICS (1)
(1)Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive
output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2)Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3)Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
Symbol Parameter Typical -55 to 125°C Units
(2) Min Max
Worst Case (3)
HIGH
IMPEDANCE
NCS
NOE
DATA VALID
CE
T
AVAVR
T
AVQV
T
AXQX
T
SLQV
T
SLQX
T
SHQZ
T
EHQX
T
EHQV
T
GLQX
T
GLQV
T
GHQZ
T
ELQZ
ADDRESS
(NWE = high)
DATA OUT
HC6856
7
Worst Case (3)
(1)Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2)Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3)Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4)SER ≤1E-10 u/b-d from -55 to 80°.
(5)TAVAVW= TWLWH + TWHWL
TAVAVW Write Cycle Time (5) 30 40 60 ns
TWLWH Write Enable Write Pulse Width 25 35 55 ns
TSLWH Chip Select to End of Write Time 25 35 55 ns
TDVWH Data Valid to End of Write Time 20 30 50 ns
TAVWH Address Valid to End of Write Time 25 35 55 ns
TWHDX Data Hold Time after End of Write Time 0 0 0 ns
TAVWL Address Valid Setup to Start of Write Time 0 0 0 ns
TWHAX Address Valid Hold after End of Write Time 0 0 0 ns
TWLQZ Write Enable to Output Disable Time 5 0 10 0 10 ns
TWHQX Write Disable to Output Enable Time 15 5 5 ns
TWHWL Write Disable to Write Enable Pulse Width 4 5 5 ns
TEHWH Chip Enable to End of Write Time 25 35 55 ns
Symbol Parameter Typical (2) SER <1E-9 (4) SER <1E-10
Min Max Min Max Units
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
ADDRESS
HIGH
IMPEDANCE
DATA OUT
NWE
DATA IN DATA VALID
TAVAVW
NCS
CE
TAVWH
TWLWH
TAVWL
TWLQZ
TDVWH
TWHQX
TWHDX
TSLWH
TEHWH
TWHAX
TWHWL
HC6856
8
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write
enable (NWE) must be high. The output drivers can be
controlled independently by the NOE signal. Consecutive
read cycles can be executed with NCS held continuously
low, and with CE held continuously high.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid TAVQV time following the latest
occurring address edge transition. The minimum address
activated read cycle time is TAVAV. When the RAM is
operated at the minimum address activated read cycle
time, the data outputs will remain valid on the RAM I/O until
TAXQX time following the next sequential address transi-
tion.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS; however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.
DYNAMIC ELECTRICAL CHARACTERISTICS
Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Only the
NWE controlled mode is shown in the table and diagram on
the previous page for simplicity; however, each mode of
control provides the same write cycle timing characteris-
tics. Thus, some of the parameter names referenced below
are not shown in the write cycle table or diagram, but
indicate which control pin is in control as it switches high or
low.
To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
HC6856
9
TESTER AC TIMING CHARACTERISTICS
QUALITY AND RADIATION HARDNESS
ASSURANCE
Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a com-
plete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radia-
tion hardness assurance strategy.
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitor-
ing key parameters which are sensitive to ionizing radia-
tion. Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.
SCREENING LEVELS
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MIL-
STD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are avail-
able per the applicable Standard Military Drawing (SMD).
QML devices offer ease of procurement by eliminating the
need to create detailed specifications and offer benefits of
improved quality and cost savings through standardization.
RELIABILITY
Honeywell understands the stringent reliability require-
ments that space and defense systems require and has
extensive experience in reliability testing on programs of
this nature. This experience is derived from comprehen-
sive testing of VLSI processes. Reliability attributes of the
RICMOS™ process were characterized by testing specially
designed irradiated and non-irradiated test structures from
which specific failure mechanisms were evaluated. These
specific mechanisms included, but were not limited to, hot
carriers, electromigration and time dependent dielectric
breakdown. This data was then used to make changes to
the design models and process to ensure more reliable
products.
In addition, the reliability of the RICMOS™ process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is quali-
fied by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
High Z = 2.9V








3 V
0 V 1.5 V


VDD-0.5 V
0.5 V VDD/2






1.5 V
VDD-0.4V
0.4 V High Z
3.4 V
2.4 V
High Z
VDD/2
0.4 V High Z
3.4 V
2.4 V
High Z
TTL I/O Configuration
Input
Levels*
Output
Sense
Levels
CMOS I/O Configuration
High Z = 2.9V
* Input rise and fall times <1 ns/V
VDD-0.4V
HC6856
10
PACKAGING
The 32K x 8 SRAM is offered in a custom 36-lead flat pack
(FP), 28-Lead FP, or standard 28-lead DIP. Each package
is constructed of multilayer ceramic (Al2O3) and features
internal power and ground planes. The 36-lead FP also
features a non-conductive ceramic tie bar on the lead
frame. The purpose of the tie bar is to allow electrical testing
of the device, while preserving the lead integrity during
shipping and handling, up to the point of lead forming and
insertion. Ceramic chip capacitors can be mounted to the
package by the user to maximize supply noise decoupling
and increase board packing density. These capacitors
attach directly to the internal package power and ground
planes. This design minimizes resistance and inductance
of the bond wire and package, both of which are critical in
a transient radiation environment. All NC (no connect) pins
must be connected to either VDD, VSS or an active driver
to prevent charge build up in the radiation environment.
36-LEAD FLAT PACK (22017194-001)
36-LEAD FLAT PACK PINOUT28-LEAD DIP & FP PINOUT
VDD
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top
View
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
A
b
C
D
E
e
F
G
H
I
J
L
0.095 ± 0.010
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
0.285 ± 0.015
M
N
O
P
R
S
T
U
V
W
X
Y
0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
0.450 ref
0.400 ref
All dimensions are in inches
[1]
Non-
Conductive
Tie-Bar
D
b
(width)
e
(pitch)


E
1
H
G
L L
Kovar
Lid [3]
Ceramic
Body
A
J
IC M
Top
Side
0.004
N
X
Optional
Standoff
1
F
VSS VDD
V
S
W
PU
1
Y






VDD VSS



O
T
R
Optional
Capacitors
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Top
View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HC6856
11
VDD = 6.5V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
VDD = 5.5V, R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
STATIC BURN-IN DIAGRAMDYNAMIC BURN-IN DIAGRAM
28-LEAD FLAT PACK (22017362-001)
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
28-LEAD DIP (22017502-001)
[1] BSC - Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
A
b
C
D
e
E
E2
E3
F
G
L
Q
S
U
V
W
X
Y
Z
0.135 ± 0.015
0.015 ± 0.002
0.004 to 0.009
0.720 ± 0.008
0.050 ± 0.005 [1]
0.530 ± 0.008
0.420 ± 0.008
0.055 ref
0.650 ± 0.005 [2]
0.050 ± 0.005
0.295 min [3]
0.026 to 0.045
0.035 ± 0.010
0.065 ref
0.300 ref
0.050 ref
0.030 ref
0.100 ref
0.080 ref
All dimensions in inches
E2
A
Lead
Alloy 42
Ceramic
Body
C
E3
G
Cutout
Area
Q
Kovar
Lid [4]

V
1
X
W
Y
BOTTOM
VIEW




VSSVDD VDD
Optional capacitors
in cutout
S
ZU

E
1
e
b
D
(width)
(pitch)
F
L
TOP
VIEW
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
NC
VSS
VDD
NWE*
CE*
A13*
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
VDD
32K x 8 SRAM
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQO
DQ1
DQ2
VDD
VSS
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NOTE — *Denotes package pinout option dependent (28-Lead DIP/FP diagrams not shown but have similar connections)
R
R
R
R
R
R
R
R
R
R
R
R
R
NC
R
R
R
R
R
R
R
R
R
R
R
R
R
R
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VDD
NWE*
CE*
A13*
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
VSS VDD
32K x 8 SRAM
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQO
DQ1
DQ2
VDD
VSS
F16
F7
F6
F5
F4
F3
F2
F8
F13
F14
F1
F1
F1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
F0
F17
F15
F12
F11
F10
F17
F9
F17
F1
F1
F1
F1
F1
VSS
HC6856
12
Helping You Control Your World
900049
2/96
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
TOTAL DOSE
HARDNESS
R=1x105rad(SiO2)
F=3x105rad(SiO2)
H=1x106rad(SiO2)
N=No Level Guaranteed
PART NUMBER
Pinout options (2) SCREEN LEVEL (1)
V=QML Class V
Q=QML Class Q
S=Level S
B=Level B
E=Engr Device (4)
Q
C
HX
PROCESS
C=CMOS
SOURCE
H=HONEYWELL PACKAGE DESIGNATION
W=36-Lead FP
X=36-Lead FP, with standoff
Y=36-Lead FP, with standoff & caps
N=28-Lead FP
R=28-Lead DIP
- = Bare Die (No Package)
H
SOFT ERROR
RATE
Z
Z=<1x10-10 upsets/bit-day
A=<1x10-9 upsets/bit-day (3)
C=<1x10-7 upsets/bit-day
- =No SER Guaranteed
C
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Pinout options:
(3) SER <1E-10 u/b-d from -55 to 80°C.
(4) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
(5) Only specified for Engineering Devices. Number defines worst case maximum Write Cycle time in nano-seconds (ns).
Contact Factory with other needs.
ORDERING INFORMATION (1)
INPUT BUFFER TYPE
C=CMOS Level
T=TTL Level
To learn more about Honeywell Solid State Electronics Center,
visit our web site at http://www.ssec.honeywell.com
40
6856/1
SPEED (5)
60 ns
40 ns
35 ns
36-Lead FP 28-Lead FP & DIP
pin 32 pin 33 pin 34
HC6856/1 A13 CE NWE JEDEC Pinout
HC6856/2 CE NWE A13 N/A