DS90LT012AHMF/NOPB - NATIONAL SEMICONDUCTOR

DS90LT012AH

DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

Literature Number: SNLS199

DS90LT012AH

High Temperature 3V LVDS Differential Line Receiver

General Description

The DS90LT012AH is a single CMOS differential line re-

ceiver designed for applications requiring ultra low power

dissipation, low noise, and high data rates. The devices are

designed to support data rates in excess of 400 Mbps (200

MHz) utilizing Low Voltage Differential Swing (LVDS) tech-

nology

The DS90LT012AH accepts low voltage (350 mV typical)

differential input signals and translates them to 3V CMOS

output levels. The DS90LT012AH includes an input line ter-

mination resistor for point-to-point applications.

The DS90LT012AH and companion LVDS line driver

DS90LV011AH provide a new alternative to high power

PECL/ECL devices for high speed interface applications.

Features

n-40 to +125˚C temperature range operation

nCompatible with ANSI TIA/EIA-644-A Standard

n>400 Mbps (200 MHz) switching rates

n100 ps differential skew (typical)

n3.5 ns maximum propagation delay

nIntegrated line termination resistor (100Ωtypical)

nSingle 3.3V power supply design (2.7V to 3.6V range)

nPower down high impedance on LVDS inputs

nLVDS inputs accept LVDS/CML/LVPECL signals

nPinout simplifies PCB layout

nLow Power Dissipation (10mW typical@3.3V static)

nSOT-23 5-lead package

Connection Diagram

20161626

(Top View)

Order Number DS90LT012AHMF

See NS Package Number MF05A

Functional Diagram

DS90LT012AH

20161625

Truth Table

INPUTS OUTPUT

[IN+] − [IN−] TTL OUT

≥0V H

≤−0.1V L

Full Fail-safe OPEN/SHORT or

Terminated

September 2005

DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

) −0.3V to +4V

Input Voltage (IN+, IN−) −0.3V to +3.9V

Output Voltage (TTL OUT) −0.3V to (V

+ 0.3V)

Output Short Circuit Current −100mA

Maximum Package Power Dissipation @+25˚C

MF Package 902mW

Derate MF Package 7.22 mW/˚C above +25˚C

Thermal resistance (θ

) 138.5˚C/W

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range Soldering

(4 sec.) +260˚C

Maximum Junction

Temperature +150˚C

ESD Ratings (Note 4)

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (V

) +2.7 +3.3 +3.6 V

Operating Free Air

Temperature (T

) −40 25 +125 ˚C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

Differential Input High Threshold V

dependant on V

(Note 11) IN+, IN− −30 0 mV

Differential Input Low Threshold −100 −30 mV

Common-Mode Voltage V

= 2.7V, V

= 100mV 0.05 2.35 V

= 3.0V to 3.6V, V

= 100mV 0.05 V

- 0.3V V

= 125˚C 0.10 2.35 V

Input Current (DS90LV012A) V

= +2.8V V

= 3.6V or 0V −10 ±1 +10 µA

= 0V −10 ±1 +10 µA

= +3.6V V

= 0V −20 +20 µA

∆I

Change in Magnitude of I

= +2.8V V

= 3.6V or 0V 4 µA

=0V 4 µA

= +3.6V V

=0V 4 µA

IND

Differential Input Current V

IN+

= +0.4V, V

IN−

= +0V 3 3.9 4.4 mA

IN+

= +2.4V, V

IN−

= +2.0V

Integrated Termination Resistor 100 Ω

Input Capacitance IN+ = IN− = GND 3 pF

Output High Voltage I

= −0.4 mA, V

= +200 mV TTL OUT 2.4 3.1 V

= −0.4 mA, Inputs terminated 2.4 3.1 V

= −0.4 mA, Inputs shorted 2.4 3.1 V

Output Low Voltage I

= 2 mA, V

= −200 mV 0.3 0.5 V

Output Short Circuit Current V

OUT

= 0V (Note 5) −15 −50 −100 mA

Input Clamp Voltage I

= −18 mA −1.5 −0.7 V

No Load Supply Current Inputs Open V

5.4 9 mA

DS90LT012AH

www.national.com 2

Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 6, 7)

Symbol Parameter Conditions Min Typ Max Units

PHLD

Differential Propagation Delay High to Low C

= 15 pF 1.0 1.8 3.5 ns

PLHD

Differential Propagation Delay Low to High V

= 200 mV 1.0 1.7 3.5 ns

SKD1

Differential Pulse Skew |t

PHLD

−t

PLHD

| (Note 8) (Figure 1 and Figure 2) 0 100 400 ps

SKD3

Differential Part to Part Skew (Note 9) 0 0.3 1.0 ns

SKD4

Differential Part to Part Skew (Note 10) 0 0.4 1.5 ns

TLH

Rise Time 350 800 ps

THL

Fall Time 175 800 ps

MAX

Maximum Operating Frequency (Note 12) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise

specified (such as VID).

Note 3: All typicals are given for: VDD = +3.3V and TA= +25˚C.

Note 4: ESD Ratings:

DS90LT012AH:

HBM (1.5 kΩ, 100 pF) ≥2kV

EIAJ (0Ω, 200 pF) ≥700V

CDM ≥2000V

IEC direct (330Ω, 150 pF) ≥7kV

Note 5: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

exceed maximum junction temperature specification.

Note 6: CLincludes probe and jig capacitance.

Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, ZO=50Ω,t

rand tf(0% to 100%) ≤3 ns for IN±.

Note 8: tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

Note 9: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VDD

and within 5˚C of each other within the operating temperature range.

Note 10: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the

recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.

Note 11: VDD is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05V to +2.35V when VDD = 2.7V and |VID|/2to

VDD − 0.3V when VDD = 3.0V to 3.6V. VID is not allowed to be greater than 100 mV when VCM = 0.05V to 2.35V when VDD = 2.7V or when VCM =|V

ID|/2to

VDD − 0.3V when VDD = 3.0V to 3.6V.

Note 12: fMAX generator input conditions: tr=t

f<1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,

VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes). The parameter is guaranteed by design. The limit is based on the statistical analysis of the device

over the PVT range by the transition times (tTLH and tTHL).

Parameter Measurement Information

20161603

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

DS90LT012AH

www.national.com3

Parameter Measurement Information (Continued)

Typical Applications

Applications Information

General application guidelines and hints for LVDS drivers

and receivers may be found in the following application

notes: LVDS Owner’s Manual (lit #550062-003), AN-808,

AN-977, AN-971, AN-916, AN-805, AN-903.

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

in Figure 3. This configuration provides a clean signaling

environment for the fast edge rates of the drivers. The re-

ceiver is connected to the driver through a balanced media

which may be a standard twisted pair cable, a parallel pair

cable, or simply PCB traces. Typically the characteristic

impedance of the media is in the range of 100Ω. The internal

termination resistor converts the driver output (current mode)

into a voltage that is detected by the receiver. Other configu-

rations are possible such as a multi-receiver configuration,

but the effects of a mid-stream connector(s), cable stub(s),

and other impedance discontinuities as well as ground shift-

ing, noise margin limits, and total termination loading must

be taken into account.

The DS90LT012AH differential line receiver is capable of

detecting signals as low as 100 mV, over a ±1V common-

mode range centered around +1.2V. This is related to the

driver offset voltage which is typically +1.2V. The driven

signal is centered around this voltage and may shift ±1V

around this center point. The ±1V shifting may be the result

of a ground potential difference between the driver’s ground

reference and the receiver’s ground reference, the common-

mode effects of coupled noise, or a combination of the two.

The AC parameters of both receiver input pins are optimized

for a recommended operating input voltage range of 0V to

+2.4V (measured from each pin to ground). The device will

operate for receiver input voltages up to V

, but exceeding

will turn on the ESD protection circuitry which will clamp

the bus voltages.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high

frequency ceramic (surface mount is recommended) 0.1µF

and 0.001µF capacitors in parallel at the power supply pin

with the smallest value capacitor closest to the device supply

pin. Additional scattered capacitors over the printed circuit

board will improve decoupling. Multiple vias should be used

to connect the decoupling capacitors to the power planes. A

10µF (35V) or greater solid tantalum capacitor should be

connected at the power entry point on the printed circuit

board between the supply and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS

signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL

signals may couple onto the LVDS lines. It is best to put TTL

and LVDS signals on different layers which are isolated by a

power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side)

connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differen-

tial impedance of your transmission medium (ie. cable) and

termination resistor. Run the differential pair trace lines as

close together as possible as soon as they leave the IC

(stubs should be <10mm long). This will help eliminate

20161604

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

Balanced System

20161628

FIGURE 3. Point-to-Point Application (DS90LT012AH)

DS90LT012AH

www.national.com 4

Applications Information (Continued)

reflections and ensure noise is coupled as common-mode.

In fact, we have seen that differential signals which are 1mm

apart radiate far less noise than traces 3mm apart since

magnetic field cancellation is much better with the closer

traces. In addition, noise induced on the differential lines is

much more likely to appear as common-mode which is re-

jected by the receiver.

Match electrical lengths between traces to reduce skew.

Skew between the signals of a pair means a phase differ-

ence between signals which destroys the magnetic field

cancellation benefits of differential signals and EMI will re-

sult! (Note that the velocity of propagation,v=c/E

where c

(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not

rely solely on the autoroute function for differential traces.

Carefully review dimensions to match differential impedance

and provide isolation for the differential lines. Minimize the

number of vias and other discontinuities on the line.

Avoid 90˚ turns (these cause impedance discontinuities).

Use arcs or 45˚ bevels.

Within a pair of traces, the distance between the two traces

should be minimized to maintain common-mode rejection of

the receivers. On the printed circuit board, this distance

should remain constant to avoid discontinuities in differential

impedance. Minor violations at connection points are allow-

able.

TERMINATION

The DS90LT012AH integrates the terminating resistor for

point-to-point applications. The resistor value will be be-

tween 90Ωand 133Ω.

THRESHOLD

The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maxi-

mum threshold of ±100mV for the LVDS receiver. The

DS90LV012A and DS90LT012A support an enhanced

threshold region of −100mV to 0V. This is useful for fail-safe

biasing. The threshold region is shown in the Voltage Trans-

fer Curve (VTC) in Figure 4. The typical DS90LT012AH

LVDS receiver switches at about −30mV. Note that with V

= 0V, the output will be in a HIGH state. With an external

fail-safe bias of +25mV applied, the typical differential noise

margin is now the difference from the switch point to the bias

point. In the example below, this would be 55mV of Differ-

ential Noise Margin (+25mV − (−30mV)). With the enhanced

threshold region of −100mV to 0V, this small external fail-

safe biasing of +25mV (with respect to 0V) gives a DNM of a

comfortable 55mV. With the standard threshold region of

±100mV, the external fail-safe biasing would need to be

+25mV with respect to +100mV or +125mV, giving a DNM of

155mV which is stronger fail-safe biasing than is necessary

for the DS90LT012AH. If more DNM is required, then a

stronger fail-safe bias point can be set by changing resistor

values.

FAIL SAFE BIASING

External pull up and pull down resistors may be used to

provide enough of an offset to enable an input failsafe under

open-circuit conditions. This configuration ties the positive

LVDS input pin to VDD thru a pull up resistor and the

negative LVDS input pin is tied to GND by a pull down

resistor. The pull up and pull down resistors should be in the

5kΩto 15kΩrange to minimize loading and waveform dis-

tortion to the driver. The common-mode bias point ideally

should be set to approximately 1.2V (less than 1.75V) to be

compatible with the internal circuitry. Please refer to applica-

tion note AN-1194, “Failsafe Biasing of LVDS Interfaces” for

more information.

PROBING LVDS TRANSMISSION LINES

Always use high impedance (>100kΩ), low capacitance

(<2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is impor-

tant to remember:

Use controlled impedance media. The cables and connec-

tors you use should have a matched differential impedance

of about 100Ω. They should not introduce major impedance

discontinuities.

Balanced cables (e.g. twisted pair) are usually better than

unbalanced cables (ribbon cable, simple coax) for noise

reduction and signal quality. Balanced cables tend to gener-

ate less EMI due to field canceling effects and also tend to

pick up electromagnetic radiation a common-mode (not dif-

ferential mode) noise which is rejected by the receiver.

For cable distances <0.5M, most cables can be made to

work effectively. For distances 0.5M ≤d≤10M, CAT 3

(category 3) twisted pair cable works well, is readily available

and relatively inexpensive.

20161629

FIGURE 4. VTC of the DS90LT012AH LVDS Receiver

DS90LT012AH

www.national.com5

Pin Descriptions

Package Pin Number Pin Name Description

SOT23

4 IN− Inverting receiver input pin

3 IN+ Non-inverting receiver input pin

5 TTL OUT Receiver output pin

Power supply pin, +3.3V ±0.3V

2 GND Ground pin

NC No connect

Ordering Information

Operating Package Type/ Order Number

Temperature Number

−40˚C to +125˚C MF05A DS90LT012AHMF

DS90LT012AH

www.national.com 6

Physical Dimensions inches (millimeters) unless otherwise noted

5-Lead SOT23, JEDEC MO-178, 1.6mm

Order Number DS90LT012AHMF

NS Package Number MF05A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

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2. A critical component is any component of a life support

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DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

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