User's Manual PD789104A, 789114A, 789124A, 789134A Subseries 8-Bit Single-Chip Microcontrollers PD789101A PD789101A(A1) PD789102A PD789102A(A1) PD789104A PD789104A(A1) PD789111A PD789111A(A1) PD789112A PD789112A(A1) PD789114A PD789114A(A1) PD78F9116A PD78F9116B(A1) PD78F9116B PD789101A(A2) PD789101A(A) PD789102A(A2) PD789102A(A) PD789104A(A2) PD789104A(A) PD789111A(A2) PD789111A(A) PD789112A(A2) PD789112A(A) PD789114A(A2) PD789114A(A) PD78F9116B(A) Document No. U14643EJ2V0UD00 (2nd edition) Date Published December 2003 N CP(K) 2000, 2003 Printed in Japan PD789121A PD789121A(A1) PD789122A PD789122A(A1) PD789124A PD789124A(A1) PD789131A PD789131A(A1) PD789132A PD789132A(A1) PD789134A PD789134A(A1) PD78F9136A PD78F9136B(A1) PD78F9136B PD789121A(A2) PD789121A(A) PD789122A(A2) PD789122A(A) PD789124A(A2) PD789124A(A) PD789131A(A2) PD789131A(A) PD789132A(A2) PD789132A(A) PD789134A(A2) PD789134A(A) PD78F9136B(A) [MEMO] 2 User's Manual U14643EJ2V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. User's Manual U14643EJ2V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U14643EJ2V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65 03 01 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J03.4 User's Manual U14643EJ2V0UD 5 Major Revisions in This Edition Pages Throughout Description * Addition of PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2), 78F9116B, 78F9136B, 78F9116B(A), 78F9136B(A), 78F9116B(A1), 78F9136B(A1) * Addition of description related to expanded-specification products pp.24, 36 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) * Addition of 1.1 Expanded-Specification Products and Conventional-Specification Products * Addition of 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products p.48 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) * Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products pp.116 to 118, 121 CHAPTER 8 16-BIT TIMER 20 * Modification of description in 8.4.1 Operation as timer interrupt * Modification of Figure 8-5 Timing of Timer Interrupt Operation * Modification of description in 8.4.2 Operation as timer output * Modification of description in Figure 8-7 Timer Output Timing * Addition of 8.5 Notes on Using 16-Bit Timer 20 p.134 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 * Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80 p.152 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) * Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins pp.155, 164 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) * Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0) * Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins pp.167, 177, 190 CHAPTER 13 SERIAL INTERFACE 20 * Modification of Figure 13-1 Block Diagram of Serial Interface 20 * Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial I/O mode * Addition of 13.4.2 (2) (f) Reading receive data p.210 CHAPTER 15 INTERRUPT FUNCTIONS * Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register p.233 Revision of CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B p.258 Addition of CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS p.387 Addition of CHAPTER 32 and CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) p.393 Addition of CHAPTER 34 and CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) p.397 Addition of CHAPTER 36 PACKAGE DRAWING p.398 Addition of CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS p.400 Revision of APPENDIX A DEVELOPMENT TOOLS p.406 Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN p.412 Addition of APPENDIX D REVISION HISTORY p.257 in 1st edition Deletion of APPENDIX B EMBEDDED SOFTWARE The mark 6 shows major revised points. User's Manual U14643EJ2V0UD INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the PD789104A, 789114A, 789124A, 789134A Subseries and to design and develop application systems and programs using these microcontrollers. The target devices are shown as follows: * PD789104A Subseries: PD789101A, 789102A, 789104A, 789101A(A), 789102A(A), 789104A(A), 789101A(A1), 789102A(A1), 789104A(A1), 789101A(A2), 789102A(A2), 789104A(A2) * PD789114A Subseries: PD789111A, 789112A, 789114A, 78F9116A, 78F9116B, 789111A(A), 789112A(A), 789114A(A), 78F9116B(A), 789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1), 789111A(A2), 789112A(A2), 789114A(A2) * PD789124A Subseries: PD789121A, 789122A, 789124A, 789121A(A), 789122A(A), 789124A(A), 789121A(A1), 789122A(A1), 789124A(A1), 789121A(A2), 789122A(A2), 789124A(A2) * PD789134A Subseries: PD789131A, 789132A, 789134A, 78F9136A, 78F9136B, 789131A(A), 789132A(A), 789134A(A), 78F9136B(A), 789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1), 789131A(A2), 789132A(A2), 789134A(A2) The PD789104A/114A/124A/134A Subseries is a generic term for all the target devices in this manual. Generic names in this document indicate the following products. [Standard quality grade products] PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116A, 78F9116B, 789121A, 789122A, 789124A, 789131A, 789132A, 789134A, 78F9136A, 78F9136B [(A) products] PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A), 789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A), 78F9136B(A) [(A1) products] PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1) [(A2) products] PD789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2) User's Manual U14643EJ2V0UD 7 PD789101A, 789102A, 789104A, 789111A, 789112A, [Mask ROM products] 789114A, 789121A, 789122A, 789124A, 789131A, 789132A, 789134A, 789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A), 789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2) [Flash memory products] PD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1), 78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1) The oscillation frequency of the system clock is regarded as fX for ceramic/crystal oscillation (PD789104A and 789114A Subseries), and regarded as fCC for an RC oscillation (PD789124A and 789134A Subseries). Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The PD789104A, 789114A, 789124A, 789134A Subseries User's Manual is divided into two parts: this manual and instructions (common to the 78K/0S Series). PD789104A, 789114A, 789124A, 789134A Subseries Instructions User's Manual (This manual) User's Manual * Pin functions * CPU function * Internal block functions * Instruction set * Interrupts * Instruction description * Other internal peripheral functions * Electrical specifications 8 78K/0S Series User's Manual U14643EJ2V0UD How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. When using this manual as a manual for the PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A), 789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A), 78F9136B(A), 789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), and 789134A(A2) Only the quality grade, supply voltage, operating ambient temperature, minimum instruction execution time, and electrical specifications differ from the PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116B, 789121A, 789122A, 789124A, 789131A, 789132A, 789134A, and 78F9136B (refer to 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products, 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products). For the (A), (A1), and (A2) products, read the part numbers in CHAPTER 3 to CHAPTER 20 as follows. PD789101A PD789101A(A), 789101A(A1), 789101A(A2) PD789102A PD789102A(A), 789102A(A1), 789102A(A2) PD789104A PD789104A(A), 789104A(A1), 789104A(A2) PD789111A PD789111A(A), 789111A(A1), 789111A(A2) PD789112A PD789112A(A), 789112A(A1), 789112A(A2) PD789114A PD789114A(A), 789114A(A1), 789114A(A2) PD78F9116B PD78F9116B(A), 78F9116B(A1) PD789121A PD789121A(A), 789121A(A1), 789121A(A2) PD789122A PD789122A(A), 789122A(A1), 789122A(A2) PD789124A PD789124A(A), 789124A(A1), 789124A(A2) PD789131A PD789131A(A), 789131A(A1), 789131A(A2) PD789132A PD789132A(A), 789132A(A1), 789132A(A2) PD789134A PD789134A(A), 789134A(A1), 789134A(A2) PD78F9136B PD78F9136B(A), 78F9136B(A1) To understand the overall functions in general Read this manual in the order of the CONTENTS. How to interpret register formats The name of a bit whose number is in angle brackets (<>) is reserved in the assembler and is defined in the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known Refer to APPENDIX C REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E). To know the electrical specifications of the PD789104A/114A/124A/134A Subseries Refer to CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS. Caution The application examples in this manual are created for "Standard" quality grade products for general electric equipment. When using the application examples in this manual for purposes which require "Special" quality grades, thoroughly examine the quality grade of each part and circuit actually used. User's Manual U14643EJ2V0UD 9 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. PD789104A, 789114A, 789124A, 789134A Subseries User's Manual This manual 78K/0S Series Instructions User's Manual U11047E Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Assembler Package CC78K0S C Compiler Document No. Operation U14876E Language U14877E Structured Assembly Language U11623E Operation U14871E Language SM78K Series System Simulator Ver. 2.30 or Later ID78K Series Integrated Debugger Ver. 2.30 or Later U14872E TM Operation (Windows Based) U15373E External Part User Open Interface Specification U15802E Operation (Windows Based) U15185E Project Manager Ver. 3.12 or Later (Windows Based) U14610E Documents Related to Development Hardware Tools (User's Manuals) Document Name Document No. IE-78K0S-NS In-Circuit Emulator U13549E IE-78K0S-NS-A In-Circuit Emulator U15207E IE-789136-NS-EM1 Emulation Board U14363E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 10 User's Manual U14643EJ2V0UD Documents Related to Flash Memory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User's Manual U13502E PG-FP4 Flash Memory Programmer User's Manual U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U14643EJ2V0UD 11 CONTENTS CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES)........................................................ 24 1.1 Expanded-Specification Products and Conventional-Specification Products ...................... 24 1.2 Features......................................................................................................................................... 25 1.3 Applications .................................................................................................................................. 25 1.4 Ordering Information.................................................................................................................... 26 1.5 Quality Grade ................................................................................................................................ 27 1.6 Pin Configuration (Top View) ...................................................................................................... 28 1.7 78K/0S Series Lineup ................................................................................................................... 30 1.8 Block Diagram............................................................................................................................... 33 1.9 Outline of Functions..................................................................................................................... 34 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 36 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES)........................................................ 37 2.1 Features......................................................................................................................................... 37 2.2 Applications .................................................................................................................................. 37 2.3 Ordering Information.................................................................................................................... 38 2.4 Quality Grade ................................................................................................................................ 39 2.5 Pin Configuration (Top View) ...................................................................................................... 40 2.6 78K/0S Series Lineup ................................................................................................................... 42 2.7 Block Diagram............................................................................................................................... 45 2.8 Outline of Functions..................................................................................................................... 46 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 48 CHAPTER 3 PIN FUNCTIONS ............................................................................................................... 49 3.1 Pin Function List........................................................................................................................... 49 3.2 Description of Pin Functions....................................................................................................... 51 3.2.1 P00 to P03 (Port 0) .............................................................................................................................51 3.2.2 P10, P11 (Port 1) ................................................................................................................................51 3.2.3 P20 to P25 (Port 2) .............................................................................................................................51 3.2.4 P50 to P53 (Port 5) .............................................................................................................................52 3.2.5 P60 to P63 (Port 6) .............................................................................................................................52 3.2.6 RESET ................................................................................................................................................52 3.2.7 X1, X2 (PD789104A, 789114A Subseries) .......................................................................................52 3.2.8 CL1, CL2 (PD789124A, 789134A Subseries) ...................................................................................52 3.2.9 AVDD ...................................................................................................................................................52 3.2.10 AVSS ...................................................................................................................................................52 3.2.11 VDD .....................................................................................................................................................52 3.2.12 VSS .....................................................................................................................................................52 3.2.13 VPP (PD78F9116A, 78F9116B, 78F9136A, 78F9136B only).............................................................53 3.2.14 IC0 (pin No.20) (mask ROM versions only).........................................................................................53 3.2.15 IC0 (pins No.10 and No.21) ................................................................................................................53 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 54 CHAPTER 4 CPU ARCHITECTURE ...................................................................................................... 56 4.1 Memory Space .............................................................................................................................. 56 12 User's Manual U14643EJ2V0UD 4.2 4.3 4.4 4.1.1 Internal program memory space .........................................................................................................60 4.1.2 Internal data memory (internal high-speed RAM) space.....................................................................61 4.1.3 Special-function register (SFR) area...................................................................................................61 4.1.4 Data memory addressing....................................................................................................................61 Processor Registers .....................................................................................................................65 4.2.1 Control registers .................................................................................................................................65 4.2.2 General-purpose registers ..................................................................................................................67 4.2.3 Special-function registers (SFRs) .......................................................................................................68 Instruction Address Addressing .................................................................................................71 4.3.1 Relative addressing ............................................................................................................................71 4.3.2 Immediate addressing.........................................................................................................................72 4.3.3 Table indirect addressing....................................................................................................................73 4.3.4 Register addressing ............................................................................................................................73 Operand Address Addressing .....................................................................................................74 4.4.1 Direct addressing................................................................................................................................74 4.4.2 Short direct addressing .......................................................................................................................75 4.4.3 Special-function register (SFR) addressing ........................................................................................76 4.4.4 Register addressing ............................................................................................................................77 4.4.5 Register indirect addressing ...............................................................................................................78 4.4.6 Based addressing ...............................................................................................................................79 4.4.7 Stack addressing ................................................................................................................................79 CHAPTER 5 PORT FUNCTIONS............................................................................................................80 5.1 Functions of Ports.........................................................................................................................80 5.2 Port Configuration.........................................................................................................................82 5.3 5.4 5.2.1 Port 0 ..................................................................................................................................................82 5.2.2 Port 1 ..................................................................................................................................................83 5.2.3 Port 2 ..................................................................................................................................................84 5.2.4 Port 5 ..................................................................................................................................................88 5.2.5 Port 6 ..................................................................................................................................................89 Port Function Control Registers..................................................................................................90 Operation of Port Functions ........................................................................................................93 5.4.1 Writing to I/O port................................................................................................................................93 5.4.2 Reading from I/O port .........................................................................................................................93 5.4.3 Arithmetic operation of I/O port ...........................................................................................................94 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) ....................................95 6.1 Function of Clock Generator........................................................................................................95 6.2 Configuration of Clock Generator ...............................................................................................95 6.3 Register Controlling Clock Generator ........................................................................................96 6.4 System Clock Oscillator ...............................................................................................................97 6.5 6.6 6.4.1 System clock oscillator .......................................................................................................................97 6.4.2 Divider ................................................................................................................................................99 Operation of Clock Generator....................................................................................................100 Changing Setting of CPU Clock.................................................................................................101 6.6.1 Time required for switching CPU clock .............................................................................................101 6.6.2 Switching CPU clock.........................................................................................................................101 User's Manual U14643EJ2V0UD 13 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) ................................. 102 7.1 Function of Clock Generator ..................................................................................................... 102 7.2 Configuration of Clock Generator ............................................................................................ 102 7.3 Register Controlling Clock Generator...................................................................................... 103 7.4 System Clock Oscillator ............................................................................................................ 104 7.5 7.6 7.4.1 System clock oscillator......................................................................................................................104 7.4.2 Examples of incorrect resonator connection .....................................................................................105 7.4.3 Divider...............................................................................................................................................106 Operation of Clock Generator ................................................................................................... 107 Changing Setting of CPU Clock ................................................................................................ 108 7.6.1 Time required for switching CPU clock .............................................................................................108 7.6.2 Switching CPU clock .........................................................................................................................109 CHAPTER 8 16-BIT TIMER 20 ............................................................................................................ 110 8.1 16-Bit Timer 20 Functions.......................................................................................................... 110 8.2 16-Bit Timer 20 Configuration ................................................................................................... 111 8.3 Registers Controlling 16-Bit Timer 20 ...................................................................................... 113 8.4 16-Bit Timer 20 Operation.......................................................................................................... 116 8.5 8.4.1 Operation as timer interrupt ..............................................................................................................116 8.4.2 Operation as timer output..................................................................................................................118 8.4.3 Capture operation .............................................................................................................................119 8.4.4 16-bit timer counter 20 readout .........................................................................................................120 Notes on Using 16-Bit Timer 20 ................................................................................................ 121 8.5.1 Restrictions on rewriting 16-bit compare register 20 .........................................................................121 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 ............................................................................. 123 9.1 Functions of 8-Bit Timer/Event Counter 80 ............................................................................. 123 9.2 8-Bit Timer/Event Counter 80 Configuration ........................................................................... 124 9.3 Registers Controlling 8-Bit Timer/Event Counter 80 .............................................................. 126 9.4 Operation of 8-Bit Timer/Event Counter 80.............................................................................. 128 9.5 9.4.1 Operation as interval timer ................................................................................................................128 9.4.2 Operation as external event counter .................................................................................................130 9.4.3 Operation as square-wave output .....................................................................................................131 9.4.4 Operation as PWM output.................................................................................................................133 Notes on Using 8-Bit Timer/Event Counter 80 ........................................................................ 134 CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 136 10.1 Functions of Watchdog Timer................................................................................................... 136 10.2 Configuration of Watchdog Timer ............................................................................................ 137 10.3 Watchdog Timer Control Registers .......................................................................................... 138 10.4 Operation of Watchdog Timer ................................................................................................... 140 10.4.1 Operation as watchdog timer ............................................................................................................140 10.4.2 Operation as interval timer ................................................................................................................141 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) ........................... 142 11.1 8-Bit A/D Converter Functions .................................................................................................. 142 11.2 8-Bit A/D Converter Configuration............................................................................................ 142 11.3 Registers Controlling 8-Bit A/D Converter .............................................................................. 144 14 User's Manual U14643EJ2V0UD 11.4 8-Bit A/D Converter Operation ...................................................................................................146 11.4.1 Basic operation of 8-bit A/D converter ..............................................................................................146 11.4.2 Input voltage and conversion result ..................................................................................................147 11.4.3 Operation mode of 8-bit A/D converter .............................................................................................149 11.5 Notes on Using 8-Bit A/D Converter .........................................................................................150 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) ..........................154 12.1 10-Bit A/D Converter Functions.................................................................................................154 12.2 10-Bit A/D Converter Configuration ..........................................................................................154 12.3 Registers Controlling 10-Bit A/D Converter .............................................................................156 12.4 10-Bit A/D Converter Operation .................................................................................................158 12.4.1 Basic operation of 10-bit A/D converter ............................................................................................158 12.4.2 Input voltage and conversion result ..................................................................................................159 12.4.3 Operation mode of 10-bit A/D converter ...........................................................................................161 12.5 Notes on Using 10-Bit A/D Converter .......................................................................................162 CHAPTER 13 SERIAL INTERFACE 20 ...............................................................................................166 13.1 Functions of Serial Interface 20.................................................................................................166 13.2 Serial Interface 20 Configuration...............................................................................................166 13.3 Serial Interface 20 Control Registers ........................................................................................170 13.4 Operation of Serial Interface 20 .................................................................................................178 13.4.1 Operation stop mode ........................................................................................................................178 13.4.2 Asynchronous serial interface (UART) mode....................................................................................179 13.4.3 3-wire serial I/O mode.......................................................................................................................192 CHAPTER 14 MULTIPLIER ...................................................................................................................202 14.1 Multiplier Function ......................................................................................................................202 14.2 Multiplier Configuration..............................................................................................................202 14.3 Multiplier Control Register .........................................................................................................204 14.4 Multiplier Operation ....................................................................................................................205 CHAPTER 15 INTERRUPT FUNCTIONS .............................................................................................206 15.1 Interrupt Function Types ............................................................................................................206 15.2 Interrupt Sources and Configuration ........................................................................................207 15.3 Interrupt Function Control Registers ........................................................................................209 15.4 Interrupt Servicing Operation ....................................................................................................214 15.4.1 Non-maskable interrupt request acknowledgment operation ............................................................214 15.4.2 Maskable interrupt request acknowledgment operation....................................................................216 15.4.3 Multiple interrupt servicing ................................................................................................................218 15.4.4 Interrupt request hold........................................................................................................................220 CHAPTER 16 STANDBY FUNCTION...................................................................................................221 16.1 Standby Function and Configuration........................................................................................221 16.1.1 Standby function ...............................................................................................................................221 16.1.2 Standby function control register (PD789104A, 789114A Subseries).............................................222 16.2 Operation of Standby Function .................................................................................................223 16.2.1 HALT mode.......................................................................................................................................223 16.2.2 STOP mode ......................................................................................................................................226 User's Manual U14643EJ2V0UD 15 CHAPTER 17 RESET FUNCTION ....................................................................................................... 229 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B .................................................... 233 18.1 Flash Memory Characteristics .................................................................................................. 234 18.1.1 Programming environment................................................................................................................234 18.1.2 Communication mode .......................................................................................................................235 18.1.3 On-board pin processing...................................................................................................................240 18.1.4 Connection when using flash memory writing adapter ......................................................................243 CHAPTER 19 MASK OPTION (MASK ROM VERSION).................................................................. 247 CHAPTER 20 INSTRUCTION SET ...................................................................................................... 248 20.1 Operation..................................................................................................................................... 248 20.1.1 Operand identifiers and description methods ....................................................................................248 20.1.2 Description of "operation" column .....................................................................................................249 20.1.3 Description of "flag operation" column...............................................................................................249 20.2 Operation List ............................................................................................................................. 250 20.3 Instructions Listed by Addressing Type.................................................................................. 255 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)............................................................... 258 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)...................................................... 271 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) .................................. 283 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) ............................ 294 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) ............................................. 307 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) .................................................... 318 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) .................................................... 330 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) .................................. 341 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) ............................ 352 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) ............................................. 364 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) .................................................... 375 CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) .................................................... 387 16 User's Manual U14643EJ2V0UD CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))...................................390 CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A) .......................................................................................................................393 CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))...................................................................................................................395 CHAPTER 36 PACKAGE DRAWING ...................................................................................................397 CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS ...........................................................398 APPENDIX A DEVELOPMENT TOOLS ...............................................................................................400 A.1 Software Package........................................................................................................................402 A.2 Language Processing Software.................................................................................................402 A.3 Control Software .........................................................................................................................403 A.4 Flash Memory Writing Tools ......................................................................................................403 A.5 Debugging Tools (Hardware) .....................................................................................................404 A.6 Debugging Tools (Software) ......................................................................................................405 APPENDIX B NOTES ON TARGET SYSTEM DESIGN....................................................................406 APPENDIX C REGISTER INDEX..........................................................................................................408 C.1 Register Name Index (Alphabetical Order)...............................................................................408 C.2 Register Symbol Index (Alphabetical Order)............................................................................410 APPENDIX D REVISION HISTORY ......................................................................................................412 User's Manual U14643EJ2V0UD 17 LIST OF FIGURES (1/4) Figure No. Title Page 3-1 Pin I/O Circuits..............................................................................................................................................55 4-1 Memory Map (PD789101A, 789111A, 789121A, 789131A) .......................................................................56 4-2 Memory Map (PD789102A, 789112A, 789122A, 789132A) .......................................................................57 4-3 Memory Map (PD789104A, 789114A, 789124A, 789134A) .......................................................................58 4-4 Memory Map (PD78F9116A, 78F9116B, 78F9136A, 78F9136B) ..............................................................59 4-5 Data Memory Addressing (PD789101A, 789111A, 789121A, 789131A)....................................................61 4-6 Data Memory Addressing (PD789102A, 789112A, 789122A, 789132A)....................................................62 4-7 Data Memory Addressing (PD789104A, 789114A, 789124A, 789134A)....................................................63 4-8 Data Memory Addressing (PD78F9116A, 78F9116B, 78F9136A, 78F9136B) ...........................................64 4-9 Program Counter Configuration....................................................................................................................65 4-10 Program Status Word Configuration.............................................................................................................65 4-11 Stack Pointer Configuration ..........................................................................................................................66 4-12 Data to Be Saved to Stack Memory..............................................................................................................66 4-13 Data to Be Restored from Stack Memory .....................................................................................................66 4-14 General-Purpose Register Configuration......................................................................................................67 5-1 Port Types ....................................................................................................................................................80 5-2 Block Diagram of P00 to P03........................................................................................................................82 5-3 Block Diagram of P10 and P11.....................................................................................................................83 5-4 Block Diagram of P20...................................................................................................................................84 5-5 Block Diagram of P21...................................................................................................................................85 5-6 Block Diagram of P22, P23, and P25 ...........................................................................................................86 5-7 Block Diagram of P24...................................................................................................................................87 5-8 Block Diagram of P50 to P53........................................................................................................................88 5-9 Block Diagram of P60 to P63........................................................................................................................89 5-10 Port Mode Register Format ..........................................................................................................................91 5-11 Format of Pull-up Resistor Option Register 0 ...............................................................................................91 5-12 Format of Pull-up Resistor Option Register B2.............................................................................................92 6-1 Block Diagram of Clock Generator ...............................................................................................................95 6-2 Format of Processor Clock Control Register ................................................................................................96 6-3 External Circuit of System Clock Oscillator...................................................................................................97 6-4 Examples of Incorrect Resonator Connection .............................................................................................98 6-5 Switching CPU Clock..................................................................................................................................101 7-1 Block Diagram of Clock Generator .............................................................................................................102 7-2 Format of Processor Clock Control Register ..............................................................................................103 7-3 External Circuit of System Clock Oscillator.................................................................................................104 7-4 Examples of Incorrect Resonator Connection ...........................................................................................105 7-5 Switching CPU Clock..................................................................................................................................109 8-1 Block Diagram of 16-Bit Timer 20...............................................................................................................111 18 User's Manual U14643EJ2V0UD LIST OF FIGURES (2/4) Figure No. Title Page 8-2 Format of 16-Bit Timer Mode Control Register 20......................................................................................114 8-3 Format of Port Mode Register 2 .................................................................................................................115 8-4 Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation .......................................116 8-5 Timing of Timer Interrupt Operation ...........................................................................................................117 8-6 Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation.........................................118 8-7 Timer Output Timing...................................................................................................................................118 8-8 Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation.................................................119 8-9 Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) ........................................................119 8-10 16-Bit Timer Counter 20 Readout Timing ...................................................................................................120 9-1 Block Diagram of 8-Bit Timer/Event Counter 80.........................................................................................125 9-2 Format of 8-Bit Timer Mode Control Register 80........................................................................................126 9-3 Format of Port Mode Register 2 .................................................................................................................127 9-4 Interval Timer Operation Timing .................................................................................................................129 9-5 External Event Counter Operation Timing (with Rising Edge Specified) ....................................................130 9-6 Square-Wave Output Timing ......................................................................................................................132 9-7 PWM Output Timing ...................................................................................................................................133 9-8 Start Timing of 8-Bit Timer Counter............................................................................................................134 9-9 External Event Counter Operation Timing ..................................................................................................134 9-10 Timing After Writing Compare Register During PWM Output .....................................................................135 10-1 Block Diagram of Watchdog Timer.............................................................................................................137 10-2 Format of Timer Clock Select Register 2....................................................................................................138 10-3 Format of Watchdog Timer Mode Register ................................................................................................139 11-1 Block Diagram of 8-Bit A/D Converter ........................................................................................................142 11-2 Format of A/D Converter Mode Register 0 .................................................................................................144 11-3 Format of Analog Input Channel Specification Register 0 ..........................................................................145 11-4 Basic Operation of 8-Bit A/D Converter......................................................................................................147 11-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................148 11-6 Software-Started A/D Conversion ..............................................................................................................149 11-7 How to Reduce Current Consumption in Standby Mode ............................................................................150 11-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................151 11-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................151 11-10 Analog Input Pin Treatment........................................................................................................................151 11-11 A/D Conversion End Interrupt Request Generation Timing ........................................................................152 11-12 AVDD Pin Treatment ...................................................................................................................................153 12-1 Block Diagram of 10-Bit A/D Converter ......................................................................................................154 12-2 Format of A/D Converter Mode Register 0 .................................................................................................156 12-3 Format of Analog Input Channel Specification Register 0 ..........................................................................157 12-4 Basic Operation of 10-Bit A/D Converter....................................................................................................159 12-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160 User's Manual U14643EJ2V0UD 19 LIST OF FIGURES (3/4) Figure No. Title Page 12-6 Software-Started A/D Conversion...............................................................................................................161 12-7 How to Reduce Current Consumption in Standby Mode ............................................................................162 12-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................163 12-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value) .......................................163 12-10 Analog Input Pin Treatment ........................................................................................................................163 12-11 A/D Conversion End Interrupt Request Generation Timing ........................................................................164 12-12 AVDD Pin Treatment....................................................................................................................................165 13-1 Block Diagram of Serial Interface 20 ..........................................................................................................167 13-2 Baud Rate Generator Block Diagram .........................................................................................................168 13-3 Format of Serial Operating Mode Register 20 ............................................................................................171 13-4 Format of Asynchronous Serial Interface Mode Register 20 ......................................................................172 13-5 Format of Asynchronous Serial Interface Status Register 20 .....................................................................174 13-6 Format of Baud Rate Generator Control Register 20 .................................................................................175 13-7 Asynchronous Serial Interface Transmit/Receive Data Format ..................................................................185 13-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................187 13-9 Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................188 13-10 Receive Error Timing..................................................................................................................................189 13-11 3-Wire Serial I/O Mode Timing ...................................................................................................................195 14-1 Block Diagram of Multiplier .........................................................................................................................203 14-2 Format of Multiplier Control Register 0 .......................................................................................................204 14-3 Multiplier Operation Timing.........................................................................................................................205 15-1 Basic Configuration of Interrupt Function....................................................................................................208 15-2 Format of Interrupt Request Flag Register .................................................................................................210 15-3 Format of Interrupt Mask Flag Register ......................................................................................................211 15-4 Format of External Interrupt Mode Register 0.............................................................................................212 15-5 Program Status Word Configuration...........................................................................................................213 15-6 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment.....................................215 15-7 Timing of Non-Maskable Interrupt Request Acknowledgment ....................................................................215 15-8 Acknowledging Non-Maskable Interrupt Request .......................................................................................215 15-9 Interrupt Acknowledgment Program Algorithm ...........................................................................................217 15-10 Interrupt Request Acknowledgment Timing (Example of MOV A,r) ............................................................218 15-11 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated at Last Clock During Instruction Execution) ..........................218 15-12 Example of Multiple Interrupt Servicing ......................................................................................................219 16-1 Format of Oscillation Stabilization Time Select Register ............................................................................222 16-2 Releasing HALT Mode by Interrupt ............................................................................................................224 16-3 Releasing HALT Mode by RESET Input .....................................................................................................225 16-4 Releasing STOP Mode by Interrupt............................................................................................................227 16-5 Releasing STOP Mode by RESET Input ....................................................................................................228 20 User's Manual U14643EJ2V0UD LIST OF FIGURES (4/4) Figure No. Title Page 17-1 Block Diagram of Reset Function ...............................................................................................................229 17-2 Reset Timing by RESET Input ...................................................................................................................230 17-3 Reset Timing by Overflow in Watchdog Timer ...........................................................................................230 17-4 Reset Timing by RESET Input in STOP Mode ...........................................................................................230 18-1 Environment for Writing Program to Flash Memory....................................................................................234 18-2 Communication Mode Selection Format ....................................................................................................236 18-3 Example of Connection with Dedicated Flash Programmer ......................................................................237 18-4 VPP Pin Connection Example......................................................................................................................240 18-5 Signal Conflict (Input Pin of Serial Interface) ..............................................................................................241 18-6 Abnormal Operation of Other Device .........................................................................................................241 18-7 Signal Conflict (RESET Pin) .......................................................................................................................242 18-8 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch0) ...243 18-9 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch1) ...244 18-10 Example of Flash Memory Writing Adapter Connection When Using UART Mode ....................................245 18-11 Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode ......................246 A-1 Development Tools ....................................................................................................................................401 B-1 Distance Between In-Circuit Emulator and Conversion Adapter ................................................................406 B-2 Connection Condition of Target System (NP-H44GB-TQ) .........................................................................407 User's Manual U14643EJ2V0UD 21 LIST OF TABLES (1/2) Table No. Title Page 1-1 Differences Between Expanded-Specification Products and Conventional-Specification Products..............24 1-2 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................36 2-1 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................48 3-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins...................................................54 4-1 Internal ROM Capacity .................................................................................................................................60 4-2 Vector Table .................................................................................................................................................60 4-3 Special-Function Register List .....................................................................................................................69 5-1 Port Functions ..............................................................................................................................................81 5-2 Configuration of Port.....................................................................................................................................82 5-3 Port Mode Register and Output Latch Settings When Using Alternate Functions ........................................90 6-1 Configuration of Clock Generator .................................................................................................................95 6-2 Maximum Time Required for Switching CPU Clock....................................................................................101 7-1 Configuration of Clock Generator ...............................................................................................................102 7-2 Maximum Time Required for Switching CPU Clock....................................................................................108 8-1 Configuration of 16-Bit Timer 20.................................................................................................................111 8-2 Interval Time of 16-Bit Timer 20 .................................................................................................................116 8-3 Settings of Capture Edge............................................................................................................................119 9-1 Interval Time of 8-Bit Timer/Event Counter 80............................................................................................123 9-2 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 ...................................................................124 9-3 8-Bit Timer/Event Counter 80 Configuration ...............................................................................................124 9-4 Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) ..............................128 9-5 Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)..............................................128 9-6 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) ......131 9-7 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation) .....................131 10-1 Program Loop Detection Time of Watchdog Timer.....................................................................................136 10-2 Interval Time...............................................................................................................................................136 10-3 Configuration of Watchdog Timer ...............................................................................................................137 10-4 Program Loop Detection Time of Watchdog Timer.....................................................................................140 10-5 Interval Time of Interval Timer ....................................................................................................................141 11-1 Configuration of 8-Bit A/D Converter ..........................................................................................................142 12-1 Configuration of 10-Bit A/D Converter ........................................................................................................154 22 User's Manual U14643EJ2V0UD LIST OF TABLES (2/2) Table No. Title Page 13-1 Configuration of Serial Interface 20 ............................................................................................................166 13-2 Serial Interface 20 Operating Mode Settings..............................................................................................173 13-3 Example of Relationship Between System Clock and Baud Rate ..............................................................176 13-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......177 13-5 Example of Relationship Between System Clock and Baud Rate ..............................................................184 13-6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......184 13-7 Receive Error Causes ................................................................................................................................189 15-1 Interrupt Source List ...................................................................................................................................207 15-2 Flags Corresponding to Interrupt Request Signals.....................................................................................209 15-3 Time from Generation of Maskable Interrupt Request to Servicing ............................................................216 16-1 HALT Mode Operating Status ....................................................................................................................223 16-2 Operation After Release of HALT Mode.....................................................................................................225 16-3 STOP Mode Operating Status....................................................................................................................226 16-4 Operation After Release of STOP Mode ....................................................................................................228 17-1 Hardware Status After Reset .....................................................................................................................231 18-1 Differences Between Flash Memory and Mask ROM Versions ..................................................................233 18-2 Communication Mode List (PD78F9116A, 78F9136A).............................................................................235 18-3 Communication Mode List (PD78F9116B, 78F9136B).............................................................................235 18-4 Pin Connection List ....................................................................................................................................239 19-1 Selection of Mask Option for Pins ..............................................................................................................247 20-1 Operand Identifiers and Description Methods ............................................................................................248 37-1 Surface Mounting Type Soldering Conditions ...........................................................................................398 User's Manual U14643EJ2V0UD 23 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.1 Expanded-Specification Products and Conventional-Specification Products The expanded-specification products and the conventional-specification products indicate the following products. Expanded-specification products......... Products other than rankNote 1 K * Mask ROM products ordered on or later than December 1, 2001 (excluding (A1) and (A2) productsNote 2) * Flash memory products shipped on or later than January 1, 2002 (excluding (A1), (A2) productsNote 2 and the PD78F9116A) Conventional-specification products .....RankNote 1 K products * Products other than above Notes 1. The rank is indicated by the letter at the 5th digit from the left in the lot number in the package marking. Lot number Year code Week code Rank 2. For (A1) and (A2) products, refer to 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products. The operating frequency specification differs between the expanded-specification products and the conventionalspecification products as shown in Table 1-1. Table 1-1. Differences Between Expanded-Specification Products and Conventional-Specification Products Supply Voltage (VDD) Remark 24 Guaranteed Operating Speed (Operating Frequency) Conventional-Specification Expanded-Specification Products Products 4.5 to 5.5 V 5 MHz (0.4 s) 10 MHz (0.2 s) 3.0 to 5.5 V 5 MHz (0.4 s) 6 MHz (0.33 s) 2.7 to 5.5 V 5 MHz (0.4 s) 5 MHz (0.4 s) 1.8 to 5.5 V 1.25 MHz (1.6 s) 1.25 MHz (1.6 s) The figures in parentheses indicate the minimum instruction execution time. User's Manual U14643EJ2V0UD CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.2 Features * ROM and RAM capacities Item Program Memory Data Memory (Internal High-Speed RAM) Part Number PD789101A, 789111A, 789101A(A), 789111A(A), Mask ROM 2 KB 256 bytes 789101A(A1), 789111A(A1), 789101A(A2), 789111A(A2) PD789102A, 789112A, 789102A(A), 789112A(A), 4 KB 789102A(A1), 789112A(A1), 789102A(A2), 789112A(A2) PD789104A, 789114A, 789104A(A), 789114A(A), 8 KB 789104A(A1), 789114A(A1), 789104A(A2), 789114A(A2) PD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1) Flash memory 16 KB * System clock: Crystal/ceramic oscillation * Minimum instruction execution times switchable between high speed (0.2 s) and low speed (0.8 s) (system clock: 10.0 MHzNote) * 20 I/O ports * Serial interface: 1 channel 3-wire serial I/O mode/UART mode selectable * 8-bit resolution A/D converter: 4 channels (PD789104A Subseries) * 10-bit resolution A/D converter: 4 channels (PD789114A Subseries) * 3 timers * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel * Multiplier: 8 bits x 8 bits = 16 bits * Vectored interrupt sources: 10 * Supply voltage * VDD = 1.8 to 5.5 V (PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A)) * VDD = 4.5 to 5.5 V (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2), 78F9116B(A1)) * Operating ambient temperature * TA = -40 to + 85C (PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A)) * TA = -40 to +105C (PD78F9116B(A1)) * TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)) * TA = -40 to +125C (PD78910xA(A2), 78911xA(A2)) Note When VDD = 4.5 to 5.5 V and for expanded-specification products only 1.3 Applications Vacuum cleaners, washing machines, refrigerators, battery chargers, etc. User's Manual U14643EJ2V0UD 25 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.4 Ordering Information Part Number PD789101AMC-xxx-5A4 PD789102AMC-xxx-5A4 PD789104AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD78F9116AMC-5A4 PD78F9116BMC-5A4 PD789101AMC(A)-xxx-5A4 PD789102AMC(A)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 PD78F9116BMC(A)-5A4 PD789101AMC(A1)-xxx-5A4 PD789102AMC(A1)-xxx-5A4 PD789104AMC(A1)-xxx-5A4 PD789111AMC(A1)-xxx-5A4 PD789112AMC(A1)-xxx-5A4 PD789114AMC(A1)-xxx-5A4 PD78F9116BMC(A1)-5A4 PD789101AMC(A2)-xxx-5A4 PD789102AMC(A2)-xxx-5A4 PD789104AMC(A2)-xxx-5A4 PD789111AMC(A2)-xxx-5A4 PD789112AMC(A2)-xxx-5A4 PD789114AMC(A2)-xxx-5A4 Remark 26 Package Internal ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM xxx indicates ROM code suffix. User's Manual U14643EJ2V0UD CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.5 Quality Grade Part Number PD789101AMC-xxx-5A4 PD789102AMC-xxx-5A4 PD789104AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD78F9116AMC-5A4 PD78F9116BMC-5A4 PD789101AMC(A)-xxx-5A4 PD789102AMC(A)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 PD78F9116BMC(A)-5A4 PD789101AMC(A1)-xxx-5A4 PD789102AMC(A1)-xxx-5A4 PD789104AMC(A1)-xxx-5A4 PD789111AMC(A1)-xxx-5A4 PD789112AMC(A1)-xxx-5A4 PD789114AMC(A1)-xxx-5A4 PD78F9116BMC(A1)-5A4 PD789101AMC(A2)-xxx-5A4 PD789102AMC(A2)-xxx-5A4 PD789104AMC(A2)-xxx-5A4 PD789111AMC(A2)-xxx-5A4 PD789112AMC(A2)-xxx-5A4 PD789114AMC(A2)-xxx-5A4 Remark Package Quality Grade 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U14643EJ2V0UD 27 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.6 Pin Configuration (Top View) * 30-pin plastic SSOP (7.62 mm (300)) PD789101AMC-xxx-5A4 PD789111AMC-xxx-5A4 PD78F9116AMC-5A4 PD789101AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4 PD78F9116BMC(A)-5A4 PD789101AMC(A1)-xxx-5A4 PD789111AMC(A1)-xxx-5A4 PD78F9116BMC(A1)-5A4 PD789101AMC(A2)-xxx-5A4 PD789111AMC(A2)-xxx-5A4 PD789102AMC-xxx-5A4 PD789112AMC-xxx-5A4 PD78F9116BMC-5A4 PD789102AMC(A)-xxx-5A4 PD789112AMC(A)-xxx-5A4 PD789104AMC-xxx-5A4 PD789114AMC-xxx-5A4 PD789102AMC(A1)-xxx-5A4 PD789112AMC(A1)-xxx-5A4 PD789104AMC(A1)-xxx-5A4 PD789114AMC(A1)-xxx-5A4 PD789102AMC(A2)-xxx-5A4 PD789112AMC(A2)-xxx-5A4 PD789104AMC(A2)-xxx-5A4 PD789114AMC(A2)-xxx-5A4 PD789104AMC(A)-xxx-5A4 PD789114AMC(A)-xxx-5A4 P23/INTP0/CPT20/SS20 1 30 P22/SI20/RXD20 P24/INTP1/TO80/TO20 2 29 P21/SO20/TXD20 P25/INTP2/TI80 3 28 P20/SCK20/ASCK20 AVDD 4 27 P11 P60/ANI0 5 26 P10 P61/ANI1 6 25 VDD P62/ANI2 7 24 VSS P63/ANI3 8 23 X1 AVSS 9 22 X2 IC0 10 21 IC0 P50 11 20 IC0 (VPP) P51 12 19 RESET P52 13 18 P03 P53 14 17 P02 P00 15 16 P01 Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. Remark The pin connection in parentheses is intended for the PD78F9116A, 78F9116B, 78F9116B(A), and 78F9116B(A1). 28 User's Manual U14643EJ2V0UD CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) ANI0 to ANI3: Analog input RxD20: Receive data ASCK20: Asynchronous serial input SCK20: Serial clock AVDD: Analog power supply SI20: Serial input AVSS: Analog ground SO20: Serial output CPT20: Capture trigger input SS20: Chip select input IC0: Internally connected TI80: Timer input INTP0 to INTP2: External interrupt input TO20, TO80: Timer output P00 to P03: Port 0 TxD20: Transmit data P10, P11: Port 1 VDD: Power supply P20 to P25: Port 2 VPP: Programming power supply P50 to P53: Port 5 VSS: Ground P60 to P63: Port 6 X1, X2: Crystal 1, 2 RESET: Reset User's Manual U14643EJ2V0UD 29 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.7 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications PD789046 44-pin 42-/44-pin PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation RC oscillation version of the PD789052 PD789860 without EEPROMTM, POC, and LVI PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 30-pin 30-pin 28-pin 20-pin 20-pin Small-scale package, general-purpose applications and A/D converter PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177Y PD789167Y PD789167 with enhanced A/D converter (10 bits) PD789104A with enhanced timer PD789146 with enhanced A/D converter (10 bits) PD789104A with added EEPROM PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the PD789104A PD789104A with enhanced A/D converter (10 bits) PD789026 with added 8-bit A/D converter and multiplier LCD drive 78K/0S Series 144-pin 88-pin PD789835 PD789830 UART, 8-bit A/D, and dot LCD (Total display output pins: 96) UART and dot LCD (40 x 16) 80-pin PD789488 80-pin 80-pin SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 52-pin PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 52-pin PD789327 8-bit A/D and on-chip voltage booster type LCD (23 x 4) SIO and resistance division type LCD (24 x 4) PD789800 For PC keyboard and on-chip USB function 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin USB 44-pin Inverter control 44-pin PD789842 On-chip inverter controller and UART On-chip bus controller 44-pin 30-pin PD789852 PD789850A with enhanced functions such as timer and A/D converter PD789850A On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin PD789862 PD789861 PD789860 PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity RC oscillation version of the PD789860 On-chip POC and key return circuit VFD drive 52-pin PD789871 On-chip VFD controller (Total display output pins: 25) Meter control 64-pin Remark PD789881 UART and resistance division type LCD (26 x 4) VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 30 User's Manual U14643EJ2V0UD CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) The major functional differences between the subseries are listed below. Series for general-purpose applications and LCD drive Function ROM Capacity Timer 8-Bit 10-Bit 8-Bit 16-Bit Watch WDT A/D A/D Serial I/O Interface package, general- PD789026 PD789088 purpose applications Remarks MIN. Subseries Name Small-scale PD789046 VDD Value 16 KB 1 ch 1 ch 1 ch - - - 4 KB to 16 KB 16 KB to 1 ch 1 ch (UART: 1 ch) 3 ch 34 - 1.8 V 24 32 KB PD789074 2 KB to 8 KB 1 ch PD789014 2 KB to 4 KB 2 ch PD789062 4 KB - 22 - 14 RC oscillation version PD789052 - Small-scale PD789177 16 KB to package, PD789167 24 KB PD789156 8 KB to 16 KB 1 ch generalpurpose 3 ch 1 ch 1 ch 1 ch - - 8 ch - - 4 ch 4 ch - applications PD789146 and A/D PD789134A 2 KB to 8 KB converter PD789124A - 4 ch 4 ch - PD789114A - 4 ch PD789104A 4 ch - 3 ch - LCD drive PD789835 24 KB to 6 ch - 1 ch 1 ch 31 8 ch 1 ch 60 KB 24 KB 1 ch PD789488 32 KB to 48 KB 3 ch PD789478 24 KB to 48 KB 1 ch EEPROM RC oscillation version - 37 1 ch - 8 ch 2 ch (UART: 1 ch) - 30 2.7 V 45 1.8 V 43 - 6 ch 30 6 ch - PD789436 - 6 ch PD789426 6 ch - PD789456 12 KB to 16 KB PD789446 PD789316 7 ch 2 ch - 8 KB to 16 KB Dot LCD - 40 2 ch (UART: 1 ch) 23 PD789306 PD789467 Note supported 7 ch 1 ch (UART: 1 ch) - PD789407A 1.8 V - 8 ch PD789417A 12 KB to 24 KB On-chip 20 (UART: 1 ch) PD789830 - 1.8 V (UART: 1 ch) RC oscillation version - 4 KB to 24 KB PD789327 - - 1 ch - 1 ch 18 21 Note Flash memory version: 3.0 V User's Manual U14643EJ2V0UD 31 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) Series for ASSP Function ROM Capacity Timer 8-Bit 10-Bit 8-Bit 16-Bit Watch WDT A/D A/D - - Serial I/O Interface PD789800 8 KB 2 ch - - 1 ch 2 ch Remarks MIN. Value Subseries Name USB VDD 31 4.0 V - 30 4.0 V - 31 4.0 V - (USB: 1 ch) Inverter PD789842 8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch - control 1 ch (UART: 1 ch) On-chip bus PD789852 controller 24 KB to 32 KB PD789850A 16 KB 3 ch 1 ch - 1 ch 1 ch - 4 ch 8 ch 3 ch (UART: 2 ch) - 2 ch 18 (UART: 1 ch) Keyless PD789861 4 KB 2 ch - - 1 ch - - - 14 1.8 V entry RC oscillation version, onchip EEPROM PD789860 PD789862 On-chip 16 KB 1 ch 2 ch 1 ch EEPROM 22 (UART: 1 ch) VFD drive PD789871 Meter control PD789881 4 KB to 8 KB 16 KB 3 ch 2 ch - 1 ch 1 ch - 1 ch - - 1 ch - - Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V 32 User's Manual U14643EJ2V0UD 1 ch 1 ch (UART: 1 ch) 33 2.7 V 28 2.7 V Note 2 - - CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.8 Block Diagram TI80/INTP2/P25 TO80/TO20 /INTP1/P24 TO20/TO80 /INTP1/P24 8-bit timer/ event counter 80 16-bit timer 20 Port 0 P00 to P03 Port 1 P10, P11 Port 2 P20 to P25 Port 5 P50 to P53 Port 6 P60 to P63 CPT20/INTP0 /SS20/P23 Watchdog timer ROM (flash memory) 78K/0S CPU core SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 Serial interface 20 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D converter VDD VSS IC0 (VPP) System control RESET X1 X2 Interrupt control INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25 Remarks 1. The size of the internal ROM varies depending on the product. 2. Items in parentheses apply to the PD78F9116A, 78F9116B, 78F9116B(A), and 78F9116B(A1). User's Manual U14643EJ2V0UD 33 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.9 Outline of Functions Item Internal memory ROM PD789101A, 789111A, PD789102A, 789112A, PD789104A, 789114A, 789101A(A), 789111A(A), 789102A(A), 789112A(A), 789104A(A), 789114A(A), PD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1) 789101A(A1), 789111A(A1), 789102A(A1), 789112A(A1), 789104A(A1), 789114A(A1), 789101A(A2), 789111A(A2) 789102A(A2), 789112A(A2) 789104A(A2), 789114A(A2) Mask ROM Flash memory 2 KB High-speed RAM 4 KB 8 KB 16 KB 256 bytes System clock Crystal/ceramic oscillation Minimum instruction execution time Expanded-specification products of the PD78910xA, 78910xA(A), 78911xA, 78911xA(A), 78F9116B, 78F9116B(A) * 0.2 s/0.8 s (@ system clock: 10.0 MHz operation, VDD = 4.5 to 5.5 V) Other * 0.4 s/1.6 s (@ system clock: 5.0 MHz operation) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operations * Bit manipulations (such as set, reset, and test) Multiplier 8 bits x 8 bits = 16 bits I/O ports Total: 20 * CMOS input: 4 * CMOS I/O: * N-ch open-drain: 12 4 A/D converter 8-bit resolution x 4 channels (PD789104A Subseries) 10-bit resolution x 4 channels (PD789114A Subseries) Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel Timer Timer outputs Vectored interrupts 16-bit timer: 1 channel 8-bit timer/event counter: Watchdog timer: 1 channel 1 channel One output Maskable Internal: 6, External: 3 Non-maskable Internal: 1 Supply voltage VDD = 1.8 to 5.5 V (PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A)) VDD = 4.5 to 5.5 V (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2), 78F9116B(A1)) Operating ambient temperature TA = -40 to +85C (PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A)) TA = -40 to +105C (PD78F9116B(A1)) TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)) TA = -40 to +125C (PD78910xA(A2), 78911xA(A2)) Package 34 30-pin plastic SSOP (7.62 mm (300)) User's Manual U14643EJ2V0UD CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) An outline of the timers is shown below. Operating Mode Function 16-Bit Timer 20 8-Bit Timer/Event Counter 80 Interval timer - 1 channel External event timer - 1 channel - Timer output 1 output 1 output - PWM output - 1 output - Square-wave output - 1 output - 1 input - - 1 1 1 Capture Interrupt sources Watchdog Timer 1 channel Note Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the two functions can be used at a time. User's Manual U14643EJ2V0UD 35 CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products The standard quality grade products and the (A), (A1), and (A2) products refer to the following products. [Standard quality grade products]... PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116A, 78F9116B [(A) products] .... PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A) [(A1) products] .... PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1) [(A2) products] .... PD789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2) The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in Table 1-2. Table 1-2. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products Products Item Standard Quality Grade (A) Products (A1) Products (A2) Products Products Quality grade Standard Special Supply voltage VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V Operating TA = -40 to +85C * PD78F9116B(A1) TA = -40 to +125C TA = -40 to +105C ambient temperature * Other than PD78F9116B(A1) TA = -40 to +110C Minimum instruction execution time Electrical Note Expanded-specification products : 0.4 s (@ 5.0 MHz operation) 0.2 s (@ 10.0 MHz operation) Note Conventional-specification products : 0.4 s (@ 5.0 MHz operation) Refer to the relevant electrical specifications chapter. specifications Note Refer to 1.1 Expanded-Specification Products and Conventional-Specification Products. 36 User's Manual U14643EJ2V0UD CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) Caution All PD789124A, 789134A Subseries products are conventional-specification products. No expanded-specification products are available in the PD789124A, 789134A Subseries. 2.1 Features * ROM and RAM capacities Item Program Memory Data Memory (Internal High-Speed RAM) Part Number PD789121A, 789131A, 789121A(A), 789131A(A), Mask ROM 2 KB 256 bytes 789121A(A1), 789131A(A1), 789121A(A2), 789131A(A2) PD789122A, 789132A, 789122A(A), 789132A(A), 4 KB 789122A(A1), 789132A(A1), 789122A(A2), 789132A(A2) PD789124A, 789134A, 789124A(A), 789134A(A), 8 KB 789124A(A1), 789134A(A1), 789124A(A2), 789134A(A2) PD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1) Flash memory 16 KB * System clock: RC oscillation * Minimum instruction execution times switchable between high speed (0.5 s) and low speed (2.0 s) (system clock: 4.0 MHz) * 20 I/O ports * Serial interface: 1 channel 3-wire serial I/O mode/UART mode selectable * 8-bit resolution A/D converter: 4 channels (PD789124A Subseries) * 10-bit resolution A/D converter: 4 channels (PD789134A Subseries) * 3 timers * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel * Multiplier: 8 bits x 8 bits = 16 bits * Vectored interrupt sources: 10 * Supply voltage * VDD = 1.8 to 5.5 V (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A)) * VDD = 4.5 to 5.5 V (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2), 78F9136B(A1)) * Operating ambient temperature * TA = -40 to + 85C (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A)) * TA = -40 to +105C (PD78F9136B(A1)) * TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)) * TA = -40 to +125C (PD78912xA(A2), 78913xA(A2)) 2.2 Applications Vacuum cleaners, washing machines, refrigerators, battery chargers, etc. User's Manual U14643EJ2V0UD 37 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.3 Ordering Information Part Number PD789121AMC-xxx-5A4 PD789122AMC-xxx-5A4 PD789124AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD78F9136AMC-5A4 PD78F9136BMC-5A4 PD789121AMC(A)-xxx-5A4 PD789122AMC(A)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 PD78F9136BMC(A)-5A4 PD789121AMC(A1)-xxx-5A4 PD789122AMC(A1)-xxx-5A4 PD789124AMC(A1)-xxx-5A4 PD789131AMC(A1)-xxx-5A4 PD789132AMC(A1)-xxx-5A4 PD789134AMC(A1)-xxx-5A4 PD78F9136BMC(A1)-5A4 PD789121AMC(A2)-xxx-5A4 PD789122AMC(A2)-xxx-5A4 PD789124AMC(A2)-xxx-5A4 PD789131AMC(A2)-xxx-5A4 PD789132AMC(A2)-xxx-5A4 PD789134AMC(A2)-xxx-5A4 Remark 38 Package Internal ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Flash memory 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM 30-pin plastic SSOP (7.62 mm (300)) Mask ROM xxx indicates ROM code suffix. User's Manual U14643EJ2V0UD CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.4 Quality Grade Part Number PD789121AMC-xxx-5A4 PD789122AMC-xxx-5A4 PD789124AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD78F9136AMC-5A4 PD78F9136BMC-5A4 PD789121AMC(A)-xxx-5A4 PD789122AMC(A)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 PD78F9136BMC(A)-5A4 PD789121AMC(A1)-xxx-5A4 PD789122AMC(A1)-xxx-5A4 PD789124AMC(A1)-xxx-5A4 PD789131AMC(A1)-xxx-5A4 PD789132AMC(A1)-xxx-5A4 PD789134AMC(A1)-xxx-5A4 PD78F9136BMC(A1)-5A4 PD789121AMC(A2)-xxx-5A4 PD789122AMC(A2)-xxx-5A4 PD789124AMC(A2)-xxx-5A4 PD789131AMC(A2)-xxx-5A4 PD789132AMC(A2)-xxx-5A4 PD789134AMC(A2)-xxx-5A4 Remark Package Quality Grade 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Standard 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special 30-pin plastic SSOP (7.62 mm (300)) Special xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U14643EJ2V0UD 39 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.5 Pin Configuration (Top View) * 30-pin plastic SSOP (7.62 mm (300)) PD789121AMC-xxx-5A4 PD789131AMC-xxx-5A4 PD78F9136AMC-5A4 PD789121AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4 PD78F9136BMC(A)-5A4 PD789121AMC(A1)-xxx-5A4 PD789131AMC(A1)-xxx-5A4 PD78F9136BMC(A1)-5A4 PD789121AMC(A2)-xxx-5A4 PD789131AMC(A2)-xxx-5A4 PD789122AMC-xxx-5A4 PD789132AMC-xxx-5A4 PD78F9136BMC-5A4 PD789122AMC(A)-xxx-5A4 PD789132AMC(A)-xxx-5A4 PD789124AMC-xxx-5A4 PD789134AMC-xxx-5A4 PD789122AMC(A1)-xxx-5A4 PD789132AMC(A1)-xxx-5A4 PD789124AMC(A1)-xxx-5A4 PD789134AMC(A1)-xxx-5A4 PD789122AMC(A2)-xxx-5A4 PD789132AMC(A2)-xxx-5A4 PD789124AMC(A2)-xxx-5A4 PD789134AMC(A2)-xxx-5A4 PD789124AMC(A)-xxx-5A4 PD789134AMC(A)-xxx-5A4 P23/INTP0/CPT20/SS20 1 30 P22/SI20/RXD20 P24/INTP1/TO80/TO20 2 29 P21/SO20/TXD20 P25/INTP2/TI80 3 28 P20/SCK20/ASCK20 AVDD 4 27 P11 P60/ANI0 5 26 P10 P61/ANI1 6 25 VDD P62/ANI2 7 24 VSS P63/ANI3 8 23 CL1 AVSS 9 22 CL2 IC0 10 21 IC0 P50 11 20 IC0 (VPP) P51 12 19 RESET P52 13 18 P03 P53 14 17 P02 P00 15 16 P01 Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. Remark The pin connection in parentheses is intended for the PD78F9136A, 78F9136B, 78F9136B(A), and 78F9136B(A1). 40 User's Manual U14643EJ2V0UD CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) ANI0 to ANI3: Analog input RESET: Reset ASCK20: Asynchronous serial input RxD20: Receive data AVDD: Analog power supply SCK20: Serial clock AVSS: Analog ground SI20: Serial input CL1, CL2: RC oscillator SO20: Serial output CPT20: Capture trigger input SS20: Chip select input IC0: Internally connected TI80: Timer input INTP0 to INTP2: External interrupt input TO20, TO80: Timer output P00 to P03: Port 0 TxD20: Transmit data P10, P11: Port 1 VDD: Power supply P20 to P25: Port 2 VPP: Programming power supply P50 to P53: Port 5 VSS: Ground P60 to P63: Port 6 User's Manual U14643EJ2V0UD 41 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.6 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications PD789046 44-pin 42-/44-pin PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation RC oscillation version of the PD789052 PD789860 without EEPROM, POC, and LVI PD789026 PD789088 PD789074 PD789014 PD789062 PD789052 30-pin 30-pin 28-pin 20-pin 20-pin Small-scale package, general-purpose applications and A/D converter PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177Y PD789167Y PD789167 with enhanced A/D converter (10 bits) PD789104A with enhanced timer PD789146 with enhanced A/D converter (10 bits) PD789104A with added EEPROM PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the PD789104A PD789104A with enhanced A/D converter (10 bits) PD789026 with added 8-bit A/D converter and multiplier LCD drive 78K/0S Series 144-pin 88-pin PD789835 PD789830 UART, 8-bit A/D, and dot LCD (Total display output pins: 96) UART and dot LCD (40 x 16) 80-pin PD789488 80-pin 80-pin SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 52-pin PD789478 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 52-pin PD789327 8-bit A/D and on-chip voltage booster type LCD (23 x 4) SIO and resistance division type LCD (24 x 4) PD789800 For PC keyboard and on-chip USB function 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin USB 44-pin Inverter control 44-pin PD789842 On-chip inverter controller and UART On-chip bus controller 44-pin 30-pin PD789852 PD789850A with enhanced functions such as timer and A/D converter PD789850A On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin PD789862 PD789861 PD789860 PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity RC oscillation version of the PD789860 On-chip POC and key return circuit VFD drive 52-pin PD789871 On-chip VFD controller (Total display output pins: 25) Meter control 64-pin Remark PD789881 UART and resistance division type LCD (26 x 4) VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 42 User's Manual U14643EJ2V0UD CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) The major functional differences between the subseries are listed below. Series for general-purpose applications and LCD drive Function ROM Capacity Timer 8-Bit 10-Bit 8-Bit 16-Bit Watch WDT A/D A/D Serial I/O Interface package, general- PD789026 PD789088 purpose applications Remarks MIN. Subseries Name Small-scale PD789046 VDD Value 16 KB 1 ch 1 ch 1 ch - - - 4 KB to 16 KB 16 KB to 1 ch 1 ch (UART: 1 ch) 3 ch 34 - 1.8 V 24 32 KB PD789074 2 KB to 8 KB 1 ch PD789014 2 KB to 4 KB 2 ch PD789062 4 KB - 22 - 14 RC oscillation version PD789052 - Small-scale PD789177 16 KB to package, PD789167 24 KB PD789156 8 KB to 16 KB 1 ch generalpurpose 3 ch 1 ch 1 ch 1 ch - - 8 ch - - 4 ch 4 ch - applications PD789146 and A/D PD789134A 2 KB to 8 KB converter PD789124A - 4 ch 4 ch - PD789114A - 4 ch PD789104A 4 ch - 3 ch - LCD drive PD789835 24 KB to 6 ch - 1 ch 1 ch 31 8 ch 1 ch 60 KB 24 KB 1 ch PD789488 32 KB to 48 KB 3 ch PD789478 24 KB to 48 KB 1 ch EEPROM RC oscillation version - 37 1 ch - 8 ch 2 ch (UART: 1 ch) - 30 2.7 V 45 1.8 V 43 - 6 ch 30 6 ch - PD789436 - 6 ch PD789426 6 ch - PD789456 12 KB to 16 KB PD789446 PD789316 7 ch 2 ch - 8 KB to 16 KB Dot LCD - 40 2 ch (UART: 1 ch) 23 PD789306 PD789467 Note supported 7 ch 1 ch (UART: 1 ch) - PD789407A 1.8 V - 8 ch PD789417A 12 KB to 24 KB On-chip 20 (UART: 1 ch) PD789830 - 1.8 V (UART: 1 ch) RC oscillation version - 4 KB to 24 KB PD789327 - - 1 ch - 1 ch 18 21 Note Flash memory version: 3.0 V User's Manual U14643EJ2V0UD 43 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) Series for ASSP Function ROM Capacity Timer 8-Bit 10-Bit 8-Bit 16-Bit Watch WDT A/D A/D - - Serial I/O Interface PD789800 8 KB 2 ch - - 1 ch 2 ch Remarks MIN. Value Subseries Name USB VDD 31 4.0 V - 30 4.0 V - 31 4.0 V - (USB: 1 ch) Inverter PD789842 8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch - control 1 ch (UART: 1 ch) On-chip bus PD789852 controller 24 KB to 32 KB PD789850A 16 KB 3 ch 1 ch - 1 ch 1 ch - 4 ch 8 ch 3 ch (UART: 2 ch) - 2 ch 18 (UART: 1 ch) Keyless PD789861 4 KB 2 ch - - 1 ch - - - 14 1.8 V entry RC oscillation version, onchip EEPROM PD789860 PD789862 On-chip 16 KB 1 ch 2 ch 1 ch EEPROM 22 (UART: 1 ch) VFD drive PD789871 Meter control PD789881 4 KB to 8 KB 16 KB 3 ch 2 ch - 1 ch 1 ch - 1 ch - - 1 ch - - Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V 44 User's Manual U14643EJ2V0UD 1 ch 1 ch (UART: 1 ch) 33 2.7 V 28 2.7 V Note 2 - - CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.7 Block Diagram TI80/INTP2/P25 TO80/TO20 /INTP1/P24 TO20/TO80 /INTP1/P24 8-bit timer/ event counter 80 16-bit timer 20 Port 0 P00 to P03 Port 1 P10, P11 Port 2 P20 to P25 Port 5 P50 to P53 Port 6 P60 to P63 CPT20/INTP0 /SS20/P23 Watchdog timer ROM (flash memory) 78K/0S CPU core SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 Serial interface 20 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D converter VDD VSS IC0 (VPP) System control RESET CL1 CL2 Interrupt control INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25 Remarks 1. The size of the internal ROM varies depending on the product. 2. Items in parentheses apply to the PD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1). User's Manual U14643EJ2V0UD 45 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.8 Outline of Functions Item Internal memory ROM PD789121A, 789131A, PD789122A, 789132A, PD789124A, 789134A, 789121A(A), 789131A(A), 789122A(A), 789132A(A), 789124A(A), 789134A(A), PD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1) 789121A(A1), 789131A(A1), 789122A(A1), 789132A(A1), 789124A(A1), 789134A(A1), 789121A(A2), 789131A(A2) 789122A(A2), 789132A(A2) 789124A(A2), 789134A(A2) Mask ROM Flash memory 2 KB High-speed RAM 4 KB 8 KB 16 KB 256 bytes System clock RC oscillation Minimum instruction execution time 0.5/2.0 s (@ system clock: 4.0 MHz operation) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operations * Bit manipulations (such as set, reset, and test) Multiplier 8 bits x 8 bits = 16 bits I/O ports Total: 20 * CMOS input: 4 * CMOS I/O: * N-ch open-drain: 12 4 8-bit resolution x 4 channels (PD789124A Subseries) A/D converter 10-bit resolution x 4 channels (PD789134A Subseries) Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel Timer Timer outputs Vectored interrupts 16-bit timer: 1 channel 8-bit timer/event counter: Watchdog timer: 1 channel 1 channel One output Maskable Internal: 6, External: 3 Non-maskable Internal: 1 Supply voltage VDD = 1.8 to 5.5 V (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A)) VDD = 4.5 to 5.5 V (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2), 78F9136B(A1)) Operating ambient temperature TA = -40 to +85C (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A)) TA = -40 to +105C (PD78F9136B(A1)) TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)) TA = -40 to +125C (PD78912xA(A2), 78913xA(A2)) Package 46 30-pin plastic SSOP (7.62 mm (300)) User's Manual U14643EJ2V0UD CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) An outline of the timers is shown below. Operating Mode Function 16-Bit Timer 20 8-Bit Timer/Event Counter 80 Interval timer - 1 channel External event timer - 1 channel - Timer output 1 output 1 output - PWM output - 1 output - Square-wave output - 1 output - 1 input - - 1 1 1 Capture Interrupt sources Watchdog Timer 1 channel Note Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the two functions can be used at a time. User's Manual U14643EJ2V0UD 47 CHAPTER 2 GENERAL (PD789124A, 789134A SUBSERIES) 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products The standard quality grade products and the (A), (A1), and (A2) products refer to the following products. [Standard quality grade products]... PD789121A, 789122A, 789124A, 789131A, 789132A, 789134A, 78F9136A, 78F9136B [(A) products] .... PD789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A) , 78F9136B(A) [(A1) products] .... PD789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1) [(A2) products] .... PD789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2) The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in Table 2-1. Table 2-1. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products Products Item Standard Quality Grade (A) Products (A1) Products Quality grade Standard Supply voltage VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V Operating Special TA = -40 to +85C * PD78F9136B(A1) TA = -40 to +105C ambient temperature * Other than PD78F9136B(A1) TA = -40 to +110C Electrical Refer to the relevant electrical specifications chapter. specifications 48 (A2) Products Products User's Manual U14643EJ2V0UD TA = -40 to +125C CHAPTER 3 PIN FUNCTIONS 3.1 Pin Function List (1) Port pins Pin Name P00 to P03 I/O I/O Function Port 0 After Reset Alternate Function Input - Input - 4-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). P10, P11 I/O Port 1 2-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). P20 I/O Port 2 Input 6-bit I/O port P21 SCK20/ASCK20 SO20/TxD20 Input/output can be specified in 1-bit units. P22 SI20/RxD20 Use of an on-chip pull-up resistor can be specified by pull-up resistor option register B2 (PUB2). P23 INTP0/CPT20/SS20 P24 INTP1/TO80/TO20 P25 INTP2/TI80 P50 to P53 I/O Port 5 Input - 4-bit N-channel open-drain I/O port Input/output can be specified in 1-bit units. For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option. P60 to P63 Input Port 6 Input ANI0 to ANI3 4-bit input-only port User's Manual U14643EJ2V0UD 49 CHAPTER 3 PIN FUNCTIONS (2) Non-port pins Pin Name INTP0 I/O Input Function External interrupt input for which the valid edge (rising edge, After Reset Input falling edge, or both rising and falling edges) can be specified. INTP1 Alternate Function P23/CPT20/SS20 P24/TO80/TO20 INTP2 P25/TI80 SI20 Input Serial data input to serial interface Input P22/RxD20 SO20 Output Serial data output from serial interface Input P21/TxD20 SCK20 I/O Serial clock I/O for serial interface Input P20/ASCK20 ASCK20 Input Serial clock input to asynchronous serial interface Input P20/SCK20 SS20 Input Chip select input to serial interface Input P23/CPT20/INTP0 RxD20 Input Serial data input to asynchronous serial interface Input P22/SI20 TxD20 Output Serial data output from asynchronous serial interface Input P21/SO20 TI80 Input External count clock input to 8-bit timer/event counter 80 Input P25/INTP2 TO80 Output 8-bit timer/event counter 80 output Input P24/INTP1/TO20 TO20 Output 16-bit timer 20 output Input P24/INTP1/TO80 CPT20 Input Capture edge input Input P23/INTP0/SS20 ANI0 to ANI3 Input A/D converter analog input Input P60 to P63 AVSS - A/D converter ground potential - - AVDD - A/D converter analog power supply - - Connecting ceramic resonator/crystal resonator for system - - - - - - - - X1 X2 CL1 CL2 RESET Input - Input - Input clock oscillation (PD789104A, 789114A Subseries) Connecting resistor (R) and capacitor (C) for system clock oscillation (PD789124A and 789134A Subseries) System reset input Input - VDD - Positive power supply - - VSS - Ground potential - - IC0 - Internally connected. Directly connect to the VSS pin. - - VPP - Sets flash memory programming mode. Applies a high voltage - - when a program is written or verified. 50 User's Manual U14643EJ2V0UD CHAPTER 3 PIN FUNCTIONS 3.2 3.2.1 Description of Pin Functions P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). 3.2.2 P10, P11 (Port 1) These pins constitute a 2-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). 3.2.3 P20 to P25 (Port 2) These pins constitute a 6-bit I/O port. In addition, they function as timer I/O, external interrupt inputs, and serial interface data and clock I/O. Port 2 can be specified in the following operation modes in 1-bit units. (1) Port mode In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be specified as input or output mode in 1-bit units by using port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2). (2) Control mode In this mode, P20 to P25 function as timer I/O, external interrupt input, clock I/O of the serial interface and the data I/O. (a) TI80 This is the external clock input pin for 8-bit timer/event counter 80. (b) TO20, TO80 TO20 is the output pin of 16-bit timer 20. TO80 is the output pin of 8-bit timer/event counter 80. (c) CPT20 This is the input pin of the capture edge. (d) INTP0 to INTP2 These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising and falling edges) can be specified. (e) SI20, SO20 These are the serial data I/O pins of the serial interface. (f) SCK20 These are the serial clock I/O pins of the serial interface. (g) SS20 This is the chip select input pin of the serial interface. User's Manual U14643EJ2V0UD 51 CHAPTER 3 PIN FUNCTIONS (h) RxD20, TxD20 These are the serial data I/O pins of the asynchronous serial interface. (i) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using these pins as serial interface pins, the I/O mode and output latch must be set according to the function to be used. For details of the setting, refer to Table 13-2 Serial Interface 20 Operating Mode Settings. 3.2.4 P50 to P53 (Port 5) These pins constitute a 4-bit N-ch open-drain I/O port and can be specified in input or output mode in 1-bit units by using port mode register 5 (TM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option. 3.2.5 P60 to P63 (Port 6) These pins constitute a 4-bit input-only port. In addition to general-purpose input ports, these pins function as the A/D converter input pins. (1) Port mode In the port mode, these pins function as a 4-bit input-only port. (2) Control mode In the control mode, the pins of port 6 can be used as A/D converter analog inputs (ANI0 to ANI3). 3.2.6 RESET This pin inputs an active-low system reset signal. 3.2.7 X1, X2 (PD789104A, 789114A Subseries) These pins are used to connect a ceramic resonator/crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 3.2.8 CL1, CL2 (PD789124A, 789134A Subseries) These are resistor (R) and capacitor (C) connection pins for system clock oscillation. 3.2.9 AVDD This is the analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even when the A/D converter is not used. 3.2.10 AVSS This is the ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even when the A/D converter is not used. 3.2.11 VDD This is the positive power supply pin. 3.2.12 VSS This is the ground pin. 52 User's Manual U14643EJ2V0UD CHAPTER 3 PIN FUNCTIONS 3.2.13 VPP (PD78F9116A, 78F9116B, 78F9136A, 78F9136B only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Connect this pin in either of the following ways. * Independently connect to a 10 k pull-down resistor. * By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to VSS in the normal operation mode. If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the user program may malfunction. 3.2.14 IC0 (pin No.20) (mask ROM versions only) The IC0 (internally connected) pin (No. 20) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration (Top View)) is used to set the PD789104A/114A/124A/134A Subseries in the test mode before shipment. In the normal operation mode, connect this pin directly to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length between the IC0 pin and VSS pin or external noise superimposed on the IC0 pin, the user program may malfunction. Connect the IC0 pin directly to the VSS pin. VSS IC0 (pin No.20) Keep short 3.2.15 IC0 (pins No.10 and No.21) The IC0 pins (No.10 and No.21) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration (Top View) are internally connected. Connect the IC0 pins directly to VSS. User's Manual U14643EJ2V0UD 53 CHAPTER 3 PIN FUNCTIONS 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type for each pin and the recommended connection of pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name P00 to P03 I/O Circuit Type I/O 5-A I/O Input: Independently connect these pins to VDD or VSS via a resistor. Output: Leave open P10, P11 P20/SCK20/ASCK20 Recommended Connection of Unused Pins 8-A P21/SO20/TxD20 P22/SI20/RxD20 Input: Independently connect these pins to VSS via a resistor. Output: Leave open P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 P50 to P53 (Mask ROM version) 13-W P50 to P53 13-V Input: Directly connect these pins to VSS. Output: Leave these pins open at low-level output after setting the port output latch to 0. (PD78F9116A, 78F9116B, 78F9136A, 78F9136B) P60/ANI0 to P63/ANI3 AVDD 9-C Input - - AVSS Directly connect to VDD. Directly connect to VSS. RESET 2 Input IC0 - - VPP Directly connect to VDD or VSS. - Directly connect to VSS. Independently connect 10 k pull-down resistor to this pin or connect this pin directly to VSS. 54 User's Manual U14643EJ2V0UD CHAPTER 3 PIN FUNCTIONS Figure 3-1. Pin I/O Circuits Type 2 Type 9-C IN Comparator P-ch N-ch IN + - AVSS VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Type 5-A Type 13-V VDD Pull-up enable P-ch IN/OUT Output data Output disable VDD Data P-ch N-ch VSS IN/OUT Output disable Input enable Input enable N-ch Middle-voltage input buffer VSS Input enable Type 8-A Type 13-W VDD VDD Pull-up enable Pull-up resistor (mask option) P-ch IN/OUT VDD Data Output data Output disable P-ch IN/OUT Output disable N-ch N-ch VSS Input enable VSS Middle-voltage input buffer User's Manual U14643EJ2V0UD 55 CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space The PD789104A/114A/124A/134A Subseries can access 64 KB of memory space. Figures 4-1 to 4-4 show the memory maps. Figure 4-1. Memory Map (PD789101A, 789111A, 789121A, 789131A) FFFFH Special-function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 07FFH 0800H 07FFH Program area Program memory space Internal ROM 2,048 x 8 bits 0080H 007FH 0040H 003FH CALLT table area Program area 0016H 0015H Vector table area 0000H 0000H 56 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE Figure 4-2. Memory Map (PD789102A, 789112A, 789122A, 789132A) FFFFH Special-function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Internal ROM 4,096 x 8 bits 0080H 007FH 0040H 003FH CALLT table area Program area 0016H 0015H Vector table area 0000H 0000H User's Manual U14643EJ2V0UD 57 CHAPTER 4 CPU ARCHITECTURE Figure 4-3. Memory Map (PD789104A, 789114A, 789124A, 789134A) FFFFH Special-function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 1FFFH 2000H 1FFFH Program area Program memory space Internal ROM 8,192 x 8 bits 0080H 007FH 0040H 003FH CALLT table area Program area 0016H 0015H Vector table area 0000H 58 0000H User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE Figure 4-4. Memory Map (PD78F9116A, 78F9116B, 78F9136A, 78F9136B) FFFFH Special-function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space 3FFFH 4000H 3FFFH Program area Program memory space Flash memory 16,384 x 8 bits 0080H 007FH 0040H 003FH CALLT table area Program area 0016H 0015H Vector table area 0000H 0000H User's Manual U14643EJ2V0UD 59 CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789104A/114A/124A/134A Subseries provides the following internal ROMs (or flash memory) containing the following capacities. Table 4-1. Internal ROM Capacity Part Number Internal ROM Structure PD789101A, 789111A, 789121A, 789131A Mask ROM Capacity 2,048 x 8 bits PD789102A, 789112A, 789122A, 789132A 4,096 x 8 bits PD789104A, 789114A, 789124A, 789134A 8,192 x 8 bits PD78F9116A, 78F9116B, 78F9136A, 78F9136B Flash memory 16,384 x 8 bits The following areas are allocated to the internal program memory space. (1) Vector table area The 22-byte area of addresses 0000H to 0015H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 4-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000CH INTSR20/INTCSI20 0004H INTWDT 000EH INTST20 0006H INTP0 0010H INTTM80 0008H INTP1 0012H INTTM20 000AH INTP2 0014H INTAD0 (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. 60 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE 4.1.2 Internal data memory (internal high-speed RAM) space The PD789104A/114A/124A/134A Subseries provides a 256-byte internal high-speed RAM. The internal high-speed RAM can also be used as a stack memory. 4.1.3 Special-function register (SFR) area Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (refer to Table 4-3). 4.1.4 Data memory addressing The PD789104A/114A/124A/134A Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH), particular addressing modes can be used to meet the functions of the special-function registers (SFRs) and generalpurpose registers. Figures 4-5 to 4-8 show the data memory addressing modes. Figure 4-5. Data Memory Addressing (PD789101A, 789111A, 789121A, 789131A) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 0800H 07FFH Internal ROM 2,048 x 8 bits 0000H User's Manual U14643EJ2V0UD 61 CHAPTER 4 CPU ARCHITECTURE Figure 4-6. Data Memory Addressing (PD789102A, 789112A, 789122A, 789132A) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 1000H 0FFFH Internal ROM 4,096 x 8 bits 0000H 62 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE Figure 4-7. Data Memory Addressing (PD789104A, 789114A, 789124A, 789134A) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 2000H 1FFFH Internal ROM 8,192 x 8 bits 0000H User's Manual U14643EJ2V0UD 63 CHAPTER 4 CPU ARCHITECTURE Figure 4-8. Data Memory Addressing (PD78F9116A, 78F9116B, 78F9136A, 78F9136B) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Reserved 4000H 3FFFH Flash memory 16,384 x 8 bits 0000H 64 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers The PD789104A/114A/124A/134A Subseries provides the following on-chip processor registers. 4.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 4-9. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 4-10. Program Status Word Configuration 7 PSW IE 0 Z 0 AC 0 0 1 CY (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of CPU. When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupt requests except nonmaskable interrupts are disabled. When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment is controlled by the interrupt mask flag for each interrupt source. This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. User's Manual U14643EJ2V0UD 65 CHAPTER 4 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 4-11. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of a write (save) to the stack memory and is incremented after a read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 4-12 and 4-13. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 4-12. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Register pair lower SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Register pair higher SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 4-13. Data to Be Restored from Stack Memory POP rp instruction SP RET instruction RETI instruction SP Register pair lower SP PC7 to PC0 SP PC7 to PC0 SP + 1 Register pair higher SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP 66 User's Manual U14643EJ2V0UD SP + 3 CHAPTER 4 CPU ARCHITECTURE 4.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 4-14. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Functional names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 User's Manual U14643EJ2V0UD 0 67 CHAPTER 4 CPU ARCHITECTURE 4.2.3 Special-function registers (SFRs) Unlike general-purpose registers, special-function registers have their own functions and are allocated to the 256byte area FF00H to FFFFH. Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit manipulation instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on the special-function register type. Each bit unit for manipulation can be specified as follows. * 1-bit manipulation A symbol reserved by the assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This manipulation can also be specified with an address. * 8-bit manipulation A symbol reserved by the assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This manipulation can also be specified with an address. * 16-bit manipulation A symbol reserved by the assembler is described as the operand of a 16-bit manipulation instruction. When specifying an address, describe an even address. Table 4-3 lists the special-function registers. The meanings of the symbols in this table are as follows. * Symbol Indicates the addresses of the implemented special-function register. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file "sfrbit.h" in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special-function register in question can be read or written. R/W: Read/write R: Read only W: Write only * Bit units for manipulation Indicates the bit units (1, 8, and 16) in which the special-function register in question can be manipulated. * After reset Indicates the status of the special-function register when the RESET signal is input. 68 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special-Function Register List (1/2) Address Special-Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset R/W 1 Bit 8 Bits 16 Bits - FF00H Port 0 P0 FF01H Port 1 P1 - FF02H Port 2 P2 - FF05H Port 5 P5 - FF06H Port 6 P6 FF10H 16-bit multiplication result storage register 0 FF11H FF14H MUL0L R - MUL0 Note 1 00H - Note 2 Undefined MUL0H A/D conversion result register Note 3 - ADCR0 Note 2 FF15H FF16H 16-bit compare register 20 FF17H FF18H CR20 W - FFFFH TM20 R - 0000H - Undefined Note 1 Note 2 CR20H 16-bit timer counter 20 FF19H FF1AH CR20L TM20L Note 1 Note 2 TM20H 16-bit capture register 20 FF1BH TCP20L TCP20 Note 1 Note 2 TCP20H - PM1 - Port mode register 2 PM2 - FF25H Port mode register 5 PM5 - FF32H Pull-up resistor option register B2 PUB2 - FF42H Time clock select register 2 TCL2 - - FF48H 16-bit timer mode control register 20 TMC20 - FF50H 8-bit compare register 80 CR80 W - - FF51H 8-bit timer counter 80 TM80 R - - Undefined FF53H 8-bit timer mode control register 80 TMC80 R/W - 00H FF20H Port mode register 0 PM0 FF21H Port mode register 1 FF22H R/W FFH 00H Notes 1. Although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units. Access these registers in 8-bit units by means of direct addressing. 2. These registers can be accessed in 16-bit units only by means of short direct addressing. 3. When this register is used for an 8-bit A/D converter (PD789104A and 789124A Subseries), it can be accessed only in 8-bit units. At this time, the register address is FF15H. When this register is used for a 10-bit A/D converter (PD789114A and 789134A Subseries), it can be accessed only in 16-bit units. When using the PD78F9116A and 78F9116B as the flash memory versions of the PD789101A, 789102A, or 789104A, or when using the PD78F9136A and 78F9136B as the flash memory versions of the PD789121A, 789122A, or 789124A, this register can be accessed in 8-bit units. However, only the object file assembled with the PD789101A, 789102A, or 789104A, or object file assembled with the PD789121A, 789122A, or 789124A can be used. User's Manual U14643EJ2V0UD 69 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special-Function Register List (2/2) Address Special-Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FF70H Asynchronous serial interface mode register 20 ASIM20 R/W - FF71H Asynchronous serial interface status register 20 ASIS20 R - FF72H Serial operating mode register 20 CSIM20 R/W - FF73H Baud rate generator control register 20 BRGC20 - - FF74H Transmit shift register 20 TXS20 W - - FFH Receive buffer register 20 RXB20 R - - Undefined R/W - 00H - - - - SIO20 FF80H A/D converter mode register 0 ADM0 FF84H Analog input channel specification register 0 ADS0 FFD0H Multiplication data register A0 MRA0 FFD1H Multiplication data register B0 MRB0 FFD2H Multiplier control register 0 MULC0 FFE0H Interrupt request flag register 0 IF0 - FFE1H Interrupt request flag register 1 IF1 - FFE4H Interrupt mask flag register 0 MK0 - FFE5H Interrupt mask flag register 1 MK1 - FFECH External interrupt mode register 0 INTM0 - - FFF7H Pull-up resistor option register 0 PU0 - FFF9H Watchdog timer mode register WDTM - W R/W 00H Undefined 00H FFH 00H FFFAH Oscillation stabilization time select register OSTS - - 04H FFFBH Processor clock control register PCC - 02H Note Note PD789104A, 789114A Subseries only 70 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to the 78K/0S Series Instructions User's Manual (U11047E)). 4.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 8 15 7 6 0 S jdisp8 15 0 PC When S = 0, indicates all bits "0". When S = 1, indicates all bits "1". User's Manual U14643EJ2V0UD 71 CHAPTER 4 CPU ARCHITECTURE 4.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. The CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16, BR !addr16 instruction 7 0 CALL or BR Low Addr. High Addr. 15 8 7 PC 72 User's Manual U14643EJ2V0UD 0 CHAPTER 4 CPU ARCHITECTURE 4.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration] 7 Instruction code 6 1 5 1 1 ta4-0 1 15 Effective address 0 7 0 0 0 0 0 0 0 Memory (Table) 8 7 6 0 0 1 5 1 0 0 0 Low Addr. High Addr. Effective address + 1 15 8 0 7 PC 4.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC User's Manual U14643EJ2V0UD 73 CHAPTER 4 CPU ARCHITECTURE 4.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 4.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low) addr16 (high) Memory 74 User's Manual U14643EJ2V0UD CHAPTER 4 CPU ARCHITECTURE 4.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration]. [Operand format] Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. User's Manual U14643EJ2V0UD 75 CHAPTER 4 CPU ARCHITECTURE 4.4.3 Special-function register (SFR) addressing [Function] Memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Description sfr Special-function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 8 7 15 Effective address 76 1 1 1 1 1 1 1 1 User's Manual U14643EJ2V0UD 0 CHAPTER 4 CPU ARCHITECTURE 4.4.4 Register addressing [Function] General-purpose registers are accessed as operands. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code User's Manual U14643EJ2V0UD 77 CHAPTER 4 CPU ARCHITECTURE 4.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 8 7 D DE 0 E 7 The contents of addressed memory are transferred 7 0 A 78 User's Manual U14643EJ2V0UD 0 Memory address specified by register pair DE CHAPTER 4 CPU ARCHITECTURE 4.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 4.4.7 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing can be used to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 User's Manual U14643EJ2V0UD 1 0 79 CHAPTER 5 PORT FUNCTIONS 5.1 Functions of Ports The PD789104A/114A/124A/134A Subseries provides the ports shown in Figure 5-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port function. For more information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS. Figure 5-1. Port Types P50 P00 P53 P03 P60 P10 P11 Port 0 Port 5 Port 6 Port 1 P63 P20 Port 2 P25 80 User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Pin Name P00 to P03 I/O I/O Function Port 0 After Reset Alternate Function Input - Input - 4-bit I/O port Input/output can be specified in 1-bit units. When used as input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). P10, P11 I/O Port 1 2-bit I/O port Input/output can be specified in 1-bit units. When used as input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). P20 I/O Port 2 Input 6-bit I/O port P21 ASCK20/SCK20 TxD20/SO20 Input/output can be specified in 1-bit units. P22 RxD20/SI20 Use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2). P23 INTP0/CPT20/SS20 P24 INTP1/TO80/TO20 P25 INTP2/TI80 P50 to P53 I/O Port 5 Input - 4-bit N-ch open-drain I/O port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified for mask ROM versions by a mask option. P60 to 63 Input Port 6 Input ANI0 to ANI3 4-bit input-only port User's Manual U14643EJ2V0UD 81 CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration A port consists of the following hardware. Table 5-2. Configuration of Port Item Configuration Control register Port mode register (PM0 to PM2, PM5) Pull-up resistor option register 0 (PU0) Pull-up option register B2 (PUB2) Port Total: 20 (input: 4, I/O: 16) Pull-up resistor * Mask ROM versions Total: 16 (software control: 12, mask option specification: 4) * Flash memory versions Total: 12 (software control only) 5.2.1 Port 0 This is a 4-bit I/O port with output latches. Port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (PM0). When pins P00 to P03 are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 0 to input mode. Figure 5-2 shows the block diagram of port 0. Figure 5-2. Block Diagram of P00 to P03 VDD WRPU0 PU00 P-ch Selector Internal bus RD WRPORT Output latch (P00 to P03) P00 to P03 WRPM PM00 to PM03 PU0: Pull-up resistor option register 0 82 PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 This is a 2-bit I/O port with output latches. Port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 1 to input mode. Figure 5-3 shows the block diagram of port 1. Figure 5-3. Block Diagram of P10 and P11 VDD WRPU0 PU01 P-ch Selector Internal bus RD WRPORT Output latch (P10, P11) P10, P11 WRPM PM10, PM11 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 1 read signal WR: Port 1 write signal User's Manual U14643EJ2V0UD 83 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 This is a 6-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using pull-up resistor option register B2 (PUB2). The port is also used as the serial interface data I/O, clock I/O, timer I/O, and external interrupt input. RESET input sets port 2 to input mode. Figures 5-4 to 5-7 show block diagrams of port 2. Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Table 13-2 Serial Interface 20 Operating Mode Settings. Figure 5-4. Block Diagram of P20 VDD WRPUB2 PUB20 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P20) P20/ASCK20/ SCK20 WRPM PM20 Alternate function PUB2: Pull-up resistor option register B2 84 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P21 VDD WRPUB2 PUB21 P-ch Internal bus Selector RD WRPORT Output latch (P21) P21/TxD20/ SO20 WRPM PM21 Alternate function Serial output enable signal PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14643EJ2V0UD 85 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P22, P23, and P25 VDD WRPUB2 PUB22, PUB23, PUB25 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P22, P23, P25) P22/RxD20/SI20 P23/INTP0/CPT20/ SS20 P25/INTP2/TI80 WRPM PM22, PM23, PM25 PUB2: Pull-up resistor option register B2 86 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P24 VDD WRPUB2 P-ch PUB24 Alternate function Selector Internal bus RD P24/INTP1/ TO80/TO20 WRPORT Output latch (P24) WRPM PM24 Alternate function Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User's Manual U14643EJ2V0UD 87 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 5 This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be specified by a mask option. RESET input sets port 5 to input mode. Figure 5-8 shows a block diagram of port 5. Figure 5-8. Block Diagram of P50 to P53 VDD RD Internal bus Selector Mask option resistor Mask ROM versions only. For flash memory versions, a pull-up resistor is not incorporated. P50 to P53 WRPORT Output latch N-ch (P50 to P53) WRPM PM50 to PM53 PM: Port mode register RD: Port 5 read signal WR: Port 5 write signal Caution When using port 5 of the PD78F9116A and 78F9136A as an input port, be sure to observe the restrictions listed below. <1> When VDD = 1.8 to 5.5 V Use within the range of TA = 25 to 85C <2> When TA = -40 to +85C Use within the range of VDD = 2.7 to 5.5 V <3> When TA = -40 to +85C and VDD = 1.8 to 5.5 V Issue three consecutive read instructions when reading port 5. If the above restrictions are not observed, the input value may be read incorrectly. Note, however, that these restrictions do not apply when port 5 pins are used as output pins, or when the product is other than PD78F9116A or 78F9136A. 88 User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 6 This is a 4-bit input port. The port is also used for analog input to the A/D converter. RESET input sets port 6 to input mode. Figure 5-9 shows a block diagram of port 6. Figure 5-9. Block Diagram of P60 to P63 Internal bus RD + P60/ANI0 to P63/ANI3 A/D converter - VREF User's Manual U14643EJ2V0UD 89 CHAPTER 5 PORT FUNCTIONS 5.3 Port Function Control Registers The following three types of registers control the ports. * Port mode registers (PM0 to PM2, PM5) * Pull-up resistor option register 0 (PU0) * Pull-up resistor option register B2 (PUB2) (1) Port mode registers (PM0 to PM2, PM5) These registers are used to set port I/O in 1-bit units. Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 5-3. Caution As port 2 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function Name P23 P24 P25 Caution PMxx Pxx I/O INTP0 Input 1 x CPT20 Input 1 x INTP1 Input 1 x TO80 Output 0 0 TO20 Output 0 0 INTP2 Input 1 x TI80 Input 1 x When Port 2 is used for serial interface pins, the I/O latch or output latch must be set according to its function. For the setting method, refer to Table 13-2 Serial Interface 20 Operating Mode Settings. Remark x: don't care PMxx: Port mode register Pxx: 90 Port output latch User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS Figure 5-10. Port Mode Register Format Address After reset R/W FF20H FFH R/W PM11 PM10 FF21H FFH R/W PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W FF25H FFH R/W Symbol 7 6 5 4 PM0 1 1 1 1 PM1 1 1 1 1 PM2 1 1 PM5 1 1 1 1 3 2 1 0 PM03 PM02 PM01 PM00 1 1 PM53 PM52 PM51 PM50 Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7) PMmn 0 Output mode (output buffer on) 1 Input mode (output buffer off) (2) Pull-up resistor option register 0 (PU0) Pull-up resistor option register 0 (PU0) sets whether to use on-chip pull-up resistors at each port or not. At a port where use of on-chip pull-up resistors has been specified by PU0, the pull-up resistors can be internally used only for the bits set in input mode. No on-chip pull-up resistors can be used for the bits set in output mode, in spite of the setting of PU0. On-chip pull-up resistors can also not be used when the pins are used as the alternate-function output pins. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PU0 to 00H. Figure 5-11. Format of Pull-up Resistor Option Register 0 Symbol 7 6 5 4 3 2 PU0 0 0 0 0 0 0 PU0m <1> <0> PU01 PU00 Address After reset R/W FFF7H 00H R/W Pm on-chip pull-up resistor selection (m = 0, 1) 0 On-chip pull-up resistor not used 1 On-chip pull-up resistor used User's Manual U14643EJ2V0UD 91 CHAPTER 5 PORT FUNCTIONS (3) Pull-up resistor option register B2 (PUB2) This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. A pin so specified by PUB2 is connected to an on-chip pull-up resistor regardless of the setting of the port mode register. PUB2 is set with a 1-bit or 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 5-12. Format of Pull-up Resistor Option Register B2 Symbol 7 6 PUB2 0 0 PUB2n 92 <5> <4> <3> <2> <1> <0> PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 Address After reset R/W FF32H 00H R/W P2n on-chip pull-up resistor selection (n = 0 to 5) 0 On-chip pull-up resistor not used 1 On-chip pull-up resistor used User's Manual U14643EJ2V0UD CHAPTER 5 PORT FUNCTIONS 5.4 Operation of Port Functions The operation of a port differs depending on whether the port is set in input or output mode, as described below. 5.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is off. Once data is written to the output latch, it is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 5.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. Caution When using port 5 of PD78F9116A and 78F9136A as an input port, be sure to observe the restrictions listed below. <1> When VDD = 1.8 to 5.5 V Use within the range of TA = 25 to 85C <2> When TA = -40 to +85C Use within the range of VDD = 2.7 to 5.5 V <3> When TA = -40 to +85C and VDD = 1.8 to 5.5 V Issue three consecutive read instructions when reading port 5. If the above restrictions are not observed, the input value may be read incorrectly. Note, however, that these restrictions do not apply when port 5 pins are used as output pins, or when the product is other than PD78F9116A or 78F9136A. User's Manual U14643EJ2V0UD 93 CHAPTER 5 PORT FUNCTIONS 5.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed on the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is off. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 94 User's Manual U14643EJ2V0UD CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. Oscillation is stopped by executing the STOP instruction. The system clock oscillator is as follows. * System clock (crystal/ceramic) oscillator <Expanded-specification products> This circuit oscillates a clock at a frequency of 1.0 to 10.0 MHz. <Conventional-specification products> This circuit oscillates a clock at a frequency of 1.0 to 5.0 MHz. 6.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator Crystal/ceramic oscillator Figure 6-1. Block Diagram of Clock Generator Prescaler X2 System clock oscillator Clock to peripheral hardware fX Prescaler fX 22 STOP Selector X1 Standby controller Wait controller CPU clock (fCPU) PCC1 Processor clock control register (PCC) Internal bus User's Manual U14643EJ2V0UD 95 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.3 Register Controlling Clock Generator The clock generator is controlled by the following register. * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 6-2. Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PCC 0 0 0 0 0 0 PCC1 0 FFFBH 02H R/W PCC1 Minimum instruction execution time: 2/fCPU CPU clock (fCPU) selection @ fX = 10.0 MHzNote operation 0 fX 0.2 s 0.4 s 1 fX/22 0.8 s 1.6 s Note Expanded-specification products only 96 @ fX = 5.0 MHz operation Caution Bit 0 and bits 2 to 7 must be set to 0. Remark fX: System clock oscillation frequency User's Manual U14643EJ2V0UD CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.4 6.4.1 System Clock Oscillator System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator connected across the X1 and X2 pins. An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1 pin, and leave the X2 pin open. Figure 6-3 shows the external circuit of the system clock oscillator. Figure 6-3. External Circuit of System Clock Oscillator (a) Crystal or ceramic oscillation VSS X1 (b) External clock External clock X1 X2 X2 Crystal or ceramic resonator Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Figure 6-4 shows examples of incorrect resonator connection. User's Manual U14643EJ2V0UD 97 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) VSS 98 X1 X2 VSS User's Manual U14643EJ2V0UD X1 X2 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B C High current (e) Signal is fetched VSS 6.4.2 X1 X2 Divider The divider divides the output of the system clock oscillator (fX) to generate various clocks. User's Manual U14643EJ2V0UD 99 CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode. * System clock * CPU clock fX fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC), as follows. (a) The slow mode (0.8 s: at 10.0 MHz operation, 1.6 s: at 5.0 MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of minimum instruction execution time (0.2 s and 0.8 s: at 10.0 MHz operation, 0.4 s and 1.6 s: at 5.0 MHz operation) can be selected by setting the PCC register. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral hardware is stopped when the system clock is stopped (except the external clock input operation). 100 User's Manual U14643EJ2V0UD CHAPTER 6 CLOCK GENERATOR (PD789104A, 789114A SUBSERIES) 6.6 6.6.1 Changing Setting of CPU Clock Time required for switching CPU clock The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is used for the duration of several instructions after that (refer to Table 6-2). Table 6-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching PCC1 Set Value After Switching PCC1 PCC1 0 1 0 4 clocks 1 Remark 2 clocks Two clocks are the minimum instruction execution time of the CPU clock before switching. 6.6.2 Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 6-5. Switching CPU Clock VDD RESET CPU clock Slow operation Fastest operation Wait (3.28 ms: at 10.0 MHz operation, 6.55 ms: at 5.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during which oscillation stabilizes (215/fX) is automatically secured. After that, the CPU starts instruction execution at the low speed of the system clock (8.0 s: at 10.0 MHz operation, 1.6 s: at 5.0 MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be selected. User's Manual U14643EJ2V0UD 101 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator is as follows. * System clock (RC) oscillator This circuit oscillates a clock at a frequency of 2.0 to 4.0 MHz. Oscillation can be stopped by executing the STOP instruction. 7.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 7-1. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator RC oscillator Figure 7-1. Block Diagram of Clock Generator Prescaler CL2 System clock oscillator Clock to peripheral hardware fCC Prescaler fCC 22 STOP Selector CL1 Standby controller Wait controller PCC1 Processor clock control register (PCC) Internal bus 102 User's Manual U14643EJ2V0UD CPU clock (fCPU) CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.3 Register Controlling Clock Generator The clock generator is controlled by the following register. * Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 02H. Figure 7-2. Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PCC 0 0 0 0 0 0 PCC1 0 FFFBH 02H R/W PCC1 CPU clock (fCPU) selection Minimum instruction execution time: 2/fCPU @ fCC = 4.0 MHz operation 0 fCC 0.5 s 1 fCC/22 2.0 s Caution Bit 0 and bits 2 to 7 must be set to 0. Remark fCC: System clock oscillation frequency User's Manual U14643EJ2V0UD 103 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.4 7.4.1 System Clock Oscillator System clock oscillator The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the CL1 pin, and leave the CL2 pin open. Figure 7-3 shows the external circuit of the system clock oscillator. Figure 7-3. External Circuit of System Clock Oscillator (a) RC oscillation (b) External clock External clock CL1 C R CL2 VSS Caution CL1 CL2 When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 104 User's Manual U14643EJ2V0UD CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.4.2 Examples of incorrect resonator connection Figure 7-4 shows examples of incorrect resonator connection. Figure 7-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) CL1 CL2 CL1 VSS User's Manual U14643EJ2V0UD CL2 VSS 105 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A and B fluctuates) VDD PORTn (n = 0 to 2, 5, 6) CL1 CL2 VSS CL2 VSS High current CL1 A B High current (e) Signal is fetched CL1 7.4.3 CL2 VSS Divider The divider divides the output of the system clock oscillator (fCC) to generate various clocks. 106 User's Manual U14643EJ2V0UD CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode. * System clock * CPU clock fCC fCPU * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC), as follows. (a) The slow mode (2.0 s: at 4.0 MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the system clock is stopped. (b) Two types of minimum instruction execution time (0.5 s and 2.0 s: at 4.0 MHz operation) can be selected by setting the PCC register. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral hardware is stopped when the system clock is stopped (except the external clock input operation). User's Manual U14643EJ2V0UD 107 CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.6 7.6.1 Changing Setting of CPU Clock Time required for switching CPU clock The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is used for the duration of several instructions after that (refer to Table 7-2). Table 7-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching PCC1 Set Value After Switching PCC1 PCC1 0 1 0 1 Remark 4 clocks 2 clocks Two clocks are the minimum instruction execution time of the CPU clock before switching. 108 User's Manual U14643EJ2V0UD CHAPTER 7 CLOCK GENERATOR (PD789124A, 789134A SUBSERIES) 7.6.2 Switching CPU clock The following figure illustrates how the CPU clock is switched. Figure 7-5. Switching CPU Clock VDD RESET CPU clock Slow operation Fastest operation Wait (32 s: at 4.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during which oscillation stabilizes (27/fCC) is automatically secured. After that, the CPU starts instruction execution at the low speed of the system clock (2.0 s: at 4.0 MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be selected. User's Manual U14643EJ2V0UD 109 CHAPTER 8 16-BIT TIMER 20 The 16-bit timer counter references the free-running counter and provides functions such as timer interrupt and timer output. In addition, the count value can be captured by a capture trigger pin. 8.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. * Timer interrupt * Timer output * Count value capture (1) Timer interrupt An interrupt is generated when the count value and compare value match. (2) Timer output Timer output control is possible when the count value and compare value match. (3) Count value capture The TM20 count value is latched in synchronization with the capture trigger and held. 110 User's Manual U14643EJ2V0UD CHAPTER 8 16-BIT TIMER 20 8.2 16-Bit Timer 20 Configuration 16-bit timer 20 consists of the following hardware. Table 8-1. Configuration of 16-Bit Timer 20 Item Configuration Timer counter 16 bits x 1 (TM20) Registers Compare register: 16 bits x 1 (CR20) Capture register: 16 bits x 1 (TCP20) Timer output 1 (TO20) Control registers 16-bit timer mode control register 20 (TMC20) Port mode register 2 (PM2) Port 2 (P2) Figure 8-1. Block Diagram of 16-Bit Timer 20 Internal bus 16-bit timer mode control register 20 (TMC20) P24 output latch TOF20 CPT201CPT200 TOC20 TCL201TCL200 TOE20 F/F TOD20 16-bit timer mode control register 20 16-bit compare register 20 (CR20) Match PM24 TO20/P24/ INTP1/TO80 fCLK/2 CPT20/P23/ INTP0/SS20 6 Selector INTTM20 fCLK/22 Edge detector 16-bit timer counter 20 (TM20) 16-bit capture register 20 (TCP20) OVF 16-bit counter read buffer Internal bus Remark fCLK: fX or fCC User's Manual U14643EJ2V0UD 111 CHAPTER 8 16-BIT TIMER 20 (1) 16-bit compare register 20 (CR20) This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when they match, generates an interrupt request (INTTM20). CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set. RESET input sets this register to FFFFH. Cautions 1. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8bit memory manipulation instruction can also be used. When manipulating with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 2. When rewriting CR20 during a count operation, set CR20 to the interrupt-disabled state using interrupt mask flag register 0 (MK10) beforehand. Also, set the timer output data to inversion disabled using 16-bit timer mode control register 20 (TMC20). When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 20 (TM20) This is a 16-bit register that counts count pulses. TM20 is read with a 16-bit memory manipulation instruction. This register is free running during count clock input. RESET input clears this register to 0000H and after which it resumes free running. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8bit memory manipulation instruction can also be used. When manipulating with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 3. When manipulating with an 8-bit memory manipulation instruction, readout should be performed in the order of lower byte to higher byte and must be performed in pairs. (3) 16-bit capture register 20 (TCP20) This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20). TCP20 is set with a 16-bit memory manipulation instruction. RESET input makes this register undefined. Caution Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. When manipulating with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. (4) 16-bit counter read buffer This buffer latches the counter value and holds the count value of 16-bit timer counter 20 (TM20). 112 User's Manual U14643EJ2V0UD CHAPTER 8 16-BIT TIMER 20 8.3 Registers Controlling 16-Bit Timer 20 The following three registers control 16-bit timer 20. * 16-bit timer mode control register 20 (TMC20) * Port mode register 2 (PM2) * Port 2 (P2) (1) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc. TMC20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC20 to 00H. User's Manual U14643EJ2V0UD 113 CHAPTER 8 16-BIT TIMER 20 Figure 8-2. Format of 16-Bit Timer Mode Control Register 20 Symbol TMC20 7 <6> 5 4 3 2 1 <0> TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TOD20 Address After reset R/W FF48H 00H R/WNote 1 Timer output data 0 Timer output of 0 1 Timer output of 1 TOF20 Overflow flag set 0 Clear by reset and software 1 Set by overflow of 16-bit timer CPT201 CPT200 Capture edge selection 0 0 Capture operation disabled 0 1 Rising edge of CPT20 1 0 Falling edge of CPT20 1 1 Both edges of CPT20 TOC20 Timer output data inversion control 0 Inversion disabled 1 Inversion enabled TCL201 TCL200 16-bit timer counter 20 count clock selection @ fX = 10.0 MHzNote 2 operation @ fX = 5.0 MHz operation @ fCC = 4.0 MHz operation 0 0 fX/22 or fCC/22 2.5 MHz 1.25 MHz 1.0 MHz 0 1 fX/26 or fCC/26 156.2 kHz 78.1 kHz 62.5 kHz Other than above Setting prohibited TOE20 16-bit timer 20 output control 0 Output disabled (port mode) 1 Output enabled Notes 1. Bit 7 is read-only. 2. Expanded-specification products only. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 114 User's Manual U14643EJ2V0UD CHAPTER 8 16-BIT TIMER 20 (2) Port mode register 2 (PM2) This register sets the input/output of port 2 in 1-bit units. To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 8-3. Format of Port Mode Register 2 Symbol 7 6 PM2 1 1 5 4 3 2 1 0 PM25 PM24 PM23 PM22 PM21 PM20 PM24 Address After reset R/W FF22H FFH R/W P24 pin I/O mode selection 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U14643EJ2V0UD 115 CHAPTER 8 16-BIT TIMER 20 8.4 16-Bit Timer 20 Operation 8.4.1 Operation as timer interrupt An interrupt is generated repeatedly each time the free-running counter value reaches the value set to CR20. After interrupt occurs, the counter is not cleared and continues counting. Therefore, the interval time is equivalent to one count clock cycle set by TCL201 and TCL200. To operate the 16-bit timer 20 as a timer interrupt, the following settings are required. * Set count values to CR20. * Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-4. Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 - TMC20 0/1 0/1 0/1 0/1 0 0/1 0/1 Setting of count clock (see Table 8-2) Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited. When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20 continues and an interrupt request signal (INTTM20) is generated. Table 8-2 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation. Caution When rewriting CR20 during count operation, be sure to follow the procedure below. <1> Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1). <2> Set inversion control of timer output data to disable (TOC20 = 0) When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. Table 8-2. Interval Time of 16-Bit Timer 20 TCL201 TCL200 Count Clock @ fX = 10.0 @ fX = 5.0 @ fCC = 4.0 @ fX = 10.0 @ fX = 5.0 @ fCC = 4.0 MHz Operation MHz Operation MHz Operation MHz Operation MHz Operation MHz Operation 0.4 s 0.8 s 1.0 s 26.2 ms 52.4 ms 65.5 ms 419.4 ms 838.9 ms 1048 ms Note 0 2 0 2 /fX or Interval Time 2 6 1 2 /fX or 2 /fCC 6.4 s 12.8 s 16 s 6 22 2 /fX or 22 2 /fCC Other than above 18 2 /fX or 18 2 /fCC 0 Note 2 /fCC Setting prohibited Note Expanded-specification products only. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 116 User's Manual U14643EJ2V0UD CHAPTER 8 16-BIT TIMER 20 Figure 8-5. Timing of Timer Interrupt Operation t Count clock TM20 count value CR20 0000H 0001H N FFFFH 0000H 0001H N N N N N N INTTM20 Interrupt acknowledged Interrupt acknowledged TO20 TOF20 Overflow flag set Remark N = 0000H to FFFFH User's Manual U14643EJ2V0UD 117 CHAPTER 8 16-BIT TIMER 20 8.4.2 Operation as timer output The timer output is inverted repeatedly each time the free-running counter value reaches the value set to CR20. After the timer output is inverted, the counter is not cleared and continues counting. Therefore, the interval time is equivalent to one count clock cycle set by TCL201 and TCL200. To operate the 16-bit timer 20 as a timer output, the following settings are required. * Set P24 to output mode (PM24 = 0). * Set the P24 output latch to 0. * Set the count value to CR20. * Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-6. Figure 8-6. Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 - 0/1 0/1 0/1 1 0 0/1 1 TO20 output enable Setting of count clock (see Table 8-2) Inversion enable for timer output data Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation prohibited. When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the TO20/P24/INTP1/TO80 pin is inverted. This enables timer output. At that time, TM20 continues counting and an interrupt request signal (INTTM20) is generated. Figure 8-7 shows the timing of timer output (refer to Table 8-2 for the interval time of 16-bit timer 20). Figure 8-7. Timer Output Timing t Count clock TM20 count value CR20 0000H 0001H N FFFFH 0000H 0001H N N N N N N INTTM20 Interrupt acknowledged TO20Note TOF20 Overflow flag set Note The TO20 initial value becomes low level while output is enabled (TOE20 = 1). Remark 118 N = 0000H to FFFFH User's Manual U14643EJ2V0UD Interrupt acknowledged CHAPTER 8 16-BIT TIMER 20 8.4.3 Capture operation The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) in synchronization with a capture trigger. Set as shown in Figure 8-8 to allow 16-bit timer 20 to start the capture operation. Figure 8-8. Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 - TMC20 0/1 0/1 0/1 0/1 0 0/1 0/1 Count clock selection Capture edge selection (see Table 8-3) 16-bit capture register 20 (TCP20) starts the capture operation after the CPT20 capture trigger edge has been detected, and latches and holds the count value of 16-bit timer counter 20. TCP20 fetches the count value within 2 clocks and holds the count value until the next capture edge detection. Table 8-3 and Figure 8-9 show the setting contents of the capture edge and the capture operation timing, respectively. Table 8-3. Settings of Capture Edge CPT201 CPT200 0 0 Capture operation prohibited 0 1 CPT20 pin rising edge 1 0 CPT20 pin falling edge 1 1 CPT20 pin both edges Caution Capture Edge Selection Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable capture trigger detection during TCP20 read. Figure 8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) Count clock TM20 0000H 0001H N Count read buffer 0000H 0001H N TCP20 Undefined M-1 M M N Capture start M Capture start CPT20 Capture edge detection Remark Capture edge detection N, M = 0000H to FFFFH User's Manual U14643EJ2V0UD 119 CHAPTER 8 16-BIT TIMER 20 8.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed via a counter read buffer. The counter read buffer latches the TM20 count value. The buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises and the count value is held. The counter read buffer value in the hold state can be read out as the count value. Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20 higher byte falls. RESET input clears TM20 to 0000H and restarts free running. Figure 8-10 shows the timing of 16-bit timer counter 20 readout. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during oscillation stabilization time. 2. Although TM20 is a dedicated 16-bit transfer instruction register, an 8-bit transfer instruction can also be used. Execute an 8-bit transfer instruction by direct addressing. 3. When using an 8-bit transfer instruction, execute in the order of lower byte to higher byte in pairs. If the only lower byte is read, the pending state of the counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. Figure 8-10. 16-Bit Timer Counter 20 Readout Timing CPU clock Count clock TM20 0000H 0001H Count read buffer 0000H 0001H N N+1 N TM20 read signal Read signal latch prohibited period Remark 120 N = 0000H to FFFFH User's Manual U14643EJ2V0UD CHAPTER 8 16-BIT TIMER 20 8.5 Notes on Using 16-Bit Timer 20 8.5.1 Restrictions on rewriting 16-bit compare register 20 (1) When rewriting the compare register (CR20), be sure to disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0) first. If CR20 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite. (2) The interval time may be double the intended time depending on the timing at which the compare register (CR20) is rewritten. Likewise, the timer output waveform may be shorter or double the intended output. To avoid this, rewrite using one of the following procedures. <Prevention method A> Rewriting by 8-bit access <1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0). <2> Rewrite the higher byte of CR20 (16 bits) first. <3> Next, rewrite the lower byte of CR20 (16 bits). <4> Clear the interrupt request flag (TMIF20). <5> After more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupts and timer output inversion. <Program example A> (When count clock = 64/fX, CPU clock = fX) TM20_VCT: SET1 TMMK20 ;Timer interrupt disable (6 clocks) CLR1 TMC20.3 ;Timer output inversion disable (6 clocks) MOV A,#xxH ;Higher byte rewrite value setting (6 clocks) MOV !0FF17H,A ;CR20 higher byte rewriting (8 clocks) More than 32 clocks MOV A,#yyH in total MOV !0FF16H,A ;CR20 lower byte rewriting (8 clocks) CLR1 TMIF20 ;Interrupt request flag clearing (6 clocks) CLR1 TMMK20 ;Timer interrupt enable (6 clocks) SET1 TMC20.3 ;Timer output inversion enable ;Lower byte rewrite value setting (6 clocks) Note Note This is because the INTTM20 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if TOC20 is set to 1 during this period. User's Manual U14643EJ2V0UD 121 CHAPTER 8 16-BIT TIMER 20 <Prevention method B> Rewriting by 16-bit access <1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0). <2> Rewrite CR20 (16 bits). <3> Wait for more than one cycle of the count clock. <4> Clear the interrupt request flag (TMIF20). <5> Enable timer interrupts and timer output inversion <Program example B> (When count clock = 64/fX, CPU clock = fX) TM20_VCT: SET1 TMMK20 ;Timer interrupt disable CLR1 TMC20.3 ;Timer output inversion disable MOVW AX,#xxyyH ;CR20 rewrite value setting MOVW CR20,AX ;CR20 rewriting NOP NOP ;32 NOP (Wait for 64/fX)Note : NOP NOP CLR1 TMIF20 ;Interrupt request flag clearing CLR1 TMMK20 ;Timer interrupt enable SET1 TMC20.3 ;Timer output inversion enable Note Wait for more than one cycle of the count clock after the instruction rewriting CR20 (MOVW CR20, AX) before clearing the interrupt request flag (TMIF20). 122 User's Manual U14643EJ2V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square-wave output and PWM output of arbitrary frequency. 9.1 Functions of 8-Bit Timer/Event Counter 80 8-bit timer/event counter 80 has the following functions. * Interval timer * External event counter * Square-wave output * PWM output (1) 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance. Table 9-1. Interval Time of 8-Bit Timer/Event Counter 80 Minimum Interval Time At fX = 10.0 MHz Note 2 /fX (25.6 s) 1/fX (100 ns) 2 /fX (0.8 s) 2 /fX (204.8 s) 2 /fX (0.8 s) 1/fX (200 ns) 2 /fX (51.2 s) 1/fX (200 ns) 2 /fX (1.6 s) 2 /fX (409.6 s) 2 /fX (1.6 s) 1/fCC (250 ns) 2 /fCC (64 s) 1/fCC (250 ns) 2 /fCC (2.0 s) 2 /fCC (512 s) 2 /fCC (2.0 s) 3 At fCC = 4.0 MHz Resolution 1/fX (100 ns) 3 At fX = 5.0 MHz Maximum Interval Time 3 8 11 8 11 8 11 3 3 3 Note Expanded-specification products only Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) External event counter The number of pulses of an externally input signal can be measured. User's Manual U14643EJ2V0UD 123 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 (3) Square-wave output A square wave of arbitrary frequency can be output. Table 9-2. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 Minimum Pulse Width At fX = 10.0 MHz Note 2 /fX (25.6 s) 1/fX (100 ns) 2 /fX (0.8 s) 2 /fX (204.8 s) 2 /fX (0.8 s) 1/fX (200 ns) 2 /fX (51.2 s) 1/fX (200 ns) 2 /fX (1.6 s) 2 /fX (409.6 s) 2 /fX (1.6 s) 1/fCC (250 ns) 2 /fCC (64 s) 1/fCC (250 ns) 2 /fCC (2.0 s) 2 /fCC (512 s) 2 /fCC (2.0 s) 3 At fCC = 4.0 MHz Resolution 1/fX (100 ns) 3 At fX = 5.0 MHz Maximum Pulse Width 3 8 11 8 11 8 11 3 3 3 Note Expanded-specification products only Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (4) PWM output 8-bit resolution PWM output can be produced. 9.2 8-Bit Timer/Event Counter 80 Configuration 8-bit timer/event counter 80 consists of the following hardware. Table 9-3. 8-Bit Timer/Event Counter 80 Configuration Item Configuration Timer counter 8 bits x 1 (TM80) Register Compare register: 8 bits x 1 (CR80) Timer output 1 (TO80) Control registers 8-bit timer mode control register 80 (TMC80) Port mode register 2 (PM2) Port 2 (P2) 124 User's Manual U14643EJ2V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80 Internal bus 8-bit compare register 80 (CR80) Match Selector fCLK fCLK/23 INTTM80 TO20 output Note 8-bit timer counter 80 (TM80) Clear R INV Q TI80/P25/ INTP2 Q S OVF TO80/P24/ INTP1/TO20 TCE80 PWME80 TCL801 TCL800 TOE80 P24 output latch PM24 8-bit timer mode control register 80 (TMC80) Internal bus Note Refer to block diagram of 16-bit timer 20 Remark fCLK: fX or fCC (1) 8-bit compare register 80 (CR80) This is an 8-bit register that compares the value set to CR80 with the 8-bit timer counter 80 (TM80) count value, and if they match, generates an interrupt request (INTTM80). CR80 is set with an 8-bit memory manipulation instruction. The values 00H to FFH can be set. RESET input makes CR80 undefined. Cautions 1. When rewriting CR80 in timer counter operation mode (i.e., PWME80 (bit 6 of 8-bit timer mode control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM may not be output normally. (2) 8-bit timer counter 80 (TM80) This is an 8-bit register used to count count pulses. TM80 is read with an 8-bit memory manipulation instruction. RESET input clears TM80 to 00H. User's Manual U14643EJ2V0UD 125 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.3 Registers Controlling 8-Bit Timer/Event Counter 80 The following three registers are used to control 8-bit timer/event counter 80. * 8-bit timer mode control register 80 (TMC80) * Port mode register 2 (PM2) * Port 2 (P2) (1) 8-bit timer mode control register 80 (TMC80) This register enables/stops operation of 8-bit timer counter 80 (TM80), sets the counter clock of TM80, and controls the operation of the output controller of 8-bit timer/event counter 80. TMC80 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC80 to 00H. Figure 9-2. Format of 8-Bit Timer Mode Control Register 80 Symbol TMC80 <7> <6> TCE80 PWME80 5 4 3 0 0 0 2 1 <0> TCL801TCL800 TOE80 TCE80 Address After reset R/W FF53H 00H R/W 8-bit timer counter 80 operation control 0 Operation stop (TM80 cleared to 0) 1 Operation enable Operation mode selection PWME80 0 Timer counter operating mode 1 PWM output operating mode TCL801 TCL800 8-bit timer counter 80 count clock selection @ fX = 10.0 MHzNote operation @ fX = 5.0 MHz operation @ fCC = 4.0 MHz operation 0 0 fX or fCC 10.0 MHz 5.0 MHz 4.0 MHz 0 1 fX/23 or fCC/23 1.25 MHz 625 kHz 500 kHz 1 0 Rising edge of TI80 1 1 Falling edge of TI80 TOE80 8-bit timer/event counter 80 output control 0 Output disable (port mode) 1 Output enable Note Expanded-specification products only Caution Be sure to set TMC80 after stopping timer operation. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 126 User's Manual U14643EJ2V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 (2) Port mode register 2 (PM2) This register sets port 2 to input/output in 1-bit units. When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0. When using it for timer input, set PM24 to 1. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 9-3. Format of Port Mode Register 2 Symbol 7 6 PM2 1 1 5 4 3 2 1 0 PM25 PM24 PM23 PM22 PM21 PM20 Address After reset R/W FF22H FFH R/W P2n pin I/O mode selection (n = 0 to 5) PM2n 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U14643EJ2V0UD 127 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4 9.4.1 Operation of 8-Bit Timer/Event Counter 80 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required. <1> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). <2> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2) <3> Set the count value to CR80 <4> Set TM80 to operation enable (TCE80 = 1) When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, the value of TM80 is cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Tables 9-4 and 9-5 show the interval time, and Figure 9-4 shows the timing of interval timer operation. Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as an interval timer. Table 9-4. Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) TCL801 TCL800 0 0 1/fX (100 ns) [200 ns] 2 /fX (25.6 s) [51.2 s] 1/fX (100 ns) [200 ns] 0 1 2 /fX (0.8 s) [1.6 s] 2 /fX (204.8 s) [409.6 s] 2 /fX (0.8 s) [1.6 s] 1 0 TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle 1 1 Minimum Interval Time 3 Maximum Interval Time 8 11 8 8 Resolution 3 Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products only). 3. The values in square brackets [ ] are for operation at fX = 5.0 MHz. Table 9-5. Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation) TCL801 TCL800 0 0 1/fCC (250 ns) 2 /fCC (64 s) 1/fCC (250 ns) 0 1 2 /fCC (2.0 s) 2 /fCC (512 s) 2 /fCC (2.0 s) 1 0 TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle TI80 input cycle 2 x TI80 input cycle TI80 input edge cycle 1 Remark 128 1 Minimum Interval Time 3 Maximum Interval Time 8 11 8 8 fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ2V0UD Resolution 3 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-4. Interval Timer Operation Timing t Count clock TM80 count value 00H 01H N 00H 01H Clear CR80 N N 00H 01H N Clear N N N Interrupt acknowledged Interrupt acknowledged TCE80 Count start INTTM80 TO80 Interval time Remark Interval time Interval time Interval time = (N + 1) x t : N = 00H to FFH User's Manual U14643EJ2V0UD 129 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using 8bit timer counter 80 (TM80). To operate 8-bit timer/event counter 80 as an external event counter, the following settings are required. <1> Set P25 to input mode (PM25 = 1). <2> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). <3> Specify the rising/falling edges of TI80 (refer to Figure 9-2), and set TO80 to output disabled (i.e., set TOE80 (bit 0 of TMC80) to 0) and PWM output to disabled (i.e., set PWME80 (bit 6 of TMC80) to 0). <4> Set the count value to CR80. <5> Set TM80 to operation enabled (TCE80 = 1). Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80) is incremented. When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Figure 9-5 shows the timing of the external event counter operation (with the rising edge specified). Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as an external event counter. Figure 9-5. External Event Counter Operation Timing (with Rising Edge Specified) TI80 pin input TM80 count value 00H CR80 01H 02H 03H 04H 05H N-1 N TCE80 INTTM80 Remark 130 N = 00H to FFH User's Manual U14643EJ2V0UD N 00H 01H 02H 03H CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.3 Operation as square-wave output The 8-bit timer/event counter can output square waves of a given frequency at intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To operate 8-bit timer/event counter 80 as square-wave output, the following settings are required. <1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0. <2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0). <3> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1), and PWM output to disabled (PWME80 = 0). <4> Set the count value to CR80. <5> Set TM80 to operation enabled (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80/P24/INTP1/TO20 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, the TM80 value is cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated. Square-wave output is cleared (0) when bit 7 (TCE80) of TMC80 is set to 0. Tables 9-6 and 9-7 show the square-wave output range, and Figure 9-6 shows the timing of square-wave output. Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating the 8-bit timer/event counter as square-wave output. Table 9-6. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) TCL801 TCL800 0 0 1/fX (100 ns) [200 ns] 2 /fX (25.6 s) [51.2 s] 1/fX (100 ns) [200 ns] 1 2 /fX (0.8 s) [1.6 s] 2 /fX (204.8 s) [409.6 s] 2 /fX (0.8 s) [1.6 s] 0 Minimum Pulse Width 3 Maximum Pulse Width 8 11 Resolution 3 Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products only). 3. The values in square brackets [ ] are for operation at fX = 5.0 MHz. Table 9-7. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation) TCL801 Remark TCL800 Minimum Interval Time Maximum Interval Time Resolution 0 0 1/fCC (250 ns) 2 /fCC (64 s) 1/fCC (250 ns) 0 1 2 /fCC (2.0 s) 2 /fCC (512 s) 2 /fCC (2.0 s) 3 8 11 3 fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ2V0UD 131 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Figure 9-6. Square-Wave Output Timing Count clock TM80 count value CR80 00H 01H N N 00H 01H N 00H Clear Clear N N 01H TCE80 Count start INTTM80 Interrupt acknowledged Interrupt acknowledged TO80Note Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1). 132 User's Manual U14643EJ2V0UD N N CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.4.4 Operation as PWM output PWM output enables interrupt generation repeatedly at intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To use 8-bit timer/counter 80 for PWM output, the following settings are required. <1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0. <2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0). <3> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1), and PWM output to enabled (PWME80 = 1). <4> Set the count value to CR80. <5> Set TM80 to operation enabled (TCE80 = 1). When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, TM80 continues counting, and an interrupt request signal (INTTM80) is generated. Cautions 1. When CR80 is rewritten during timer operation, a high level may be output for the next cycle (refer to 9.5 (2) Setting of 8-bit compare register 80). 2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. Therefore, always follow the above procedure when operating 8bit compare register 80 as a PWM output. Figure 9-7. PWM Output Timing Count clock TM80 00H 01H *** CR80 M *** FFH 00H 01H 02H *** M M+1 M+2 *** FFH 00H 01H *** M *** *** M TCE80 OVF INTTM80 TO80Note M = 01H to FFH Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1). Caution Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally. User's Manual U14643EJ2V0UD 133 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 9.5 Notes on Using 8-Bit Timer/Event Counter 80 (1) Error on starting timer An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8bit timer counter 80 (TM80) is started asynchronous to the count pulse. Figure 9-8. Start Timing of 8-Bit Timer Counter Count pulse TM80 count value 00H 01H 02H 03H 04H Timer start (2) Setting of 8-bit compare register 80 8-bit compare register 80 (CR80) can be set to 00H. Therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter. Figure 9-9. External Event Counter Operation Timing Tl80 input CR80 00H TM80 count value 00H 00H 00H 00H Interrupt request flag Cautions 1. When rewriting CR80 in timer counter operation mode (i.e., PWME80 (bit 6 of 8-bit timer mode control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. If CR80 is rewritten while the timer is operating in PWM output operation mode (PWME80 = 1), a pulse may not be generated just in the cycle immediately after the rewrite. 3. Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally. 134 User's Manual U14643EJ2V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 (3) Operation after rewriting compare register during PWM output When 8-bit compare register 80 (CR80) is rewritten during PWM output, a high level may be output for a cycle after rewriting CR80 (count pulse x 256) if the 8-bit compare register 80 value is smaller than the 8-bit timer counter 80 (TM80) value. The timing in this case is shown in Figure 9-10. Figure 9-10. Timing After Rewriting Compare Register During PWM Output Count clock TM80 00H 01H ... M CR80 TCE80 ... FFH 00H 01H 02H ... ... M ... FFH 00H 01H ... ... 01H H OVF INTTM80 TO80 Rewriting CR80 M = 02H to FFH (4) Notes on STOP mode setting Before executing the STOP instruction, be sure to set the timer to operation stopped (TCE80 = 0). (5) External event counter start timing When the rising edge of TI80 is selected as the count clock, start the timer (TCE80 = 0 1) at the timing when TI80 changes to low level. Similarly, when the falling edge of TI80 is selected as the count clock, start the timer (TCE80 = 0 1) at the timing when TI80 changes to high level. User's Manual U14643EJ2V0UD 135 CHAPTER 10 WATCHDOG TIMER The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET at arbitrary preset intervals. 10.1 Functions of Watchdog Timer The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect a program loop. When a program loop is detected, a non-maskable interrupt or the RESET signal can be generated. Table 10-1. Program Loop Detection Time of Watchdog Timer Program Loop Detection At fX = 10.0 MHz Time 205 s 2 x 1/fW 2 x 1/fW 2 x 1/fW 13 15 17 At fX = 5.0 MHz At fCC = 4.0 MHz Operation Operation Operation 2 x 1/fW 11 Note 410 s 512 s 819 s 1.64 ms 2.05 ms 3.28 ms 6.55 ms 8.19 ms 13.1 ms 26.2 ms 32.8 ms Note Expanded-specification products only Remark fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) Interval timer The interval timer generates an interrupt at a given interval set in advance. Table 10-2. Interval Time Interval Time At fX = 10.0 MHz Note At fX = 5.0 MHz Operation Operation 2 x 1/fW 205 s 410 s 512 s 2 x 1/fW 819 s 1.64 ms 2.05 ms 2 x 1/fW 3.28 ms 6.55 ms 8.19 ms 2 x 1/fW 13.1 ms 26.2 ms 32.8 ms 11 13 15 17 Note Expanded-specification products only Remark fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 136 At fCC = 4.0 MHz Operation User's Manual U14643EJ2V0UD CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 10-1. Block Diagram of Watchdog Timer Internal bus fW 24 TMMK4 Prescaler fW 26 fW 28 fW 210 7-bit counter Clear Controller Selector TMIF4 INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request 3 TCL22 TCL21 TCL20 RUN WDTM4 WDTM3 Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Internal bus Remark fW: fX or fCC User's Manual U14643EJ2V0UD 137 CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Figure 10-2. Format of Timer Clock Select Register 2 Symbol 7 6 5 4 3 TCL2 0 0 0 0 0 TCL22 TCL21 TCL20 2 1 0 TCL22 TCL21 TCL20 Address After reset R/W FF42H 00H R/W Interval time Watchdog timer count clock selection @ fX = 10.0 MHzNote @ fX = 5.0 @ fCC = 4.0 MHz operation MHz operation operation 0 0 0 fX/24 or fCC/24 625 kHz 0 1 0 fX/26 or fCC/26 156.2 kHz 78.1 kHz 1 0 0 fX/28 or fCC/28 39.0 kHz 0 fX/210 or fCC/210 1 1 Other than above 9.76 kHz 211/fX or 211/fCC 205 s 410 s 512 s 62.5 kHz 213/fX or 213/fCC 819 s 1.64 ms 2.05 ms 15.6 kHz 215/fX or 215/fCC 3.28 ms 6.55 ms 8.19 ms 3.91 kHz 217/fX or 217/fCC 26.2 ms 32.8 ms 312.5 kHz 250 kHz 19.5 kHz 4.88 kHz @ fX = 10.0 MHzNote @ fX = 5.0 @ fCC = 4.0 MHz operation MHz operation operation 13.1 ms Setting prohibited Note Expanded-specification products only Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 138 User's Manual U14643EJ2V0UD CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3. Format of Watchdog Timer Mode Register Symbol <7> 6 5 WDTM RUN 0 0 4 3 WDTM4 WDTM3 2 1 0 Address After reset R/W 0 0 0 FFF9H 00H R/W Selection of operation of watchdog timerNote 1 RUN 0 Stop counting 1 Clear counter and start counting Selection of operation mode of watchdog timerNote 2 WDTM4 WDTM3 0 0 Operation stop 0 1 Interval timer mode (overflow and maskable interrupt occur)Note 3 1 0 Watchdog timer mode 1 (overflow and non-maskable interrupt occur) 1 1 Watchdog timer mode 2 (overflow occurs and reset operation started) Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software. 3. The watchdog timer starts operations as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock select register 2 (TCL2). 2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under the condition that TMIF4 is 1, a non-maskable interrupt occurs at the completion of rewriting. User's Manual U14643EJ2V0UD 139 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Operation as watchdog timer The watchdog timer operates to detect a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer is started by setting bit 7 (RUN) of WDTM to 1. Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated according to the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction. Caution The actual program loop detection time may be up to 0.8% shorter than the set time. Table 10-4. Program Loop Detection Time of Watchdog Timer TCL21 TCL20 0 0 0 2 x 1/fW 205 s 410 s 512 s 0 2 x 1/fW 819 s 1.64 ms 2.05 ms 0 2 x 1/fW 3.28 ms 6.55 ms 8.19 ms 0 2 x 1/fW 13.1 ms 26.2 ms 32.8 ms 0 1 1 1 0 1 Program Loop Detection Time 11 13 15 17 At fX = 10.0 MHz Operation Note TCL22 At fX = 5.0 MHz Operation Note Expanded-specification products only Remark fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) 140 User's Manual U14643EJ2V0UD At fCC = 4.0 MHz Operation CHAPTER 10 WATCHDOG TIMER 10.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 1, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by the count value set in advance. Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input. 2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time. Table 10-5. Interval Time of Interval Timer TCL21 TCL20 0 0 0 2 x 1/fW 205 s 410 s 512 s 0 2 x 1/fW 819 s 1.64 ms 2.05 ms 0 2 x 1/fW 3.28 ms 6.55 ms 8.19 ms 0 2 x 1/fW 13.1 ms 26.2 ms 32.8 ms 0 1 1 1 0 1 Interval Time 11 13 15 17 At fX = 10.0 MHz Operation Note TCL22 At fX = 5.0 MHz Operation At fCC = 4.0 MHz Operation Note Expanded-specification products only Remark fW: fX or fCC fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) User's Manual U14643EJ2V0UD 141 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs into digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software. One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D session is completed. 11.2 8-Bit A/D Converter Configuration The 8-bit A/D converter consists of the following hardware. Table 11-1. Configuration of 8-Bit A/D Converter Item Configuration Analog input 4 channels (ANI0 to ANI3) Registers Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control registers A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Figure 11-1. Block Diagram of 8-Bit A/D Converter AVDD Sample & hold circuit Selector ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 Voltage comparator AVSS AVSS Successive approximation register (SAR) Controller A/D conversion result register 0 (ADCR0) 2 ADS01 ADS00 Analog input channel specification register 0 (ADS0) ADCS0 FR02 FR01 FR00 A/D converter mode register 0 (ADM0) Internal bus 142 Tap selector P-ch User's Manual U14643EJ2V0UD INTAD0 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) Each time A/D conversion ends, the conversion result received from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the result of A/D conversion. ADCR0 can be read with an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against which analog inputs are compared. (6) ANI0 to ANI3 pins Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. (8) AVDD pin The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. User's Manual U14643EJ2V0UD 143 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.3 Registers Controlling 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADM0 to 00H. Figure 11-2. Format of A/D Converter Mode Register 0 Symbol <7> 6 ADM0 0 ADCS0 5 4 3 FR02 FR01 FR00 2 1 0 Address After reset R/W 0 0 0 FF80H 00H R/W ADCS0 A/D conversion control 0 Conversion disabled 1 Conversion enabled A/D conversion time selectionNote 1 FR02 FR01 FR00 @ fX = 10.0 MHzNote 2 operation @ fX = 5.0 MHz operation @ fCC = 4.0 MHz operation 0 0 0 144/fX or 144/fCC 14.4 s 28.8 s 36 s 0 0 1 120/fX or 120/fCC 12 s 0 1 0 96/fX or 96/fCC 24 s 30 s Setting prohibitedNote 3 19.2 s 24 s prohibitedNote 3 14.4 s 18 s 1 0 0 72/fX or 72/fCC Setting 1 0 1 60/fX or 60/fCC Setting prohibitedNote 3 12 sNote 4 15 s 1 1 0 48/fX or 48/fCC Setting prohibitedNote 3 Setting prohibitedNote 3 Setting prohibitedNote 3 Other than above Setting prohibited Notes 1. Set the A/D conversion time to satisfy the following specifications. <Expanded-specification products> When 4.5 V VDD 5.5 V: 12 s min. When 2.7 V VDD < 4.5 V: 14 s min. When 1.8 V VDD < 2.7 V: 28 s min. <Conventional-specification products> When 2.7 V VDD 5.5 V: 14 s min. When 1.8 V VDD < 2.7 V: 28 s min. 2. Expanded-specification products only 3. Setting prohibited because the A/D conversion time does not satisfy the rating shown in Note 1. 4. Can be set only for expanded-specification products when 4.5 V VDD 5.5 V. Otherwise, setting prohibited. 144 User's Manual U14643EJ2V0UD CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to 11.5 (5) Timing when A/D conversion result become undefined). Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) Analog input channel specification register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H. Figure 11-3. Format of Analog Input Channel Specification Register 0 Symbol 7 6 5 4 3 2 ADS0 0 0 0 0 0 0 1 0 ADS01 ADS00 Address After reset R/W FF84H 00H R/W Analog input channel specification ADS01 ADS00 0 0 ANI0 0 1 ANI1 1 0 ANI2 1 1 ANI3 User's Manual U14643EJ2V0UD 145 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.4 8-Bit A/D Converter Operation 11.4.1 Basic operation of 8-bit A/D converter <1> Select the channel for A/D conversion using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 7 of the successive approximation register (SAR) is set. The tap selector sets the series resistor string voltage tap to half AVDD. <5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half AVDD, the MSB is reset. <6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows. * Bit 7 = 1: Three quarters of AVDD * Bit 7 = 0: One quarter of AVDD The voltage tap is compared with the analog input voltage. Bit 6 is set or reset according to the result of comparison. * Analog input voltage voltage tap: Bit 6 = 1 * Analog input voltage < voltage tap: Bit 6 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation may be undefined. 2. When in standby mode, the A/D converter stops operation. 146 User's Manual U14643EJ2V0UD CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter operation SAR Sampling Undefined A/D conversion 80H C0H or 40H Conversion result Conversion result ADCR0 INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the A/D conversion in progress is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted from the beginning. RESET input makes A/D conversion result register 0 (ADCR0) undefined. 11.4.2 Input voltage and conversion result The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) is represented by: ADCR0 = INT ( VIN AVDD x 256 + 0.5) or (ADCR0 - 0.5) x AVDD 256 VIN < (ADCR0 + 0.5) x AVDD 256 INT( ): Function that returns the integer part of the parenthesized value VIN: Analog input voltage AVDD: A/D converter supply voltage ADCR0: Value in A/D conversion result register 0 (ADCR0) Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result. User's Manual U14643EJ2V0UD 147 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR0) 3 2 1 0 1 3 2 5 3 1 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 Input voltage/AVDD 148 User's Manual U14643EJ2V0UD 1 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.4.3 Operation mode of 8-bit A/D converter The 8-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can only be started by software; that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion in progress is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped. Figure 11-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 A/D conversion ANIn Rewriting ADM0 ADCS0 = 1 ANIn ANIn ADCS0 = 0 ANIm Conversion is discontinued; no conversion result is preserved. ADCR0 ANIn ANIn ANIm Stop ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 User's Manual U14643EJ2V0UD 149 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) 11.5 Notes on Using 8-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops operating. Clearing bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0 can reduce the current consumption. Figure 11-7 shows how to reduce the current consumption in the standby mode. Figure 11-7. How to Reduce Current Consumption in Standby Mode AVDD ADCS0 P-ch Series resistor string AVSS (2) Input range for the ANI0 to ANI3 pins Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or grater or AVSS or lower (even if within the absolute maximum ratings) is input to a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end interrupt request signal (INTAD0) is generated. (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and discarding the first conversion result. (5) Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D converter operation has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 11-8 and 11-9. 150 User's Manual U14643EJ2V0UD CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) A/D conversion end ADCR0 A/D conversion end Normal conversion result Undefined value INTAD0 ADCS0 Normal conversion result read out A/D operation stopped Undefined value read out Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) A/D conversion end ADCR0 Normal conversion result INTAD0 ADCS0 A/D operation stopped Normal conversion result read out (6) Noise prevention To maintain a resolution of 8 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-10. Figure 11-10. Analog Input Pin Treatment If noise of AVDD or greater or AVSS or lower is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD ANI0 to ANI3 C = 100 to 1000 pF AVSS VSS User's Manual U14643EJ2V0UD 151 CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (7) ANI0 to ANI3 The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to P63). If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pin being A/D converted. (8) Input impedance of ANI0 to ANI3 pins This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. Therefore at times other than sampling, only the leakage current flows. During sampling, the current for charging the capacitor also flows, so the input impedance fluctuates and has no meaning. However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source be set to 10 k or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure 11-10). (9) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) A/D conversion ANIn ADCR0 Rewriting to ADM0 (to begin conversion for ANIm) ANIn ANIn ANIm ANIn INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 152 ADIF0 has been set, but conversion for ANIm has not been completed. User's Manual U14643EJ2V0UD ANIm ANIm ANIm CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) (10) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3 input circuit. Therefore, if the application is designed to be switched to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD pin, as shown in Figure 11-12. Figure 11-12. AVDD Pin Treatment VDD Main power source AVDD Backup capacitor VSS AVSS (11) Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference voltage error. User's Manual U14643EJ2V0UD 153 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software. One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D session is completed. 12.2 10-Bit A/D Converter Configuration The A/D converter consists of the following hardware. Table 12-1. Configuration of 10-Bit A/D Converter Item Configuration Analog input 4 channels (ANI0 to ANI3) Registers Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control registers A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Figure 12-1. Block Diagram of 10-Bit A/D Converter AVDD Sample & hold circuit Selector ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 Voltage comparator AVSS AVSS Successive approximation register (SAR) Controller A/D conversion result register 0 (ADCR0) 2 ADS01 ADS00 Analog input channel specification register 0 (ADS0) ADCS0 FR02 FR01 FR00 A/D converter mode register 0 (ADM0) Internal bus 154 Tap selector P-ch User's Manual U14643EJ2V0UD INTAD0 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) ADCR0 is a 16-bit register that holds the result of A/D conversion. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0. The results are stored in ADCR0 from the most significant bit. The higher 8 bits of the conversion result are stored in FF15H and the lower 2 bits of the conversion result are stored in FF14H. ADCR0 can be read with a 16-bit memory manipulation instruction. RESET input makes ADCR0 undefined. FF14H FF15H Symbol ADCR0 0 Caution 0 0 Address After reset R/W 0 0 0 FF14H, Undefined FF15H R When using the PD78F9116A and 78F9116B as flash memory versions of the PD789101A, 789102A, and 789104A, or the PD78F9136A and 78F9136B as flash memory versions of the PD789121A, 789122A, and 789124A, an 8-bit access can be made by ADCR0. However, it is performed only with the object file assembled by the PD789101A, 789102A, or 789104A, or by the PD789121A, 789122A, or 789124A, respectively. (3) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against which analog inputs are compared. (6) ANI0 to ANI3 pins Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. User's Manual U14643EJ2V0UD 155 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (8) AVDD pin The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. 12.3 Registers Controlling 10-Bit A/D Converter The following two registers are used to control the 10-bit A/D converter. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears the ADM0 to 00H. Figure 12-2. Format of A/D Converter Mode Register 0 Symbol <7> 6 ADM0 0 ADCS0 5 4 3 FR02 FR01 FR00 2 1 0 Address After reset R/W 0 0 0 FF80H 00H R/W ADCS0 A/D conversion control 0 Conversion disabled 1 Conversion enabled A/D conversion time selectionNote 1 FR02 FR01 FR00 @ fX = 10.0 MHzNote 2 operation @ fX = 5.0 MHz operation @ fCC = 4.0 MHz operation 0 0 0 144/fX or 144/fCC 14.4 s 28.8 s 36 s 0 0 1 120/fX or 120/fCC 12 s 24 s 30 s 0 1 0 96/fX or 96/fCC Setting prohibitedNote 3 19.2 s 24 s Setting prohibitedNote 3 14.4 s 18 s prohibitedNote 3 12 s 15 s 1 0 0 72/fX or 72/fCC Note 4 1 0 1 60/fX or 60/fCC Setting 1 1 0 48/fX or 48/fCC Setting prohibitedNote 3 Setting prohibitedNote 3 Other than above Setting prohibitedNote 3 Setting prohibited Notes 1. Set the A/D conversion time to satisfy the following specifications. <Expanded-specification products> When 4.5 V VDD 5.5 V: 12 s min. When 2.7 V VDD < 4.5 V: 14 s min. When 1.8 V VDD < 2.7 V: 28 s min. <Conventional-specification products> When 2.7 V VDD 5.5 V: 14 s min. When 1.8 V VDD < 2.7 V: 28 s min. 2. Expanded-specification products only 3. Setting prohibited because the A/D conversion time does not satisfy the rating shown in Note 1. 4. Can be set only for expanded-specification products when 4.5 V VDD 5.5 V. Otherwise, setting prohibited. 156 User's Manual U14643EJ2V0UD CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to 12.5 (5) Timing when A/D conversion result becomes undefined). Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) (2) Analog input channel specification register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H. Figure 12-3. Format of Analog Input Channel Specification Register 0 Symbol 7 6 5 4 3 2 ADS0 0 0 0 0 0 0 1 0 ADS01 ADS00 Address After reset R/W FF84H 00H R/W Analog input channel specification ADS01 ADS00 0 0 ANI0 0 1 ANI1 1 0 ANI2 1 1 ANI3 User's Manual U14643EJ2V0UD 157 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.4 10-Bit A/D Converter Operation 12.4.1 Basic operation of 10-bit A/D converter <1> Select the channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 9 of the successive approximation A/D conversion register (SAR) is set. The tap selector sets the series resistor string voltage tap to half AVDD. <5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half AVDD, the MSB is reset. <6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows. * Bit 9 = 1: Three quarters of AVDD * Bit 9 = 0: One quarter of AVDD The voltage tap is compared with the analog input voltage. Bit 8 is set or reset according to the result of comparison. * Analog input voltage voltage tap: Bit 8 = 1 * Analog input voltage < voltage tap: Bit 8 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The A/D conversion value immediately after starting the A/D conversion operation may be undefined. 2. When in standby mode, the A/D converter stops operation. 158 User's Manual U14643EJ2V0UD CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter operation SAR A/D conversion Sampling Conversion result Undefined Conversion result ADCR0 INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the A/D conversion in progress is canceled. In this case, A/D conversion is restarted from the beginning, if ADCS0 is set (1). RESET input makes A/D conversion result register 0 (ADCR0) undefined. 12.4.2 Input voltage and conversion result The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) is represented by: ADCR0 = INT ( VIN AVDD x 1,024 + 0.5) or (ADCR0 - 0.5) x AVDD 1,024 VIN < (ADCR0 + 0.5) x AVDD 1,024 INT( ): Function that returns the integer part of the parenthesized value VIN: Analog input voltage AVDD: A/D converter supply voltage ADCR0: Value in A/D conversion result register 0 (ADCR0) Figure 12-5 shows the relationship between the analog input voltage and the A/D conversion result. User's Manual U14643EJ2V0UD 159 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1,023 1,022 1,021 A/D conversion result (ADCR0) 3 2 1 0 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 2,048 1,024 2,048 1,024 2,048 Input voltage/AVDD 160 User's Manual U14643EJ2V0UD 1 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.4.3 Operation mode of 10-bit A/D converter The 10-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can be started only by software; that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion in progress is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped. Figure 12-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 A/D conversion ANIn Rewriting ADM0 ADCS0 = 1 ANIn ANIn ADCS0 = 0 ANIm ANIm Conversion is discontinued; no conversion result is preserved. ADCR0 ANIn ANIn Stop ANIm INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 User's Manual U14643EJ2V0UD 161 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) 12.5 Notes on Using 10-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops operating. Clearing bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0 can reduce the current consumption. Figure 12-7 shows how to reduce the current consumption in the standby mode. Figure 12-7. How to Reduce Current Consumption in Standby Mode AVDD ADCS0 P-ch Series resistor string AVSS (2) Input range for the ANI0 to ANI3 pins Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is input a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end interrupt request signal (INTAD0) is generated. (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and discarding the first conversion result. (5) Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D converter operation has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 12-8 and 12-9. 162 User's Manual U14643EJ2V0UD CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) A/D conversion end ADCR0 A/D conversion end Normal conversion result Undefined value INTAD0 ADCS0 Normal conversion result read out A/D operation stopped Undefined value read out Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) A/D conversion end ADCR0 Normal conversion result INTAD0 ADCS0 A/D operation stopped Normal conversion result read out (6) Noise prevention To maintain a resolution of 10 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 12-10. Figure 12-10. Analog Input Pin Treatment If noise of AVDD or greater or AVSS or lower is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD ANI0 to ANI3 C = 100 to 1000 pF AVSS VSS User's Manual U14643EJ2V0UD 163 CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (7) ANI0 to ANI3 The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to P63). If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise, the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pin being A/D converted. (8) Input impedance of ANI0 to ANI3 pins This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. Therefore at times other than sampling, only the leakage current flows. During sampling, the current for charging the capacitor also flows, so the input impedance fluctuates and has no meaning. However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source be set to 10 k or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure 12-10). (9) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. Figure 12-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) A/D conversion ANIn ADCR0 Rewriting to ADM0 (to begin conversion for ANIm) ANIn ANIn ANIm ANIn INTAD0 Remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3 164 User's Manual U14643EJ2V0UD ADIF0 has been set, but conversion for ANIm has not been completed. ANIm ANIm ANIm CHAPTER 12 10-BIT A/D CONVERTER (PD789114A, 789134A SUBSERIES) (10) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3 input circuit. Therefore, if the application is designed to be changed to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD pin, as shown in Figure 12-12. Figure 12-12. AVDD Pin Treatment VDD AVDD Main power source Backup capacitor VSS AVSS (11) Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference voltage error. User's Manual U14643EJ2V0UD 165 CHAPTER 13 SERIAL INTERFACE 20 13.1 Functions of Serial Interface 20 Serial interface 20 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. (2) Asynchronous serial interface (UART) mode This mode is used to transmit and receive the one byte of data that follows a start bit. It supports full-duplex communication. Serial interface channel 0 contains a dedicated UART baud rate generator, enabling communication over a wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock pulse at the ASCK20 pin. It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in transmit/receive operations. (3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines (SI20 and SO20). As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time for data transmission than asynchronous serial interface mode. Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, channel 0 can be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having conventional clocked serial interfaces, such as those of the 75XL, 78K, and 17K Series devices. 13.2 Serial Interface 20 Configuration Serial interface 20 consists of the following hardware. Table 13-1. Configuration of Serial Interface 20 Item Registers Configuration Transmit shift register 20 (TXS20) Receive shift register 20 (RXS20) Receive buffer register 20 (RXB20) Control registers Serial operating mode register 20 (CSIM20) Asynchronous serial interface mode register 20 (ASIM20) Asynchronous serial interface status register 20 (ASIS20) Baud rate generator control register 20 (BRGC20) Port mode register 2 (PM2) Port 2 (P2) 166 User's Manual U14643EJ2V0UD Figure 13-1. Block Diagram of Serial Interface 20 Internal bus Serial operation mode register 20 (CSIM20) CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 Receive buffer register 20 (RXB20) Switching of first bit SI20/P22/ RxD20 Receive shift register 20 (RXS20) Transmit shift register 20 (TXS20) Transmit shift clock Selector Reception shift clock Port mode register (PM21) User's Manual U14643EJ2V0UD SO20/P21/ TxD20 Data phase control CSIE20 DAP20 Parity operation Stop bit addition 4 Parity detection INTST20 Transmission data counter SL20, CL20, PS200, PS201 INTSR20/INTCSI20 Stop bit detection Reception data counter Reception enabled Transmission and reception Baud rate clock control generatorNote Reception clock Start bit detection Detection clock fX/2 to fX/28 Reception detected SS20/P23/ CPT20/INTP0 SCK20/P20/ ASCK20 CSIE20 Clock phase control 4 TPS203 TPS202 TPS201 TPS200 CSCK20 CSIE20 CSCK20 Internal clock output Baud rate generator control register 20 (BRGC20) External clock input Internal bus Note Refer to Figure 13-2 for the configuration of the baud rate generator. CHAPTER 13 SERIAL INTERFACE 20 Output latch (P21) Asynchronous serial interface mode register 20 (ASIM20) TXE20 RXE20 PS201 PS200 CL20 SL20 Asynchronous serial interface status register 20 (ASIS20) PE20 FE20 OVE20 167 168 Figure 13-2. Baud Rate Generator Block Diagram Reception detection clock 1/2 Selector Selector Reception shift clock 1/2 Transmission clock counter Reception clock counter User's Manual U14643EJ2V0UD TXE20 SCK20/ASCK20/P20 RXE20 CSIE20 Reception detection 4 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus CHAPTER 13 SERIAL INTERFACE 20 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 Selector Transmission shift clock CHAPTER 13 SERIAL INTERFACE 20 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20 triggers transmission. TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read. RESET input sets TXS20 to FFH. Caution Do not write to TXS20 during transmission. TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any attempt to read from TXS20 results in a value being read from RXB20. (2) Receive shift register 20 (RXS20) RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one entire byte has been received, RXS20 transfers the receive data to receive buffer register 20 (RXB20). RXS20 cannot be manipulated directly by a program. (3) Receive buffer register 20 (RXB20) RXB20 holds receive data. New receive data is transferred from receive shift register 0 (RXS20) per 1 byte of data received. When the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the MSB is always fixed to 0. RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written to. RESET input makes RXB20 undefined. Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any attempt to write to RXB20 results in a value being written to TXS20. (4) Transmission controller The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data in transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20 (ASIM20). (5) Reception controller The reception controller controls reception according to the setting of asynchronous serial interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error. User's Manual U14643EJ2V0UD 169 CHAPTER 13 SERIAL INTERFACE 20 13.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following six registers. * Serial operating mode register 20 (CSIM20) * Asynchronous serial interface mode register 20 (ASIM20) * Asynchronous serial interface status register 20 (ASIS20) * Baud rate generator control register 20 (BRGC20) * Port mode register 2 (PM2) * Port 2 (P2) (1) Serial operating mode register 20 (CSIM20) CSIM20 is used to make the settings related to 3-wire serial I/O mode. CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. 170 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 Figure 13-3. Format of Serial Operating Mode Register 20 Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 Operation disabled 1 Operation enabled SSE20 After reset R/W FF72H 00H R/W Port function Not used Used Communication status Communication enabled 0 Communication enabled 1 Communication disabled 3-wire serial I/O mode data phase selection 0 Output at falling edge of SCK20 1 Output at rising edge of SCK20 DIR20 First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock pulse input to SCK20 pin 1 Output of dedicated baud rate generator CKP20 Address Function of SS20/P23 pin SS20-pin selection DAP20 CSCK20 0 3-wire serial I/O mode operation control 0 1 1 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 2 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is at high level in the idle state 1 Clock is active high, and SCK20 is at low level in the idle state Cautions 1. Bits 4 and 5 must be fixed to 0. 2. CSIM20 must be cleared to 00H if UART mode is selected. User's Manual U14643EJ2V0UD 171 CHAPTER 13 SERIAL INTERFACE 20 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure 13-4. Format of Asynchronous Serial Interface Mode Register 20 Symbol <7> ASIM20 <6> 5 4 3 TXE20 RXE20 PS201 PS200 CL20 2 1 0 Address After reset R/W SL20 0 0 FF70H 00H R/W TXE20 Transmit operation control 0 Transmit operation stop 1 Transmit operation enable RXE20 Receive operation control 0 Receive operation stop 1 Receive operation enable PS201 PS200 Parity bit specification 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception (no parity error is generated). 1 0 Odd parity 1 1 Even parity CL20 Transmit data character length specification 0 7 bits 1 8 bits SL20 Transmit data stop bit length 0 1 bit 1 2 bits Cautions 1. Bits 0 and 1 must be fixed to 0. 2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H. 3. Switch operating modes after halting the serial transmit/receive operation. 172 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 Table 13-2. Serial Interface 20 Operating Mode Settings (1) Operation stopped mode ASIM20 PM22 CSIM20 TXE20 RXE20 CSIE20 P21 PM21 P21 PM20 P20 First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20 Clock DIR20 CSCK20 Pin Function Pin Function P20/SCK20/ ASCK20 Pin Function 0 0 x 0 x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Other than above - - P22 P21 P20 Setting prohibited (2) 3-wire serial I/O mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 PM22 P21 PM21 P21 PM20 P20 First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20 Clock DIR20 CSCK20 Pin Function Pin Function P20/SCK20/ ASCK20 Pin Function 0 0 1 0 0 x Note 1 x Note 2 0 1 x 1 MSB External SI20 Note 2 clock 1 0 SCK20(CMOS Internal 1 SCK20 input output) SCK20 output clock 1 1 0 x 1 LSB External SCK20 input clock 1 0 Internal 1 SCK20 output clock Other than above Setting prohibited (3) Asynchronous serial interface mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 PM22 P21 PM21 P21 PM20 P20 First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20 Clock DIR20 CSCK20 Pin Function Pin Function P20/SCK20/ ASCK20 Pin Function 1 0 0 0 0 x Note 1 x Note 1 0 x 1 1 x Note 1 x LSB Note 1 External P22 TxD20 clock (CMOS output) ASCK20 input P20 Internal clock 0 1 0 0 0 1 x x Note 1 x Note 1 x 1 External RD20 P21 ASCK20 input clock x Note 1 x Note 1 P20 Internal clock 1 1 0 0 0 1 x 0 1 x 1 x Note 1 x Note 1 External TxD20 clock (CMOS output) Internal ASCK20 input P20 clock Other than above Setting prohibited Notes 1. These pins can be used for port functions. 2. When only transmission is used, these pins can be used as P22 (CMOS I/O). Remark x: don't care. User's Manual U14643EJ2V0UD 173 CHAPTER 13 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode. RESET input clears ASIS20 to 00H. Figure 13-5. Format of Asynchronous Serial Interface Status Register 20 Symbol ASIS20 7 6 5 4 3 0 0 0 0 0 2 1 0 PE20 FE20 OVE20 PE20 Address After reset R/W FF71H 00H R Parity error flag 0 No parity error has occurred. 1 A parity error has occurred (when the transmission parity and reception parity do not match). FE20 Framing error flag 0 No framing error has occurred. 1 A framing error has occurred (when no stop bit is detected).Note 1 OVE20 Overrun error flag 0 No overrun error has occurred. 1 An overrun error has occurred.Note 2 (Before data was read from the reception buffer register, the subsequent reception sequence was completed.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error will occur. 174 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for the serial interface. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 13-6. Format of Baud Rate Generator Control Register 20 Symbol BRGC20 7 6 5 4 TPS203 TPS202 TPS201 TPS200 3 2 1 0 Address After reset R/W 0 0 0 0 FF73H 00H R/W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator Note 1 @ fX = 10.0 MHz operation n @ fX = 5.0 MHz operation 0 0 0 0 fX/2 5.0 MHz 2.5 MHz 1 0 0 0 1 fX/22 2.5 MHz 1.25 MHz 2 0 0 1 0 fX/23 1.25 MHz 625 kHz 3 625 kHz 313 kHz 4 0 0 1 1 fX/24 0 1 0 0 fX/25 313 kHz 156 kHz 5 0 1 0 1 fX/26 156 kHz 78.1 kHz 6 0 1 1 0 fX/27 78.1 kHz 39.1 kHz 7 1 fX/28 39.1 kHz 19.5 kHz 8 0 1 1 0 1 0 Other than above 0 Note 2 External clock pulse input at the ASCK20 pin - Setting prohibited Notes 1. Expanded-specification products only 2. An external clock can only be used in UART mode. Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operations. 2. Be sure not to select n = 1 when fX > 2.5 MHz in UART mode because n = 1 exceeds the rating of the baud rate. 3. Be sure not to select n = 2 when fX > 5.0 MHz in UART mode because n = 2 exceeds the rating of the baud rate. 4. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1 exceeds the rating of the serial clock. 5. When the external input clock is selected, set port mode register 2 (PM2) in input mode. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Value specified in TPS200 to TPS203 (1 n 8) User's Manual U14643EJ2V0UD 175 CHAPTER 13 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the ASCK20 pin. (a) Generation of baud rate UART transmit/receive clock by means of system clock The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the system clock is estimated by using the following expression. [Baud rate] = fX n+1 2 x8 [bps] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in Figure 13-6 specified by the setting in TPS200 to TPS203 (2 n 8) Table 13-3. Example of Relationship Between System Clock and Baud Rate Note Baud Rate (bps) fX = 10.0 MHz n fX = 5.0 MHz BRGC20 Error Setting (%) 1.73 n fX = 4.9152 MHz BRGC20 Error Setting (%) 8 70H 1.73 n BRGC20 Error Setting (%) 8 70H 0 1,200 - - 2,400 8 70H 7 60H 7 60H 4,800 7 60H 6 50H 6 50H 9,600 6 50H 5 40H 5 40H 19,200 5 40H 4 30H 4 30H 38,400 4 30H 3 20H 3 20H 76,800 3 20H 2 10H 2 10H Note Expanded-specification products only. Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate. 2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate. 176 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (b) Generation of baud rate UART transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression. fASCK [Baud rate] = [bps] 16 fASCK: Frequency of clock pulse received at the ASCK20 pin Table 13-4. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) ASCK20 Pin Input Frequency (kHz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) Generation of serial clock from system clock in 3-wire serial I/O mode The serial clock is generated by dividing the system clock. The serial clock frequency is estimated by using the following expression. BRGC20 does not need to be set when an external serial clock is input to the SCK20 pin. Serial clock frequency = fX 2n + 1 [Hz] fX: System clock oscillation frequency n: Value determined by the settings of TPS200 to TPS203 as shown in Figure 13-6 (1 n 8) User's Manual U14643EJ2V0UD 177 CHAPTER 13 SERIAL INTERFACE 20 13.4 Operation of Serial Interface 20 Serial interface 20 provides the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 13.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O port pins. (1) Register setting Operation stop mode is set by serial operating mode register 20 (CSIM20) and asynchronous serial interface mode register 20 (ASIM20). (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. <7> Symbol 6 CSIM20 CSIE20 SSE20 5 4 0 0 3 2 0 Address After reset R/W FF72H 00H R/W DAP20 DIR20 CSCK20 CKP20 CSIE20 Operation control in 3-wire serial I/O mode 0 Operation disabled 1 Operation enabled Caution 1 Be sure to clear bits 4 and 5 to 0. (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 1 0 Address After reset R/W 0 0 FF70H 00H R/W Transmit operation control 0 Transmit operation stopped 1 Transmit operation enabled RXE20 Receive operation control 0 Receive operation stopped 1 Receive operation enabled Caution 178 2 Be sure to clear bits 0 and 1 to 0. User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 13.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communication at the desired transfer rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK pin. The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI standard. It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in transmit/receive operations. (1) Register setting The UART mode is set by serial operating mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2). User's Manual U14643EJ2V0UD 179 CHAPTER 13 SERIAL INTERFACE 20 (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 2 0 After reset R/W FF72H 00H R/W 3-wire serial I/O mode operation control 0 Operation disabled 1 Operation enabled SSE20 Not used 1 Used Port function Communication enabled 0 Communication enabled 1 Communication disabled 3-wire serial I/O mode data phase selection DAP20 0 Output at falling edge of SCK20 1 Output at rising edge of SCK20 DIR20 First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock pulse input to SCK20 pin 1 Output of dedicated baud rate generator 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is high level in the idle state 1 Clock is active high, and SCK20 is low level in the idle state Cautions 1. Bits 4 and 5 must be fixed to 0. 2. When UART mode is selected, clear CSIM20 to 00H. 180 Communication status Function of SS20/P23 pin SS20-pin selection 0 CKP20 Address DAP20 DIR20 CSCK20 CKP20 CSIE20 CSCK20 1 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 1 0 Address After reset R/W 0 0 FF70H 00H R/W Transmit operation control 0 Transmit operation stopped 1 Transmit operation enabled RXE20 Receive operation control 0 Receive operation stopped 1 Receive operation enabled PS201 PS200 Parity bit specification 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception (no parity error is generated). 1 0 Odd parity 1 1 Even parity CL20 Character length specification 0 7 bits 1 8 bits SL20 Transmit data stop bit length specification 0 1 bit 1 2 bits Cautions 1. Be sure to clear bits 0 and 1 to 0. 2. Switch operating modes after halting the serial transmit/receive operation. User's Manual U14643EJ2V0UD 181 CHAPTER 13 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS20 to 00H. Symbol ASIS20 7 6 5 4 3 0 0 0 0 0 2 1 0 PE20 FE20 OVE20 PE20 Address After reset R/W FF71H 00H R Parity error flag 0 No parity error has occurred. 1 A parity error has occurred (when the transmission parity and reception parity do not match). FE20 Framing error flag 0 No framing error has occurred. 1 A framing error has occurred (when no stop bit is detected).Note 1 Overrun error flag OVE20 0 No overrun error has occurred. 1 An overrun error has occurred.Note 2 (Before data was read from the reception buffer register, the subsequent reception sequence was completed.) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit. 2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error will occur. 182 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol 7 6 5 4 BRGC20 TPS203 TPS202 TPS201 TPS200 3 2 1 0 Address After reset R/W 0 0 0 0 FF73H 00H R/W TPS203 TPS202 TPS201 TPS200 Selection of source clock for baud rate generator Note @ fX = 10.0 MHz operation n @ fX = 5.0 MHz operation 0 0 0 0 fX/2 5.0 MHz 2.5 MHz 1 0 0 0 1 fX/22 2.5 MHz 1.25 MHz 2 0 0 1 0 fX/23 1.25 MHz 625 kHz 3 1 fX/24 625 kHz 313 kHz 4 313 kHz 156 kHz 5 0 0 1 0 1 0 0 fX/25 0 1 0 1 fX/26 156 kHz 78.1 kHz 6 0 1 1 0 fX/27 78.1 kHz 39.1 kHz 7 39.1 kHz 19.5 kHz 8 0 1 1 1 fX/28 1 0 0 0 External clock input to ASCK20 pin Other than above - Setting prohibited Note Expanded-specification products only Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during communication operations. 2. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate. 3. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate. 4. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Values specified by the setting in TPS200 to TPS203 (1 n 8) The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the ASCK20 pin. (i) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the system clock is estimated by using the following expression. [Baud rate] = fX n+1 2 x8 [bps] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in the above table specified by the setting in TPS200 to TPS203 (2 n 8) User's Manual U14643EJ2V0UD 183 CHAPTER 13 SERIAL INTERFACE 20 Table 13-5. Example of Relationship Between System Clock and Baud Rate Note Baud Rate (bps) fX = 10.0 MHz n fX = 5.0 MHz BRGC20 Error Setting (%) 1.73 n fX = 4.9152 MHz BRGC20 Error Setting (%) 8 70H 1.73 n BRGC20 Error Setting (%) 8 70H 0 1,200 - - 2,400 8 70H 7 60H 7 60H 4,800 7 60H 6 50H 6 50H 9,600 6 50H 5 40H 5 40H 19,200 5 40H 4 30H 4 30H 38,400 4 30H 3 20H 3 20H 76,800 3 20H 2 10H 2 10H Note Expanded-specification products only. Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate. 2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate. (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK 16 [bps] fASCK: Frequency of clock input to ASCK20 pin Table 13-6. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) 184 Baud Rate (bps) ASCK20 Pin Input Frequency (kHz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit, character bits, parity bit and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 20 (ASIM20). Figure 13-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit * Start bits ..................... 1 bit * Character bits .............. 7 bits/8 bits * Parity bits..................... Even parity/odd parity/0 parity/no parity * Stop bits ...................... 1 bit/2 bits Stop bit When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by baud rate generator control register 20 (BRGC20). If a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (ASIS20). User's Manual U14643EJ2V0UD 185 CHAPTER 13 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a "1" bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The transmission operation is controlled so that the number of bits with a value of "1" in the transmit data including parity bit is even. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 1 The number of bits with a value of "1" is an even number in transmit data: 0 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) Odd parity * At transmission Opposite to even parity, the transmission operation is controlled so that the number of bits with a value of "1" in the transmit data including parity bit is odd. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 0 The number of bits with a value of "1" is an even number in transmit data: 1 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 Parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. Therefore, a parity error does not occur, irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error does not occur. 186 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated. Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP D0 TxD20 (Output) D1 D2 D6 D7 D7 Parity Parity START INTST20 (b) Stop bit length: 2 D0 TxD20 (Output) D1 D2 D6 STOP START INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit operation. If the ASIM20 register is rewritten during transmission, subsequent transmission may not be performed (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by INTST20. User's Manual U14643EJ2V0UD 187 CHAPTER 13 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by BRGC20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20 is generated. If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not changed, and INTSR20 is not generated. Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 188 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in asynchronous serial interface status register 20 (ASIS20). Receive error causes are shown in Table 13-7. It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing (refer to Table 13-7 and Figure 13-10). The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 13-7. Receive Error Causes Receive Errors Cause Parity error Transmission-time parity specification and receive data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 13-10. Receive Error Timing (a) Parity error occurred STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 (b) Framing error or overrun error occurred STOP D0 RxD20 (Input) D1 D2 D6 D7 Parity START INTSR20 Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20 before reading RXB20. 2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. User's Manual U14643EJ2V0UD 189 CHAPTER 13 SERIAL INTERFACE 20 (f) Reading receive data When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the value of receive buffer register 20 (RXB20). To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled (RXE20 = 1). Remark However, if it is necessary to read receive data after reception has stopped (RXE20 = 0), read using either of the following methods. (a) Read after setting RXE20 = 0 after waiting for one cycle or more of the source clock selected by BRGC20. (b) Read after bit 2 (DIR20) of serial operating mode register 20 (CSIM20) is set (1). Program example of (a) (BRGC20 = 00H (source clock = fX/2)) INTRXE: ;<Reception completion interrupt routine> NOP ;2 clocks CLR1 RXE20 ;Reception stopped MOV ;Read receive data A, RXB20 Program example of (b) INTRXE: 190 ;<Reception completion interrupt routine> SET1 CSIM20.2 ;DIR20 flag is set to LSB first CLR1 RXE20 ;Reception stopped MOV ;Read receive data A, RXB20 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (3) UART mode cautions (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission. (b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, receive buffer register 20 (RXB20) and receive completion interrupt 20 (INTSR20) are as follows. RxD20 Pin Parity RXB20 INTSR20 <1> <3> <2> When RXE20 is set to 0 at the time indicated by <1>, RXB20 holds the previous data and does not generate INTSR20. When RXE20 is set to 0 at the time indicated by <2>, RXB20 renews the data and does not generate INTSR20. When RXE20 is set to 0 at the time indicated by <3>, RXB20 renews the data and generates INTSR20. User's Manual U14643EJ2V0UD 191 CHAPTER 13 SERIAL INTERFACE 20 13.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input (SI20). (1) Register setting 3-wire serial I/O mode settings are performed using serial operating mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2). (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol <7> CSIM20 6 CSIE20 SSE20 5 4 0 0 3 Operation disabled 1 Operation enabled SSE20 Used R/W FF72H 00H R/W Output at falling edge of SCK20 1 Output at rising edge of SCK20 Communication enabled 0 Communication enabled 1 Communication disabled First-bit specification 0 MSB 1 LSB 3-wire serial I/O mode clock selection 0 External clock pulse input to SCK20 pin 1 Output of dedicated baud rate generator 3-wire serial I/O mode clock phase selection 0 Clock is active low, and SCK20 is at high level in the idle state 1 Clock is active high, and SCK20 is at low level in the idle state Caution Communication status 3-wire serial I/O mode data phase selection DIR20 192 After reset Port function Not used 0 CKP20 Address Function of SS20/P23 pin SS20-pin selection DAP20 CSCK20 0 3-wire serial I/O mode operation control 0 1 1 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 2 Bits 4 and 5 must be fixed to 0. User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol ASIM20 <7> <6> 5 4 3 2 TXE20 RXE20 PS201 PS200 CL20 SL20 TXE20 1 0 Address After reset R/W 0 0 FF70H 00H R/W Transmit operation control 0 Transmit operation stopped 1 Transmit operation enabled RXE20 Receive operation control 0 Receive operation stopped 1 Receive operation enabled PS201 PS200 Parity bit specification 0 0 No parity 0 1 Always add 0 parity at transmission. Parity check is not performed at reception (no parity error is generated). 1 0 Odd parity 1 1 Even parity CL20 Character length specification 0 7 bits 1 8 bits SL20 Transmit data stop bit length specification 0 1 bit 1 2 bits Cautions 1. Be sure to clear bits 0 and 1 to 0. 2. When the 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H. 3. Switching operation modes must be performed after the serial transmit/receive operation is halted. User's Manual U14643EJ2V0UD 193 CHAPTER 13 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Symbol 7 6 5 4 BRGC20 TPS203 TPS202 TPS201 TPS200 3 2 1 0 Address After reset R/W 0 0 0 0 FF73H 00H R/W Selection of source clock for baud rate generator TPS203 TPS202 TPS201 TPS200 @ fX = 10.0 MHzNote operation 0 0 0 0 0 0 n @ fX = 5.0 MHz operation 0 fX/2 5.0 MHz 2.5 MHz 1 1 fX/22 2.5 MHz 1.25 MHz 2 1.25 MHz 625 kHz 3 0 0 1 0 fX/23 0 0 1 1 fX/24 625 kHz 313 kHz 4 0 1 0 0 fX/25 313 kHz 156 kHz 5 1 fX/26 156 kHz 78.1 kHz 6 78.1 kHz 39.1 kHz 7 39.1 kHz 19.5 kHz 8 0 1 0 0 1 1 0 fX/27 0 1 1 1 fX/28 Other than above Setting prohibited Note Expanded-specification products only Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Be sure not to write to BRGC20 during communication operations. 2. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1 exceeds the rating of the serial clock. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. n: Values specified by TPS200 to TPS203 (1 n 8) If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203 bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula. When the serial clock is input from off-chip, setting BRGC20 is not necessary. Serial clock frequency = fX 2n + 1 [Hz] fX: System clock oscillation frequency (ceramic/crystal oscillation) n: Values in the above table specified by the setting in TPS200 to TPS203 (1 n 8) 194 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and output from the SO20 pin. Also, receive data input to the SI0 pin is latched in the receive buffer register (RXB20/SIO20) on the rise of SCK20. At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and an interrupt request signal (INTCSI20) is generated. Figure 13-11. 3-Wire Serial I/O Mode Timing (1/7) (i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 SO20 SI20 1 Note 2 3 4 5 6 7 8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO0 DI0 INTCSI20 Note The value of the last bit previously output is output. User's Manual U14643EJ2V0UD 195 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 SI20 SO20 Note 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 1 SI20 SO20 Hi-Z Note 1 2 3 4 5 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. 196 6 User's Manual U14643EJ2V0UD Hi-Z CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 (v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write 1 SCK20 2 3 4 5 6 7 8 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO20 Write (master)Note SI20 SO20 DI7 DO7 INTCSI20 Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. User's Manual U14643EJ2V0UD 197 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 SIO20 Write (master)Note 1 SI20 SO20 Hi-Z DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. (vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 198 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write 1 SCK20 2 3 4 5 6 7 8 SIO20 Write (master)Note SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. (ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1) SS20 SIO20 Write SCK20 1 2 3 4 5 6 7 8 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO20 Write (master)Note 1 SI20 SO20 DI7 Hi-Z DO7 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. User's Manual U14643EJ2V0UD 199 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 1 Note 2 DO7 DO6 DI7 SI20 3 4 DO5 DI6 5 DOI4 DI5 6 DO3 DI4 7 DO2 DI3 8 DO1 DI2 DO0 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 1 SI20 SO20 Note 2 3 4 5 6 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DOI4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. 200 7 User's Manual U14643EJ2V0UD CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 1 SI20 Hi-Z SO20 Note 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. (3) Transfer start Serial transfer is started by setting transfer data to the transmit shift register (TXS20/SIO20) when the following two conditions are satisfied. * Serial operating mode register 20 (CSIM20) bit 7 (CSIE20) = 1 * Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer. Caution If CSIE20 is set to "1" after data is written to TXS20/SIO20, transfer does not start. Termination of 8-bit transfer stops the serial transfer automatically and generates an interrupt request signal (INTCSI20). User's Manual U14643EJ2V0UD 201 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function. * Calculation of 8 bits x 8 bits = 16 bits 14.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed. MUL0 is set with a 16-bit memory manipulation instruction. RESET input makes this register undefined. Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can also be manipulated with an 8-bit memory manipulation instruction. When using an 8-bit memory manipulation instruction, however, access the register by means of direct addressing. (2) Multiplication data registers A and B (MRA0 and MRB0) These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0. MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instructions. RESET input makes these registers undefined. Figure 14-1 shows the block diagram of the multiplier. 202 User's Manual U14643EJ2V0UD CHAPTER 14 MULTIPLIER Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication data register A (MRA0) Multiplication data register B (MRB0) Counter value Selector 3-bit counter 3 Clear Counter output Start CPU clock 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) MULST0 Reset Multiplier control register 0 (MULC0) Internal bus User's Manual U14643EJ2V0UD 203 CHAPTER 14 MULTIPLIER 14.3 Multiplier Control Register The multiplier is controlled by the following register. * Multiplier control register 0 (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 14-2. Format of Multiplier Control Register 0 Symbol MULC0 7 6 5 4 3 2 1 0 Address After reset R/W 0 0 0 0 0 0 0 MULST0 FFD2H 00H R/W MULST0 Caution 204 Multiplier operation start control bit Operating status of multiplier 0 Stop operation after resetting counter to 0. Operation stopped 1 Enable operation Operation in progress Be sure to clear bits 1 to 7 to 0. User's Manual U14643EJ2V0UD CHAPTER 14 MULTIPLIER 14.4 Multiplier Operation The multiplier of the PD789104A/114A/124A/134A Subseries can execute the calculation of 8 bits x 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1> Counting is started by setting MULST0. <2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is incremented by one. <3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the data. <4> While MULST0 is low, the counter and slave are cleared. Figure 14-3. Multiplier Operation Timing CPU clock MRA0 AA D3 MRB0 MULST0 Counter 000B 00AA Selector output MUL0 (Master) (Slave) 001B 010B 011B 100B 101B 110B 111B 000B 0154 0000 0000 0AA0 0000 2A80 5500 00AA 00AA 0000 01FE 00AA 01FE 01FE 01FE 01FE User's Manual U14643EJ2V0UD 0C9E 0C9E 01FE 0C9E 371E 0C9E 371E 8C1E 0000 205 CHAPTER 15 INTERRUPT FUNCTIONS 15.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. There is one non-maskable interrupt source, which is from the watchdog timer. (2) Maskable interrupt These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 15-1. A standby release signal is generated. There are nine maskable interrupt sources: three external interrupts and six internal interrupts. 206 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS 15.2 Interrupt Sources and Configuration There are total of 10 non-maskable and maskable interrupt sources (refer to Table 15-1). Table 15-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Name - Non- INTWDT maskable Trigger Watchdog timer overflow (watchdog timer mode 1 Internal/ External Internal Vector Basic Table Address Configuration Note 2 Type 0004H (A) selected) Maskable 0 INTWDT Watchdog timer overflow (interval timer mode (B) selected) 1 INTP0 2 INTP1 0008H 3 INTP2 000AH 4 INTSR20 End of serial interface 20 UART reception INTCSI20 End of serial interface 20 3-wire transfer 5 INTST20 End of serial interface 20 UART transmission 000EH 6 INTTM80 Generation of 8-bit timer/event counter 80 match 0010H Pin input edge detection External Internal 0006H 000CH (C) (B) signal 7 INTTM20 Generation of 16-bit timer 20 match signal 0012H 8 INTAD0 A/D conversion completion signal 0014H Notes 1. Priority is the priority applicable when two or more maskable interrupts are simultaneously generated. 0 is the highest priority and 8 is the lowest priority. 2. Basic configuration types A to C correspond to A to C in Figure 15-1. Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable interrupt (internal) can be selected. User's Manual U14643EJ2V0UD 207 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus External interrupt mode register (INTM0) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 208 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Interrupt Function Control Registers The following four registers are used to control the interrupt functions. * Interrupt request flag registers (IF0, IF1) * Interrupt mask flag registers (MK0, MK1) * External interrupt mode register (INTM0) * Program status word (PSW) Table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 15-2. Flags Corresponding to Interrupt Request Signals Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT TMIF4 TMMK4 INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 INTP2 PIF2 PMK2 INTSR20/INTCSI20 SRIF20 SRMK20 INTST20 STIF20 STMK20 INTTM80 TMIF80 TMMK80 INTTM20 INTAD0 TMIF20 ADIF0 TMMK20 ADMK0 User's Manual U14643EJ2V0UD 209 CHAPTER 15 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 15-2. Format of Interrupt Request Flag Register Symbol <7> IF0 <6> <5> <4> <3> <2> <1> <0> TMIF20 TMIF80 STIF20 SRIF20 PIF2 PIF1 PIF0 TMIF4 Address After reset R/W FFE0H 00H R/W Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W IF1 0 0 0 0 0 0 0 ADIF0 FFE1H 00H R/W xxIFx Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request signal is generated; interrupt request state Cautions 1. TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If watchdog timer mode 1 and 2 are used, set the TMIF4 flag to 0. 2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and the interrupt routine is entered. 210 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 15-3. Format of Interrupt Mask Flag Register Symbol MK0 <7> <6> <5> <4> <3> <2> <1> <0> TMMK20 TMMK80 STMK20 SRMK20 PMK2 PMK1 PMK0 TMMK4 Address After reset R/W FFE4H FFH R/W Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W MK1 1 1 1 1 1 1 1 ADMK0 FFE5H FFH R/W xxMKx Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 and 2, its value becomes undefined. 2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. User's Manual U14643EJ2V0UD 211 CHAPTER 15 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 15-4. Format of External Interrupt Mode Register 0 Symbol INTM0 7 6 5 4 3 2 ES21 ES20 ES11 ES10 ES01 ES00 1 0 Address After reset R/W 0 0 FFECH 00H R/W ES21 ES20 INTP2 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP1 valid edge selection ES11 ES10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP0 valid edge selection ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Cautions 1. Be sure to clear bits 0 and 1 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. 212 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag used to set maskable interrupt enable/disable is mapped to the PSW. This register can be read/written in 8-bit units and can carry out operations using bit manipulation and dedicated instructions (EI, DI). When a vectored interrupt request is acknowledged, the PSW is automatically saved into a stack, and the IE flag is reset to 0. It is restored from the stack by the RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 15-5. Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used when normal instruction is executed IE Interrupt acknowledgment enable/disable 0 Disabled 1 Enabled User's Manual U14643EJ2V0UD 213 CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Servicing Operation 15.4.1 Non-maskable interrupt request acknowledgment operation A non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 15-6 shows the flowchart from non-maskable interrupt request generation to acknowledgment. Figure 15-7 shows the timing of non-maskable interrupt request acknowledgment. Figure 15-8 shows the acknowledgment operation if multiple non-maskable interrupts are generated. Caution During non-maskable interrupt servicing program execution, do not input another non-maskable interrupt request; if it is input, the servicing program will be interrupted and the new interrupt request will be acknowledged. 214 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) No Interval timer Yes No WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Reset processing Yes Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 15-7. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction Instruction Save PSW and PC, and jump to interrupt servicing Interrupt servicing program TMIF4 Figure 15-8. Acknowledging Non-Maskable Interrupt Request Main routine First interrupt servicing NMI request (first) NMI request (second) Second interrupt servicing User's Manual U14643EJ2V0UD 215 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 15-3. Refer to Figures 15-10 and 15-11 for the interrupt request acknowledgment timing. Table 15-3. Time from Generation of Maskable Interrupt Request to Servicing Note Minimum Time 9 clocks Maximum Time 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before the BT or BF instruction. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when the status in which it can be acknowledged is set. Figure 15-9 shows the algorithm of acknowledging interrupt requests. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. 216 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-9. Interrupt Acknowledgment Program Algorithm Start No xxIF = 1 ? Yes (Interrupt request generated) xxMK = 0 ? No Yes Interrupt request pending No IE = 1 ? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgment (1 = Enable, 0 = Disable) User's Manual U14643EJ2V0UD 217 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Interrupt Request Acknowledgment Timing (Example of MOV A,r) 8 clocks Clock CPU Save PSW and PC, jump to interrupt servicing MOV A,r Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 15-10 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the MOV A,r instruction is completed. Figure 15-11. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A,r Save PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 15-11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests are held pending while the interrupt request flag register (IF0, IF1) or the interrupt mask flag register (MK0, MK1) is being accessed. 15.4.3 Multiple interrupt servicing Multiple interrupt servicing, in which an interrupt is acknowledged while another interrupt is being serviced, can be executed by priority. When the priority is controlled by the default priority and two or more interrupts are generated at the same time, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (refer to Table 15-1). 218 User's Manual U14643EJ2V0UD CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-12. Example of Multiple Interrupt Servicing Example 1. Multiple interrupts are acknowledged INTxx servicing Main processing EI IE = 0 EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupt servicing occurs. The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment enabled state is set. Example 2. Multiple interrupt servicing does not occur because interrupts are not enabled INTxx servicing Main processing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt servicing does not occur. The INTyy request is held pending and acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled User's Manual U14643EJ2V0UD 219 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request hold Some instructions may hold the acknowledgment of an instruction request pending until completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions (interrupt request hold instructions). * Manipulation instruction for the interrupt request flag registers (IF0, IF1) * Manipulation instruction for the interrupt mask flag registers (MK0, MK1) 220 User's Manual U14643EJ2V0UD CHAPTER 16 STANDBY FUNCTION 16.1 Standby Function and Configuration 16.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The low voltage of the data memory (VDD = 1.8 V) can be held. Therefore, this mode is useful for holding the contents of the data memory at an extremely low current consumption. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operations. However, some time is required until the system clock oscillator stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all held. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. User's Manual U14643EJ2V0UD 221 CHAPTER 16 STANDBY FUNCTION 16.1.2 Standby function control register (PD789104A, 789114A Subseries) The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS)Note. OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of 17 2 /fX. Note PD789104A and 789114A Subseries only. The PD789124A and 789134A Subseries do not provide an oscillation stabilization time select register. The oscillation stabilization time of the PD789124A and 789134A Subseries is fixed to 27/fCC. Figure 16-1. Format of Oscillation Stabilization Time Select Register Symbol 7 6 5 4 3 OSTS 0 0 0 0 0 2 1 0 OSTS2 OSTS1 OSTS0 Address After reset R/W FFFAH 04H R/W Oscillation stabilization time selection OSTS2 OSTS1 OSTS0 @ fX = 10.0 MHzNote operation @ fX = 5.0 MHz operation 0 0 0 212/fX 0 1 0 215/fX 3.28 ms 6.55 ms 1 0 0 217/fX 13.1 ms 26.2 ms Other than above 409 s 819 s Setting prohibited Note Expanded-specification products only Caution The wait time after the STOP mode is released when using a ceramic/crystal oscillator does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of whether STOP mode was released by RESET input or by interrupt generation. STOP mode release X1 pin voltage waveform a Remark 222 fX: System clock oscillation frequency (ceramic/crystal oscillation) User's Manual U14643EJ2V0UD CHAPTER 16 STANDBY FUNCTION 16.2 Operation of Standby Function 16.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 16-1. HALT Mode Operating Status Item Clock generator HALT Mode Operating Status System clock can be oscillated. Clock supply to CPU stops. CPU Operation stopped Port (output latch) Holds status before setting the HALT mode. 16-bit timer 20 Operable 8-bit timer/event counter 80 Operable Watchdog timer Operable Serial interface 20 Operable A/D converter Operation stopped Multiplier Operation stopped External interrupt Operable Note Note Maskable interrupt that is not masked User's Manual U14643EJ2V0UD 223 CHAPTER 16 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able to be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at the next address is executed. Figure 16-2. Releasing HALT Mode by Interrupt HALT instruction Wait Standby release signal Operating mode HALT mode Wait Operating mode Oscillation Clock Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is performed: 9 to 10 clocks * When vectored interrupt servicing is not performed: 1 to 2 clocks (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. 224 User's Manual U14643EJ2V0UD CHAPTER 16 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as an ordinary reset operation, and program execution is started. Figure 16-3. Releasing HALT Mode by RESET Input HALT instruction WaitNote RESET signal Operating mode Clock HALT mode Reset period Oscillation stabilization wait status Oscillation Oscillation stop Oscillation Operating mode Note In the PD789104A and 789114A Subseries, 15 2 /fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation) In the PD789124A and 789134A Subseries, 27/fCC: 32 s (at fCC = 4.0 MHz operation) Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) Table 16-2. Operation After Release of HALT Mode Releasing Source MKxx IE 0 0 Next address instruction is executed 0 1 Interrupt servicing is executed 1 x HALT mode is held Non-maskable interrupt request - x Interrupt servicing is executed RESET input - - Reset processing Maskable interrupt request Operation x: don't care User's Manual U14643EJ2V0UD 225 CHAPTER 16 STANDBY FUNCTION 16.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time select register (OSTS) elapses, and then an operation mode is set. The operation status in the STOP mode is shown in the following table. Table 16-3. STOP Mode Operating Status Item STOP Mode Operating Status Clock generator System clock oscillation stopped CPU Operation stopped Port (output latch) Holds the status before setting the STOP mode 16-bit timer 20 Operation stopped 8-bit timer/event counter 80 Operable Watchdog timer Operation stopped Serial interface 20 Operable A/D converter Operation stopped Multiplier Operation stopped External interrupt Operable Note 1 Note 2 Note 3 Notes 1. Operation is possible only when TI80 is selected as the count clock. 2. Operation is possible in both 3-wire serial I/O and UART modes while an external clock is being used. 3. Maskable interrupt that is not masked 226 User's Manual U14643EJ2V0UD CHAPTER 16 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. If interrupts are disabled, the instruction at the next address is executed. Figure 16-4. Releasing STOP Mode by Interrupt WaitNote (set time by OSTS) STOP instruction Standby release signal Clock Operating mode STOP mode Oscillation stabilization wait status Oscillation Oscillation stop Oscillation Operating mode Note OSTS is not provided in the PD789124A and 789134A Subseries, and the wait time is fixed to 27/fCC. Remark The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. User's Manual U14643EJ2V0UD 227 CHAPTER 16 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 16-5. Releasing STOP Mode by RESET Input STOP instruction WaitNote RESET signal Operating mode Clock Reset period STOP mode Oscillation stabilization wait status Oscillation stop Oscillation Operating mode Oscillation Note In the PD789104A and 789114A Subseries, 215/fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation) In the PD789124A and 789134A Subseries, 7 2 /fCC: 32 s (at fCC = 4.0 MHz operation) Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) fCC: System clock oscillation frequency (RC oscillation) Table 16-4. Operation After Release of STOP Mode Releasing Source Maskable interrupt request RESET input MKxx IE Operation 0 0 Next address instruction is executed 0 1 Interrupt servicing is executed 1 x STOP mode is held - - Reset processing x: don't care 228 User's Manual U14643EJ2V0UD CHAPTER 17 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by program loop time detection with watchdog timer External and internal resets have no functional differences. In both cases, program execution starts at addresses 0000H and 0001H by reset signal input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (refer to Figures 17-2 to 17-4). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 17-1. Block Diagram of Reset Function RESET Count clock Reset signal Reset controller Watchdog timer Overflow Interrupt function Stop User's Manual U14643EJ2V0UD 229 CHAPTER 17 RESET FUNCTION Figure 17-2. Reset Timing by RESET Input X1, CL1 Reset period (oscillation stops) During normal operation Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 17-3. Reset Timing by Overflow in Watchdog Timer X1, CL1 Reset period (oscillation continues) During normal operation Oscillation stabilization time wait Normal operation (reset processing) Overflow in watchdog timer Internal reset signal Hi-Z Port pin Figure 17-4. Reset Timing by RESET Input in STOP Mode X1, CL1 STOP instruction execution Stop status (oscillation During normal operation stops) Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin 230 User's Manual U14643EJ2V0UD CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status After Reset (1/2) Hardware Note 1 Program counter (PC) Status After Reset The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined Note 2 General-purpose registers Undefined Note 2 Ports (P0 to P2, P5) (output latch) 00H Port mode registers (PM0 to PM2, PM5) FFH Pull-up resistor option register 0 (PU0) 00H Pull-up resistor option register B2 (PUB2) 00H Processor clock control register (PCC) 02H Oscillation stabilization time select register (OSTS) 16-bit timer 20 8-bit timer/event counter 80 Watchdog timer A/D converter Serial interface 20 Note 3 04H Timer counter (TM20) 0000H Compare register (CR20) FFFFH Mode control register (TMC20) 00H Capture register (TPC20) Undefined Timer counter (TM80) 00H Compare register (CR80) Undefined Mode control register (TMC80) 00H Timer clock select register (TCL2) 00H Mode register (WDTM) 00H Mode register (ADM0) 00H Input channel specification register (ADS0) 00H Conversion result register (ADCR0) Undefined Mode register (CSIM20) 00H Asynchronous serial interface mode register (ASIM20) 00H Asynchronous serial interface status register (ASIS20) 00H Baud rate generator control register (BRGC20) 00H Transmit shift register (TXS20) FFH Receive buffer register (RXB20) Undefined Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware remains unchanged after reset. 2. If the reset signal is input in the standby mode, the status before reset is retained even after reset. 3. PD789104A, 789114A Subseries only User's Manual U14643EJ2V0UD 231 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status After Reset (2/2) Hardware Multiplier Interrupts 232 Status After Reset 16-bit multiplication result storage register (MUL0) Undefined Data register A (MRA0) Undefined Data register B (MRB0) Undefined Control register (MULC0) 00H Request flag register (IF0, IF1) 00H Mask flag register (MK0, MK1) FFH External interrupt mode register (INTM0) 00H User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B The PD78F9116A and 78F9116B are versions with flash memory instead of the internal ROM of the mask ROM versions in the PD789104A and 789114A Subseries. The PD78F9136A and 78F9136B are versions with flash memory instead of the internal ROM of the mask ROM versions in the PD789124A and 789134A Subseries. The differences between the flash memory and the mask ROM versions are shown in Table 18-1. Table 18-1. Differences Between Flash Memory and Mask ROM Versions Item Internal Flash Memory ROM PD78F9116A PD78F9116B PD789101A PD789111A PD789102A PD789112A PD789104A PD789114A PD78F9136A PD78F9136B PD789121A PD789131A PD789122A PD789132A PD789124A PD789134A 16 KB memory Mask ROM 2 KB 4 KB 8 KB (flash memory) High-speed RAM 256 bytes Pull-up resistors 12 (software control only) 16 (software control: 12, mask option specification: 4) VPP pin Provided Not provided Electrical specifications Refer to the relevant electrical specifications chapter. Cautions 1. There are differences in noise immunity and noise radiation between the flash memory versions and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. 2. A/D conversion result register 0 (ADCR0) is manipulated by an 8-bit memory manipulation instruction or a 16-bit memory manipulation instruction, when used as an 8-bit A/D converter (PD789104A, 789124A Subseries) or 10-bit A/D converter (PD789114A, 789134A Subseries), respectively. However, if the PD78F9116A and 78F9116B are used as the flash memory versions of the PD789101A, 789102A, and 789104A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction, providing an object file has been assembled in the PD789101A, 789102A, 789104A. If the PD78F9136A and 78F9136B are used as the flash memory versions of the PD789121A, 789122A, and 789124A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction, providing an object file has been assembled in the PD789121A, 789122A, or 789124A. User's Manual U14643EJ2V0UD 233 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B 18.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board programming). A flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities low-quantity, varied model production * Easy data adjustment when starting mass production 18.1.1 Programming environment The following shows the environment required for PD78F9116A, 78F9116B, 78F9136A, and 78F9136B flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (Part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 18-1. Environment for Writing Program to Flash Memory VPP VDD RS-232C VSS USB RESET Dedicated flash programmer Host machine 234 3-wire serial I/O or UART or pseudo 3-wire User's Manual U14643EJ2V0UD PD78F9116A, 78F9116B, 78F9136A, 78F9136B CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B 18.1.2 Communication mode Use the communication mode shown in Table 18-2 or 18-3 to perform communication between the dedicated flash programmer and the PD78F9116A, 78F9116B, 78F9136A, or 78F9136B. Table 18-2. Communication Mode List (PD78F9116A, 78F9136A) Communication Mode Note 1 Pins Used TYPE Setting COMM PORT SIO Clock 3-wire serial SIO ch-0 I/O (SIO3) (3-wire, sync.) 1.25 MHz 100 Hz to UART UART ch-0 CPU Clock Flash Clock Note 3 Optional 1 to 5 MHz 1.0 4800 to 76800 Optional Note 5 Note 3 Optional TxD20/SO20/P21 8 RxD20/SI20/P22 MHz 100 Hz to 1 (pseudo 3wire) 1.0 4.91 or 5 Note 3 bps Port A SCK20/ASCK20/P20 0 SO20/TxD20/P21 SI20/RxD20/P22 Note 3, 4 Pseudo 3-wire Number of VPP Pulses Multiple Rate Note 3 (UART0) Note 2 1 to 5 MHz 1.0 Note 3 MHz P00 12 P01 P02 Table 18-3. Communication Mode List (PD78F9116B, 78F9136B) Communication Mode Note 1 Pins Used TYPE Setting COMM PORT SIO Clock CPU Clock Flash Clock Note 3 Optional 1 to 10 MHz Note 2 Multiple Rate 3-wire serial SIO ch-0 I/O (3-wire, sync.) 1.25 MHz SO20/TxD20/P21 SI20/RxD20/P22 SIO ch-1 P00 (3-wire, sync.) P01 P02 100 Hz to 1.0 Note 3 UART UART ch-0 4800 to 76800 Optional Note 3, 4 bps Note 5 4.91, 5, or 10 Number of VPP Pulses 1.0 Note 3 MHz SCK20/ASCK20/P20 0 TxD20/SO20/P21 1 8 RxD20/SI20/P22 Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III/Flashpro IV). 2. When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD or VSS via a resistor. 3. The possible setting range differs depending on the voltage. For details, refer to the relevant electrical specifications chapter. 4. Because signal wave slew also affects UART communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on the board. UART cannot be used with the clock supplied by Flashpro III. Caution Be sure to select the communication mode according to the number of VPP pulses shown in Table 18-2 or 18-3. User's Manual U14643EJ2V0UD 235 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-2. Communication Mode Selection Format 10 V VPP VDD 1 2 n VSS VPP pulses VDD RESET VSS 236 User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-3. Example of Connection with Dedicated Flash Programmer (1/2) (a) 3-wire serial I/O mode (SIO ch-0) Dedicated flash programmer PD78F9116A, 78F9116B, 78F9136A, 78F9136B VPP1 VPP VDD VDD, AVDD RESET RESET CLKNote 1 X1 (P03Note 2) SCK SCK20 SO SI20 SI SO20 GND VSS, AVSS (b) 3-wire serial I/O mode (SIO ch-1) (PD78F9116B, 78F9136B only) Dedicated flash programmer VPP1 PD78F9116B, 78F9136B VPP VDD VDD, AVDD RESET RESET CLKNote 1 X1 (P03Note 2) SCK P00 (Serial clock) SO P02 (Serial input) SI P01 (Serial output) VSS, AVSS GND Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a resonator has already been connected to the X1 pin, the CLK pin does not need to be connected. 2. PD78F9136A, 78F9136B only Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. Before using the power supply connected to the VDD pin, supply voltage before starting programming. 2. In the PD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the dedicated flash programmer. User's Manual U14643EJ2V0UD 237 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-3. Example of Connection with Dedicated Flash Programmer (2/2) (c) UART mode Dedicated flash programmer VPP1 PD78F9116A, 78F9116B, 78F9136A, 78F9136B VPP VDD, AVDD VDD RESET RESET CLKNote 1 X1 (P03Note 2) SO RxD20 SI TxD20 VSS, AVSS GND (d) Pseudo 3-wire mode (PD78F9116A, 78F9136A only) Dedicated flash programmer VPP1 PD78F9116A, 78F9136A VPP VDD VDD, AVDD RESET RESET CLKNote 1 X1 (P03Note 2) SCK P00 (Serial clock) SO P02 (Serial input) P01 (Serial output) SI VSS, AVSS GND Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a resonator has already been connected to the X1 pin, the CLK pin does not need to be connected. 2. PD78F9136A, 78F9136B only Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. Before using the power supply connected to the VDD pin, supply voltage before starting programming. 2. In the PD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the dedicated flash programmer. 238 User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B If Flashpro III/Flashpro IV is used as the dedicated flash programmer, the following signals are generated for the PD78F9116A, 78F9116B, 78F9136A, and 78F9136B. For details, refer to the manual of Flashpro III/Flashpro IV. Table 18-4. Pin Connection List Signal Name VPP1 I/O Output Pin Function Write voltage - VPP2 VDD I/O Pin Name 3-Wire Serial I/O UART Pseudo 3-Wire x x x VDD/AVDD Note 1 Note 1 Note 1 VSS/AVSS VPP - VDD voltage generation/ - voltage monitoring - GND Ground Note 2 CLK Output Clock output X1 (P03 RESET Output Reset signal RESET SI Input Reception signal SO20/P01/TxD20 SO Output Transmit signal SI20/P02/RxD20 SCK Output Transfer clock SCK20/P00 x x x x - HS - ) - Notes 1. VDD voltage must be supplied before programming is started. 2. PD78F9136A, 78F9136B only Remark : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. x: Pin does not need to be connected. User's Manual U14643EJ2V0UD 239 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B 18.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. <VPP pin> In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform the following. (1) Connect a pull-down resistor (RVPP = 10 k) to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND. A VPP pin connection example is shown below. Figure 18-4. VPP Pin Connection Example PD78F9116A, 78F9116B, 78F9136A, 78F9136B Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP) <Serial interface pins> The following shows the pins used by the serial interface. <PD78F9116A, 78F9136A> Serial Interface Pins Used 3-wire serial I/O SCK20, SO20, SI20 UART TxD20, RxD20 Pseudo 3-wire P00, P01, P02 <PD78F9116B, 78F9136B> Serial Interface 3-wire serial I/O Pins Used SCK20, SO20, SI20 P00, P01, P02 UART TxD20, RxD20 When connecting the dedicated flash programmer to a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such connections. 240 User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 18-5. Signal Conflict (Input Pin of Serial Interface) PD78F9116A, 78F9116B, 78F9136A, 78F9136B Signal conflict Connection pin of dedicated flash programmer Input pin Other device Output pin In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict; therefore, isolate the signal of the other device. (2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. Figure 18-6. Abnormal Operation of Other Device PD78F9116A, 78F9116B, 78F9136A, 78F9136B Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the PD78F9116A, 78F9116B, 78F9136A, or 78F9136B affects another device in the flash memory programming mode, isolate the signals of the other device. PD78F9116A, 78F9116B, 78F9136A, 78F9136B Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. User's Manual U14643EJ2V0UD 241 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 18-7. Signal Conflict (RESET Pin) PD78F9116A, 78F9116B, 78F9136A, 78F9136B Signal Conflict Connection pin of dedicated flash programmer RESET Reset signal generator Output pin The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. <Port pins> When the flash memory programming mode is set, all the pins other than those that communicate with the flash programmer are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD or VSS. <Oscillation pins> When using the on-board clock, connect X1 and X2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator on-board, and leave the X2 pin open. <Power supply> When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND of the flash programmer, respectively. When using the on-board power supply, connect it as required in the normal operation mode. Because the flash programmer monitors the voltage, however, VDD of the flash programmer must be connected. For the other power pins (AVDD and ASS), supply the same power supply as in the normal operation mode. 242 User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B 18.1.4 Connection when using flash memory writing adapter The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 18-8. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch0) (a) PD78F9116A, 78F9116B VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9116A PD78F9116B 1 7 8 9 10 24 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS (b) PD78F9136A, 78F9136B VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9136A PD78F9136B 1 7 8 9 10 11 24 23 22 21 20 12 19 13 18 14 17 16 15 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS User's Manual U14643EJ2V0UD 243 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-9. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch1) (a) PD78F9116B VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9116B 1 7 8 9 10 11 24 23 22 21 20 12 19 13 18 14 17 16 15 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS (b) PD78F9136B VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9136B 1 7 8 9 10 24 23 22 21 11 20 12 19 13 18 14 17 16 15 GND VDD VDD2 (LVDD) Flash programmer interface 244 SI SO SCK CLKOUT RESET VPP RESERVE/HS User's Manual U14643EJ2V0UD CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-10. Example of Flash Memory Writing Adapter Connection When Using UART Mode (a) PD78F9116A, 78F9116B VDD (2.7 to 5.5 V) GND 1 30 2 29 3 28 4 27 5 26 6 25 PD78F9116A PD78F9116B 7 8 9 10 24 23 22 21 11 20 12 19 13 18 14 17 16 15 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS (b) PD78F9136A, 78F9136B VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 7 24 PD78F9136A PD78F9136B 1 8 9 10 23 22 21 11 20 12 19 13 18 14 17 16 15 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS User's Manual U14643EJ2V0UD 245 CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B Figure 18-11. Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode (a) PD78F9116A VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9116A 1 7 8 9 10 24 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) Flash programmer interface SI SO SCK CLKOUT RESET VPP RESERVE/HS (b) PD78F9136A VDD (2.7 to 5.5 V) GND 30 2 29 3 28 4 27 5 26 6 25 PD78F9136A 1 7 8 9 10 24 23 22 21 11 20 12 19 13 18 14 17 15 16 GND VDD VDD2 (LVDD) Flash programmer interface 246 SI SO SCK CLKOUT RESET VPP RESERVE/HS User's Manual U14643EJ2V0UD CHAPTER 19 MASK OPTION (MASK ROM VERSION) Table 19-1. Selection of Mask Option for Pins Pin P50 to P53 Mask Option On-chip pull-up resistor can be specified in 1-bit units. For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is specified in 1-bit units. Caution The flash memory versions do not provide the on-chip pull-up resistor function. User's Manual U14643EJ2V0UD 247 CHAPTER 20 INSTRUCTION SET This chapter lists the instruction set of the PD789104A/114A/124A/134A Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to the 78K/0S Series Instructions User's Manual (U11047E). 20.1 Operation 20.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * $: Relative address specification * !: * [ ]: Indirect address specification Absolute address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For the operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 20-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp sfr AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte bit 8-bit immediate data or label 3-bit immediate data or label Remark 248 Refer to Table 4-3 Special-Function Register List for the symbols of the special-function registers. User's Manual U14643EJ2V0UD CHAPTER 20 INSTRUCTION SET 20.1.2 Description of "operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parentheses xH, xL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : : Exclusive logical sum (exclusive OR) Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 20.1.3 Description of "flag operation" column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored User's Manual U14643EJ2V0UD 249 CHAPTER 20 INSTRUCTION SET 20.2 Operation List Mnemonic MOV Operands Clocks Operation r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte Note 1 2 4 Ar Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL+byte] 2 6 A (HL+byte) [HL+byte], A 2 6 (HL+byte) A A, X 1 4 AX A, r 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL+byte] 2 8 A (HL+byte) A, r r, A XCH Bytes Note 2 Flag Z AC CY x x x x x x Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 250 User's Manual U14643EJ2V0UD CHAPTER 20 INSTRUCTION SET Mnemonic MOVW Operands Bytes Clocks Operation rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) saddrp, AX 2 8 (saddrp) AX Note 1 4 AX rp Note 1 4 rp AX Note 1 8 AX rp AX, rp rp, AX Flag Z AC CY XCHW AX, rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL+byte] 2 6 A, CY A + (HL+byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL+byte] 2 6 A, CY A + (HL+byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL+byte] 2 6 A, CY A - (HL+byte) x x x ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14643EJ2V0UD 251 CHAPTER 20 INSTRUCTION SET Mnemonic SUBC AND OR XOR Remark Operands Bytes Clocks Operation Z AC CY A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL+byte] 2 6 A, CY A - (HL+byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL+byte] 2 6 A A (HL+byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL+byte] 2 6 A A (HL+byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL+byte] 2 6 A A (HL+byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 252 Flag User's Manual U14643EJ2V0UD CHAPTER 20 INSTRUCTION SET Mnemonic Operands Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL+byte] 2 6 A - (HL+byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U14643EJ2V0UD 253 CHAPTER 20 INSTRUCTION SET Mnemonic CALL Operands !addr16 Bytes 3 Clocks 6 Operation Flag Z AC CY R R R R R R (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 RETI 1 8 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PUSH POP MOVW BR BF DBNZ PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 254 User's Manual U14643EJ2V0UD CHAPTER 20 INSTRUCTION SET 20.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None 1st Operand A r ADD MOVNote MOV MOV ADDC XCHNote XCH XCH SUB ADD ADD SUBC ADDC AND MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV MOV INC DEC B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC DEC ADD ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV [HL+byte] MOV Note Except r = A. User's Manual U14643EJ2V0UD 255 CHAPTER 20 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word Note AX rp saddrp SP None 1st Operand AX rp ADDW MOVW SUBW CMPW XCHW MOVW MOVW MOVW Note MOVW INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 SET1 CLR1 CY SET1 CLR1 NOT1 256 User's Manual U14643EJ2V0UD CHAPTER 20 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U14643EJ2V0UD 257 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Supply voltage VDD, AVDD VDD = AVDD Input voltage VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Per pin Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -10 mA -30 mA -7 mA -22 mA 30 mA 160 mA 10 mA 120 mA PD78910xA, 78911xA Total for all pins Per pin Total for all pins Output current, low IOL Per pin PD78910xA(A), 78911xA(A) PD78910xA, 78911xA Total for all pins Per pin Total for all pins PD78910xA(A), 78911xA(A) Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 258 User's Manual U14643EJ2V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic Recommended Parameter Circuit IC0 X1 X2 Conditions Note 1 Oscillation frequency (fX) resonator MAX. Unit 10 MHz 4 ms 10 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 ms 1.0 10 MHz VDD = 4.5 to 5.5 V 45 500 ns VDD = 3.0 to 5.5 V 75 500 ns VDD = 1.8 to 5.5 V 85 500 ns VDD = 2.7 to 5.5 V 1.0 5.0 MHz 85 500 ns VDD = oscillation voltage MIN. 1.0 TYP. range C1 IC0 X1 Crystal C2 X2 resonator After VDD reaches Oscillation stabilization Note 2 time oscillation voltage range MIN. Note 1 Oscillation frequency (fX) Oscillation stabilization C1 External X1 C2 X2 clock time 1.0 Note 2 Note 1 X1 input frequency (fX) X1 input high-/low-level width (tXH, tXL) X1 X2 Note 1 X1 input frequency (fX) X1 input high-/low-level OPEN width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U14643EJ2V0UD 259 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (Expanded-specification products) Manufacturer Murata Mfg. Co., Ltd. Part Number CSBLA1M00J58-B0 Frequency (MHz) Note CSBFB1M00J58-R1 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 2.1 5.5 2.0 - - 1.8 Remark Rd = 2.2 k Note CSTCC2M00G56-R0 CSTLS2M00G56-B0 CSTCR4M00G53-R0 On-chip capacitor version 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 4.915 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 CSTCR6M00G53-R0 6.0 CSTLS6M00GG53-B0 CSTCE8M00G52-R0 8.0 CSTLS8M00G53-B0 CSTCE8M38G52-R0 8.388 CSTLS8M38G53-B0 CSTCE10M0G52-R0 10.0 CSTLS10M00G53-B0 Note A limiting resistor (Rd = 2.2 k) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0 MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is not necessary when other recommended resonators are used. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Caution Rd C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the PD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are within the specifications of the DC and AC characteristics. 260 User's Manual U14643EJ2V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH Conditions MIN. PD78910xA, 78911xA Per pin Total for all pins PD78910xA(A), 78911xA(A) Per pin Total for all pins Output current, low IOL PD78910xA, 78911xA Per pin Total for all pins PD78910xA(A), 78911xA(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 Pins other than described below P50 to P53 With N-ch open drain With on-chip pull-up resistor VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low X1, X2 Pins other than described below P50 to P53 RESET, P20 to P25 X1, X2 MAX. Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Remark RESET, P20 to P25 TYP. P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78910xA, 78911xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78910xA(A), 78911xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78910xA, 78911xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78910xA(A), 78911xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 261 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than X1, X2, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD or P50 to P53 ILIH2 ILIH3 X1, X2 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than X1, X2, low or P50 to P53 ILIL2 X1, X2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 or P60 to current, high Output leakage current, low Software pull-up resistance Mask option pull-up 50 100 200 k 10 30 60 k P63 R2 VI = 0 V, P50 to P53 resistance Power supply current Note 2 IDD1 10.0 MHz crystal oscillation operating mode VDD = 5.0 V 10% 3.2 8.0 mA 6.0 MHz crystal oscillation VDD = 5.0 V 10% 2.0 4.7 mA 5.0 MHz crystal VDD = 5.0 V 10% 1.8 3.2 mA oscillation operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 0.45 0.9 mA VDD = 2.0 V 10% 0.25 0.45 mA VDD = 5.0 V 10% 1.5 3.0 mA 6.0 MHz crystal oscillation HALT mode VDD = 5.0 V 10% 0.9 1.8 mA 5.0 MHz crystal VDD = 5.0 V 10% 0.8 1.6 mA oscillation HALT mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 0.3 0.6 mA VDD = 2.0 V 10% 0.15 0.3 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% 0.05 5.0 A VDD = 5.0 V 10% 4.4 10.3 mA VDD = 5.0 V 10% 3.2 7.0 mA 5.0 MHz crystal VDD = 5.0 V 10% 3.0 5.5 mA oscillation A/D operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 1.65 3.2 mA VDD = 2.0 V 10% 1.25 2.7 mA Note 4 Note 4 operating mode Note 4 Note 5 Note 5 Note 2 IDD2 10.0 MHz crystal Note 4 oscillation HALT mode Note 4 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode 10.0 MHz crystal oscillation Note 4 A/D operating mode 6.0 MHz crystal oscillation Note 4 A/D operating mode Note 4 Note 5 Note 5 262 User's Manual U14643EJ2V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 263 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 4.5 to 5.5 V 0.2 8 s VDD = 3.0 to 5.5 V 0.33 8 s VDD = 2.7 to 5.5 V 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level width tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL TCY vs VDD 60 Cycle time TCY [s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 264 User's Manual U14643EJ2V0UD 6 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (to SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. User's Manual U14643EJ2V0UD 265 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF 266 MIN. User's Manual U14643EJ2V0UD CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 267 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 268 User's Manual U14643EJ2V0UD tF CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) 8-Bit A/D Converter Characteristics (PD78910xA, 78910xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 Bits VDD = 2.7 to 5.5 V 0.4 0.6 %FSR VDD = 1.8 to 5.5 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time Analog input tCONV VDD = 4.5 to 5.5 V 12 100 s VDD = 2.7 to 5.5 V 14 100 s VDD = 1.8 to 5.5 V 28 100 s 0 AVDD V VIAN voltage Notes 1. Excludes quantization error (0.2%). 2. This value is indicated as a ratio to the full-scale value (%FSR). 10-Bit A/D Converter Characteristics (PD78911xA, 78911xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Differential linearity error ILE Note 1 DLE Note 1 Analog input voltage 4.5 V VDD 5.5 V 12 100 s 2.7 V VDD < 4.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 269 CHAPTER 21 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note 1 time s 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 270 User's Manual U14643EJ2V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Supply voltage VDD, AVDD VDD = AVDD Input voltage VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Per pin Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -10 mA -30 mA -7 mA -22 mA 30 mA 160 mA 10 mA 120 mA PD78910xA, 78911xA Total for all pins Per pin Total for all pins Output current, low IOL Per pin PD78910xA(A), 78911xA(A) PD78910xA, 78911xA Total for all pins Per pin Total for all pins PD78910xA(A), 78911xA(A) Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 271 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic Recommended Parameter Circuit IC0 X1 X2 Conditions Note 1 Oscillation frequency (fX) resonator MAX. Unit 5.0 MHz 4 ms 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 VDD = oscillation voltage MIN. 1.0 TYP. range C1 IC0 X1 Crystal C2 X2 resonator After VDD reaches Oscillation stabilization Note 2 time oscillation voltage range MIN. Note 1 Oscillation frequency (fX) Oscillation stabilization C1 External X1 C2 X2 clock time 1.0 Note 2 Note 1 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level 85 500 ns 1.0 5.0 MHz 85 500 ns width (tXH, tXL) X1 X2 Note 1 X1 input frequency (fX) VDD = 2.7 to 5.5 V X1 input high-/low-level OPEN width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 272 User's Manual U14643EJ2V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (Conventional-specification products) Manufacturer Murata Mfg. Co., Ltd. Part Number Frequency (MHz) Note CSBLA1M00J58-B0 CSBFB1M00J58-R1 Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 2.1 5.5 2.0 - - 1.8 Remark Rd = 2.2 k Note CSTCC2M00G56-R0 version CSTLS2M00G56-B0 CSTCR4M00G53-R0 On-chip capacitor 4.0 CSTLS4M00GG53-B0 CSTCR4M19G53-R0 4.194 CSTLS4M19GG53-B0 CSTCR4M91G53-R0 4.915 CSTLS4M91GG53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00GG53-B0 Note A limiting resistor (Rd = 2.2 k) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0 MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is not necessary when other recommended resonators are used. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Caution Rd C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the PD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U14643EJ2V0UD 273 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH Conditions MIN. PD78910xA, 78911xA Per pin Total for all pins PD78910xA(A), 78911xA(A) Per pin Total for all pins Output current, low IOL PD78910xA, 78911xA Per pin Total for all pins PD78910xA(A), 78911xA(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low 274 Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V P50 to P53 VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V Pins other than described below VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V P50 to P53 VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V With N-ch open drain RESET, P20 to P25 X1, X2 RESET, P20 to P25 X1, X2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Remark MAX. Pins other than described below With on-chip pull-up resistor VIH3 TYP. P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78910xA, 78911xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78910xA(A), 78911xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78910xA, 78911xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78910xA(A), 78911xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than X1, X2, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD or P50 to P53 ILIH2 ILIH3 X1, X2 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than X1, X2, low or P50 to P53 ILIL2 X1, X2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 or P60 to current, high Output leakage current, low Software pull-up resistance 50 100 200 k 10 30 60 k P63 Mask option pull-up R2 VI = 0 V, P50 to P53 resistance Note 2 Power supply current IDD1 5.0 MHz crystal VDD = 5.0 V 10% 1.8 3.2 mA oscillation operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 0.45 0.9 mA VDD = 2.0 V 10% 0.25 0.45 mA 5.0 MHz crystal VDD = 5.0 V 10% 0.8 1.6 mA oscillation HALT mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 0.3 0.6 mA VDD = 2.0 V 10% 0.15 0.3 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% 0.05 5.0 A 5.0 MHz crystal VDD = 5.0 V 10% 3.0 5.5 mA oscillation A/D operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 1.65 3.2 mA VDD = 2.0 V 10% 1.25 2.7 mA Note 4 Note 5 Note 5 Note 2 IDD2 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode Note 4 Note 5 Note 5 Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 275 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 276 User's Manual U14643EJ2V0UD 6 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (for SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. User's Manual U14643EJ2V0UD 277 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF 278 MIN. User's Manual U14643EJ2V0UD CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 279 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 280 User's Manual U14643EJ2V0UD tF CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) 8-Bit A/D Converter Characteristics (PD78910xA, 78910xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 Bits VDD = 2.7 to 5.5 V 0.4 0.6 %FSR VDD = 1.8 to 5.5 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time Analog input voltage tCONV VDD = 2.7 to 5.5 V 14 100 s VDD = 1.8 to 5.5 V 28 100 s 0 AVDD V VIAN Notes 1. Excludes quantization error (0.2%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 10-Bit A/D Converter Characteristics (PD78911xA, 78911xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Differential linearity error ILE Note 1 DLE Note 1 Analog input voltage 2.7 V VDD 5.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 281 CHAPTER 22 ELECTRICAL SPECIFICATIONS (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note 1 time s 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 282 User's Manual U14643EJ2V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -4 mA -14 mA -2 mA -6 mA 5 mA 80 mA 2 mA 40 mA PD78910xA(A1), 78911xA(A1) -40 to +110 C PD78910xA(A2), 78911xA(A2) -40 to +125 C -65 to +150 C Supply voltage VDD, AVDD VDD = AVDD Input voltage VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Per pin Total for all pins Per pin Total for all pins Output current, low IOL Per pin Total for all pins Per pin Total for all pins Operating ambient temperature Storage temperature Caution TA PD78910xA(A1), 78911xA(A1) PD78910xA(A2), 78911xA(A2) PD78910xA(A1), 78911xA(A1) PD78910xA(A2), 78911xA(A2) Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 283 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) System Clock Oscillator Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) Resonator Ceramic Recommended Parameter Circuit IC0 X1 X2 Conditions Note 1 Oscillation frequency (fX) resonator VDD = oscillation voltage MIN. TYP. 1.0 MAX. Unit 5.0 MHz 4 ms range C1 C2 Oscillation stabilization time External X1 X2 Note 2 After VDD reaches oscillation voltage range MIN. Note 1 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level 85 500 ns clock OPEN width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate under the following conditions. PD78910xA(A1), 78911xA(A1): TA = 110C PD78910xA(A2), 78911xA(A2): TA = 125C Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 284 User's Manual U14643EJ2V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) DC Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) (1/2) Parameter Output current, high Symbol IOH Conditions PD78910xA(A1), Per pin Total for all pins Total for all pins IOL Total for all pins Output voltage, high Output voltage, low Input leakage current, 78911xA(A1) PD78910xA(A2), Per pin Input voltage, low 78911xA(A2) PD78910xA(A1), Per pin Total for all pins Input voltage, high 78911xA(A1) PD78910xA(A2), Per pin Output current, low MIN. 78911xA(A2) TYP. MAX. Unit -1 mA -7 mA -1 mA -3 mA 1.6 mA 40 mA 1.6 mA 20 mA VIH1 Pins other than described below 0.7VDD VDD V VIH2 P50 to P53 With N-ch open drain 0.7VDD 10 V With on-chip pull-up resistor 0.7VDD VDD V 0.8VDD VDD V VDD - 0.1 VDD V VIH3 RESET, P20 to P25 VIH4 X1, X2 VIL1 Pins other than described below 0 0.3VDD V VIL2 P50 to P53 0 0.3VDD V VIL3 RESET, P20 to P25 0 0.2VDD V VIL4 X1, X2 0 0.1 V VOH1 IOH = -1 mA VDD - 2.0 V VOH2 IOH = -100 A VDD - 1.0 V VOL1 Pins other than P50 to P53 IOL = 1.6 mA 2.0 V IOL = 400 A 1.0 V VOL2 P50 to P53 IOL = 1.6 mA 1.0 V ILIH1 Pins other than X1, X2, or P50 10 A 20 A high VI = VDD to P53 Input leakage current, ILIH2 X1, X2 ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80 A ILIL1 Pins other than X1, X2, or P50 VI = 0 V -10 A -20 A low to P53 ILIL2 Output leakage X1, X2 Note A ILIL3 P50 to P53 (N-ch open drain) ILOH VO = VDD 10 A ILOL VO = 0 V -10 A -10 current, high Output leakage current, low Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 285 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) DC Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) (2/2) Parameter Software pull-up Symbol R1 resistance Conditions MIN. TYP. MAX. Unit VI = 0 V, for pins other than P50 to P53 or P60 to 50 100 300 k 10 30 100 k 1.8 8.0 mA 0.8 5.0 mA P63 Mask option pull-up R2 VI = 0 V, P50 to P53 resistance Note 1 Power supply IDD1 current 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) Note 1 IDD2 Note 3 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) Note 3 Note 1 STOP mode 0.1 1000 A Note 2 5.0 MHz crystal oscillation A/D operating mode Note 3 (C1 = C2 = 22 pF) 3.0 10 mA IDD3 IDD4 Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 286 User's Manual U14643EJ2V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) AC Characteristics (1) Basic operation (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) Parameter Cycle time Symbol Conditions MIN. TCY 0.4 TI80 input high-/lowlevel width tTIH, tTIL 0.1 TI80 input frequency fTI Interrupt input high- tINTH, /low-level width tINTL RESET low-level TYP. MAX. Unit 8 s (minimum instruction execution time) 0 s 4 MHz 10 s tRSL 10 s tCPH, tCPL 10 s INTP0 to INTP2 width TCY vs VDD 60 10 Cycle time TCY [ s] CPT20 input high/low-level width Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 287 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) (2) Serial interface (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time tKCY1 800 ns SCK20 high-/low- tKH1, tKCY1/2 - 50 ns level width tKL1 SI20 setup time tSIK1 150 ns tKSI1 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO1 Note R = 1 k, C = 100 pF 0 250 ns MAX. Unit time from SCK20 Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter Symbol Conditions MIN. TYP. SCK20 cycle time tKCY2 800 ns SCK20 high-/low- tKH2, 400 ns level width tKL2 SI20 setup time tSIK2 100 ns tKSI2 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO2 Note R = 1 k, C = 100 pF 0 300 ns tKAS2 120 ns tKDS2 240 ns time from SCK20 SO20 setup time (to SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) SS20 setup time tSSK2 100 ns tKSS2 400 ns (to SCK20 first edge) SS20 hold time (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate 288 User's Manual U14643EJ2V0UD MIN. TYP. MAX. Unit 78125 bps CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) (iv) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time tKCY3 800 ns ASCK20 high-/lowlevel width tKH3, tKL3 400 ns Transfer rate ASCK20 rise/fall time tR, 39063 bps 1 s tF User's Manual U14643EJ2V0UD 289 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET 290 User's Manual U14643EJ2V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14643EJ2V0UD 291 CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) 8-Bit A/D Converter Characteristics (PD78910xA(A1), 78910xA(A2) only) (AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = -40 to +110C (PD78910xA(A1)), -40 to +125C (PD78910xA(A2)) ) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 Bits 0.4 1.0 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV 14 28 s Analog input voltage VIAN 0 AVDD V Notes 1. Excludes quantization error (0.2%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 10-Bit A/D Converter Characteristics (PD78911xA(A1), 78911xA(A2) only) (AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = -40 to +110C (PD78911xA(A1)), -40 to +125C (PD78911xA(A2)) ) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 0.4 0.6 %FSR 28 s 0.6 %FSR 0.6 %FSR ILE 4.5 LSB DLE 2.0 LSB AVDD V Resolution Notes 1, 2 Overall error Conversion time tCONV 14 Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 292 User's Manual U14643EJ2V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110C (PD78910xA(A1), 78911xA(A1)), -40 to +125C (PD78910xA(A2), 78911xA(A2)) ) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 tSREL 0 TYP. MAX. Unit 5.5 V supply voltage Release signal s set time Oscillation tWAIT stabilization wait Note 1 time 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14643EJ2V0UD 293 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage Conditions VDD = AVDD -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V -10 mA -30 mA -7 mA -22 mA 30 mA 160 mA 10 mA 120 mA -40 to +85 C 10 to 40 C -40 to +125 C VO Output current, high IOH Per pin With N-ch open drain PD78F9116B Total for all pins Per pin PD78F9116B(A) Total for all pins IOL Per pin PD78F9116B Total for all pins Per pin PD78F9116B(A) Total for all pins Operating ambient temperature TA In normal operation mode During flash memory programming Storage temperature Unit VDD, AVDD Output voltage Output current, low Ratings Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 294 User's Manual U14643EJ2V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Parameter Circuit Conditions Note 1 Ceramic resonator Oscillation frequency (fX) VPP X1 C1 X2 C2 Oscillation stabilization Note 2 time resonator C1 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz 4 ms VDD = 4.5 to 5.5 V 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 Note 2 Note 1 X2 X1 input frequency (fX) X1 input high-/low-level width (tXH, tXL) X1 1.0 C2 time X1 Unit X2 Oscillation stabilization External clock MAX. oscillation voltage range MIN. Oscillation frequency (fX) VPP X1 TYP. VDD = 4.5 to 5.5 V After VDD reaches Note 1 Crystal MIN. X2 Note 1 X1 input frequency (fX) VDD = 4.5 to 5.5 V 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 1.8 to 5.5 V 1.0 5.0 MHz VDD = 4.5 to 5.5 V 45 500 ns VDD = 3.0 to 5.5 V 75 500 ns VDD = 1.8 to 5.5 V 85 500 ns VDD = 2.7 to 5.5 V 1.0 5.0 MHz 85 500 ns X1 input high-/low-level OPEN width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U14643EJ2V0UD 295 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (PD78F9116B, 78F9116B(A)) Manufacturer Murata Mfg. Co., Ltd. (Standard products) Part Number Frequency (MHz) Note Recommended Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. 2.0 CSBLA1M00J58-B0 1.0 100 100 CSTCC2M00G56-R0 2.0 - - CSTCR4M00G53-R0 4.0 Remark MAX. 5.5 Rd = 2.2 k On-chip capacitor version CSTLS4M00G53-B0 CSTCR5M00G53-R0 2.1 5.0 CSTLS5M00G53-B0 CSTCR6M00G53-R0 6.0 CSTLS6M00G53-B0 CSTCE8M38G52-R0 2.2 2.0 8.388 CSTLS8M38G53-B0 CSTCE10M0G52-R0 2.2 2.1 10.0 CSTLS10M0G53-B0 Murata Mfg. Co., Ltd. (Low-voltage drive type) 2.4 CSTCR4M00G53U-R0 4.0 - - 1.8 CSTLS4M00G53093-B0 CSTCR5M00G53U-R0 5.5 On-chip capacitor version 5.0 CSTLS5M00G53U-B0 CSTCR6M00G53093-R0 6.0 1.9 CSTLS8M38G53193-B0 8.0 2.0 CSTLS10M0G53U-B0 10.0 CSTLS6M00G53U-B0 Note A limiting resistor (Rd = 2.2 k) is required when the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). A limiting resistor is not necessary when other recommended resonators are used. X1 X2 Rd CSBLA1M00J58-B0 C1 C2 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the PD78F9116B and 78F9116B(A) so that the internal operating conditions are within the specifications of the DC and AC characteristics. 296 User's Manual U14643EJ2V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH Conditions MIN. PD78F9116B Per pin Total for all pins PD78F9116B(A) Per pin Total for all pins Output current, low IOL PD78F9116B Per pin Total for all pins PD78F9116B(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V N-ch open drain VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V N-ch open drain VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V X1, X2 Pins other than described below RESET, P20 to P25 X1, X2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Remark Unit 0.7VDD RESET, P20 to P25 P50 to P53 MAX. VDD = 2.7 to 5.5 V Pins other than described below P50 to P53 TYP. P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9116B) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9116B(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9116B) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9116B(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 297 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, high Input leakage current, low Symbol ILIH1 MIN. TYP. Unit 3 A 20 A A A ILIH3 P50 to P53 (N-ch open drain) VI = 12 V 20 ILIL1 -3 ILIL2 Pins other than X1, X2, or P50 to P53 X1, X2 ILIL3 P50 to P53 (N-ch open drain) Note 2 IDD1 Note 2 IDD2 Note 2 IDD3 Note 3 IDD4 VI = VDD MAX. ILIH2 Output leakage current, ILOH high Output leakage current, ILOL low Software pull-up resistance R1 Power supply current Conditions Pins other than X1, X2, or P50 to P53 X1, X2 VI = 0 V VO = VDD 3 A A A VO = 0 V -3 A -20 -3 VI = 0 V, for pins other than P50 to P53 or P60 to P63 50 Note 1 100 200 k 10.0 20.0 mA 10.0 MHz crystal oscillation operating mode 6.0 MHz crystal oscillation operating mode 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) VDD = 5.0 V 10% Note 4 VDD = 5.0 V 10% Note 4 6.0 12.0 mA VDD = 5.0 V 10% Note 4 4.0 10.0 mA VDD = 3.0 V 10% Note 5 1.0 2.5 mA VDD = 2.0 V 10% Note 5 0.8 2.0 mA 10.0 MHz crystal oscillation HALT mode 6.0 MHz crystal oscillation HALT mode 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) VDD = 5.0 V 10% Note 4 1.2 6.0 mA VDD = 5.0 V 10% Note 4 0.9 2.8 mA VDD = 5.0 V 10% Note 4 0.6 2.5 mA VDD = 3.0 V 10% Note 5 0.3 2.0 mA VDD = 2.0 V 10% Note 5 0.2 1.5 mA STOP mode VDD = 5.0 V 10% 0.1 30 VDD = 3.0 V 10% 0.05 10 10.0 MHz crystal oscillation A/D operating mode 6.0 MHz crystal oscillation A/D operating mode 5.0 MHz crystal oscillation A/D operating mode (C1 = C2 = 22 pF) VDD = 2.0 V 10% 0.05 10 A A A VDD = 5.0 V 10% Note 4 11.0 22.5 mA VDD = 5.0 V 10% Note 4 7.0 14.5 mA VDD = 5.0 V 10% Note 4 5.0 12.5 mA VDD = 3.0 V 10% Note 5 2.0 5.0 mA VDD = 2.0 V 10% Note 5 1.8 4.5 mA Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 298 User's Manual U14643EJ2V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Operating frequency Symbol fX Conditions MIN. TYP. MAX. Unit VDD = 4.5 to 5.5 V 1.0 10.0 MHz VDD = 3.0 to 5.5 V 1.0 6.0 MHz VDD = 2.7 to 5.5 V 1.0 5.0 MHz VDD = 1.8 to 5.5 V 1.0 1.25 MHz Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 21 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 21 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 0.2 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.2 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 0.2 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. User's Manual U14643EJ2V0UD 299 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 4.5 to 5.5 V 0.2 8 s VDD = 3.0 to 5.5 V 0.33 8 s VDD = 2.7 to 5.5 V 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL width TCY vs VDD 60 Cycle time TCY [s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 300 User's Manual U14643EJ2V0UD 6 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (for SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. User's Manual U14643EJ2V0UD 301 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF 302 MIN. User's Manual U14643EJ2V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 303 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 304 User's Manual U14643EJ2V0UD tF CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) 10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity Note 1 error Differential linearity error ILE DLE Note 1 Analog input voltage 4.5 V VDD 5.5 V 12 100 s 2.7 V VDD < 4.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 305 CHAPTER 24 ELECTRICAL SPECIFICATIONS (PD78F9116B, 78F9116B(A)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note 1 time s 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 306 User's Manual U14643EJ2V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V Per pin -4 mA Total for all pins -14 mA Per pin 5 mA Total for all pins 80 mA -40 to +105 C 10 to 40 C -40 to +125 C Output current, high IOH IOL TA With N-ch open drain In normal operation mode During flash memory programming Storage temperature Unit VDD = AVDD VO Operating ambient temperature Ratings VDD, AVDD Output voltage Output current, low Conditions Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (4.5 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (4.5 V) of the operating voltage range of VDD (see b in the figure below). VDD 4.5 V 0V a b VPP 4.5 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 307 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) System Clock Oscillator Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) Resonator Ceramic Recommended Circuit VPP X1 X2 Parameter Conditions Note 1 Oscillation frequency (fX) resonator VDD = oscillation voltage MIN. TYP. 1.0 MAX. Unit 5.0 MHz 4 ms range C1 External X1 C2 Oscillation stabilization Note 2 time After VDD reaches oscillation voltage range MIN. Note 1 X2 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns OPEN clock Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate at TA = 105C. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 308 User's Manual U14643EJ2V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) DC Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current, Symbol IOH IOL Conditions MIN. TYP. MAX. Unit Per pin -1 mA Total for all pins -7 mA Per pin 1.6 mA Total for all pins 40 mA VIH1 Pins other than described below 0.7VDD VDD V VIH2 P50 to P53 0.7VDD 10 V VIH3 RESET, P20 to P25 0.8VDD VDD V VIH4 X1, X2 VDD - 0.1 VDD V VIL1 Pins other than described below 0 0.3VDD V VIL2 P50 to P53 0 0.3VDD V VIL3 RESET, P20 to P25 0 0.2VDD V VIL4 X1, X2 0 0.1 V VOH1 IOH = -1 mA VDD - 2.0 V VOH2 IOH = -100 A VDD - 1.0 V VOL1 Pins other than P50 to P53 IOL = 1.6 mA 2.0 V IOL = 400 A 1.0 V VOL2 P50 to P53 IOL = 1.6 mA 1.0 V ILIH1 Pins other than X1, X2, or P50 10 A 20 A high With N-ch open drain VI = VDD to P53 Input leakage current, ILIH2 X1, X2 ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80 A ILIL1 Pins other than X1, X2, or P50 VI = 0 V -10 A -20 A low to P53 ILIL2 Output leakage X1, X2 Note A ILIL3 P50 to P53 (N-ch open drain) ILOH VO = VDD 10 A ILOL VO = 0 V -10 A -10 current, high Output leakage current, low Note When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 309 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) DC Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (2/2) Parameter Symbol Software pull-up R1 resistance Conditions MIN. TYP. MAX. Unit VI = 0 V, for pins other than P50 to P53 or P60 to 50 100 300 k P63 Power supply current Note 1 5.0 MHz crystal oscillation operating mode Note 3 (C1 = C2 = 22 pF) 7.5 20.0 mA Note 1 5.0 MHz crystal oscillation HALT mode 3.0 5.5 mA 1 1000 A 8.7 22.3 mA IDD1 IDD2 (C1 = C2 = 22 pF) Note 1 IDD3 Note 2 IDD4 Note 3 STOP mode 5.0 MHz crystal oscillation A/D operating mode (C1 = C2 = 22 pF) Note 3 Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 4.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 21 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 21 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 0.2 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.2 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 0.2 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 310 User's Manual U14643EJ2V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) AC Characteristics (1) Basic operation (TA = -40 to +105C, VDD = 4.5 to 5.5 V) Parameter Cycle time Symbol Conditions MIN. TCY 0.4 TI80 input high-/low- tTIH, 0.1 level width tTIL TI80 input frequency fTI Interrupt input high- tINTH, /low-level width tINTL RESET low-level TYP. MAX. Unit 8 s (minimum instruction execution time) 0 s 4 MHz 10 s tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL INTP0 to INTP2 width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 311 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) (2) Serial interface (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time tKCY1 800 ns SCK20 high-/low- tKH1, tKCY1/2 - 50 ns level width tKL1 SI20 setup time tSIK1 150 ns tKSI1 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO1 Note R = 1 k, C = 100 pF 0 250 ns MAX. Unit time from SCK20 Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter Symbol Conditions MIN. TYP. SCK20 cycle time tKCY2 800 ns SCK20 high-/low- tKH2, 400 ns level width tKL2 SI20 setup time tSIK2 100 ns tKSI2 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay Note 300 ns tKAS2 120 ns tKDS2 240 ns tKSO2 R = 1 k, C = 100 pF 0 time from SCK20 SO20 setup time (to SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) SS20 setup time tSSK2 100 ns tKSS2 400 ns (to SCK20 first edge) SS20 hold time (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate 312 User's Manual U14643EJ2V0UD MIN. TYP. MAX. Unit 78125 bps CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) (iv) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time tKCY3 800 ns ASCK20 high-/lowlevel width tKH3, tKL3 400 ns Transfer rate ASCK20 rise/fall time tR, 39063 bps 1 s tF User's Manual U14643EJ2V0UD 313 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET 314 User's Manual U14643EJ2V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14643EJ2V0UD 315 CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) 10-Bit A/D Converter Characteristics (TA = -40 to +105C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 0.4 0.6 %FSR 28 s 0.6 %FSR 0.6 %FSR ILE 4.5 LSB DLE 2.0 LSB AVDD V Resolution Notes 1,2 Overall error Conversion time tCONV 14 Notes 1,2 Zero-scale error Full-scale error Notes 1,2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 316 User's Manual U14643EJ2V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS (PD78F9116B(A1)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +105C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note 1 time s 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14643EJ2V0UD 317 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V Per pin -10 mA Total for all pins -30 mA Per pin 30 mA Total for all pins 160 mA -40 to +85 C 10 to 40 C -40 to +125 C Output current, high IOH IOL TA With N-ch open drain In normal operation mode During flash memory programming Storage temperature Unit VDD = AVDD VO Operating ambient temperature Ratings VDD, AVDD Output voltage Output current, low Conditions Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 318 User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic Recommended Parameter Circuit VPP X1 X2 Conditions Note 1 Oscillation frequency (fX) resonator MAX. Unit 5.0 MHz 4 ms 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 1.8 to 5.5 V 30 VDD = oscillation voltage MIN. 1.0 TYP. range C1 VPP X1 Crystal Oscillation stabilization Note 2 time C2 X2 resonator After VDD reaches oscillation voltage range MIN. Note 1 Oscillation frequency (fX) Oscillation stabilization C1 External X1 time C2 X2 clock 1.0 Note 2 Note 1 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level 85 500 ns 1.0 5.0 MHz 85 500 ns width (tXH, tXL) X1 Note 1 X2 X1 input frequency (fX) OPEN X1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U14643EJ2V0UD 319 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL VIH1 VIH2 Conditions MAX. Unit Per pin -1 mA Total for all pins -15 mA Per pin 10 mA Total for all pins 80 mA Pins other than described below P50 to P53 N-ch open drain MIN. TYP. VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V, 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V, 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V TA = 25 to 85C VIH3 VIH4 Input voltage, low VIL1 VIL2 RESET, P20 to P25 X1, X2 Pins other than described below P50 to P53 N-ch open drain TA = 25 to 85C VIL3 VIL4 Output voltage, high Output voltage, low 320 X1, X2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V VOL2 Remark RESET, P20 to P25 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than X1, X2, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD or P50 to P53 ILIH2 ILIH3 X1, X2 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than X1, X2, low or P50 to P53 ILIL2 X1, X2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 or P60 to 100 200 k current, high Output leakage current, low Software pull-up resistance 50 P63 Note 2 Power supply IDD1 current 5.0 MHz crystal VDD = 5.0 V 10% 5.0 15.0 mA oscillation operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 1.9 4.9 mA VDD = 2.0 V 10% 1.5 3.0 mA 5.0 MHz crystal VDD = 5.0 V 10% 2.5 5.0 mA oscillation HALT mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 1.0 2.0 mA VDD = 2.0 V 10% 0.75 1.5 mA VDD = 5.0 V 10% 0.1 30 A VDD = 3.0 V 10% 0.05 10 A VDD = 2.0 V 10% 0.05 10 A 5.0 MHz crystal VDD = 5.0 V 10% 6.2 17.3 mA oscillation A/D operating mode (C1 = C2 = 22 pF) VDD = 3.0 V 10% 3.1 7.2 mA VDD = 2.0 V 10% 2.5 5.0 mA Note 4 Note 5 Note 5 Note 2 IDD2 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode Note 4 Note 5 Note 5 Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 321 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 18 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 (@ 5.0 MHz operation) 18 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 1 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.5 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 1 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 322 User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 0.4 8 s VDD = 1.8 to 5.5 V 1.6 8 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 323 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (to SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. 324 User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF User's Manual U14643EJ2V0UD 325 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET 326 User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14643EJ2V0UD 327 CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) 10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Differential linearity error ILE Note 1 DLE Note 1 Analog input voltage 2.7 V VDD 5.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 328 User's Manual U14643EJ2V0UD CHAPTER 26 ELECTRICAL SPECIFICATIONS (PD78F9116A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note 1 time s 15 Release by RESET Release by interrupt request 2 /fX s Note 2 s Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register. Remark fX: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14643EJ2V0UD 329 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Supply voltage VDD, AVDD VDD = AVDD Input voltage VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Per pin Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -10 mA -30 mA -7 mA -22 mA 30 mA 160 mA 10 mA 120 mA PD78912xA, 78913xA Total for all pins Per pin Total for all pins Output current, low IOL Per pin PD78912xA(A), 78913xA(A) PD78912xA, 78913xA Total for all pins Per pin Total for all pins PD78912xA(A), 78913xA(A) Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 330 User's Manual U14643EJ2V0UD CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Recommended Resonator Circuit CL1 RC Parameter Conditions MIN. TYP. MAX. Unit 2.0 4.0 MHz CL2 Oscillation frequency (fCC) CL2 CL1 input frequency (fCC) 1.0 5.0 MHz CL1 input high-/low-level 85 500 ns Note oscillator External CL1 clock Note width (tXH, tXL) CL2 CL1 OPEN Note Note CL1 input frequency (fCC) VDD = 2.7 to 5.5 V 1.0 5.0 MHz CL1 input high-/low-level VDD = 2.7 to 5.5 V 85 500 ns width (tXH, tXL) Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. RC Oscillator Frequency Characteristics (TA = -40 to +85C) Parameter Oscillator frequency Symbol Conditions TYP. MAX. Unit fCC1 R = 11.0 k, C = 22 pF VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz fCC2 Target: 2 MHz VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz fCC3 fCC4 R = 6.8 k, C = 22 pF VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz fCC5 Target: 3 MHz VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz fCC6 fCC7 R = 4.7 k, C = 22 pF VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz fCC8 Target: 4 MHz VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz fCC9 Remark MIN. So that the TYP. spec. is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and C. User's Manual U14643EJ2V0UD 331 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH Conditions MIN. PD78912xA, 78913xA Per pin Total for all pins PD78912xA(A), 78913xA(A) Per pin Total for all pins Output current, low IOL PD78912xA, 78913xA Per pin Total for all pins PD78912xA(A), 78913xA(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low 332 Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V P50 to P53 VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V Pins other than described below VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V P50 to P53 VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V With N-ch open drain RESET, P20 to P25 CL1, CL2 RESET, P20 to P25 CL1, CL2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Remark MAX. Pins other than described below With on-chip pull-up resistor VIH3 TYP. P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78912xA, 78913xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78912xA(A), 78913xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78912xA, 78913xA) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78912xA(A), 78913xA(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than CL1, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD CL2, or P50 to P53 ILIH2 CL1, CL2 ILIH3 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than CL1, low CL2, or P50 to P53 ILIL2 CL1, CL2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 50 100 200 k R2 VI = 0 V, P50 to P53 10 30 60 k current, high Output leakage current, low Software pull-up resistor Mask option pull-up resistor Note 2 Power supply current IDD1 4.0 MHz RC oscillation VDD = 5.0 V 10% 1.8 3.2 mA operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 0.45 0.9 mA VDD = 2.0 V 10% 0.25 0.45 mA 4.0 MHz RC oscillation VDD = 5.0 V 10% 0.8 1.6 mA HALT mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 0.3 0.6 mA VDD = 2.0 V 10% 0.15 0.3 mA VDD = 5.0 V 10% 0.1 10 A VDD = 3.0 V 10% 0.05 5.0 A VDD = 2.0 V 10% 0.05 5.0 A 4.0 MHz RC oscillation VDD = 5.0 V 10% 3.0 5.5 mA A/D operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 1.65 3.2 mA VDD = 2.0 V 10% 1.25 2.7 mA Note 4 Note 5 Note 5 Note 2 IDD2 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode Note 4 Note 5 Note 5 Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 333 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 0.4 16 s VDD = 1.8 to 5.5 V 1.6 16 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 334 User's Manual U14643EJ2V0UD 6 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (to SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. User's Manual U14643EJ2V0UD 335 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF 336 MIN. User's Manual U14643EJ2V0UD CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) AC Timing Measurement Points (Excluding CL1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fCC tXL tXH VIH4 (MIN.) CL1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 337 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 338 User's Manual U14643EJ2V0UD tF CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) 8-Bit A/D Converter Characteristics (PD78912xA, 78912xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 Bits VDD = 2.7 to 5.5 V 0.4 0.6 %FSR VDD = 1.8 to 5.5 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time Analog input voltage tCONV VDD = 2.7 to 5.5 V 14 100 s VDD = 1.8 to 5.5 V 28 100 s 0 AVDD V VIAN Notes 1. Excludes quantization error (0.2%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 10-Bit A/D Converter Characteristics (PD78913xA, 78913xA(A)) (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error ILE Note 1 Differential linearity Note 1 error Analog input voltage DLE 4.5 V VDD 5.5 V 14 100 s 2.7 V VDD 5.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 339 CHAPTER 27 ELECTRICAL SPECIFICATIONS (PD78912xA, 78913xA, 78912xA(A), 78913xA(A)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note time s Release by RESET 7 s 7 s 2 /fCC Release by interrupt request 2 /fCC Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. Remark fCC: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 340 User's Manual U14643EJ2V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -4 mA -14 mA -2 mA -6 mA 5 mA 80 mA 2 mA 40 mA PD78912xA(A1), 78913xA(A1) -40 to +110 C PD78912xA(A2), 78913xA(A2) -40 to +125 C -65 to +150 C Supply voltage VDD, AVDD VDD = AVDD Input voltage VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Per pin Total for all pins Per pin Total for all pins Output current, low IOL Per pin Total for all pins Per pin Total for all pins Operating ambient temperature Storage temperature Caution TA PD78912xA(A1), 78913xA(A1) PD78912xA(A2), 78913xA(A2) PD78912xA(A1), 78913xA(A1) PD78912xA(A2), 78913xA(A2) Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 341 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) System Clock Oscillator Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) Resonator RC Recommended Circuit Parameter Conditions CL1 CL2 Oscillation frequency (fCC) CL1 CL2 MIN. TYP. MAX. Unit Note 2.0 4.0 MHz CL1 input frequency (fCC) Note 1.0 5.0 MHz CL1 input high-/low-level 85 500 ns oscillator External clock OPEN width (tXH, tXL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Construct the oscillator with R and C devices that are guaranteed to operate under the following temperature conditions. PD78912xA(A1), 78913xA(A1): TA = 110C PD78912xA(A2), 78913xA(A2): TA = 125C 342 User's Manual U14643EJ2V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) DC Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) (1/2) Parameter Output current, high Symbol IOH Conditions PD78912xA(A1), Per pin Total for all pins Total for all pins IOL Total for all pins Output voltage, high Output voltage, low Input leakage current, 78913xA(A1) PD78912xA(A2), Per pin Input voltage, low 78913xA(A2) PD78912xA(A1), Per pin Total for all pins Input voltage, high 78913xA(A1) PD78912xA(A2), Per pin Output current, low MIN. 78913xA(A2) TYP. MAX. Unit -1 mA -7 mA -1 mA -3 mA 1.6 mA 40 mA 1.6 mA 20 mA VIH1 Pins other than described below 0.7VDD VDD V VIH2 P50 to P53 With N-ch open drain 0.7VDD 10 V With on-chip pull-up resistor 0.7VDD VDD V 0.8VDD VDD V VDD - 0.1 VDD V VIH3 RESET, P20 to P25 VIH4 CL1, CL2 VIL1 Pins other than described below 0 0.3VDD V VIL2 P50 to P53 0 0.3VDD V VIL3 RESET, P20 to P25 0 0.2VDD V VIL4 CL1, CL2 0 0.1 V VOH1 IOH = -1 mA VDD - 2.0 V VOH2 IOH = -100 A VDD - 1.0 V VOL1 Pins other than P50 to P53 IOL = 1.6 mA 2.0 V IOL = 400 A 1.0 V VOL2 P50 to P53 IOL = 1.6 mA 1.0 V ILIH1 Pins other than CL1, CL2, or 10 A 20 A high VI = VDD P50 to P53 Input leakage current, ILIH2 CL1, CL2 ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80 A ILIL1 Pins other than CL1, CL2, or VI = 0 V -10 A -20 A low P50 to P53 ILIL2 Output leakage CL1, CL2 Note A ILIL3 P50 to P53 (N-ch open drain) ILOH VO = VDD 10 A ILOL VO = 0 V -10 A -10 current, high Output leakage current, low Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 343 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) DC Characteristics (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) (2/2) Parameter Software pull-up Symbol R1 resistance Conditions MIN. TYP. MAX. Unit VI = 0 V, for pins other than P50 to P53 or P60 to 50 100 300 k 10 30 100 k 1.8 8.0 mA 0.8 5.0 mA P63 Mask option pull-up R2 VI = 0 V, P50 to P53 resistance Note 1 Power supply IDD1 current 4.0 MHz crystal oscillation operating mode (R = 4.7 k, C = 22 pF) Note 1 IDD2 Note 3 4.0 MHz crystal oscillation HALT mode (R = 4.7 k, C = 22 pF) Note 3 Note 1 STOP mode 0.1 1000 A Note 2 4.0 MHz crystal oscillation A/D operating mode Note 3 (R = 4.7 k, C = 22 pF) 3.0 10 mA IDD3 IDD4 Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 344 User's Manual U14643EJ2V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) AC Characteristics (1) Basic operation (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) Parameter Cycle time Symbol Conditions MIN. TCY 0.4 TI80 input high-/lowlevel width tTIH, tTIL 0.1 TI80 input frequency fTI Interrupt input high- tINTH, /low-level width tINTL RESET low-level TYP. MAX. Unit 8 s (minimum instruction execution time) 0 s 4 MHz 10 s tRSL 10 s tCPH, tCPL 10 s INTP0 to INTP2 width TCY vs VDD 60 10 Cycle time TCY [ s] CPT20 input high/low-level width Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 345 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) (2) Serial interface (VDD = 4.5 to 5.5 V, TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time tKCY1 800 ns SCK20 high-/low- tKH1, tKCY1/2 - 50 ns level width tKL1 SI20 setup time tSIK1 150 ns tKSI1 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO1 Note R = 1 k, C = 100 pF 0 250 ns MAX. Unit time from SCK20 Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter Symbol Conditions MIN. TYP. SCK20 cycle time tKCY2 800 ns SCK20 high-/low- tKH2, 400 ns level width tKL2 SI20 setup time tSIK2 100 ns tKSI2 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO2 Note R = 1 k, C = 100 pF 0 300 ns tKAS2 120 ns tKDS2 240 ns time from SCK20 SO20 setup time (to SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) SS20 setup time tSSK2 100 ns tKSS2 400 ns (to SCK20 first edge) SS20 hold time (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate 346 User's Manual U14643EJ2V0UD MIN. TYP. MAX. Unit 78125 bps CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) (iv) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time tKCY3 800 ns ASCK20 high-/lowlevel width tKH3, tKL3 400 ns Transfer rate ASCK20 rise/fall time tR, 39063 bps 1 s tF User's Manual U14643EJ2V0UD 347 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) AC Timing Measurement Points (Excluding CL1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fCC tXL tXH VIH4 (MIN.) CL1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET 348 User's Manual U14643EJ2V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14643EJ2V0UD 349 CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) 8-Bit A/D Converter Characteristics (PD78912xA(A1), 78912xA(A2) only) (AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = -40 to +110C (PD78912xA(A1)), -40 to +125C (PD78912xA(A2)) ) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 Bits 0.4 1.0 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV 14 28 s Analog input voltage VIAN 0 AVDD V Notes 1. Excludes quantization error (0.2%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 10-Bit A/D Converter Characteristics (PD78913xA(A1), 78913xA(A2) only) (AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = -40 to +110C (PD78913xA(A1)), -40 to +125C (PD78913xA(A2)) ) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 0.4 0.6 %FSR 28 s 0.6 %FSR 0.6 %FSR ILE 4.5 LSB DLE 2.0 LSB AVDD V Resolution Notes 1, 2 Overall error Conversion time tCONV 14 Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 350 User's Manual U14643EJ2V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110C (PD78912xA(A1), 78913xA(A1)), -40 to +125C (PD78912xA(A2), 78913xA(A2)) ) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 tSREL 0 TYP. MAX. Unit 5.5 V supply voltage Release signal s set time Oscillation tWAIT stabilization wait Note time Release by RESET 7 s 7 s 2 /fCC Release by interrupt request 2 /fCC Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. Remark fcc: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14643EJ2V0UD 351 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage Conditions VDD = AVDD -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V -10 mA -30 mA -7 mA -22 mA 30 mA 160 mA 10 mA 120 mA -40 to +85 C 10 to 40 C -40 to +125 C VO Output current, high IOH With N-ch open drain Per pin PD78F9136B Total for all pins Per pin PD78F9136B(A) Total for all pins IOL Per pin PD78F9136B Total for all pins Per pin PD78F9136B(A) Total for all pins Operating ambient temperature TA In normal operation mode During flash memory programming Storage temperature Unit VDD, AVDD Output voltage Output current, low Ratings Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 352 User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Recommended Resonator Circuit CL1 RC Parameter Conditions MIN. TYP. MAX. Unit 2.0 4.0 MHz CL2 Oscillation frequency (fCC) CL2 CL1 input frequency (fCC) 1.0 5.0 MHz CL1 input high-/low-level 85 500 ns Note oscillator External CL1 clock Note width (tXH, tXL) CL2 CL1 OPEN Note Note CL1 input frequency (fCC) VDD = 2.7 to 5.5 V 1.0 5.0 MHz CL1 input high-/low-level VDD = 2.7 to 5.5 V 85 500 ns width (tXH, tXL) Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. RC Oscillator Frequency Characteristics (TA = -40 to +85C) Parameter Oscillator frequency Symbol Conditions TYP. MAX. Unit fCC1 R = 11.0 k, C = 22 pF VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz fCC2 Target: 2 MHz VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz fCC3 fCC4 R = 6.8 k, C = 22 pF VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz fCC5 Target: 3 MHz VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz fCC6 fCC7 R = 4.7 k, C = 22 pF VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz fCC8 Target: 4 MHz VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz fCC9 Remark MIN. So that the TYP. spec. is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and C. User's Manual U14643EJ2V0UD 353 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH Conditions MIN. PD78F9136B Per pin Total for all pins PD78F9136B(A) Per pin Total for all pins Output current, low IOL PD78F9136B Per pin Total for all pins PD78F9136B(A) Per pin Total for all pins Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low 354 MAX. Unit -1 mA -15 mA -1 mA -11 mA 10 mA 80 mA 3 mA 60 mA Pins other than described below VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V P50 to P53 VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V Pins other than described below VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V P50 to P53 VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V With N-ch open drain RESET, P20 to P25 CL1, CL2 RESET, P20 to P25 CL1, CL2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Remark TYP. P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9136B) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9136B(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA (PD78F9136B) 1.0 V VDD = 4.5 to 5.5 V, IOL = 3 mA (PD78F9136B(A)) 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than CL1, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD CL2, or P50 to P53 ILIH2 ILIH3 CL1, CL2 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than CL1, low CL2, or P50 to P53 ILIL2 CL1, CL2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 100 200 k current, high Output leakage current, low Software pull-up 50 resistance Note 2 Power supply IDD1 current 4.0 MHz RC oscillation VDD = 5.0 V 10% 6.5 18.0 mA operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 3.9 7.9 mA VDD = 2.0 V 10% 3.0 5.0 mA 4.0 MHz RC oscillation VDD = 5.0 V 10% 2.5 5.0 mA HALT mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 1.0 2.0 mA VDD = 2.0 V 10% 0.75 1.5 mA VDD = 5.0 V 10% 0.1 30 A VDD = 3.0 V 10% 0.05 10 A VDD = 2.0 V 10% 0.05 10 A 4.0 MHz RC oscillation VDD = 5.0 V 10% 7.7 20.3 mA A/D operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 5.1 10.2 mA VDD = 2.0 V 10% 4.0 7.0 mA Note 4 Note 5 Note 5 Note 2 IDD2 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode Note 4 Note 5 Note 5 Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 355 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V, RC Oscillation Mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 21 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 21 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 0.2 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.2 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 0.2 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 356 User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 0.4 16 s VDD = 1.8 to 5.5 V 1.6 16 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 357 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k , VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (to SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. 358 User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF User's Manual U14643EJ2V0UD 359 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) AC Timing Measurement Points (Excluding CL1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fCC tXL tXH VIH4 (MIN.) CL1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET 360 User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 User's Manual U14643EJ2V0UD 361 CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) 10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1, 2 Overall error Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity Note 1 error Differential linearity error ILE DLE Note 1 Analog input voltage 4.5 V VDD 5.5 V 14 100 s 2.7 V VDD 5.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). 362 User's Manual U14643EJ2V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (PD78F9136B, 78F9136B(A)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note time s Release by RESET 7 s 7 s 2 /fCC Release by interrupt request 2 /fCC Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. Remark fCC: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT User's Manual U14643EJ2V0UD 363 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V Per pin -4 mA Total for all pins -14 mA Per pin 5 mA Total for all pins 80 mA -40 to +105 C 10 to 40 C -40 to +125 C Output current, high IOH IOL TA With N-ch open drain In normal operation mode During flash memory programming Storage temperature Unit VDD = AVDD VO Operating ambient temperature Ratings VDD, AVDD Output voltage Output current, low Conditions Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (4.5 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (4.5 V) of the operating voltage range of VDD (see b in the figure below). VDD 4.5 V 0V a b VPP 4.5 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 364 User's Manual U14643EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) System Clock Oscillator Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) Resonator RC Recommended Circuit Parameter Conditions CL1 CL2 Oscillation frequency (fCC) CL1 CL2 OPEN MIN. TYP. MAX. Unit Note 2.0 4.0 MHz CL1 input frequency (fCC) Note 1.0 5.0 MHz CL1 input high-/low-level width (tXH, tXL) 85 500 ns oscillator External clock Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Construct the oscillator with R and C devices that are guaranteed to operate at TA = 105C. User's Manual U14643EJ2V0UD 365 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) DC Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current, Symbol IOH IOL Conditions MIN. TYP. MAX. Unit Per pin -1 mA Total for all pins -7 mA Per pin 1.6 mA Total for all pins 40 mA VIH1 Pins other than described below 0.7VDD VDD V VIH2 P50 to P53 0.7VDD 10 V VIH3 RESET, P20 to P25 0.8VDD VDD V VIH4 CL1, CL2 VDD - 0.1 VDD V VIL1 Pins other than described below 0 0.3VDD V VIL2 P50 to P53 0 0.3VDD V VIL3 RESET, P20 to P25 0 0.2VDD V VIL4 CL1, CL2 0 0.1 V VOH1 IOH = -1 mA VDD - 2.0 V VOH2 IOH = -100 A VDD - 1.0 V VOL1 Pins other than P50 to P53 IOL = 1.6 mA 2.0 V IOL = 400 A 1.0 V VOL2 P50 to P53 IOL = 1.6 mA 1.0 V ILIH1 Pins other than CL1, CL2, or 10 A 20 A high With N-ch open drain VI = VDD P50 to P53 Input leakage current, ILIH2 CL1, CL2 ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80 A ILIL1 Pins other than CL1, CL2, or VI = 0 V -10 A -20 A low P50 to P53 ILIL2 Output leakage CL1, CL2 Note A ILIL3 P50 to P53 (N-ch open drain) ILOH VO = VDD 10 A ILOL VO = 0 V -10 A -10 current, high Output leakage current, low Note When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. Remark 366 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) DC Characteristics (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (2/2) Parameter Symbol Software pull-up R1 resistance Conditions MIN. TYP. MAX. Unit VI = 0 V, for pins other than P50 to P53 or P60 to 50 100 300 k 4.0 MHz RC oscillation operating mode Note 3 (R = 4.7 k, C = 22 pF) 7.5 20.0 mA 4.0 MHz RC oscillation HALT mode 3.0 5.5 mA 1 1000 A 8.7 22.3 mA P63 Note 1 Power supply current IDD1 Note 1 IDD2 (R = 4.7 k, C = 22 pF) Note 1 IDD3 Note 2 IDD4 Note 3 STOP mode 4.0 MHz RC oscillation A/D operating mode (R = 4.7 k, C = 22 pF) Note 3 Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 4.5 to 5.5 V, RC Oscillation Operating Mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 21 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 21 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 0.2 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.2 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 0.2 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. User's Manual U14643EJ2V0UD 367 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) AC Characteristics (1) Basic operation (TA = -40 to +105C, VDD = 4.5 to 5.5 V) Parameter Cycle time Symbol Conditions MIN. TCY 0.4 TI80 input high-/low- tTIH, 0.1 level width tTIL TI80 input frequency fTI Interrupt input high- tINTH, /low-level width tINTL RESET low-level TYP. MAX. Unit 8 s (minimum instruction execution time) 0 s 4 MHz 10 s tRSL 10 s CPT20 input high- tCPH, 10 s /low-level width tCPL INTP0 to INTP2 width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 368 User's Manual U14643EJ2V0UD 6 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) (2) Serial interface (TA = -40 to +105C, VDD = 4.5 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time tKCY1 800 ns SCK20 high-/low- tKH1, tKCY1/2 - 50 ns level width tKL1 SI20 setup time tSIK1 150 ns tKSI1 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay tKSO1 Note R = 1 k, C = 100 pF 0 250 ns MAX. Unit time from SCK20 Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter Symbol Conditions MIN. TYP. SCK20 cycle time tKCY2 800 ns SCK20 high-/low- tKH2, 400 ns level width tKL2 SI20 setup time tSIK2 100 ns tKSI2 400 ns (to SCK20) SI20 hold time (from SCK20) SO20 output delay Note 300 ns tKAS2 120 ns tKDS2 240 ns tKSO2 R = 1 k, C = 100 pF 0 time from SCK20 SO20 setup time (to SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) SS20 setup time tSSK2 100 ns tKSS2 400 ns (to SCK20 first edge) SS20 hold time (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate User's Manual U14643EJ2V0UD MIN. TYP. MAX. Unit 78125 bps 369 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) (iv) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time tKCY3 800 ns ASCK20 high-/lowlevel width tKH3, tKL3 400 ns Transfer rate ASCK20 rise/fall time tR, tF 370 User's Manual U14643EJ2V0UD 39063 bps 1 s CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) AC Timing Measurement Points (Excluding CL1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fCC tXL tXH VIH4 (MIN.) CL1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 371 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 372 User's Manual U14643EJ2V0UD tF CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) 10-Bit A/D Converter Characteristics (TA = -40 to +105C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 0.4 0.6 %FSR 28 s 0.6 %FSR 0.6 %FSR ILE 4.5 LSB DLE 2.0 LSB AVDD V Resolution Notes 1,2 Overall error Conversion time tCONV 14 Notes 1,2 Zero-scale error Full-scale error Notes 1,2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 373 CHAPTER 30 ELECTRICAL SPECIFICATIONS (PD78F9136B(A1)) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +105C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note time s Release by RESET 7 s 7 s 2 /fCC Release by interrupt request 2 /fCC Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. Remark fcc: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 374 User's Manual U14643EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage -0.3 to +6.5 V VPP Note -0.3 to +10.5 V VI1 Pins other than P50 to P53 -0.3 to VDD + 0.3 V VI2 P50 to P53 -0.3 to +13 V -0.3 to VDD + 0.3 V Per pin -10 mA Total for all pins -30 mA Per pin 30 mA Total for all pins 160 mA -40 to +85 C 10 to 40 C -40 to +125 C Output current, high IOH IOL TA With N-ch open drain In normal operation mode During flash memory programming Storage temperature Unit VDD = AVDD VO Operating ambient temperature Ratings VDD, AVDD Output voltage Output current, low Conditions Tstg Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 375 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Recommended Resonator Circuit CL1 RC CL2 Parameter Conditions MAX. Unit 2.0 4.0 MHz CL1 input frequency (fCC) 1.0 5.0 MHz CL1 input high-/low-level 85 500 ns 1.0 5.0 MHz 85 500 ns Note 1 Oscillation frequency (fCC) oscillator MIN. VDD = oscillation voltage TYP. range External clock CL1 CL2 Note 1 width (tXH, tXL) CL1 Note Note 1 CL2 CL1 input frequency (fCC) OPEN CL1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. RC Oscillator Frequency Characteristics (TA = -40 to +85C) Parameter Oscillator frequency Symbol Conditions MAX. Unit R = 11.0 k, C = 22 pF VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz fCC2 Target: 2 MHz VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz fCC4 R = 6.8 k, C = 22 pF VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz fCC5 Target: 3 MHz VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz fCC6 fCC7 R = 4.7 k, C = 22 pF VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz fCC8 Target: 4 MHz VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz fCC9 So that the TYP. Spec is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and C. 376 TYP. fCC1 fCC3 Remark MIN. User's Manual U14643EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL VIH1 VIH2 Conditions MAX. Unit Per pin -1 mA Total for all pins -15 mA Per pin 10 mA Total for all pins 80 mA Pins other than described below P50 to P53 With N-ch open drain MIN. TYP. VDD = 2.7 to 5.5 V 0.7VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 2.7 to 5.5 V 0.7VDD 12 V VDD = 1.8 to 5.5 V 0.9VDD 12 V VDD = 2.7 to 5.5 V 0.8VDD VDD V VDD = 1.8 to 5.5 V 0.9VDD VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VDD = 1.8 to 5.5 V VDD - 0.1 VDD V VDD = 2.7 to 5.5 V 0 0.3VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V TA = 25 to 85C VIH3 VIH4 Input voltage, low VIL1 Output voltage, low Pins other than described below P50 to P53 VDD = 2.7 to 5.5 V 0 0.3VDD V VIL3 RESET, P20 to P25 VDD = 2.7 to 5.5 V 0 0.2VDD V VDD = 1.8 to 5.5 V 0 0.1VDD V VDD = 4.5 to 5.5 V 0 0.4 V VDD = 1.8 to 5.5 V 0 0.1 V CL1, CL2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 A 0.5 V P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V VOL2 Remark CL1, CL2 VIL2 VIL4 Output voltage, high RESET, P20 to P25 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U14643EJ2V0UD 377 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 high Conditions Pins other than CL1, MIN. TYP. MAX. Unit 3 A 20 A VI = 12 V 20 A VI = 0 V -3 A -20 A VI = VDD CL2, or P50 to P53 ILIH2 ILIH3 CL1, CL2 P50 to P53 (N-ch open drain) Input leakage current, ILIL1 Pins other than CL1, low CL2, or P50 to P53 ILIL2 CL1, CL2 P50 to P53 (N-ch open ILIL3 -3 Note 1 A drain) Output leakage ILOH VO = VDD 3 A ILOL VO = 0 V -3 A R1 VI = 0 V, for pins other than P50 to P53 100 200 k current, high Output leakage current, low Software pull-up 50 resistance Note 2 Power supply IDD1 current 4.0 MHz RC oscillation VDD = 5.0 V 10% 5.0 15.0 mA operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 1.9 4.9 mA VDD = 2.0 V 10% 1.5 3.0 mA 4.0 MHz RC oscillation VDD = 5.0 V 10% 2.5 5.0 mA HALT mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 1.0 2.0 mA VDD = 2.0 V 10% 0.75 1.5 mA VDD = 5.0 V 10% 0.1 30 A VDD = 3.0 V 10% 0.05 10 A VDD = 2.0 V 10% 0.05 10 A 4.0 MHz RC oscillation VDD = 5.0 V 10% 6.2 17.3 mA A/D operating mode (R = 4.7 k, C = 22 pF) VDD = 3.0 V 10% 3.1 7.2 mA VDD = 2.0 V 10% 2.5 5.0 mA Note 4 Note 5 Note 5 Note 2 IDD2 Note 4 Note 5 Note 5 Note 2 IDD3 Note 3 IDD4 STOP mode Note 4 Note 5 Note 5 Notes 1. When port 5 is in input mode, a low-level input leakage current of -60 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. 3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 378 User's Manual U14643EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V, RC Oscillation Operating Mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current Note (VDD pin) IDDW When VPP supply voltage = VPP1 18 mA Write current Note (VPP pin) IPPW When VPP supply voltage = VPP1 22.5 mA Erase current Note (VDD pin) IDDE When VPP supply voltage = VPP1 18 mA Erase current Note (VPP pin) IPPE When VPP supply voltage = VPP1 115 mA Unit erase time ter 1 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Rewrite count VPP supply voltage 0.5 Erase/write are regarded as 1 cycle 20 VPP0 In normal operation 0 VPP1 During flash memory programming 9.7 1 20 10.0 Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD current are not included. User's Manual U14643EJ2V0UD 379 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time Symbol TCY (minimum instruction execution time) TI80 input high-/low- tTIH, level width tTIL TI80 input frequency fTI Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 0.4 16 s VDD = 1.8 to 5.5 V 1.6 16 s VDD = 2.7 to 5.5 V 0.1 s VDD = 1.8 to 5.5 V 1.8 s VDD = 2.7 to 5.5 V 0 4 MHz VDD = 1.8 to 5.5 V 0 275 kHz INTP0 to INTP2 10 s Interrupt input high- tINTH, /low-level width tINTL RESET low-level tRSL 10 s tCPH, tCPL 10 s width CPT20 input high/low-level width TCY vs VDD 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 380 User's Manual U14643EJ2V0UD 6 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) (2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...internal clock output) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/low- tKH1, level width tKL1 SI20 setup time tSIK1 (to SCK20) SI20 hold time tKSI1 (from SCK20) SO20 output delay tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2 - 50 ns VDD = 1.8 to 5.5 V tKCY1/2 - 150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 0 1000 ns MAX. Unit Note time from SCK20 C = 100 pF Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...external clock input) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/low- tKH2, level width tKL2 SI20 setup time tSIK2 (to SCK20) SI20 hold time tKSI2 (from SCK20) SO20 output delay tKSO2 MIN. TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 0 1000 ns VDD = 2.7 to 5.5 V 120 ns VDD = 1.8 to 5.5 V 400 ns VDD = 2.7 to 5.5 V 240 ns VDD = 1.8 to 5.5 V 800 ns Note time from SCK20 SO20 setup time Conditions C = 100 pF tKAS2 (to SS20 when SS20 is used) SO20 disable time tKDS2 (for SS20 when SS20 is used) SS20 setup time tSSK2 (to SCK20 first edge) SS20 hold time tKSS2 VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns (from SCK20 last edge) Note R and C are the load resistance and load capacitance of the SO output line. User's Manual U14643EJ2V0UD 381 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 78125 bps VDD = 1.8 to 5.5 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK20 cycle time Symbol tKCY3 ASCK20 high-/low- tKH3, level width tKL3 Transfer rate ASCK20 rise/fall time Conditions TYP. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 39063 bps VDD = 1.8 to 5.5 V 9766 bps 1 s tR, tF 382 MIN. User's Manual U14643EJ2V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) AC Timing Measurement Points (Excluding CL1 Input) 0.8VDD 0.2VDD 0.8VDD Measurement points 0.2VDD Clock Timing 1/fCC tXL tXH VIH4 (MIN.) CL1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Capture Input Timing tCPH tCPL CPT20 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET User's Manual U14643EJ2V0UD 383 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data tSSK2 tKSS2 SS20 SCK20 (CKP20 = 0) SCK20 (CKP20 = 1) UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 384 User's Manual U14643EJ2V0UD tF CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) 10-Bit A/D Converter Characteristics (TA = -40 to +85C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 Bits 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 1.8 V VDD < 2.7 V 0.8 1.2 %FSR Resolution Notes 1,2 Overall error Conversion time tCONV Notes 1,2 Zero-scale error Full-scale error Notes 1,2 Integral linearity error Differential linearity error ILE Note 1 DLE Note 1 Analog input voltage 2.7 V VDD 5.5 V 14 100 s 1.8 V VDD < 2.7 V 28 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 1.8 V VDD < 2.7 V 1.2 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 1.8 V VDD < 2.7 V 8.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB 1.8 V VDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Notes 1. Excludes quantization error (0.05%FSR). 2. This value is indicated as a ratio to the full-scale value (%FSR). User's Manual U14643EJ2V0UD 385 CHAPTER 31 ELECTRICAL SPECIFICATIONS (PD78F9136A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention Conditions MIN. VDDDR 1.8 Release signal set time tSREL 0 Oscillation tWAIT TYP. MAX. Unit 5.5 V supply voltage stabilization wait Note time Note s Release by RESET 7 s 7 s 2 /fCC Release by interrupt request 2 /fCC The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. Remark fCC: System clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 386 User's Manual U14643EJ2V0UD CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) IDD vs VDD (System clock: 5.0 MHz crystal resonator) (TA = 25C) 10 5.0 PCC = 00H Power supply current IDD (mA) 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 5.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power supply voltage VDD (V) User's Manual U14643EJ2V0UD 387 CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) IDD vs VDD (System clock: 4.0 MHz crystal resonator) (TA = 25C) 10 5.0 PCC = 00H Power supply current IDD (mA) 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 4.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 Power supply voltage VDD (V) 388 User's Manual U14643EJ2V0UD 6 7 8 CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) IDD vs VDD (System clock: 2.0 MHz crystal resonator) (TA = 25C) 10 5.0 1.0 Power supply current IDD (mA) PCC = 00H PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 2.0 MHz 47 pF 47 pF 0.001 0 1 2 3 4 5 6 7 8 Power supply voltage VDD (V) User's Manual U14643EJ2V0UD 389 CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) IDD vs VDD (System clock: 5.0 MHz ceramic resonator) (TA = 25C) 10 5.0 PCC = 00H Power supply current IDD (mA) 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Ceramic resonator 5.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 Power supply voltage VDD (V) 390 User's Manual U14643EJ2V0UD 6 7 8 CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) IDD vs VDD (System clock: 4.0 MHz ceramic resonator) (TA = 25C) 10 5.0 PCC = 00H Power supply current IDD (mA) 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Ceramic resonator 4.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power supply voltage VDD (V) User's Manual U14643EJ2V0UD 391 CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)) IDD vs VDD (System clock: 2.0 MHz ceramic resonator) (TA = 25C) 10 5.0 1.0 Power supply current IDD (mA) PCC = 00H PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) 0.5 0.1 0.05 0.01 X2 X1 0.005 Ceramic resonator 2.0 MHz 47 pF 47 pF 0.001 0 1 2 3 4 5 Power supply voltage VDD (V) 392 User's Manual U14643EJ2V0UD 6 7 8 CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A) fCC vs VDD (RC oscillation, R = 11 k, C= 22 pF) (TA = -40C) 2.6 System clock frequency fCC [MHz] CL1 CL2 11 k 2.4 22 pF 2.2 Sample A 2.0 Sample B Sample C 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] 5 (TA = 25C) 2.6 CL1 System clock frequency fCC [MHz] 6 CL2 11 k 2.4 22 pF 2.2 Sample A 2.0 Sample B Sample C 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] 5 (TA = 85C) 2.6 CL1 System clock frequency fCC [MHz] 6 CL2 11 k 2.4 22 pF 2.2 Sample A Sample B Sample C 2.0 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 5 6 393 CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136(A) fCC vs VDD (RC oscillation, R = 4.7 k, C= 22 pF) (TA = -40C) 4.6 System clock frequency fCC [MHz] CL1 CL2 4.7 k 4.4 22 pF 4.2 Sample A 4.0 Sample B Sample C 3.8 3.6 3.4 2 3 4 Supply voltage VDD [V] 5 6 (TA = 25C) 4.6 System clock frequency fCC [MHz] CL1 CL2 4.7 k 4.4 22 pF 4.2 Sample A Sample B 4.0 Sample C 3.8 3.6 3.4 2 3 4 Supply voltage VDD [V] 5 (TA = 85C) 4.6 System clock frequency fCC [MHz] CL1 4.4 CL2 4.7 k 22 pF 4.2 Sample A Sample B 4.0 3.8 Sample C 3.6 3.4 394 6 2 3 4 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 5 6 CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) fCC vs VDD (RC oscillation, R = 11 k, C= 22 pF) (TA = -40C) 2.6 System clock frequency fCC [MHz] CL1 CL2 11 k 2.4 22 pF 2.2 Sample A Sample B Sample C 2.0 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] 5 (TA = 25C) 2.6 CL1 System clock frequency fCC [MHz] 6 CL2 11 k 2.4 22 pF 2.2 Sample A Sample B Sample C 2.0 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] 5 (TA = 85C) 2.6 CL1 System clock frequency fCC [MHz] 6 CL2 11 k 2.4 22 pF 2.2 Sample A Sample B Sample C 2.0 1.8 1.6 1.4 2 3 4 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 5 6 395 CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)) fCC vs VDD (RC oscillation, R = 4.7 k, C= 22 pF) (TA = -40C) 4.6 System clock frequency fCC [MHz] CL1 CL2 4.7 k 4.4 22 pF 4.2 Sample A Sample B Sample C 4.0 3.8 3.6 3.4 2 3 4 Supply voltage VDD [V] 5 6 (TA = 25C) 4.6 System clock frequency fCC [MHz] CL1 CL2 4.7 k 4.4 22 pF 4.2 Sample A Sample B Sample C 4.0 3.8 3.6 3.4 2 3 4 Supply voltage VDD [V] 5 (TA = 85C) 4.6 System clock frequency fCC [MHz] CL1 4.4 CL2 4.7 k 22 pF 4.2 Sample A Sample B Sample C 4.0 3.8 3.6 3.4 396 6 2 3 4 Supply voltage VDD [V] User's Manual U14643EJ2V0UD 5 6 CHAPTER 36 PACKAGE DRAWING 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B K M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 9.850.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P +5 3 -3 T 0.25 U 0.60.15 S30MC-65-5A4-2 User's Manual U14643EJ2V0UD 397 CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS The PD789104A, 789114A, 789124A, and 789134A Subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 37-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD789101AMC-xxx-5A4, PD789102AMC-xxx-5A4, PD789104AMC-xxx-5A4 PD789111AMC-xxx-5A4, PD789112AMC-xxx-5A4, PD789114AMC-xxx-5A4 PD789121AMC-xxx-5A4, PD789122AMC-xxx-5A4, PD789124AMC-xxx-5A4 PD789131AMC-xxx-5A4, PD789132AMC-xxx-5A4, PD789134AMC-xxx-5A4 PD789101AMC(A)-xxx-5A4, PD789102AMC(A)-xxx-5A4, PD789104AMC(A)-xxx-5A4 PD789111AMC(A)-xxx-5A4, PD789112AMC(A)-xxx-5A4, PD789114AMC(A)-xxx-5A4 PD789121AMC(A)-xxx-5A4, PD789122AMC(A)-xxx-5A4, PD789124AMC(A)-xxx-5A4 PD789131AMC(A)-xxx-5A4, PD789132AMC(A)-xxx-5A4, PD789134AMC(A)-xxx-5A4 PD789101AMC(A1)-xxx-5A4, PD789102AMC(A1)-xxx-5A4, PD789104AMC(A1)-xxx-5A4 PD789111AMC(A1)-xxx-5A4, PD789112AMC(A1)-xxx-5A4, PD789114AMC(A1)-xxx-5A4 PD789121AMC(A1)-xxx-5A4, PD789122AMC(A1)-xxx-5A4, PD789124AMC(A1)-xxx-5A4 PD789131AMC(A1)-xxx-5A4, PD789132AMC(A1)-xxx-5A4, PD789134AMC(A1)-xxx-5A4 PD789101AMC(A2)-xxx-5A4, PD789102AMC(A2)-xxx-5A4, PD789104AMC(A2)-xxx-5A4 PD789111AMC(A2)-xxx-5A4, PD789112AMC(A2)-xxx-5A4, PD789114AMC(A2)-xxx-5A4 PD789121AMC(A2)-xxx-5A4, PD789122AMC(A2)-xxx-5A4, PD789124AMC(A2)-xxx-5A4 PD789131AMC(A2)-xxx-5A4, PD789132AMC(A2)-xxx-5A4, PD789134AMC(A2)-xxx-5A4 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), VP15-00-3 Count: Three times or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, WS60-00-1 Preheating temperature: 120C max. (package surface temperature) Partial heating Caution 398 Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Do not use different soldering methods together (except for partial heating). User's Manual U14643EJ2V0UD - CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS Table 37-1. Surface Mounting Type Soldering Conditions (2/2) (2) PD78F9116BMC-5A4, PD78F9136BMC-5A4, PD78F9116BMC(A)-5A4, PD78F9136BMC(A)-5A4, PD78F9116BMC(A1)-5A4, PD78F9136BMC(A1)-5A4 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Wave soldering IR35-107-2 Note VP15-107-2 Note Solder bath temperature: 260C max., Time: 10 seconds max., WS60-107-1 Count: Once Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (3) PD78F9116AMC-5A4, PD78F9136AMC-5A4 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Wave soldering IR35-107-3 Note VP15-107-3 Note Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once WS60-107-1 Preheating temperature: 120C max.(package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U14643EJ2V0UD 399 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the PD789104A/114A/124A/134A Subseries. Figure A-1 shows the development tool configuration. * Support of the PC98-NX Series Unless otherwise specified, the PD789104A/114A/124A/134A Subseries supported by IBM PC/ATTM and compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions of IBM PC/AT and compatibles. * Windows Unless otherwise specified, "Windows" indicates the following OSs. * Windows 3.1 * Windows 95 * Windows 98 * Windows 2000 * Windows NTTM Ver. 4.0 400 User's Manual U14643EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package * Software package Language processing software Debugging software * Assembler package * C compiler package * Device file * C library source fileNote 1 * Integrated debugger * System simulator Control software * Project manager (Windows version only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory writing tools Flash programmer In-circuit emulator Emulation board Flash memory writing adapter Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. The C library source file is not included in the software package. 2. The project manager is included in the assembler package and is available only for Windows. User's Manual U14643EJ2V0UD 401 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Various software tools for 78K/0S development are integrated in one package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files Part number: SxxxxSP78K0S Remark xxxx in the part number differs depending on the operating system to be used. Sxxxx SP78K0S xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium CD-ROM English Windows A.2 Language Processing Software RA78K0S Program that converts program written in mnemonic into object codes that can be executed by a Assembler package microcontroller. In addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. Used in combination with a device file (DF789136) (sold separately). <Caution when used in PC environment> The assembler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the package). Part number: SxxxxRA78K0S CC78K0S Program that converts program written in C language into object codes that can be executed by a C compiler package microcontroller. Used in combination with an assembler package (RA78K0S) and device file (DF789136) (both sold separately). <Caution when used in PC environment> The C compiler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package). Part number: SxxxxCC78K0S Note 1 DF789136 File containing the information inherent to the device. Device file Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold separately). Part number: SxxxxDF789136 CC78K0S-L Note 2 C library source file Source file of functions constituting the object library included in the C compiler package. Necessary for changing the object library included in the C compiler package according to the customer's specifications. Since this is the source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Notes 1. DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. 2. CC78K0S-L is not included in the software package (SP78K0S). 402 User's Manual U14643EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system to be used. SxxxxRA78K0S SxxxxCC78K0S xxxx AB13 BB13 Host Machine PC-9800 series, Japanese Windows IBM PC/AT and compatibles AB17 3K17 Supply Medium 3.5" 2HD FD English Windows Japanese Windows BB17 3P17 OS CD-ROM English Windows HP9000 series 700 TM TM SPARCstation HP-UX TM (Rel.10.10) TM SunOS (Rel.4.1.1), TM Solaris (Rel.2.5.1) SxxxxDF789136 SxxxxCC78K0S-L xxxx Host Machine OS Supply Medium 3.5" 2HD FD PC-9800 series, IBM PC/AT and compatibles Japanese Windows 3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT 3K13 SPARCstation SunOS (Rel.4.1.1), 3.5" 2HD FD AB13 BB13 English Windows Solaris (Rel.2.5.1) 3K15 1/4" CGMT A.3 Control Software Project Manager Control software provided for efficient user program development in the Windows environment. The Project Manager allows a series of tasks required for user program development to be performed, including starting the editor, building, and starting the debugger. <Caution> The Project Manager is included in the assembler package (RA78K0S). It cannot be used in an environment other than Windows. A.4 Flash Memory Writing Tools Flashpro III Flash programmer dedicated to microcontrollers incorporating flash memory. (part number: FL-PR3, PG-FP3) Flashpro IV (part number: FL-PR4, PG-FP4) Flash programmer FA-30MC Flash memory writing adapter. Used connected to Flashpro III. Flash memory writing adapter 30-pin plastic SSOP (MC-5A4 type) Remark FL-PR3, FL-PR4, and FA-30MC are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191) User's Manual U14643EJ2V0UD 403 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging the hardware and software of an application system using the IE-78K0S-NS-A In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further In-circuit emulator enhanced by adding a coverage function and enhancing the tracer and timer functions. IE-70000-MC-PS-B Adapter for supplying power from a 100 to 240 VAC outlet. 78K/0S Series. Used with an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine. AC adapter IE-70000-98-IF-C Adapter required when using a PC-9800 series (except notebook type) as the host machine (C Interface adapter bus supported). IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine PC card interface (PCMICA socket supported). IE-70000-PC-IF-C Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus Interface adapter supported). IE-70000-PCI-IF-A Adapter required when using a personal computer incorporating a PCI bus as the host Interface adapter machine. IE-789136-NS-EM1 Emulation board for emulating the peripheral hardware inherent to the device. Emulation board Used in combination with an in-circuit emulator. NP-30MC Probe for connecting the in-circuit emulator and target system. Emulation probe Used in combination with the NSPACK30BK and YSPACK30BK. NSPACK30BK Conversion adapter used to connect a target system board designed to allow mounting a 30- YSPACK30BK Conversion adapter pin plastic SSOP (MC-5A4 type) and the NP-30MC. Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191) 2. The NSPACK30BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 404 User's Manual U14643EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. Used in combination with a device file (DF789136) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software. System simulator It can be used to debug the target system at C source level or assembler level while simulating the operation of the target system on the host machine. Using SM78K0S, the logic and performance of the application can be verified independently of hardware development. Therefore, the development efficiency can be enhanced and the software quality can be improved. Used in combination with a device file (DF789136) (sold separately). Part number: SxxxxSM78K0S Note DF789136 File containing the information inherent to the device. Device file Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold separately). Part number: SxxxxDF789136 Note DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. Remark xxxx in the part number differs depending on the operating system to be used and the supply medium. SxxxxID78K0S-NS SxxxxSM78K0S xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows AB17 Japanese Windows BB17 English Windows User's Manual U14643EJ2V0UD CD-ROM 405 APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789136-NS-EM1 150 mm Board on end of NP-30MC CN2 Emulation probe NP-30MC Conversion adapter: YSPACK30BK, NSPACK30BK Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. The YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION. 406 User's Manual U14643EJ2V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Condition of Target System Emulation board IE-789136-NS-EM1 Emulation probe NP-30MC Board on end of NP-30MC Guide pin YQGUIDE 13 mm Conversion adapter YSPACK30BK, NSPACK30BK 5 mm 15 mm 37 mm 20 mm 31 mm Target system Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. The YSPACK30BK, NSPACK30BK, and YQGUIDE are products of TOKYO ELETECH CORPORATION. User's Manual U14643EJ2V0UD 407 APPENDIX C REGISTER INDEX C.1 Register Name Index (Alphabetical Order) [A] A/D conversion result register 0 (ADCR0) ...........................................................................................................143, 155 A/D converter mode register 0 (ADM0) ...............................................................................................................144, 156 Analog input channel specification register 0 (ADS0) .........................................................................................145, 157 Asynchronous serial interface mode register 20 (ASIM20) .................................................................172, 178, 181, 193 Asynchronous serial interface status register 20 (ASIS20) .................................................................................174, 182 [B] Baud rate generator control register 20 (BRGC20) .....................................................................................175, 183, 194 [E] 8-bit compare register 80 (CR80)............................................................................................................................... 125 8-bit timer counter 80 (TM80)..................................................................................................................................... 125 8-bit timer mode control register 80 (TMC80)............................................................................................................. 126 External interrupt mode register 0 (INTM0)................................................................................................................ 212 [I] Interrupt mask flag register 0 (MK0)............................................................................................................................211 Interrupt mask flag register 1 (MK1)............................................................................................................................211 Interrupt request flag register 0 (IF0).......................................................................................................................... 210 Interrupt request flag register 1 (IF1).......................................................................................................................... 210 [M] Multiplication data register A0 (MRA0) ....................................................................................................................... 202 Multiplication data register B0 (MRB0) ....................................................................................................................... 202 Multiplier control register 0 (MULC0).......................................................................................................................... 204 [O] Oscillation stabilization time select register (OSTS)................................................................................................... 222 [P] Port 0 (P0).................................................................................................................................................................... 82 Port 1 (P1).................................................................................................................................................................... 83 Port 2 (P2).................................................................................................................................................................... 84 Port 5 (P5).................................................................................................................................................................... 88 Port 6 (P6).................................................................................................................................................................... 89 Port mode register 0 (PM0) .......................................................................................................................................... 90 Port mode register 1 (PM1) .......................................................................................................................................... 90 Port mode register 2 (PM2) ...........................................................................................................................90, 115, 127 Port mode register 5 (PM5) .......................................................................................................................................... 90 Processor clock control register (PCC) .................................................................................................................96, 103 Pull-up resistor option register 0 (PU0) ........................................................................................................................ 91 Pull-up resistor option register B2 (PUB2).................................................................................................................... 92 408 User's Manual U14643EJ2V0UD APPENDIX C REGISTER INDEX [R] Receive buffer register 20 (RXB20) ............................................................................................................................169 Receive shift register 20 (RXS20)...............................................................................................................................169 [S] Serial operating mode register 20 (CSIM20)....................................................................................... 170, 178, 180, 192 16-bit capture register 20 (TCP20)..............................................................................................................................112 16-bit compare register 20 (CR20)..............................................................................................................................112 16-bit multiplication result storage register 0 (MUL0) ..................................................................................................202 16-bit timer counter 20 (TM20)....................................................................................................................................112 16-bit timer mode control register 20 (TMC20) ...........................................................................................................113 [T] Timer clock select register 2 (TCL2) ...........................................................................................................................138 Transmit shift register 20 (TXS20)...............................................................................................................................169 [W] Watchdog timer mode register (WDTM)......................................................................................................................139 User's Manual U14643EJ2V0UD 409 APPENDIX C REGISTER INDEX C.2 Register Symbol Index (Alphabetical Order) [A] ADCR0: A/D conversion result register 0 .........................................................................................................143, 155 ADM0: A/D converter mode register 0............................................................................................................144, 156 ADS0: Analog input channel specification register 0 .....................................................................................145, 157 ASIM20: Asynchronous serial interface mode register 20.................................................................172, 178, 181, 193 ASIS20: Asynchronous serial interface status register 20 ................................................................................174, 182 [B] BRGC20: Baud rate generator control register 20......................................................................................175, 183, 194 [C] CR20: 16-bit compare register 20 .........................................................................................................................112 CR80: 8-bit compare register 80 .......................................................................................................................... 125 CSIM20: Serial operating mode register 20 ......................................................................................170, 178, 180, 192 [I] IF0: Interrupt request flag register 0 ................................................................................................................. 210 IF1: Interrupt request flag register 1 ................................................................................................................. 210 INTM0: External interrupt mode register 0 ............................................................................................................. 212 [M] MK0: Interrupt mask flag register 0......................................................................................................................211 MK1: Interrupt mask flag register 1......................................................................................................................211 MRA0: Multiplication data register A0 ................................................................................................................... 202 MRB0: Multiplication data register B0 ................................................................................................................... 202 MUL0: 16-bit multiplication result storage register 0 ............................................................................................. 202 MULC0: Multiplier control register 0 ........................................................................................................................ 204 [O] OSTS: Oscillation stabilization time select register ............................................................................................... 222 [P] P0: Port 0........................................................................................................................................................... 82 P1: Port 1........................................................................................................................................................... 83 P2: Port 2........................................................................................................................................................... 84 P5: Port 5........................................................................................................................................................... 88 P6: Port 6........................................................................................................................................................... 89 PCC: Processor clock control register ...........................................................................................................96, 103 PM0: Port mode register 0.................................................................................................................................... 90 PM1: Port mode register 1.................................................................................................................................... 90 PM2: Port mode register 2.....................................................................................................................90, 115, 127 PM5: Port mode register 5.................................................................................................................................... 90 PU0: Pull-up resistor option register 0.................................................................................................................. 91 PUB2: Pull-up resistor option register B2 ............................................................................................................... 92 410 User's Manual U14643EJ2V0UD APPENDIX C REGISTER INDEX [R] RXB20: Receive buffer register 20 ..........................................................................................................................169 RXS20: Receive shift register 20.............................................................................................................................169 [T] TCL2: Timer clock select register 2 ......................................................................................................................138 TCP20: 16-bit capture register 20 ...........................................................................................................................112 TM20: 16-bit timer counter 20 ...............................................................................................................................112 TM80: 8-bit timer counter 80 .................................................................................................................................125 TMC20: 16-bit timer mode control register 20..........................................................................................................113 TMC80: 8-bit timer mode control register 80 ...........................................................................................................126 TXS20: Transmit shift register 20 ............................................................................................................................169 [W] WDTM: Watchdog timer mode register ...................................................................................................................139 User's Manual U14643EJ2V0UD 411 APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/2) Edition 2nd Major Revision from Previous Edition Applied to: * Addition of PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), Throughout 789114A(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2), 78F9116B, 78F9136B, 78F9116B(A), 78F9136B(A), 78F9116B(A1), 78F9136B(A1) * Addition of description related to expanded-specification products * Addition of 1.1 Expanded-Specification Products and Conventional-Specification Products * Addition of 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products CHAPTER 1 GENERAL (PD789104A, 789114A SUBSERIES) Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1), CHAPTER 2 GENERAL (A2) Products (PD789124A, 789134A SUBSERIES) * Modification of description in 8.4.1 Operation as timer interrupt CHAPTER 8 16-BIT TIMER * Modification of Figure 8-5 Timing of Timer Interrupt Operation 20 * Modification of description in 8.4.2 Operation as timer output * Modification of description in Figure 8-7 Timer Output Timing * Addition of 8.5 Notes on Using 16-Bit Timer 20 Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins CHAPTER 11 8-BIT A/D CONVERTER (PD789104A, 789124A SUBSERIES) * Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0) CHAPTER 12 10-BIT A/D * Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins CONVERTER (PD789114A, 789134A SUBSERIES) * Modification of Figure 13-1 Block Diagram of Serial Interface 20 CHAPTER 13 SERIAL * Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial INTERFACE 20 I/O mode * Addition of 13.4.2 (2) (f) Reading receive data Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register CHAPTER 15 INTERRUPT FUNCTIONS Revision of chapter CHAPTER 18 PD78F9116A, 78F9116B, 78F9136A, 78F9136B 412 User's Manual U14643EJ2V0UD APPENDIX D REVISION HISTORY (2/2) Edition 2nd Major Revision from Previous Edition Addition of chapters Applied to: CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS CHAPTER 32, CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) CHAPTER 34, CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) CHAPTER 36 PACKAGE DRAWING CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS Revision of appendix APPENDIX A DEVELOPMENT TOOLS Addition of appendices APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX D REVISION HISTORY Deletion of APPENDIX B EMBEDDED SOFTWARE User's Manual U14643EJ2V0UD - 413