User’s Manual
µ
PD789101A
µ
PD789101A(A1)
µ
PD789121A
µ
PD789121A(A1)
µ
PD789102A
µ
PD789102A(A1)
µ
PD789122A
µ
PD789122A(A1)
µ
PD789104A
µ
PD789104A(A1)
µ
PD789124A
µ
PD789124A(A1)
µ
PD789111A
µ
PD789111A(A1)
µ
PD789131A
µ
PD789131A(A1)
µ
PD789112A
µ
PD789112A(A1)
µ
PD789132A
µ
PD789132A(A1)
µ
PD789114A
µ
PD789114A(A1)
µ
PD789134A
µ
PD789134A(A1)
µ
PD78F9116A
µ
PD78F9116B(A1)
µ
PD78F9136A
µ
PD78F9136B(A1)
µ
PD78F9116B
µ
PD789101A(A2)
µ
PD78F9136B
µ
PD789121A(A2)
µ
PD789101A(A)
µ
PD789102A(A2)
µ
PD789121A(A)
µ
PD789122A(A2)
µ
PD789102A(A)
µ
PD789104A(A2)
µ
PD789122A(A)
µ
PD789124A(A2)
µ
PD789104A(A)
µ
PD789111A(A2)
µ
PD789124A(A)
µ
PD789131A(A2)
µ
PD789111A(A)
µ
PD789112A(A2)
µ
PD789131A(A)
µ
PD789132A(A2)
µ
PD789112A(A)
µ
PD789114A(A2)
µ
PD789132A(A)
µ
PD789134A(A2)
µ
PD789114A(A)
µ
PD789134A(A)
µ
PD78F9116B(A)
µ
PD78F9136B(A)
µ
PD789104A, 789114A, 789124A,
789134A Subseries
8-Bit Single-Chip Microcontrollers
2000, 2003
Printed in Japan
Document No. U14643EJ2V0UD00 (2nd edition)
Date Published December 2003 N CP(K)
User’s Manual U14643EJ2V0UD
2
[MEMO]
User’s Manual U14643EJ2V0UD 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
User’s Manual U14643EJ2V0UD
4
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of March, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
User’s Manual U14643EJ2V0UD 5
Regional Information
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J03.4
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Succursale Française
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
User’s Manual U14643EJ2V0UD
6
Major Revisions in This Edition
Pages Description
Throughout • Addition of
µ
PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1),
789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 789101A(A2),
789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2),
789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2), 78F9116B, 78F9136B, 78F9116B(A),
78F9136B(A), 78F9116B(A1), 78F9136B(A1)
• Addition of description related to expanded-specification products
pp.24, 36 CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
• Addition of 1.1 Expanded-Specification Products and Conventional-Specification Products
• Addition of 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2)
Products
p.48 CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
• Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2)
Products
pp.116 to 118, 121 CHAPTER 8 16-BIT TIMER 20
• Modification of description in 8.4.1 Operation as timer interrupt
• Modification of Figure 8-5 Timing of Timer Interrupt Operation
• Modification of description in 8.4.2 Operation as timer output
• Modification of description in Figure 8-7 Timer Output Timing
• Addition of 8.5 Notes on Using 16-Bit Timer 20
p.134 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
• Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80
p.152 CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
• Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins
pp.155, 164 CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
• Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0)
• Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins
pp.167, 177, 190 CHAPTER 13 SERIAL INTERFACE 20
• Modification of Figure 13-1 Block Diagram of Serial Interface 20
• Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial I/O mode
• Addition of 13.4.2 (2) (f) Reading receive data
p.210 CHAPTER 15 INTERRUPT FUNCTIONS
• Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register
p.233 Revision of CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
p.258 Addition of CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS
p.387 Addition of CHAPTER 32 and CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
p.393 Addition of CHAPTER 34 and CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY
CHARACTERISTICS (REFERENCE VALUES)
p.397 Addition of CHAPTER 36 PACKAGE DRAWING
p.398 Addition of CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
p.400 Revision of APPENDIX A DEVELOPMENT TOOLS
p.406 Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN
p.412 Addition of APPENDIX D REVISION HISTORY
p.257 in 1st edition Deletion of APPENDIX B EMBEDDED SOFTWARE
The mark shows major revised points.
User’s Manual U14643EJ2V0UD 7
INTRODUCTION
Target Readers This manual is intended for users who wish to understand the functions of the
µ
PD789104A, 789114A, 789124A, 789134A Subseries and to design and develop
application systems and programs using these microcontrollers.
The target devices are shown as follows:
•
µ
PD789104A Subseries:
µ
PD789101A, 789102A, 789104A, 789101A(A),
789102A(A), 789104A(A), 789101A(A1), 789102A(A1),
789104A(A1), 789101A(A2), 789102A(A2), 789104A(A2)
•
µ
PD789114A Subseries:
µ
PD789111A, 789112A, 789114A, 78F9116A, 78F9116B,
789111A(A), 789112A(A), 789114A(A), 78F9116B(A),
789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1),
789111A(A2), 789112A(A2), 789114A(A2)
•
µ
PD789124A Subseries:
µ
PD789121A, 789122A, 789124A, 789121A(A),
789122A(A), 789124A(A), 789121A(A1), 789122A(A1),
789124A(A1), 789121A(A2), 789122A(A2), 789124A(A2)
•
µ
PD789134A Subseries:
µ
PD789131A, 789132A, 789134A, 78F9136A, 78F9136B,
789131A(A), 789132A(A), 789134A(A), 78F9136B(A),
789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1),
789131A(A2), 789132A(A2), 789134A(A2)
The
µ
PD789104A/114A/124A/134A Subseries is a generic term for all the target devices
in this manual.
Generic names in this document indicate the following products.
[Standard quality grade products]
µ
PD789101A, 789102A, 789104A, 789111A,
789112A, 789114A, 78F9116A, 78F9116B,
789121A, 789122A, 789124A, 789131A, 789132A,
789134A, 78F9136A, 78F9136B
[(A) products]
µ
PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A),
789114A(A), 78F9116B(A), 789121A(A), 789122A(A), 789124A(A),
789131A(A), 789132A(A), 789134A(A), 78F9136B(A)
[(A1) products]
µ
PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1),
789112A(A1), 789114A(A1), 78F9116B(A1), 789121A(A1),
789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1),
789134A(A1), 78 F 9136B(A1)
[(A2) products]
µ
PD789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2),
789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2),
789131A(A2), 789132A(A2), 789134A(A2)
User’s Manual U14643EJ2V0UD
8
[Mask ROM products]
µ
PD789101A, 789102A, 789104A, 789111A, 789112A,
789114A, 789121A, 789122A, 789124A, 789131A, 789132A,
789134A, 789101A(A), 789102A(A), 789104A(A), 789111A(A),
789112A(A), 789114A(A), 789121A(A), 789122A(A),
789124A(A), 789131A(A), 789132A(A), 789134A(A),
789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1),
789112A(A1), 789114A(A1), 789121A(A1), 789122A(A1),
789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1),
789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2),
789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2),
789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2)
[Flash memory products]
µ
PD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1),
78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1)
The oscillation frequency of the system clock is regarded as fX for ceramic/crystal
oscillation (
µ
PD789104A and 789114A Subseries), and regarded as fCC for an RC
oscillation (
µ
PD789124A and 789134A Subseries).
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The
µ
PD789104A, 789114A, 789124A, 789134A Subseries User’s Manual is divided into
two parts: this manual and instructions (common to the 78K/0S Series).
µ
PD789104A, 789114A, 789124A,
789134A Subseries
User’s Manual (This manual)
78K/0S Series
Instructions
User’s Manual
• Pin functions
• Internal block functions
• Interrupts
• Other internal peripheral functions
• Electrical specifications
• CPU function
• Instruction set
• Instruction description
User’s Manual U14643EJ2V0UD 9
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
When using this manual as a manual for the
µ
PD789101A(A), 789102A(A),
789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A), 789121A(A),
789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A), 78F9136B(A),
789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1),
789114A(A1), 78F9116B(A1), 789121A(A1), 789122A(A1), 789124A(A1),
789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1), 789101A(A2),
789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2),
789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), and
789134A(A2)
→ Only the quality grade, supply voltage, operating ambient temperature, minimum
instruction execution time, and electrical specifications differ from the
µ
PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116B,
789121A, 789122A, 789124A, 789131A, 789132A, 789134A, and 78F9136B (refer
to 1.10 Differences Between Standard Quality Grade Products and (A), (A1),
(A2) Products, 2.9 Differences Between Standard Quality Grade Products
and (A), (A1), (A2) Products). For the (A), (A1), and (A2) products, read the part
numbers in CHAPTER 3 to CHAPTER 20 as follows.
µ
PD789101A →
µ
PD789101A(A), 789101A(A1), 789101A(A2)
µ
PD789102A →
µ
PD789102A(A), 789102A(A1), 789102A(A2)
µ
PD789104A →
µ
PD789104A(A), 789104A(A1), 789104A(A2)
µ
PD789111A →
µ
PD789111A(A), 789111A(A1), 789111A(A2)
µ
PD789112A →
µ
PD789112A(A), 789112A(A1), 789112A(A2)
µ
PD789114A →
µ
PD789114A(A), 789114A(A1), 789114A(A2)
µ
PD78F9116B →
µ
PD78F9116B(A), 78F9116B(A1)
µ
PD789121A →
µ
PD789121A(A), 789121A(A1), 789121A(A2)
µ
PD789122A →
µ
PD789122A(A), 789122A(A1), 789122A(A2)
µ
PD789124A →
µ
PD789124A(A), 789124A(A1), 789124A(A2)
µ
PD789131A →
µ
PD789131A(A), 789131A(A1), 789131A(A2)
µ
PD789132A →
µ
PD789132A(A), 789132A(A1), 789132A(A2)
µ
PD789134A →
µ
PD789134A(A), 789134A(A1), 789134A(A2)
µ
PD78F9136B →
µ
PD78F9136B(A), 78F9136B(A1)
To understand the overall functions in general
→ Read this manual in the order of the CONTENTS.
How to interpret register formats
→ The name of a bit whose number is in angle brackets (<>) is reserved in the
assembler and is defined in the C compiler by the header file sfrbit.h.
To learn the detailed functions of a register whose register name is known
→ Refer to APPENDIX C REGISTER INDEX.
To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E).
To know the electrical specifications of the
µ
PD789104A/114A/124A/134A Subseries
→ Refer to CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS.
Caution The application examples in this manual are created for “Standard”
quality grade products for general electric equipment. When using the
application examples in this manual for purposes which require
“Special” quality grades, thoroughly examine the quality grade of each
part and circuit actually used.
User’s Manual U14643EJ2V0UD
10
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ
PD789104A, 789114A, 789124A, 789134A Subseries User’s Manual This manual
78K/0S Series Instructions User’s Manual U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name Document No.
Operation U14876E
Language U14877E
RA78K0S Assembler Package
Structured Assembly Language U11623E
Operation U14871E CC78K0S C Compiler
Language U14872E
Operation (WindowsTM Based) U15373E SM78K Series System Simulator Ver. 2.30 or Later
External Part User Open Interface Specification U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E
Project Manager Ver. 3.12 or Later (Windows Based) U14610E
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name Document No.
IE-78K0S-NS In-Circuit Emulator U13549E
IE-78K0S-NS-A In-Circuit Emulator U15207E
IE-789136-NS-EM1 Emulation Board U14363E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U14643EJ2V0UD 11
Documents Related to Flash Memory Writing
Document Name Document No.
PG-FP3 Flash Memory Programmer User's Manual U13502E
PG-FP4 Flash Memory Programmer User's Manual U15260E
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U14643EJ2V0UD
12
CONTENTS
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)........................................................ 24
1.1 Expanded-Specification Products and Conventional-Specification Products...................... 24
1.2 Features......................................................................................................................................... 25
1.3 Applications.................................................................................................................................. 25
1.4 Ordering Information.................................................................................................................... 26
1.5 Quality Grade................................................................................................................................ 27
1.6 Pin Configuration (Top View)...................................................................................................... 28
1.7 78K/0S Series Lineup................................................................................................................... 30
1.8 Block Diagram............................................................................................................................... 33
1.9 Outline of Functions..................................................................................................................... 34
1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 36
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)........................................................ 37
2.1 Features......................................................................................................................................... 37
2.2 Applications.................................................................................................................................. 37
2.3 Ordering Information.................................................................................................................... 38
2.4 Quality Grade................................................................................................................................ 39
2.5 Pin Configuration (Top View)...................................................................................................... 40
2.6 78K/0S Series Lineup................................................................................................................... 42
2.7 Block Diagram............................................................................................................................... 45
2.8 Outline of Functions..................................................................................................................... 46
2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 48
CHAPTER 3 PIN FUNCTIONS............................................................................................................... 49
3.1 Pin Function List........................................................................................................................... 49
3.2 Description of Pin Functions....................................................................................................... 51
3.2.1 P00 to P03 (Port 0) .............................................................................................................................51
3.2.2 P10, P11 (Port 1)................................................................................................................................51
3.2.3 P20 to P25 (Port 2) .............................................................................................................................51
3.2.4 P50 to P53 (Port 5) .............................................................................................................................52
3.2.5 P60 to P63 (Port 6) .............................................................................................................................52
3.2.6 RESET................................................................................................................................................52
3.2.7 X1, X2 (
µ
PD789104A, 789114A Subseries) .......................................................................................52
3.2.8 CL1, CL2 (
µ
PD789124A, 789134A Subseries)...................................................................................52
3.2.9 AVDD ...................................................................................................................................................52
3.2.10 AVSS ...................................................................................................................................................52
3.2.11 VDD .....................................................................................................................................................52
3.2.12 VSS .....................................................................................................................................................52
3.2.13 VPP (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B only).............................................................53
3.2.14 IC0 (pin No.20) (mask ROM versions only).........................................................................................53
3.2.15 IC0 (pins No.10 and No.21) ................................................................................................................53
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 54
CHAPTER 4 CPU ARCHITECTURE...................................................................................................... 56
4.1 Memory Space .............................................................................................................................. 56
User’s Manual U14643EJ2V0UD 13
4.1.1 Internal program memory space.........................................................................................................60
4.1.2 Internal data memory (internal high-speed RAM) space.....................................................................61
4.1.3 Special-function register (SFR) area...................................................................................................61
4.1.4 Data memory addressing....................................................................................................................61
4.2 Processor Registers .....................................................................................................................65
4.2.1 Control registers .................................................................................................................................65
4.2.2 General-purpose registers..................................................................................................................67
4.2.3 Special-function registers (SFRs).......................................................................................................68
4.3 Instruction Address Addressing .................................................................................................71
4.3.1 Relative addressing ............................................................................................................................71
4.3.2 Immediate addressing.........................................................................................................................72
4.3.3 Table indirect addressing....................................................................................................................73
4.3.4 Register addressing............................................................................................................................73
4.4 Operand Address Addressing.....................................................................................................74
4.4.1 Direct addressing................................................................................................................................74
4.4.2 Short direct addressing.......................................................................................................................75
4.4.3 Special-function register (SFR) addressing ........................................................................................76
4.4.4 Register addressing............................................................................................................................77
4.4.5 Register indirect addressing ...............................................................................................................78
4.4.6 Based addressing...............................................................................................................................79
4.4.7 Stack addressing................................................................................................................................79
CHAPTER 5 PORT FUNCTIONS............................................................................................................80
5.1 Functions of Ports.........................................................................................................................80
5.2 Port Configuration.........................................................................................................................82
5.2.1 Port 0..................................................................................................................................................82
5.2.2 Port 1..................................................................................................................................................83
5.2.3 Port 2..................................................................................................................................................84
5.2.4 Port 5..................................................................................................................................................88
5.2.5 Port 6..................................................................................................................................................89
5.3 Port Function Control Registers..................................................................................................90
5.4 Operation of Port Functions ........................................................................................................93
5.4.1 Writing to I/O port................................................................................................................................93
5.4.2 Reading from I/O port.........................................................................................................................93
5.4.3 Arithmetic operation of I/O port...........................................................................................................94
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)....................................95
6.1 Function of Clock Generator........................................................................................................95
6.2 Configuration of Clock Generator...............................................................................................95
6.3 Register Controlling Clock Generator ........................................................................................96
6.4 System Clock Oscillator...............................................................................................................97
6.4.1 System clock oscillator .......................................................................................................................97
6.4.2 Divider ................................................................................................................................................99
6.5 Operation of Clock Generator....................................................................................................100
6.6 Changing Setting of CPU Clock.................................................................................................101
6.6.1 Time required for switching CPU clock.............................................................................................101
6.6.2 Switching CPU clock.........................................................................................................................101
User’s Manual U14643EJ2V0UD
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CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)................................. 102
7.1 Function of Clock Generator.....................................................................................................102
7.2 Configuration of Clock Generator ............................................................................................ 102
7.3 Register Controlling Clock Generator...................................................................................... 103
7.4 System Clock Oscillator ............................................................................................................ 104
7.4.1 System clock oscillator......................................................................................................................104
7.4.2 Examples of incorrect resonator connection.....................................................................................105
7.4.3 Divider...............................................................................................................................................106
7.5 Operation of Clock Generator................................................................................................... 107
7.6 Changing Setting of CPU Clock................................................................................................ 108
7.6.1 Time required for switching CPU clock .............................................................................................108
7.6.2 Switching CPU clock.........................................................................................................................109
CHAPTER 8 16-BIT TIMER 20............................................................................................................ 110
8.1 16-Bit Timer 20 Functions.......................................................................................................... 110
8.2 16-Bit Timer 20 Configuration................................................................................................... 111
8.3 Registers Controlling 16-Bit Timer 20......................................................................................113
8.4 16-Bit Timer 20 Operation..........................................................................................................116
8.4.1 Operation as timer interrupt ..............................................................................................................116
8.4.2 Operation as timer output..................................................................................................................118
8.4.3 Capture operation .............................................................................................................................119
8.4.4 16-bit timer counter 20 readout.........................................................................................................120
8.5 Notes on Using 16-Bit Timer 20 ................................................................................................121
8.5.1 Restrictions on rewriting 16-bit compare register 20.........................................................................121
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80............................................................................. 123
9.1 Functions of 8-Bit Timer/Event Counter 80 .............................................................................123
9.2 8-Bit Timer/Event Counter 80 Configuration ........................................................................... 124
9.3 Registers Controlling 8-Bit Timer/Event Counter 80..............................................................126
9.4 Operation of 8-Bit Timer/Event Counter 80..............................................................................128
9.4.1 Operation as interval timer................................................................................................................128
9.4.2 Operation as external event counter.................................................................................................130
9.4.3 Operation as square-wave output.....................................................................................................131
9.4.4 Operation as PWM output.................................................................................................................133
9.5 Notes on Using 8-Bit Timer/Event Counter 80 ........................................................................134
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 136
10.1 Functions of Watchdog Timer................................................................................................... 136
10.2 Configuration of Watchdog Timer ............................................................................................ 137
10.3 Watchdog Timer Control Registers..........................................................................................138
10.4 Operation of Watchdog Timer................................................................................................... 140
10.4.1 Operation as watchdog timer............................................................................................................140
10.4.2 Operation as interval timer................................................................................................................141
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)........................... 142
11.1 8-Bit A/D Converter Functions.................................................................................................. 142
11.2 8-Bit A/D Converter Configuration............................................................................................ 142
11.3 Registers Controlling 8-Bit A/D Converter .............................................................................. 144
User’s Manual U14643EJ2V0UD 15
11.4 8-Bit A/D Converter Operation...................................................................................................146
11.4.1 Basic operation of 8-bit A/D converter ..............................................................................................146
11.4.2 Input voltage and conversion result ..................................................................................................147
11.4.3 Operation mode of 8-bit A/D converter .............................................................................................149
11.5 Notes on Using 8-Bit A/D Converter .........................................................................................150
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)..........................154
12.1 10-Bit A/D Converter Functions.................................................................................................154
12.2 10-Bit A/D Converter Configuration ..........................................................................................154
12.3 Registers Controlling 10-Bit A/D Converter .............................................................................156
12.4 10-Bit A/D Converter Operation.................................................................................................158
12.4.1 Basic operation of 10-bit A/D converter ............................................................................................158
12.4.2 Input voltage and conversion result ..................................................................................................159
12.4.3 Operation mode of 10-bit A/D converter ...........................................................................................161
12.5 Notes on Using 10-Bit A/D Converter .......................................................................................162
CHAPTER 13 SERIAL INTERFACE 20...............................................................................................166
13.1 Functions of Serial Interface 20.................................................................................................166
13.2 Serial Interface 20 Configuration...............................................................................................166
13.3 Serial Interface 20 Control Registers........................................................................................170
13.4 Operation of Serial Interface 20.................................................................................................178
13.4.1 Operation stop mode ........................................................................................................................178
13.4.2 Asynchronous serial interface (UART) mode....................................................................................179
13.4.3 3-wire serial I/O mode.......................................................................................................................192
CHAPTER 14 MULTIPLIER ...................................................................................................................202
14.1 Multiplier Function......................................................................................................................202
14.2 Multiplier Configuration..............................................................................................................202
14.3 Multiplier Control Register.........................................................................................................204
14.4 Multiplier Operation ....................................................................................................................205
CHAPTER 15 INTERRUPT FUNCTIONS.............................................................................................206
15.1 Interrupt Function Types............................................................................................................206
15.2 Interrupt Sources and Configuration........................................................................................207
15.3 Interrupt Function Control Registers........................................................................................209
15.4 Interrupt Servicing Operation ....................................................................................................214
15.4.1 Non-maskable interrupt request acknowledgment operation............................................................214
15.4.2 Maskable interrupt request acknowledgment operation....................................................................216
15.4.3 Multiple interrupt servicing................................................................................................................218
15.4.4 Interrupt request hold........................................................................................................................220
CHAPTER 16 STANDBY FUNCTION...................................................................................................221
16.1 Standby Function and Configuration........................................................................................221
16.1.1 Standby function...............................................................................................................................221
16.1.2 Standby function control register (
µ
PD789104A, 789114A Subseries).............................................222
16.2 Operation of Standby Function .................................................................................................223
16.2.1 HALT mode.......................................................................................................................................223
16.2.2 STOP mode......................................................................................................................................226
User’s Manual U14643EJ2V0UD
16
CHAPTER 17 RESET FUNCTION ....................................................................................................... 229
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B .................................................... 233
18.1 Flash Memory Characteristics ..................................................................................................234
18.1.1 Programming environment................................................................................................................234
18.1.2 Communication mode.......................................................................................................................235
18.1.3 On-board pin processing...................................................................................................................240
18.1.4 Connection when using flash memory writing adapter......................................................................243
CHAPTER 19 MASK OPTION (MASK ROM VERSION)..................................................................247
CHAPTER 20 INSTRUCTION SET ......................................................................................................248
20.1 Operation..................................................................................................................................... 248
20.1.1 Operand identifiers and description methods....................................................................................248
20.1.2 Description of “operation” column .....................................................................................................249
20.1.3 Description of “flag operation” column...............................................................................................249
20.2 Operation List .............................................................................................................................250
20.3 Instructions Listed by Addressing Type.................................................................................. 255
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(EXPANDED-SPECIFICATION PRODUCTS)............................................................... 258
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(CONVENTIONAL-SPECIFICATION PRODUCTS)......................................................271
CHAPTER 23 ELECTRICAL SPECIFICATIONS
(
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))..................................283
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A)) ............................ 294
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1)) .............................................307
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A) ....................................................318
CHAPTER 27 ELECTRICAL SPECIFICATIONS
(
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))....................................................330
CHAPTER 28 ELECTRICAL SPECIFICATIONS
(
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))..................................341
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A)) ............................ 352
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1)) .............................................364
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A) ....................................................375
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES)
(
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))....................................................387
User’s Manual U14643EJ2V0UD 17
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
(
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))...................................390
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A),
78F9136A) .......................................................................................................................393
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2),
78913xA(A2))...................................................................................................................395
CHAPTER 36 PACKAGE DRAWING...................................................................................................397
CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS ...........................................................398
APPENDIX A DEVELOPMENT TOOLS ...............................................................................................400
A.1 Software Package........................................................................................................................402
A.2 Language Processing Software.................................................................................................402
A.3 Control Software .........................................................................................................................403
A.4 Flash Memory Writing Tools......................................................................................................403
A.5 Debugging Tools (Hardware).....................................................................................................404
A.6 Debugging Tools (Software)......................................................................................................405
APPENDIX B NOTES ON TARGET SYSTEM DESIGN....................................................................406
APPENDIX C REGISTER INDEX..........................................................................................................408
C.1 Register Name Index (Alphabetical Order)...............................................................................408
C.2 Register Symbol Index (Alphabetical Order)............................................................................410
APPENDIX D REVISION HISTORY......................................................................................................412
User’s Manual U14643EJ2V0UD
18
LIST OF FIGURES (1/4)
Figure No. Title Page
3-1 Pin I/O Circuits..............................................................................................................................................55
4-1 Memory Map (
µ
PD789101A, 789111A, 789121A, 789131A).......................................................................56
4-2 Memory Map (
µ
PD789102A, 789112A, 789122A, 789132A).......................................................................57
4-3 Memory Map (
µ
PD789104A, 789114A, 789124A, 789134A).......................................................................58
4-4 Memory Map (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B) ..............................................................59
4-5 Data Memory Addressing (
µ
PD789101A, 789111A, 789121A, 789131A)....................................................61
4-6 Data Memory Addressing (
µ
PD789102A, 789112A, 789122A, 789132A)....................................................62
4-7 Data Memory Addressing (
µ
PD789104A, 789114A, 789124A, 789134A)....................................................63
4-8 Data Memory Addressing (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B)...........................................64
4-9 Program Counter Configuration....................................................................................................................65
4-10 Program Status Word Configuration.............................................................................................................65
4-11 Stack Pointer Configuration..........................................................................................................................66
4-12 Data to Be Saved to Stack Memory..............................................................................................................66
4-13 Data to Be Restored from Stack Memory.....................................................................................................66
4-14 General-Purpose Register Configuration......................................................................................................67
5-1 Port Types....................................................................................................................................................80
5-2 Block Diagram of P00 to P03........................................................................................................................82
5-3 Block Diagram of P10 and P11.....................................................................................................................83
5-4 Block Diagram of P20...................................................................................................................................84
5-5 Block Diagram of P21...................................................................................................................................85
5-6 Block Diagram of P22, P23, and P25...........................................................................................................86
5-7 Block Diagram of P24...................................................................................................................................87
5-8 Block Diagram of P50 to P53........................................................................................................................88
5-9 Block Diagram of P60 to P63........................................................................................................................89
5-10 Port Mode Register Format ..........................................................................................................................91
5-11 Format of Pull-up Resistor Option Register 0...............................................................................................91
5-12 Format of Pull-up Resistor Option Register B2.............................................................................................92
6-1 Block Diagram of Clock Generator...............................................................................................................95
6-2 Format of Processor Clock Control Register ................................................................................................96
6-3 External Circuit of System Clock Oscillator...................................................................................................97
6-4 Examples of Incorrect Resonator Connection .............................................................................................98
6-5 Switching CPU Clock..................................................................................................................................101
7-1 Block Diagram of Clock Generator.............................................................................................................102
7-2 Format of Processor Clock Control Register ..............................................................................................103
7-3 External Circuit of System Clock Oscillator.................................................................................................104
7-4 Examples of Incorrect Resonator Connection ...........................................................................................105
7-5 Switching CPU Clock..................................................................................................................................109
8-1 Block Diagram of 16-Bit Timer 20...............................................................................................................111
User’s Manual U14643EJ2V0UD 19
LIST OF FIGURES (2/4)
Figure No. Title Page
8-2 Format of 16-Bit Timer Mode Control Register 20......................................................................................114
8-3 Format of Port Mode Register 2.................................................................................................................115
8-4 Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation.......................................116
8-5 Timing of Timer Interrupt Operation ...........................................................................................................117
8-6 Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation.........................................118
8-7 Timer Output Timing...................................................................................................................................118
8-8 Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation.................................................119
8-9 Capture Operation Timing (Both Edges of CPT20 Pin Are Specified)........................................................119
8-10 16-Bit Timer Counter 20 Readout Timing...................................................................................................120
9-1 Block Diagram of 8-Bit Timer/Event Counter 80.........................................................................................125
9-2 Format of 8-Bit Timer Mode Control Register 80........................................................................................126
9-3 Format of Port Mode Register 2.................................................................................................................127
9-4 Interval Timer Operation Timing.................................................................................................................129
9-5 External Event Counter Operation Timing (with Rising Edge Specified) ....................................................130
9-6 Square-Wave Output Timing......................................................................................................................132
9-7 PWM Output Timing...................................................................................................................................133
9-8 Start Timing of 8-Bit Timer Counter............................................................................................................134
9-9 External Event Counter Operation Timing..................................................................................................134
9-10 Timing After Writing Compare Register During PWM Output.....................................................................135
10-1 Block Diagram of Watchdog Timer.............................................................................................................137
10-2 Format of Timer Clock Select Register 2....................................................................................................138
10-3 Format of Watchdog Timer Mode Register ................................................................................................139
11-1 Block Diagram of 8-Bit A/D Converter........................................................................................................142
11-2 Format of A/D Converter Mode Register 0.................................................................................................144
11-3 Format of Analog Input Channel Specification Register 0..........................................................................145
11-4 Basic Operation of 8-Bit A/D Converter......................................................................................................147
11-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................148
11-6 Software-Started A/D Conversion ..............................................................................................................149
11-7 How to Reduce Current Consumption in Standby Mode............................................................................150
11-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value)..................................151
11-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................151
11-10 Analog Input Pin Treatment........................................................................................................................151
11-11 A/D Conversion End Interrupt Request Generation Timing........................................................................152
11-12 AVDD Pin Treatment ...................................................................................................................................153
12-1 Block Diagram of 10-Bit A/D Converter......................................................................................................154
12-2 Format of A/D Converter Mode Register 0.................................................................................................156
12-3 Format of Analog Input Channel Specification Register 0..........................................................................157
12-4 Basic Operation of 10-Bit A/D Converter....................................................................................................159
12-5 Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160
User’s Manual U14643EJ2V0UD
20
LIST OF FIGURES (3/4)
Figure No. Title Page
12-6 Software-Started A/D Conversion...............................................................................................................161
12-7 How to Reduce Current Consumption in Standby Mode ............................................................................162
12-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value)..................................163
12-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................163
12-10 Analog Input Pin Treatment........................................................................................................................163
12-11 A/D Conversion End Interrupt Request Generation Timing........................................................................164
12-12 AVDD Pin Treatment....................................................................................................................................165
13-1 Block Diagram of Serial Interface 20..........................................................................................................167
13-2 Baud Rate Generator Block Diagram .........................................................................................................168
13-3 Format of Serial Operating Mode Register 20............................................................................................171
13-4 Format of Asynchronous Serial Interface Mode Register 20 .................................................................. ....172
13-5 Format of Asynchronous Serial Interface Status Register 20.....................................................................174
13-6 Format of Baud Rate Generator Control Register 20 .................................................................................175
13-7 Asynchronous Serial Interface Transmit/Receive Data Format..................................................................185
13-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................187
13-9 Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................188
13-10 Receive Error Timing..................................................................................................................................189
13-11 3-Wire Serial I/O Mode Timing ...................................................................................................................195
14-1 Block Diagram of Multiplier.........................................................................................................................203
14-2 Format of Multiplier Control Register 0.......................................................................................................204
14-3 Multiplier Operation Timing.........................................................................................................................205
15-1 Basic Configuration of Interrupt Function....................................................................................................208
15-2 Format of Interrupt Request Flag Register .................................................................................................210
15-3 Format of Interrupt Mask Flag Register......................................................................................................211
15-4 Format of External Interrupt Mode Register 0.............................................................................................212
15-5 Program Status Word Configuration...........................................................................................................213
15-6 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment.....................................215
15-7 Timing of Non-Maskable Interrupt Request Acknowledgment....................................................................215
15-8 Acknowledging Non-Maskable Interrupt Request.......................................................................................215
15-9 Interrupt Acknowledgment Program Algorithm...........................................................................................217
15-10 Interrupt Request Acknowledgment Timing (Example of MOV A,r)............................................................218
15-11 Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated at Last Clock During Instruction Execution) ..........................218
15-12 Example of Multiple Interrupt Servicing ......................................................................................................219
16-1 Format of Oscillation Stabilization Time Select Register ............................................................................222
16-2 Releasing HALT Mode by Interrupt ............................................................................................................224
16-3 Releasing HALT Mode by RESET Input.....................................................................................................225
16-4 Releasing STOP Mode by Interrupt............................................................................................................227
16-5 Releasing STOP Mode by RESET Input ....................................................................................................228
User’s Manual U14643EJ2V0UD 21
LIST OF FIGURES (4/4)
Figure No. Title Page
17-1 Block Diagram of Reset Function...............................................................................................................229
17-2 Reset Timing by RESET Input ...................................................................................................................230
17-3 Reset Timing by Overflow in Watchdog Timer ...........................................................................................230
17-4 Reset Timing by RESET Input in STOP Mode.................................................................................. .........230
18-1 Environment for Writing Program to Flash Memory....................................................................................234
18-2 Communication Mode Selection Format ....................................................................................................236
18-3 Example of Connection with Dedicated Flash Programmer ......................................................................237
18-4 VPP Pin Connection Example......................................................................................................................240
18-5 Signal Conflict (Input Pin of Serial Interface)..............................................................................................241
18-6 Abnormal Operation of Other Device .........................................................................................................241
18-7 Signal Conflict (RESET Pin).......................................................................................................................242
18-8 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch0)...243
18-9 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch1)...244
18-10 Example of Flash Memory Writing Adapter Connection When Using UART Mode....................................245
18-11 Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode......................246
A-1 Development Tools ....................................................................................................................................401
B-1 Distance Between In-Circuit Emulator and Conversion Adapter ................................................................406
B-2 Connection Condition of Target System (NP-H44GB-TQ) .........................................................................407
User’s Manual U14643EJ2V0UD
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LIST OF TABLES (1/2)
Table No. Title Page
1-1 Differences Between Expanded-Specification Products and Conventional-Specification Products..............24
1-2 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................36
2-1 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................48
3-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins...................................................54
4-1 Internal ROM Capacity.................................................................................................................................60
4-2 Vector Table.................................................................................................................................................60
4-3 Special-Function Register List .....................................................................................................................69
5-1 Port Functions ..............................................................................................................................................81
5-2 Configuration of Port.....................................................................................................................................82
5-3 Port Mode Register and Output Latch Settings When Using Alternate Functions ........................................90
6-1 Configuration of Clock Generator.................................................................................................................95
6-2 Maximum Time Required for Switching CPU Clock....................................................................................101
7-1 Configuration of Clock Generator...............................................................................................................102
7-2 Maximum Time Required for Switching CPU Clock....................................................................................108
8-1 Configuration of 16-Bit Timer 20.................................................................................................................111
8-2 Interval Time of 16-Bit Timer 20 .................................................................................................................116
8-3 Settings of Capture Edge............................................................................................................................119
9-1 Interval Time of 8-Bit Timer/Event Counter 80............................................................................................123
9-2 Square-Wave Output Range of 8-Bit Timer/Event Counter 80...................................................................124
9-3 8-Bit Timer/Event Counter 80 Configuration...............................................................................................124
9-4 Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) ..............................128
9-5 Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)..............................................128
9-6 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)......131
9-7 Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation) .....................131
10-1 Program Loop Detection Time of Watchdog Timer.....................................................................................136
10-2 Interval Time...............................................................................................................................................136
10-3 Configuration of Watchdog Timer...............................................................................................................137
10-4 Program Loop Detection Time of Watchdog Timer.....................................................................................140
10-5 Interval Time of Interval Timer....................................................................................................................141
11-1 Configuration of 8-Bit A/D Converter ..........................................................................................................142
12-1 Configuration of 10-Bit A/D Converter ........................................................................................................154
User’s Manual U14643EJ2V0UD 23
LIST OF TABLES (2/2)
Table No. Title Page
13-1 Configuration of Serial Interface 20............................................................................................................166
13-2 Serial Interface 20 Operating Mode Settings..............................................................................................173
13-3 Example of Relationship Between System Clock and Baud Rate..............................................................176
13-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......177
13-5 Example of Relationship Between System Clock and Baud Rate..............................................................184
13-6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......184
13-7 Receive Error Causes................................................................................................................................189
15-1 Interrupt Source List...................................................................................................................................207
15-2 Flags Corresponding to Interrupt Request Signals.....................................................................................209
15-3 Time from Generation of Maskable Interrupt Request to Servicing............................................................216
16-1 HALT Mode Operating Status ....................................................................................................................223
16-2 Operation After Release of HALT Mode.....................................................................................................225
16-3 STOP Mode Operating Status....................................................................................................................226
16-4 Operation After Release of STOP Mode....................................................................................................228
17-1 Hardware Status After Reset .....................................................................................................................231
18-1 Differences Between Flash Memory and Mask ROM Versions..................................................................233
18-2 Communication Mode List (
µ
PD78F9116A, 78F9136A).............................................................................235
18-3 Communication Mode List (
µ
PD78F9116B, 78F9136B).............................................................................235
18-4 Pin Connection List ....................................................................................................................................239
19-1 Selection of Mask Option for Pins ..............................................................................................................247
20-1 Operand Identifiers and Description Methods ............................................................................................248
37-1 Surface Mounting Type Soldering Conditions ...........................................................................................398
User’s Manual U14643EJ2V0UD
24
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES )
1.1 Expanded-Specification Products and Conventional-Specification Products
The expanded-specification products and the conventional-specification products indicate the following products.
Expanded-specification products......... Products other than rankNote 1 K
• Mask ROM products ordered on or later than December 1, 2001
(excluding (A1) and (A2) pro ductsNote 2)
• Flash memory products shipped on or later than January 1, 2002
(excluding (A1), (A2) productsNote 2 and the
µ
PD78F9116A)
Conventional-specification products.....RankNote 1 K products
• Products other than above
Notes 1. The rank is indicated by the letter at the 5th digit from the left in the lot number in the package marking.
Lot number ○ ○ ○ ○ △
2. For (A1) and (A2) products, refer to 1.10 Differences Between Standard Quality Grade Products
and (A), (A1), (A2) Products.
The operating frequency specification differs between the expanded-specification products and the conventional-
specification products as shown in Table 1-1.
Table 1-1. Differences Between Expanded-Specification Products and Conventional-Specification Products
Guaranteed Operating Speed (Operating Frequency) Supply V oltage (VDD)
Conventional-Specification
Products Expanded-Specification
Products
4.5 to 5.5 V 5 MHz (0.4
µ
s) 10 MHz (0.2
µ
s)
3.0 to 5.5 V 5 MHz (0.4
µ
s) 6 MHz (0.33
µ
s)
2.7 to 5.5 V 5 MHz (0.4
µ
s) 5 MHz (0.4
µ
s)
1.8 to 5.5 V 1.25 MHz (1.6
µ
s) 1.25 MHz (1.6
µ
s)
Remark The figures in parentheses in dicate the minimum instruction execution time.
Year code Week code
Rank
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 25
1.2 Features
• ROM and RAM capacities
Item
Part Number
Program Memory Data Memory
(Internal High-Speed RAM)
µ
PD789101A, 789111A, 789101A(A), 789111A(A),
789101A(A1), 789111A(A1), 789101A(A2), 789111A(A2) 2 KB
µ
PD789102A, 789112A, 789102A(A), 789112A(A),
789102A(A1), 789112A(A1), 789102A(A2), 789112A(A2) 4 KB
µ
PD789104A, 789114A, 789104A(A), 789114A(A),
789104A(A1), 789114A(A1), 789104A(A2), 789114A(A2)
Mask ROM
8 KB
µ
PD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1) Flash memory 16 KB
256 bytes
• System clock: Crystal/ceramic oscillation
• Minimum instruction execution times switchable between high speed (0.2
µ
s) and low speed (0.8
µ
s) (system
clock: 10.0 MHzNote)
• 20 I/O ports
• Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
• 8-bit resolution A/D converter: 4 channels (
µ
PD789104A Subseries)
• 10-bit resolution A/D converter: 4 channels (
µ
PD789114A Subser ies)
• 3 timers
• 16-bit timer : 1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
• Multiplier: 8 bits × 8 bits = 16 bits
• Vectored interrupt sources: 10
• Supply voltage
• VDD = 1.8 to 5.5 V (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A))
• VDD = 4.5 to 5.5 V (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2), 78F9116B(A1))
• Operating ambient temperature
• TA = −40 to + 85°C (
µ
PD78910xA, 78911xA, 78910xA(A), 7891 1xA(A), 78F9116A, 78F9116B, 78F9116B(A))
• TA = −40 to +105°C (
µ
PD78F9116B(A1))
• TA = −40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1))
• TA = −40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2))
Note When VDD = 4.5 to 5.5 V and for expanded-specification products only
1.3 Applications
Vacuum cleaners, washing machines, refri gerators, battery chargers, etc.
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
26
1.4 Ordering Information
Part Number Package Inter nal ROM
µ
PD789101AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789102AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789104AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789111AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789112AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789114AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9116AMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD78F9116BMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789101AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789102AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789104AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789111AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789112AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789114AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9116BMC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789101AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789102AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789104AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789111AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789112AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789114AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9116BMC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789101AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789102AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789104AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789111AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789112AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789114AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
Remark ××× indicates ROM code suffix.
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 27
1.5 Quality Grade
Part Number Package Quality Grade
µ
PD789101AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789102AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789104AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789111AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789112AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789114AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F9116AMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F9116BMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789101AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789102AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789104AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789111AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789112AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789114AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F9116BMC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789101AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789102AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789104AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789111AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789112AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789114AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F9116BMC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789101AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789102AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789104AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789111AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789112AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789114AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
28
1.6 Pin Configuration (Top View)
• 30-pin plastic SSOP (7.62 mm (300))
µ
PD789101AMC-×××-5A4
µ
PD789102AMC-×××-5A4
µ
PD789104AMC-×××-5A4
µ
PD789111AMC-×××-5A4
µ
PD789112AMC-×××-5A4
µ
PD789114AMC-×××-5A4
µ
PD78F9116AMC-5A4
µ
PD78F9116BMC-5A4
µ
PD789101AMC(A)-×××-5A4
µ
PD789102AMC(A)-×××-5A4
µ
PD789104AMC(A)-×××-5A4
µ
PD789111AMC(A)-×××-5A4
µ
PD789112AMC(A)-×××-5A4
µ
PD789114AMC(A)-×××-5A4
µ
PD78F9116BMC(A)-5A4
µ
PD789101AMC(A1)-×××-5A4
µ
PD789102AMC(A1)-×××-5A4
µ
PD789104AMC(A1)-×××-5A4
µ
PD789111AMC(A1)-×××-5A4
µ
PD789112AMC(A1)-×××-5A4
µ
PD789114AMC(A1)-×××-5A4
µ
PD78F9116BMC(A1)-5A4
µ
PD789101AMC(A2)-×××-5A4
µ
PD789102AMC(A2)-×××-5A4
µ
PD789104AMC(A2)-×××-5A4
µ
PD789111AMC(A2)-×××-5A4
µ
PD789112AMC(A2)-×××-5A4
µ
PD789114AMC(A2)-×××-5A4
P23/INTP0/CPT20/SS20
P24/INTP1/TO80/TO20
P25/INTP2/TI80
AVDD
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
AVSS
P50
IC0
P51
P52
P53
P00
28
27
26
30
29
25
24
23
22
21
20
19
18
16
P22/SI20/RXD20
P21/SO20/TXD20
P20/SCK20/ASCK20
P11
P10
VDD
VSS
X1
X2
IC0 (VPP)
IC0
RESET
P03
P02
P01
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
Remark The pin connection in parentheses is intended for the
µ
PD78F9116A, 78F9116B, 78F9116B(A), and
78F9116B(A1).
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 29
ANI0 to ANI3: Analog input RxD20: Receive data
ASCK20: Asynchronous serial input SCK20: Serial clock
AVDD: Analog power supply SI20: Serial input
AVSS: Analog ground SO20: Serial output
CPT20: Capture trigger input SS20: Chip select input
IC0: Internally connected TI80: Timer input
INTP0 to INTP2: External interrupt input TO20, TO80: Timer output
P00 to P03: Port 0 TxD20: Transmit data
P10, P11: Port 1 VDD: Power supply
P20 to P25: Port 2 VPP: Programming power supply
P50 to P53: Port 5 VSS: Ground
P60 to P63: Port 6 X1, X2: Crystal 1, 2
RESET: Reset
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
30
1.7 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
52-pin
52-pin
SIO and resistance division type LCD (24
×
4)
8-bit A/D and on-chip voltage booster type LCD (23
×
4)
PD789327
PD789467
PD789446
PD789436
PD789426
PD789306
PD789316
PD789426 with enhanced A/D converter (10 bits)
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15
×
4)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5
×
4)
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24
×
4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789407A
PD789456
LCD drive
80-pin PD789417A PD789407A with enhanced A/D converter (10 bits)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28
×
4)
80-pin
SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
80-pin PD789478
PD789488
PD789881
64-pin UART and resistance division type LCD (26
×
4)
Products under development
Products in mass production
PD789014
Small-scale package, general-purpose applications
78K/0S
Series
28-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
PD789146
PD789156
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
PD789104A with added EEPROM
PD789146 with enhanced A/D converter (10 bits)
PD789177Y
PD789167Y
Y Subseries products support SMB.
88-pin PD789830
PD789835
144-pin
UART and dot LCD (40
×
16)
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
42-/44-pin
44-pin
PD789074
30-pin PD789026 with enhanced timer
30-pin PD789074 with enhanced timer and increased ROM, RAM capacity
PD789088
PD789046
PD789026
USB
44-pin PD789800 For PC keyboard and on-chip USB function
Inverter control
44-pin PD789842 On-chip inverter controller and UART
VFD drive
52-pin PD789871 On-chip VFD controller (Total display output pins: 25)
Keyless entry
20-pin PD789860
PD789861
20-pin
On-chip POC and key return circuit
RC oscillation version of the PD789860
On-chip bus controller
PD789850A On-chip CAN controller
Meter control
PD789052
20-pin PD789860 without EEPROM
TM
, POC, and LVI
PD789062
20-pin RC oscillation version of the PD789052
PD789862
30-pin
30-pin
44-pin
PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
PD789852 PD789850A with enhanced functions such as timer and A/D converter
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 31
The major functional differences betwe en the subseries are listed below.
Series for general-purpose applications and LCD drive
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D 10-Bit
A/D Serial
Interface I/O
MIN.
Value
Remarks
µ
PD789046 16 KB 1 ch
µ
PD789026 4 KB to 16 KB
1 ch 34
µ
PD789088 16 KB to
32 KB 3 ch
µ
PD789074 2 KB to 8 KB 1 ch
1 ch
24
µ
PD789014 2 KB to 4 KB
1 ch
(UART: 1 ch)
22
−
µ
PD789062 RC oscillation
version
Small-scale
package,
general-
purpose
applications
µ
PD789052
4 KB
2 ch −
−
1 ch − −
− 14
1.8 V
−
µ
PD789177 − 8 ch
µ
PD789167
16 KB to
24 KB 3 ch 1 ch
8 ch −
31 −
µ
PD789156 − 4 ch
µ
PD789146
8 KB to 16 KB
4 ch −
On-chip
EEPROM
µ
PD789134A − 4 ch
µ
PD789124A 4 ch −
RC oscillation
version
µ
PD789114A − 4 ch
Small-scale
package,
general-
purpose
applications
and A/D
converter
µ
PD789104A
2 KB to 8 KB
1 ch
1 ch
−
1 ch
4 ch −
1 ch
(UART: 1 ch)
20
1.8 V
−
µ
PD789835 24 KB to
60 KB 6 ch − 3 ch 37 1.8 VNote
µ
PD789830 24 KB 1 ch
− 1 ch
(UART: 1 ch)
30 2.7 V
Dot LCD
supported
µ
PD789488 32 KB to
48 KB
−
8 ch
µ
PD789478 24 KB to
48 KB 8 ch −
2 ch
(UART: 1 ch) 45
µ
PD789417A − 7 ch
µ
PD789407A
12 KB to
24 KB
3 ch
7 ch −
43
µ
PD789456 − 6 ch
µ
PD789446 6 ch −
30
µ
PD789436 − 6 ch
µ
PD789426
12 KB to
16 KB
6 ch
1 ch
(UART: 1 ch)
40
−
µ
PD789316 RC oscillation
version
µ
PD789306
8 KB to 16 KB
1 ch
− 2 ch
(UART: 1 ch) 23
µ
PD789467 1 ch − 18
LCD drive
µ
PD789327
4 KB to 24 KB
2 ch
−
1 ch 1 ch
−
−
1 ch 21
1.8 V
−
Note Flash memory version: 3.0 V
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
32
Series for ASSP
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D 10-Bit
A/D Serial
Interface I/O
MIN.
Value
Remarks
USB
µ
PD789800
8 KB 2 ch − − 1 ch − − 2 ch
(USB: 1 ch) 31 4.0 V −
Inverter
control
µ
PD789842
8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch
(UART: 1 ch) 30 4.0 V −
µ
PD789852
24 KB to
32 KB 3 ch − 8 ch 3 ch
(UART: 2 ch) 31 On-chip bus
controller
µ
PD789850A
16 KB 1 ch
1 ch − 1 ch
4 ch − 2 ch
(UART: 1 ch) 18
4.0 V −
µ
PD789861
RC oscillation
version, on-
chip EEPROM
µ
PD789860
4 KB 2 ch − − 14 Keyless
entry
µ
PD789862
16 KB 1 ch 2 ch
− 1 ch − −
1 ch
(UART: 1 ch) 22
1.8 V
On-chip
EEPROM
VFD drive
µ
PD789871
4 KB to 8 KB 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −
Meter
control
µ
PD789881
16 KB 2 ch 1 ch − 1 ch − − 1 ch
(UART: 1 ch) 28 2.7 VNote 2 −
Notes 1. 10-bit timer: 1 channel
2. Flash memor y version: 3.0 V
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 33
1.8 Block Diagram
78K/0S
CPU core
ROM
(flash
memory)
RAM
V
DD
V
SS
IC0
(V
PP
)
TI80/INTP2/P25 8-bit timer/
event counter 80
TO80/TO20
/INTP1/P24
P00 to P03
Port 0
P10, P11
Port 1
P20 to P25
Port 2
P50 to P53
Port 5
P60 to P63
Port 6
System control
TO20/TO80
/INTP1/P24
CPT20/INTP0
/SS20/P23
16-bit timer 20
Watchdog timer
Serial
interface 20
SCK20/ASCK20
/P20
SI20/RxD20/P22
SO20/TxD20/P21
SS20/INTP0
/CPT20/P23
A/D converter
ANI0/P60 to
ANI3/P63
AV
DD
AVSS
RESET
X1
X2
Interrupt control
INTP0/CPT20
/P23/SS20
INTP1/TO80
/TO20/P24
INTP2/TI80/P25
Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the
µ
PD78F9116A, 78F9116B, 78F9116B(A), and 78F9116B(A1).
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
34
1.9 Outline of Functions
Item
µ
PD789101A, 789111A,
789101A(A), 789111A(A),
789101A(A1), 789111A(A1),
789101A(A2), 789111A(A2)
µ
PD789102A, 789112A,
789102A (A), 789112A(A),
789102A (A1), 789112A(A1),
789102A(A2), 789112A(A2)
µ
PD789104A, 789114A,
789104A (A ), 789114A(A),
789104A(A1), 789114A(A1),
789104A (A2), 789114 A(A2)
µ
PD78F9116A, 78F9116B,
78F9116B(A),
78F9116B(A1)
Mask ROM Flash memory ROM
2 KB 4 KB 8 KB 16 KB
Internal memory
High-speed RAM 256 bytes
System clock Crystal/ceramic oscillation
Minimum instruction execution time Expanded-specification products of the
µ
PD78910xA, 78910xA(A), 78911xA,
78911xA(A), 78F9116B, 78F9116B(A)
• 0.2
µ
s/0.8
µ
s (@ system clock: 10.0 MHz operation, VDD = 4.5 to 5.5 V)
Other
• 0.4
µ
s/1.6
µ
s (@ system clock: 5.0 MHz operation)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 20
• CMOS input: 4
• CMOS I/O: 12
• N-ch open-drain: 4
A/D converter 8-bit resolution × 4 channels (
µ
PD789104A Subseries)
10-bit resolution × 4 channels (
µ
PD789114A Subseries)
Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel
Timer 16-bit timer: 1 channel
8-bit timer/event counter: 1 channel
Watchdog timer: 1 channel
Timer outputs One output
Maskable Internal: 6, External: 3 Vectored
interrupts Non-maskable Internal: 1
Supply voltage VDD = 1.8 to 5.5 V (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A,
78F9116B, 78F9116B(A))
VDD = 4.5 to 5.5 V (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2),
78F9116B(A1))
Operating ambient temperature TA = −40 to +85°C (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A,
78F9116B, 78F9116B(A))
TA = −40 to +105°C (
µ
PD78F9116B(A1))
TA = −40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1))
TA = −40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2))
Package 30-pin plastic SSOP (7.62 mm (300))
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 35
An outline of the timers is shown below.
16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer
Interval timer − 1 channel 1 channelNote Operating
Mode External event timer − 1 channel −
Timer output 1 output 1 output −
PWM output − 1 output −
Square-wave output − 1 output −
Capture 1 input − −
Function
Interrupt sources 1 1 1
Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the
two functions can be used at a time.
CHAPTER 1 GENERAL (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
36
1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
The standard quality grade products and the (A), (A1), and (A2) products refer to the following products.
[Standard quality grade products]...
µ
PD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116A,
78F9116B
[(A) products]....
µ
PD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A)
[(A1) products]....
µ
PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1),
78F9116B(A1)
[(A2) products]....
µ
PD789101A(A2), 789102A(A 2), 789104A(A2), 789111A(A2), 789112A( A 2), 789114A(A2)
The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in
Table 1-2.
Table 1-2. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
Products
Item
Standard Quality Grade
Products (A) Products (A1) Products (A2) Products
Quality grade Standard Special
Supply voltage VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V
Operating
ambient
temperature
TA = −40 to +85°C •
µ
PD78F9116B(A1)
TA = −40 to +105°C
• Other than
µ
PD78F9116B(A1)
TA = −40 to +110°C
TA = −40 to +125°C
Minimum
instruction
execution time
Expanded-specification productsNote:
0.2
µ
s (@ 10.0 MHz operation)
Conventional-specification productsNote:
0.4
µ
s (@ 5.0 MHz operation)
0.4
µ
s (@ 5.0 MHz operation)
Electrical
specifications Refer to the relevant electrical specifications chapter.
Note Refer to 1.1 Expanded-Specification Products and Conventional-Specification Products.
User’s Manual U14643EJ2V0UD 37
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES )
Caution All
µ
PD789124A, 789134A Subseries products are conventional-specification products. No
expanded-specification products are available in the
µ
PD789124A, 789134A Subseries.
2.1 Features
• ROM and RAM capacities
Item
Part Number
Program Memory Data Memory
(Internal High-Speed RAM)
µ
PD789121A, 789131A, 789121A(A), 789131A(A),
789121A(A1), 789131A(A1), 789121A(A2), 789131A(A2) 2 KB
µ
PD789122A, 789132A, 789122A(A), 789132A(A),
789122A(A1), 789132A(A1), 789122A(A2), 789132A(A2) 4 KB
µ
PD789124A, 789134A, 789124A(A), 789134A(A),
789124A(A1), 789134A(A1), 789124A(A2), 789134A(A2)
Mask ROM
8 KB
µ
PD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1) Flash memory 16 KB
256 bytes
• System clock: RC oscillation
• Minimum instruction execution times switchable between high speed (0.5
µ
s) and low speed (2.0
µ
s) (system
clock: 4.0 MHz)
• 20 I/O ports
• Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
• 8-bit resolution A/D converter: 4 channels (
µ
PD789124A Subseries)
• 10-bit resolution A/D converter: 4 channels (
µ
PD789134A Subser ies)
• 3 timers
• 16-bit timer : 1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
• Multiplier: 8 bits × 8 bits = 16 bits
• Vectored interrupt sources: 10
• Supply voltage
• VDD = 1.8 to 5.5 V (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A))
• VDD = 4.5 to 5.5 V (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2), 78F9136B(A1))
• Operating ambient temperature
• TA = −40 to + 85°C (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A))
• TA = −40 to +105°C (
µ
PD78F9136B(A1))
• TA = −40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1))
• TA = −40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2))
2.2 Applications
Vacuum cleaners, washing machines, refri gerators, battery chargers, etc.
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
38
2.3 Ordering Information
Part Number Package Internal ROM
µ
PD789121AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789122AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789124AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789131AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789132AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789134AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9136AMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD78F9136BMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789121AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789122AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789124AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789131AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789132AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789134AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9136BMC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789121AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789122AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789124AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789131AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789132AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789134AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD78F9136BMC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD789121AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789122AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789124AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789131AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789132AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
µ
PD789134AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Mask ROM
Remark ××× indicates ROM code suffix.
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 39
2.4 Quality Grade
Part Number Package Quality Grade
µ
PD789121AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789122AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789124AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789131AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789132AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789134AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F9136AMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F9136BMC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD789121AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789122AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789124AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789131AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789132AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789134AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F9136BMC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789121AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789122AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789124AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789131AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789132AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789134AMC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F9136BMC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789121AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789122AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789124AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789131AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789132AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD789134AMC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
40
2.5 Pin Configuration (Top View)
• 30-pin plastic SSOP (7.62 mm (300))
µ
PD789121AMC-×××-5A4
µ
PD789122AMC-×××-5A4
µ
PD789124AMC-×××-5A4
µ
PD789131AMC-×××-5A4
µ
PD789132AMC-×××-5A4
µ
PD789134AMC-×××-5A4
µ
PD78F9136AMC-5A4
µ
PD78F9136BMC-5A4
µ
PD789121AMC(A)-×××-5A4
µ
PD789122AMC(A)-×××-5A4
µ
PD789124AMC(A)-×××-5A4
µ
PD789131AMC(A)-×××-5A4
µ
PD789132AMC(A)-×××-5A4
µ
PD789134AMC(A)-×××-5A4
µ
PD78F9136BMC(A)-5A4
µ
PD789121AMC(A1)-×××-5A4
µ
PD789122AMC(A1)-×××-5A4
µ
PD789124AMC(A1)-×××-5A4
µ
PD789131AMC(A1)-×××-5A4
µ
PD789132AMC(A1)-×××-5A4
µ
PD789134AMC(A1)-×××-5A4
µ
PD78F9136BMC(A1)-5A4
µ
PD789121AMC(A2)-×××-5A4
µ
PD789122AMC(A2)-×××-5A4
µ
PD789124AMC(A2)-×××-5A4
µ
PD789131AMC(A2)-×××-5A4
µ
PD789132AMC(A2)-×××-5A4
µ
PD789134AMC(A2)-×××-5A4
P23/INTP0/CPT20/SS20
P24/INTP1/TO80/TO20
P25/INTP2/TI80
AVDD
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
AVSS
P50
IC0
P51
P52
P53
P00
28
27
26
30
29
25
24
23
22
21
20
19
18
16
P22/SI20/RXD20
P21/SO20/TXD20
P20/SCK20/ASCK20
P11
P10
VDD
VSS
CL1
CL2
IC0 (VPP)
IC0
RESET
P03
P02
P01
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pi n.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
Remark The pin connection in parentheses is intended for the
µ
PD78F9136A, 78F9136B, 78F9136B(A), and
78F9136B(A1).
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 41
ANI0 to ANI3: Analog input RESET: Reset
ASCK20: Asynchronous serial input RxD20: Receive data
AVDD: Analog power supply SCK20: Serial clock
AVSS: Analog ground SI20: Serial input
CL1, CL2: RC oscillator SO20: Serial output
CPT20: Capture trigger input SS20: Chip select input
IC0: Internally connected TI80: Timer input
INTP0 to INTP2: External interrupt input TO20, TO80: Timer output
P00 to P03: Port 0 TxD20: Transmit data
P10, P11: Port 1 VDD: Power supply
P20 to P25: Port 2 VPP: Programming power supply
P50 to P53: Port 5 VSS: Ground
P60 to P63: Port 6
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
42
2.6 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subser ies names.
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
52-pin
52-pin SIO and resistance division type LCD (24
×
4)
8-bit A/D and on-chip voltage booster type LCD (23
×
4)
PD789327
PD789467
PD789446
PD789436
PD789426
PD789306
PD789316
PD789426 with enhanced A/D converter (10 bits)
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15
×
4)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5
×
4)
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24
×
4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789407A
PD789456
LCD drive
80-pin PD789417A PD789407A with enhanced A/D converter (10 bits)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28
×
4)
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
80-pin PD789478
PD789488
PD789881
64-pin UART and resistance division type LCD (26
×
4)
Products under development
Products in mass production
PD789014
Small-scale package, general-purpose applications
78K/0S
Series
28-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
PD789146
PD789156
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
PD789104A with added EEPROM
PD789146 with enhanced A/D converter (10 bits)
PD789177Y
PD789167Y
Y Subseries products support SMB.
88-pin PD789830
PD789835
144-pin UART and dot LCD (40
×
16)
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
42-/44-pin
44-pin
PD789074
30-pin PD789026 with enhanced timer
30-pin PD789074 with enhanced timer and increased ROM, RAM capacity
PD789088
PD789046
PD789026
USB
44-pin PD789800 For PC keyboard and on-chip USB function
Inverter control
44-pin PD789842 On-chip inverter controller and UART
VFD drive
52-pin PD789871 On-chip VFD controller (Total display output pins: 25)
Keyless entry
20-pin PD789860
PD789861
20-pin On-chip POC and key return circuit
RC oscillation version of the PD789860
On-chip bus controller
PD789850A On-chip CAN controller
Meter control
PD789052
20-pin PD789860 without EEPROM, POC, and LVI
PD789062
20-pin RC oscillation version of the PD789052
PD789862
30-pin
30-pin
44-pin
PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
PD789852 PD789850A with enhanced functions such as timer and A/D converter
µ
µµµµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µµ
µµ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 43
The major functional differences betwe en the subseries are listed below.
Series for general-purpose applications and LCD drive
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D 10-Bit
A/D Serial
Interface I/O
MIN.
Value
Remarks
µ
PD789046 16 KB 1 ch
µ
PD789026 4 KB to 16 KB
1 ch 34
µ
PD789088 16 KB to
32 KB 3 ch
µ
PD789074 2 KB to 8 KB 1 ch
1 ch
24
µ
PD789014 2 KB to 4 KB
1 ch
(UART: 1 ch)
22
−
µ
PD789062 RC oscillation
version
Small-scale
package,
general-
purpose
applications
µ
PD789052
4 KB
2 ch −
−
1 ch − −
− 14
1.8 V
−
µ
PD789177 − 8 ch
µ
PD789167
16 KB to
24 KB 3 ch 1 ch
8 ch −
31 −
µ
PD789156 − 4 ch
µ
PD789146
8 KB to 16 KB
4 ch −
On-chip
EEPROM
µ
PD789134A − 4 ch
µ
PD789124A 4 ch −
RC oscillation
version
µ
PD789114A − 4 ch
Small-scale
package,
general-
purpose
applications
and A/D
converter
µ
PD789104A
2 KB to 8 KB
1 ch
1 ch
−
1 ch
4 ch −
1 ch
(UART: 1 ch)
20
1.8 V
−
µ
PD789835 24 KB to
60 KB 6 ch − 3 ch 37 1.8 VNote
µ
PD789830 24 KB 1 ch
− 1 ch
(UART: 1 ch)
30 2.7 V
Dot LCD
supported
µ
PD789488 32 KB to
48 KB
−
8 ch
µ
PD789478 24 KB to
48 KB 8 ch −
2 ch
(UART: 1 ch) 45
µ
PD789417A − 7 ch
µ
PD789407A
12 KB to
24 KB
3 ch
7 ch −
43
µ
PD789456 − 6 ch
µ
PD789446 6 ch −
30
µ
PD789436 − 6 ch
µ
PD789426
12 KB to
16 KB
6 ch
1 ch
(UART: 1 ch)
40
−
µ
PD789316 RC oscillation
version
µ
PD789306
8 KB to 16 KB
1 ch
− 2 ch
(UART: 1 ch) 23
µ
PD789467 1 ch − 18
LCD drive
µ
PD789327
4 KB to 24 KB
2 ch
−
1 ch 1 ch
−
−
1 ch 21
1.8 V
−
Note Flash memory version: 3.0 V
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
44
Series for ASSP
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D 10-Bit
A/D Serial
Interface I/O
MIN.
Value
Remarks
USB
µ
PD789800
8 KB 2 ch − − 1 ch − − 2 ch
(USB: 1 ch) 31 4.0 V −
Inverter
control
µ
PD789842
8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch
(UART: 1 ch) 30 4.0 V −
µ
PD789852
24 KB to
32 KB 3 ch − 8 ch 3 ch
(UART: 2 ch) 31 On-chip bus
controller
µ
PD789850A
16 KB 1 ch
1 ch − 1 ch
4 ch − 2 ch
(UART: 1 ch) 18
4.0 V −
µ
PD789861
RC oscillation
version, on-
chip EEPROM
µ
PD789860
4 KB 2 ch − − 14 Keyless
entry
µ
PD789862
16 KB 1 ch 2 ch
− 1 ch − −
1 ch
(UART: 1 ch) 22
1.8 V
On-chip
EEPROM
VFD drive
µ
PD789871
4 KB to 8 KB 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −
Meter
control
µ
PD789881
16 KB 2 ch 1 ch − 1 ch − − 1 ch
(UART: 1 ch) 28 2.7 VNote 2 −
Notes 1. 10-bit timer: 1 channel
2. Flash memor y version: 3.0 V
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 45
2.7 Block Diagram
78K/0S
CPU core
ROM
(flash
memory)
RAM
TI80/INTP2/P25 8-bit timer/
event counter 80
TO80/TO20
/INTP1/P24
P00 to P03
Port 0
P10, P11
Port 1
P20 to P25
Port 2
P50 to P53
Port 5
P60 to P63
Port 6
System control
TO20/TO80
/INTP1/P24
CPT20/INTP0
/SS20/P23
Watchdog timer
Serial
interface 20
SCK20/ASCK20
/P20
SI20/RxD20/P22
SO20/TxD20/P21
SS20/INTP0
/CPT20/P23
A/D converter
ANI0/P60 to
ANI3/P63
AV
DD
AV
SS
RESET
CL1
CL2
Interrupt control
INTP0/CPT20
/P23/SS20
INTP1/TO80
/TO20/P24
INTP2/TI80/P25
V
DD
V
SS
IC0
(V
PP
)
16-bit timer 20
Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the
µ
PD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1).
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
46
2.8 Outline of Functions
Item
µ
PD789121A, 789131A,
789121A(A), 789131A(A),
789121A(A1), 789131A(A1),
789121A(A2), 789131A(A2)
µ
PD789122A, 789132A,
789122A (A), 789132A(A),
789122A (A1), 789132A(A1),
789122A(A2), 789132A(A2)
µ
PD789124A, 789134A,
789124A (A ), 789134A(A),
789124A(A1), 789134A(A1),
789124A (A2), 789134 A(A2)
µ
PD78F9136A, 78F9136B,
78F9136B(A),
78F9136B(A1)
Mask ROM Flash memory ROM
2 KB 4 KB 8 KB 16 KB
Internal memory
High-speed RAM 256 bytes
System clock RC oscillation
Minimum instruction execution time 0.5/2.0
µ
s (@ system clock: 4.0 MHz operation)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 20
• CMOS input: 4
• CMOS I/O: 12
• N-ch open-drain: 4
A/D converter 8-bit resolution × 4 channels (
µ
PD789124A Subseries)
10-bit resolution × 4 channels (
µ
PD789134A Subseries)
Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel
Timer 16-bit timer: 1 channel
8-bit timer/event counter: 1 channel
Watchdog timer: 1 channel
Timer outputs One output
Maskable Internal: 6, External: 3 Vectored
interrupts Non-maskable Internal: 1
Supply voltage VDD = 1.8 to 5.5 V (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A,
78F9136B, 78F9136B(A))
VDD = 4.5 to 5.5 V (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2),
78F9136B(A1))
Operating ambient temperature TA = −40 to +85°C (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A,
78F9136B, 78F9136B(A))
TA = −40 to +105°C (
µ
PD78F9136B(A1))
TA = −40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1))
TA = −40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2))
Package 30-pin plastic SSOP (7.62 mm (300))
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 47
An outline of the timers is shown below.
16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer
Interval timer − 1 channel 1 channelNote Operating
Mode External event timer − 1 channel −
Timer output 1 output 1 output −
PWM output − 1 output −
Square-wave output − 1 output −
Capture 1 input − −
Function
Interrupt sources 1 1 1
Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the
two functions can be used at a time.
CHAPTER 2 GENERAL (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
48
2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
The standard quality grade products and the (A), (A1), and (A2) products refer to the following products.
[Standard quality grade products]...
µ
PD789121A, 789122A, 789124A, 789131A, 789132A, 789134A, 78F9136A,
78F9136B
[(A) products]....
µ
PD789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A) , 78F9136B(A)
[(A1) products]....
µ
PD789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1),
78F9136B(A1)
[(A2) products]....
µ
PD789121A(A2), 789122A(A 2), 789124A(A2), 789131A(A2), 789132A( A 2), 789134A(A2)
The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in
Table 2-1.
Table 2-1. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
Products
Item
Standard Quality Grade
Products (A) Products (A1) Products (A2) Products
Quality grade Standard Special
Supply voltage VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V
Operating
ambient
temperature
TA = −40 to +85°C •
µ
PD78F9136B(A1)
TA = −40 to +105°C
• Other than
µ
PD78F9136B(A1)
TA = −40 to +110°C
TA = −40 to +125°C
Electrical
specifications Refer to the relevant electrical specifications chapter.
User’s Manual U14643EJ2V0UD 49
CHAPTER 3 PIN FUNCTIONS
3.1 Pin Function List
(1) Port pins
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
Input −
P10, P11 I/O Port 1
2-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
Input −
P20 SCK20/ASCK20
P21 SO20/TxD20
P22 SI20/RxD20
P23 INTP0/CPT20/SS20
P24 INTP1/TO80/TO20
P25
I/O Port 2
6-bit I/O port
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by pull-up
resistor option register B2 (PUB2).
Input
INTP2/TI80
P50 to P53 I/O Port 5
4-bit N-channel open-drain I/O port
Input/output can be specified in 1-bit units.
For a mask ROM version, use of an on-chip pull-up resistor
can be specified by a mask option.
Input −
P60 to P63 Input Port 6
4-bit input-only port Input ANI0 to ANI3
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD
50
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P23/CPT20/SS20
INTP1 P24/TO80/TO20
INTP2
Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified. Input
P25/TI80
SI20 Input Serial data input to serial interface Input P22/RxD20
SO20 Output Serial data output from serial interface Input P21/TxD20
SCK20 I/O Serial clock I/O for serial interface Input P20/ASCK20
ASCK20 Input Serial clock input to asynchronous serial interface Input P20/SCK20
SS20 Input Chip select input to serial interface Input P23/CPT20/INTP0
RxD20 Input Serial data input to asynchronous serial interface Input P22/SI20
TxD20 Output Serial data output from asynchronous serial interface Input P21/SO20
TI80 Input External count clock input to 8-bit timer/event counter 80 Input P25/INTP2
TO80 Output 8-bit timer/event counter 80 output Input P24/INTP1/TO20
TO20 Output 16-bit timer 20 output Input P24/INTP1/TO80
CPT20 Input Capture edge input Input P23/INTP0/SS20
ANI0 to ANI3 Input A/D converter analog input Input P60 to P63
AVSS − A/D converter ground potential − −
AVDD − A/D converter analog power supply − −
X1 Input − −
X2 −
Connecting ceramic resonator/crystal resonator for system
clock oscillation (
µ
PD789104A, 789114A Subseries) − −
CL1 Input − −
CL2 −
Connecting resistor (R) and capacitor (C) for system clock
oscillation (
µ
PD789124A and 789134A Subseries) − −
RESET Input System reset input Input −
VDD − Positive power supply − −
VSS − Ground potential − −
IC0 − Internally connected. Directly connect to the VSS pin. − −
VPP − Sets flash memory programming mode. Applies a high voltage
when a program is written or verified.
− −
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD 51
3.2 Description of Pin Functions
3.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).
3.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).
3.2.3 P20 to P25 (Port 2)
These pins constitute a 6-bit I/O port. In addition, they function as timer I/O, external interrupt inputs, and serial
interface data and clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be specified as input or output mode in 1-bit
units by using port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified in 1-bit units by
using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2).
(2) Control mode
In this mode, P20 to P25 function as timer I/O, external interrupt input, clock I/O of the serial interface and the
data I/O.
(a) TI80
This is the external clock input pin for 8-bit timer/event counter 80.
(b) TO20, TO80
TO20 is the output pin of 16-bit timer 20. TO80 is the output pin of 8-bit timer/event counter 80.
(c) CPT20
This is the input pin of the capture edge.
(d) INTP0 to INTP2
These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising
and falling edges) can be specified.
(e) SI20, SO20
These are the serial data I/O pins of the serial interface.
(f) SCK20
These are the serial clock I/O pins of the serial interface.
(g) SS20
This is the chip select input pin of the serial interface.
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD
52
(h) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
(i) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
Caution When using these pins as serial interface pins, the I/O mode and output latch must be set
according to the function to be used. For details of the setting, refer to Table 13-2 Serial
Interface 20 Operating Mode Settings.
3.2.4 P50 to P53 (Port 5)
These pins constitute a 4-bit N-ch open-drain I/O port and can be specified in input or output mode in 1-bit units by
using port mode register 5 (TM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a
mask option.
3.2.5 P60 to P63 (Port 6)
These pins constitute a 4-bit input-only port. In addition to general-purpose input ports, these pins function as the
A/D converter input pins.
(1) Port mode
In the port mode, these pins function as a 4-bit input-only port.
(2) Control mode
In the control mode, the pins of port 6 can be used as A/D converter analog inputs (ANI0 to ANI3).
3.2.6 RESET
This pin inputs an active-low system reset signal.
3.2.7 X1, X2 (
µ
PD789104A, 789114A Subseries)
These pins are used to connect a ceramic resonator/crystal resonator for system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
3.2.8 CL1, CL2 (
µ
PD789124A, 789134A Subseries)
These are resistor (R) and capacitor (C) connection pins for system clock oscillation.
3.2.9 AVDD
This is the analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even
when the A/D converter is not used.
3.2.10 AVSS
This is the ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even
when the A/D converter is not used.
3.2.11 VDD
This is the positive power supply pin.
3.2.12 VSS
This is the ground pin.
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD 53
3.2.13 VPP (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Connect this pin in either of the following ways.
• Independently connect to a 10 kΩ pull-down resistor.
• By using a jumper on the board, connect dir ectly to the de dicated flash pr ogrammer in the programming mode or
to VSS in the normal operation mode.
If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the user
program may malfuncti on.
3.2.14 IC0 (pin No.20) (mask ROM versions only)
The IC0 (internally connected) pin (No. 20) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration
(Top View)) is used to set the
µ
PD789104A/114A/124A/134A Subseries in the test mode before shipment. In the
nor mal operation mode, connect this pin directly to the VSS pin with as short a wiring length as possible.
If a potential difference is ge nerated between the IC0 pin and VSS pin due to a long wir ing length between the IC 0
pin and V SS pin or external noise superimposed on the IC0 pin, the user program may malfunction.
○ Connect the IC0 pin directly to the VSS pin.
V
SS
IC0 (pin No.20)
Keep short
3.2.15 IC0 (pins No.10 and No.21)
The IC0 pins (No.10 and No.21) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration (Top View)
are inter nally connected.
Connect the IC0 pins directly to VSS.
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD
54
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type for each pin and the recommended connection of pins are shown in Table 3-1.
For the I/O circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00 to P03
P10, P11
5-A
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
Input: Independently connect these pins to VDD or VSS via a
resistor.
Output: Leave open
P23/INTP0/CPT20/SS20
P24/INTP1/TO80/TO20
P25/INTP2/TI80
8-A
Input: Independently connect these pins to VSS via a resistor.
Output: Leave open
P50 to P53
(Mask ROM version) 13-W
P50 to P53
(
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B)
13-V
I/O
Input: Directly connect these pins to VSS.
Output: Leave these pins open at low-level output after setting
the port output latch to 0.
P60/ANI0 to P63/ANI3 9-C Input Directly connect to VDD or VSS.
AVDD Directly connect to VDD.
AVSS
− −
Directly connect to VSS.
RESET 2 Input −
IC0 Directly connect to VSS.
VPP
− −
Independently connect 10 kΩ pull-down resistor to this pin or
connect this pin directly to VSS.
CHAPTER 3 PIN FUNCTIONS
User’s Manual U14643EJ2V0UD 55
Figure 3-1. Pin I/O Circuits
Schmitt-triggered input with hysteresis characteristics
Type 2
IN
Type 5-A
Pull-up
enable
Data
Output
disable
Input
enable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
Type 13-V
V
SS
V
SS
Type 8-A
Pull-up
enable
Data
Output
disable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
V
SS
Type 9-C
IN
Comparator
+
−
V
REF
(Threshold voltage)
AV
SS
P-ch
N-ch
Input
enable
Output data
Output disable
IN/OUT
V
DD
N-ch
Input enable
Pull-up resistor
(mask option)
Type 13-W
V
SS
Output data
Output disable
IN/OUT
N-ch
Middle-voltage input buffer
Middle-voltage input buffer
Input enable
User’s Manual U14643EJ2V0UD
56
CHAPTER 4 CPU ARCHITECTURE
4.1 Memory Space
The
µ
PD789104A/114A/124A/134A Subseries can access 64 KB of memory space. Figures 4-1 to 4-4 show the
memory maps.
Figure 4-1. Memory Map (
µ
PD789101A, 789111A, 789121A, 789131A)
FFFFH
FF00H
FEFFH
FE00H
FDFFH
0800H
07FFH
0000H
07FFH
0000H
0080H
007FH
0040H
003FH
0016H
0015H
Data
memory space
Program
memory space
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
2,048 × 8 bits
Program area
CALLT table area
Program area
Vector table area
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 57
Figure 4-2. Memory Map (
µ
PD789102A, 789112A, 789122A, 789132A)
FFFFH
FF00H
FEFFH
FE00H
FDFFH
1000H
0FFFH
0000H
0FFFH
0000H
0080H
007FH
0040H
003FH
0016H
0015H
Data
memory space
Program
memory space
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
4,096 × 8 bits
Program area
CALLT table area
Program area
Vector table area
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD
58
Figure 4-3. Memory Map (
µ
PD789104A, 789114A, 789124A, 789134A)
FFFFH
FF00H
FEFFH
FE00H
FDFFH
2000H
1FFFH
0000H
1FFFH
0000H
0080H
007FH
0040H
003FH
0016H
0015H
Data
memory space
Program
memory space
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
8,192 × 8 bits
Program area
CALLT table area
Program area
Vector table area
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 59
Figure 4-4. Memory Map (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B)
FFFFH
FF00H
FEFFH
FE00H
FDFFH
4000H
3FFFH
0000H
3FFFH
0000H
0080H
007FH
0040H
003FH
0016H
0015H
Data
memory space
Program
memory space
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Flash memory
16,384 × 8 bits
Program area
CALLT table area
Program area
Vector table area
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD
60
4.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The
µ
PD789104A/114A/124A/134A Subseries provides the following internal ROMs (or flash memory) containing
the following capacities.
Table 4-1. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
µ
PD789101A, 789111A, 789121A, 789131A 2,048 × 8 bits
µ
PD789102A, 789112A, 789122A, 789132A 4,096 × 8 bits
µ
PD789104A, 789114A, 789124A, 789134A
Mask ROM
8,192 × 8 bits
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B Flash memory 16,384 × 8 bits
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 22-byte area of addresses 0000H to 0015H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit
program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 4-2. Vector Table
Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H RESET input 000CH INTSR20/INTCSI20
0004H INTWDT 000EH INTST20
0006H INTP0 0010H INTTM80
0008H INTP1 0012H INTTM20
000AH INTP2 0014H INTAD0
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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User’s Manual U14643EJ2V0UD 61
4.1.2 Internal data memory (internal high-speed RAM) space
The
µ
PD789104A/114A/124A/134A Subseries provides a 256-byte internal high-speed RAM.
The internal high-speed RAM can also be used as a stack memory.
4.1.3 Special-function register (SFR) area
Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH
(refer to Table 4-3).
4.1.4 Data memory addressing
The
µ
PD789104A/114A/124A/134A Subseries provides a variety of addressing modes which take account of
memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH),
particular addressing modes can be used to meet the functions of the special-function registers (SFRs) and general-
purpose registers. Figures 4-5 to 4-8 show the data memory addressing modes.
Figure 4-5. Data Memory Addressing (
µ
PD789101A, 789111A, 789121A, 789131A)
FFFFH
0800H
07FFH
0000H
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
FE00H
FDFFH
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
2,048 × 8 bits
SFR addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
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Figure 4-6. Data Memory Addressing (
µ
PD789102A, 789112A, 789122A, 789132A)
FFFFH
1000H
0FFFH
0000H
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
FE00H
FDFFH
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
4,096 × 8 bits
SFR addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 63
Figure 4-7. Data Memory Addressing (
µ
PD789104A, 789114A, 789124A, 789134A)
FFFFH
2000H
1FFFH
0000H
FE00H
FDFFH
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Internal ROM
8,192 × 8 bits
SFR addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
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User’s Manual U14643EJ2V0UD
64
Figure 4-8. Data Memory Addressing (
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B)
FFFFH
4000H
3FFFH
0000H
FE00H
FDFFH
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Reserved
Flash memory
16,384 × 8 bits
SFR addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 65
4.2 Processor Registers
The
µ
PD789104A/114A/124A/134A Subseries provides the following on-chip processor registers.
4.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 4-9. Program Counter Configuration
015
PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 4-10. Program Status Word Configuration
70
IE Z 0 AC 0 0 1 CY
PSW
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgment operations of CPU.
When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupt requests except non-
maskable interrupts are disabled.
When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment is
controlled by the interrupt mask flag for each interrupt source.
This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(d) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register used t o hold the start address of the memor y stack area. Only the inter n al high-speed
RAM area can be set as the stack area.
Figure 4-11. Stack Pointer Configuration
015
SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of a wr ite (save) to the stack memory and is incremented after a re ad (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 4-12 and 4-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 4-12. Data to Be Saved to Stack Memory
Interrupt
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair
lower
SP SP _ 2
SP _ 2
CALL, CALLT
instructions
PUSH rp
instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Register pair
higher
Figure 4-13. Data to Be Restored from Stack Memory
RETI instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair
lower
RET instructionPOP rp
instruction
SP PC7 to PC0
Register pair
higher
SP + 1
SP SP + 2
SP
SP + 1
SP SP + 2
SP
SP + 1
SP + 2
SP SP + 3
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User’s Manual U14643EJ2V0UD 67
4.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16-bit
register (AX, BC, DE, and HL).
They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 4-14. General-Purpose Register Configuration
(a) Absolute names
R0
15 0 7 0
16-bit processing 8-bit processing
RP3
RP2
RP1
RP0
R1
R2
R3
R4
R5
R6
R7
(b) Functional names
X
15 0 7 0
16-bit processing 8-bit processing
HL
DE
BC
AX
A
C
B
E
D
L
H
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User’s Manual U14643EJ2V0UD
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4.2.3 Special-function registers (SFRs)
Unlike general-purpose registers, special-function registers have their own functions and are allocated to the 256-
byte area FF00H to FFFFH.
Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit
manipulation instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on
the special-function register type.
Each bit unit for manipulation can be specified as follows.
• 1-bit manipulation
A symbol reserved by the assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This
manipulation can also be specified with an address.
• 8-bit manipulation
A symbol reserved by the assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This
manipulation can also be specified with an address.
• 16-bit manipulation
A symbol reserved by the assembler is described as the operand of a 16-bit manipulation instruction. When
specifying an address, describe an even address.
Table 4-3 lists the special-function registers. The meanings of the symbols in this table are as follows.
• Symbol
Indicates the addresses of the implemented special-function register. The symbols shown in this column are the
reserved words of the assembler, and have already been defined in the header file “sfrbit.h” in the C compiler.
Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special-function register in question can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Bit units for manipulation
Indicates the bit units (1, 8, and 16) in which the special-function register in question can be manipulated.
• After reset
Indicates the status of the special-function register when the RESET signal is input.
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User’s Manual U14643EJ2V0UD 69
Table 4-3. Special-Function Register List (1/2)
Bit Units for ManipulationAddress Special-Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF00H Port 0 P0 √ √ −
FF01H Port 1 P1 √ √ −
FF02H Port 2 P2 √ √ −
FF05H Port 5 P5
R/W
√ √ −
FF06H Port 6 P6 √ √ −
00H
FF10H MUL0L
FF11H
16-bit multiplication result storage register 0
MUL0H
MUL0 − √Note 1 √Note 2
FF14H
FF15H
A/D conversion result registerNote 3 ADCR0
R
− √ √Note 2
Undefined
FF16H CR20L
FF17H
16-bit compare register 20
CR20H
CR20 W − √Note 1 √Note 2 FFFFH
FF18H TM20L
FF19H
16-bit timer counter 20
TM20H
TM20 − √Note 1 √Note 2 0000H
FF1AH TCP20L
FF1BH
16-bit capture register 20
TCP20H
TCP20
R
− √Note 1 √Note 2 Undefined
FF20H Port mode register 0 PM0 √ √ −
FF21H Port mode register 1 PM1 √ √ −
FF22H Port mode register 2 PM2 √ √ −
FF25H Port mode register 5 PM5 √ √ −
FFH
FF32H Pull-up resistor option register B2 PUB2 √ √ −
FF42H Time clock select register 2 TCL2 − √ −
FF48H 16-bit timer mode control register 20 TMC20
R/W
√ √ −
FF50H 8-bit compare register 80 CR80 W − √ −
00H
FF51H 8-bit timer counter 80 TM80 R − √ − Undefined
FF53H 8-bit timer mode control register 80 TMC80 R/W √ √ − 00H
Notes 1. Although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units.
Access these registers in 8-bit units by means of direct addressing.
2. These registers can be accessed in 16-bit units only by means of short direct addressing.
3. When this register is used for an 8-bit A/D converter (
µ
PD789104A and 789124A Subseries), it can be
accessed only in 8-bit units. At this time, the register address is FF15H. When this register is used for a
10-bit A/D converter (
µ
PD789114A and 789134A Subseries), it can be accessed only in 16-bit units.
When using the
µ
PD78F9116A and 78F9116B as the flash memory versions of the
µ
PD789101A,
789102A, or 789104A, or when using the
µ
PD78F9136A and 78F9136B as the flash memory versions
of the
µ
PD789121A, 789122A, or 789124A, this register can be accessed in 8-bit units. However, only
the object file assembled with the
µ
PD789101A, 789102A, or 789104A, or object file assembled with the
µ
PD789121A, 789122A, or 789124A can be used.
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User’s Manual U14643EJ2V0UD
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Table 4-3. Special-Function Register List (2/2)
Bit Units for Manipulation Address Special-Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF70H Asynchronous serial interface mode register 20 ASIM20 R/W √ √ −
FF71H Asynchronous serial interface status register 20 ASIS20 R √ √ −
FF72H Serial operating mode register 20 CSIM20 √ √ −
FF73H Baud rate generator control register 20 BRGC20
R/W
− √ −
00H
Transmit shift register 20 TXS20 W − √ − FFH FF74H
Receive buffer register 20 RXB20
SIO20
R − √ − Undefined
FF80H A/D converter mode register 0 ADM0 √ √ −
FF84H Analog input channel specification register 0 ADS0
R/W
√ √ −
00H
FFD0H Multiplication data register A0 MRA0 √ √ −
FFD1H Multiplication data register B0 MRB0
W
√ √ −
Undefined
FFD2H Multiplier control register 0 MULC0 √ √ −
FFE0H Interrupt request flag register 0 IF0 √ √ −
FFE1H Interrupt request flag register 1 IF1 √ √ −
00H
FFE4H Interrupt mask flag register 0 MK0 √ √ −
FFE5H Interrupt mask flag register 1 MK1 √ √ −
FFH
FFECH External interrupt mode register 0 INTM0 − √ −
FFF7H Pull-up resistor option register 0 PU0 √ √ −
FFF9H Watchdog timer mode register WDTM √ √ −
00H
FFFAH Oscillation stabilization time select registerNote OSTS − √ − 04H
FFFBH Processor clock control register PCC
R/W
√ √ − 02H
Note
µ
PD789104A, 789114A Subseries only
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 71
4.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each
time another instr uction is executed. When a branch instruc tion is executed, the branch destination infor mation is set
to the PC and branched by the following addressing (for details of each instruction, refer to the 78K/0S Series
Instructions User’s Manual (U11047E)).
4.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immedi ate data (dis placement value: jdisp8) of an inst ruction code to the start
address of the following instruction is transferred to the program counter (PC) and branched. The displacement
value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit. In other words, the
range of branch in relative addressing is between −128 and +127 of the start address of the following instruction.
This function is carried o ut wh en the BR $addr16 instruction or a conditional b ranch instruction is executed.
[Illustration]
15 0
PC
15 0
S
15 0
PC
+
876
α
jdisp8
When S = 0, α indicates all bits “0”.
... PC is the start address of
the next instruction of
a BR instruction.
When S = 1, α indicates all bits “1”.
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4.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
The CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.
[Illustration]
In case of CALL !addr16, BR !addr16 instruction
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 73
4.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer
to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (Table)
Effective address + 1
Effective address 01
00000000
87
87
65 0
0
111
765 10
ta
4–0
Instruction code
4.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
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74
4.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
4.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 0 0 1 0 1 0 0 1 OP code
0 0 0 0 0 0 0 0 00H
1 1 1 1 1 1 1 0 FEH
[Illustration]
70
OP code
addr16 (low)
addr16 (high)
Memory
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 75
4.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer/event counter are
mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit
8 is set to 1. Refer to [Illustration].
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code 1 1 1 1 0 1 0 1 OP code
1 0 0 1 0 0 0 0 90H (saddr-offset)
0 1 0 1 0 0 0 0 50H (immediate data)
[Illustration]
15 0
Short direct memory
Effective
address 1111111
8
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH, = 0.
When 8-bit immediate data is 00H to 1FH, = 1.
α
α
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4.4.3 Special-function register (SFR) addressing
[Function]
Memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special-function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code 1 1 1 0 0 1 1 1
0 0 1 0 0 0 0 0
[Illustration]
15 0
SFR
Effective
address 1111111
87
07
OP code
sfr-offset
1
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 77
4.4.4 Register addressing
[Function]
General-purpose registers are accessed as operands. The general-purpose register to be accessed is specified
with the register specify code and functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an 8-
bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code 0 0 0 0 1 0 1 0
0 0 1 0 0 1 0 1
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code 1 0 0 0 1 0 0 0
Register specify code
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User’s Manual U14643EJ2V0UD
78
4.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 0 0 1 0 1 0 1 1
[Illustration]
15 08
D
7
E
07
7 0
A
DE
The contents of addressed
memory are transferred
Memory address specified
by register pair DE
CHAPTER 4 CPU ARCHITECTURE
User’s Manual U14643EJ2V0UD 79
4.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code 0 0 1 0 1 1 0 1
0 0 0 1 0 0 0 0
4.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN
instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing can be used to address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code 1 0 1 0 1 0 1 0
User’s Manual U14643EJ2V0UD
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CHAPTER 5 PORT FUNCTIONS
5.1 Functions of Ports
The
µ
PD789104A/114A/124A/134A Subseries provides the ports shown in Figure 5-1, enabling various methods of
control.
Numerous other functions are provided that can be used in addition to the digital I/O port function. For more
information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS.
Figure 5-1. Port Types
Port 5
P50
P53
Port 6
P60
P63
P00
P03
P10
Port 0
Port 1
P11
P20
P25
Port 2
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 81
Table 5-1. Port Functions
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as input port, use of an on-chip pull-up resistor
can be specified by means of pull-up resistor option register 0
(PU0).
Input −
P10, P11 I/O Port 1
2-bit I/O port
Input/output can be specified in 1-bit units.
When used as input port, use of an on-chip pull-up resistor
can be specified by means of pull-up resistor option register 0
(PU0).
Input −
P20 ASCK20/SCK20
P21 TxD20/SO20
P22 RxD20/SI20
P23 INTP0/CPT20/SS20
P24 INTP1/TO80/TO20
P25
I/O Port 2
6-bit I/O port
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by means
of pull-up resistor option register B2 (PUB2).
Input
INTP2/TI80
P50 to P53 I/O Port 5
4-bit N-ch open-drain I/O port
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified for mask
ROM versions by a mask option.
Input −
P60 to 63 Input Port 6
4-bit input-only port
Input ANI0 to ANI3
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
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5.2 Port Configuration
A port consists of the following hardware.
Table 5-2. Configuration of Port
Item Configuration
Control register Port mode register (PM0 to PM2, PM5)
Pull-up resistor option register 0 (PU0)
Pull-up option register B2 (PUB2)
Port Total: 20 (input: 4, I/O: 16)
Pull-up resistor • Mask ROM versions
Total: 16 (software control: 12, mask option specification: 4)
• Flash memory versions
Total: 12 (software control only)
5.2.1 Port 0
This is a 4-bit I/O port with output latches. Port 0 can be set to input or output mode in 1-bit units by using port
mode register 0 (PM0). When pins P00 to P03 ar e use d as inp ut port pi ns, on-chip pu ll-up resistors c an be co nnect ed
in 4-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 0 to input mode.
Figure 5-2 shows the block diagram of port 0.
Figure 5-2. Block Diagram of P00 to P03
Internal bus
WR
PU0
RD
WR
PORT
WR
PM
PU00
Output latch
(P00 to P03)
PM00 to PM03
V
DD
P-ch
P00 to P03
Selector
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 83
5.2.2 Port 1
This is a 2-bit I/O port with output latches. Port 1 can be set to input or output mode in 1-bit units by using port
mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be
connected in 2-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 1 to input mode.
Figure 5-3 shows the block diagram of port 1.
Figure 5-3. Block Diagram of P10 and P11
Internal bus
WR
PU0
RD
WR
PORT
WR
PM
PU01
Output latch
(P10, P11)
PM10, PM11
V
DD
P-ch
P10, P11
Selector
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
84
5.2.3 Port 2
This is a 6-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port
mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using
pull-up resistor option register B2 (PUB2).
The port is also used as the serial interface data I/O, clock I/O, timer I/O, and external interrupt input.
RESET input sets port 2 to input mode.
Figures 5-4 to 5-7 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 13-2 Serial Interface
20 Operating Mode Settings.
Figure 5-4. Block Diagram of P20
Internal bus
VDD
P-ch
P20/ASCK20/
SCK20
WRPUB2
RD
WRPORT
WRPM
PUB20
Alternate
function
Output latch
(P20)
PM20
Alternate
function
Selector
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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User’s Manual U14643EJ2V0UD 85
Figure 5-5. Block Diagram of P21
Internal bus
VDD
P-ch
P21/TxD20/
SO20
WRPUB2
RD
WRPORT
WRPM
PUB21
Output latch
(P21)
PM21
Alternate
function
Selector
Serial output
enable signal
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
86
Figure 5-6. Block Diagram of P22, P23, and P25
Internal bus
VDD
P-ch
P22/RxD20/SI20
P23/INTP0/CPT20/
SS20
P25/INTP2/TI80
WRPUB2
RD
WRPORT
WRPM
PUB22, PUB23,
PUB25
Alternate
function
Output latch
(P22, P23, P25)
PM22, PM23,
PM25
Selector
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 87
Figure 5-7. Block Diagram of P24
WR
PUB2
Selector
RD
PM24
PUB24
Alternate
function
Alternate
function
P24/INTP1/
TO80/TO20
P-ch
WR
PORT
Output latch
(P24)
WR
PM
Internal bus
Alternate
function
V
DD
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
88
5.2.4 Port 5
This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be set to input or output mode in 1-bit units
by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be
specified by a mask option.
RESET input sets port 5 to input mode.
Figure 5-8 shows a block diagram of port 5.
Figure 5-8. Block Diagram of P50 to P53
Internal bus
Selector
RD
PM50 to PM53
P50 to P53
N-ch
WR
PORT
Output latch
(P50 to P53)
WR
PM
V
DD
Mask option resistor
Mask ROM versions only.
For flash memory versions,
a pull-up resistor is not
incorporated.
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
Caution When using port 5 of the
µ
PD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.
<1> When VDD = 1.8 to 5.5 V
Use within the range of TA = 25 to 85°C
<2> When TA = −40 to +85°C
Use within the range of VDD = 2.7 to 5.5 V
<3> When TA = −40 to +85°C and VDD = 1.8 to 5.5 V
Issue three consecutive read instructions when reading port 5.
If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these restrictions do not apply when port 5 pins are used as output pins, or
when the product is other than
µ
PD78F9116A or 78F9136A.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 89
5.2.5 Port 6
This is a 4-bit input port.
The port is also used for analog input to the A/D converter.
RESET input sets port 6 to input mode.
Figure 5-9 shows a block diagram of port 6.
Figure 5-9. Block Diagram of P60 to P63
Internal bus
VREF
RD
A/D converter
P60/ANI0 to P63/ANI3
+
−
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
90
5.3 Port Function Control Registers
The following three types of registers control the ports.
• Port mode registers (PM0 to PM2, PM5)
• Pull-up resistor option register 0 (PU0)
• Pull-up resistor option register B2 (PUB2)
(1) Port mode registers (PM0 to PM2, PM5)
These registers are used to set port I/O in 1-bit units.
Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 5-3.
Caution As port 2 has an alternate function as external interrupt input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. When the
output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions
Alternate Function Pin Name
Name I/O
PM×× P××
INTP0 Input 1
×
P23
CPT20 Input 1
×
INTP1 Input 1
×
TO80 Output 0 0
P24
TO20 Output 0 0
INTP2 Input 1
×
P25
TI80 Input 1
×
Caution When Port 2 is used for serial interface pins, the I/O latch or output latch must be set according
to its function. For the setting method, refer to Table 13-2 Serial Interface 20 Operating Mode
Settings.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 91
Figure 5-10. Port Mode Register Format
PMmn
0 Output mode (output buffer on)
Input mode (output buffer off) 1
1
1
1
1
1
1
1
1
1
1
PM25
1
1
1
PM24
1
PM03
1
PM23
PM53
PM02
1
PM22
PM52
PM01
PM11
PM21
PM51
PM00
PM10
PM20
PM50
PM0
PM1
PM2
PM5
7
Symbol Address After reset
6543210 R/W
FF20H
FF21H
FF22H
FF25H
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7)
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether to use on-chip pull-up resistors at each port or not.
At a port where use of on-chip pull-up resistors has been specified by PU0, the pull-up resistors can be
internally used only for the bits set in input mode. No on-chip pull-up resistors can be used for the bits set in
output mode, in spite of the setting of PU0. On-chip pull-up resistors can also not be used when the pins are
used as the alternate-function output pins.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 5-11. Format of Pull-up Resistor Option Register 0
PU0m
0
1
000000PU01 PU00PU0
Symbol Address
Pm on-chip pull-up resistor selection (m = 0, 1)
On-chip pull-up resistor not used
On-chip pull-up resistor used
After reset
7654 R/W
FFF7H 00H R/W
3 2 <1> <0>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
92
(3) Pull-up resistor option register B2 (PUB2)
This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. A pin so specified
by PUB2 is connected to an on-chip pull-up resistor regardless of the setting of the port mode register.
PUB2 is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets this register to 00H.
Figure 5-12. Format of Pull-up Resistor Option Register B2
PUB2n
0
1
00
PUB25 PUB24 PUB23 PUB22 PUB21 PUB20
PUB2
Symbol Address
P2n on-chip pull-up resistor selection (n = 0 to 5)
On-chip pull-up resistor not used
On-chip pull-up resistor used
After reset
7 6 <5> <4> R/W
FF32H 00H R/W
<3> <2> <1> <0>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD 93
5.4 Operation of Port Functions
The operation of a port differs depending on whether the port is set in input or output mode, as described below.
5.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is
not changed because the output buffer is off.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set
in the input mode and not subject to manipulation become undefined.
5.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch
are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
Caution When using port 5 of
µ
PD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.
<1> When VDD = 1.8 to 5.5 V
Use within the range of TA = 25 to 85°C
<2> When TA = −40 to +85°C
Use within the range of VDD = 2.7 to 5.5 V
<3> When TA = −40 to +85°C and VDD = 1.8 to 5.5 V
Issue three consecutive read instructions when reading port 5.
If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these restrictions do not apply when port 5 pins are used as output pins,
or when the product is other than
µ
PD78F9116A or 78F9136A.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U14643EJ2V0UD
94
5.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed on the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because the
output buffer is off.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set
in the input mode and not subject to manipulation become undefined.
User’s Manual U14643EJ2V0UD 95
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
6.1 Function of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. Oscillation is stopped
by executing the STOP instruction.
The system clock oscillator is as follows.
• System clock (crystal/ceramic) oscillator
<Expanded-specification products>
This circuit oscillates a clock at a frequency of 1.0 to 10.0 MHz.
<Conventional-specification products>
This circuit oscillates a clock at a frequency of 1.0 to 5.0 MHz.
6.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 6-1. Configuration of Clock Generator
Item Configuration
Control register Processor clock control register (PCC)
Oscillator Crystal/ceramic oscillator
Figure 6-1. Block Diagram of Clock Generator
f
X
Prescaler
System clock
oscillator
2
2
f
X
Selector
PCC1
Internal bus
Processor clock control register (PCC)
Prescaler
Standby
controller
Wait
controller CPU clock (f
CPU
)
Clock to peripheral
hardware
STOP
X1
X2
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
96
6.3 Register Controlling Clock Generator
The clock generator is controlled by the following register.
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC sets the CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 6-2. Format of Processor Clock Control Register
000000PCC1 0PCC
Symbol Address After reset R/W
FFFBH 02H R/W
76543210
PCC1 CPU clock (f
CPU
) selection
0
1
f
X
f
X
/2
2
0.2 s
0.8 s
µ
µ
0.4 s
1.6 s
µ
µ
Minimum instruction execution time: 2/f
CPU
@ f
X
= 10.0 MHz
Note
operation @ f
X
= 5.0 MHz operation
Note Expanded-specification products only
Caution Bit 0 and bits 2 to 7 must be set to 0.
Remark f
X: System clock oscillation frequency
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 97
6.4 System Clock Oscillator
6.4.1 System clock oscillator
The system clock oscillator is oscillated by the crystal or ceramic resonator connected across the X1 and X2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1 pin,
and leave the X2 pin open.
Figure 6-3 shows the external circuit of the system clock oscillator.
Figure 6-3. External Circuit of System Clock Oscillator
(a) Crystal or ceramic oscillation (b) External clock
VSS
X1
X2
Crystal
or
ceramic resonator
External
clock X1
X2
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Figure 6-4 shows examples of incorrect resonator connection.
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
98
Figure 6-4. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
VSS X1 X2 VSS X1 X2
PORTn
(n = 0 to 2, 5, 6)
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 99
Figure 6-4. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VSS X1 X2
High current
VSS X1
AB C
Pmn
VDD
High current
X2
(e) Signal is fetched
VSS X1 X2
6.4.2 Divider
The divider divides the output of the system clock oscillator (fX) to generate various clocks.
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD
100
6.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode.
• System clock fX
• CPU clock fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), as follows.
(a) The slow mode (0.8
µ
s: at 10.0 MHz operation, 1.6
µ
s: at 5.0 MHz operation) of the system clock is
selected when the RESET signal is generated (PCC = 02H). While a low level is being input to the RESET
pin, oscillation of the system clock is stopped.
(b) Two types of minimum instruction execution time (0.2
µ
s and 0.8
µ
s: at 10.0 MHz operation, 0.4
µ
s and 1.6
µ
s: at 5.0 MHz operation) can be selected by setting the PCC register.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except the external clock input operation).
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104A, 789114A SUBSERIES)
User’s Manual U14643EJ2V0UD 101
6.6 Changing Setting of CPU Clock
6.6.1 Time required for switching CPU clock
The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is
used for the duration of several instructions after that (refer to Table 6-2).
Table 6-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching Set Value After Switching
PCC1 PCC1 PCC1
0 1
0 4 clocks
1 2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
6.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 6-5. Switching CPU Clock
V
DD
RESET
CPU clock
Slow
operation
Fastest
operation
Wait (3.28 ms: at 10.0 MHz operation,
6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (8.0
µ
s: at 10.0 MHz
operation, 1.6
µ
s: at 5.0 MHz operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
User’s Manual U14643EJ2V0UD
102
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
7.1 Function of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock
oscillator is as follows.
• System clock (RC) oscillator
This circuit oscillates a clock at a frequency of 2.0 to 4.0 MHz. Oscillation can be stopped by executing the
STOP instruction.
7.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 7-1. Configuration of Clock Generator
Item Configuration
Control register Processor clock control register (PCC)
Oscillator RC oscillator
Figure 7-1. Block Diagram of Clock Generator
f
CC
Prescaler
System clock
oscillator
2
2
f
CC
Selector
PCC1
Internal bus
Processor clock control register (PCC)
Prescaler
Standby
controller
Wait
controller CPU clock (f
CPU
)
Clock to peripheral
hardware
STOP
CL1
CL2
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 103
7.3 Register Controlling Clock Generator
The clock generator is controlled by the following register.
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC sets the CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 02H.
Figure 7-2. Format of Processor Clock Control Register
000000PCC1 0PCC
Symbol Address After reset R/W
FFFBH 02H R/W
76543210
PCC1 CPU clock (f
CPU
) selection
0
1
f
CC
f
CC
/2
2
0.5 s
2.0 s
µ
µ
Minimum instruction execution time: 2/f
CPU
@ f
CC
= 4.0 MHz operation
Caution Bit 0 and bits 2 to 7 must be set to 0.
Remark f
CC: System clock oscillation frequency
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
104
7.4 System Clock Oscillator
7.4.1 System clock oscillator
The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the
CL1 and CL2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the CL1 pin,
and leave the CL2 pin open.
Figure 7-3 shows the external circuit of the system clock oscillator.
Figure 7-3. External Circuit of System Clock Oscillator
(a) RC oscillation (b) External clock
V
SS
CL1
RC
CL2
External
clock CL1
CL2
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 105
7.4.2 Examples of incorrect resonator connection
Figure 7-4 shows examples of incorrect resonator connection.
Figure 7-4. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
VSSCL2CL1
V
SS
CL2
PORTn
(n = 0 to 2, 5, 6)
CL1
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
106
Figure 7-4. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator
(potential at points A and B fluctuates)
V
SS
CL2CL1
High current
VSS
VDD
CL2CL1
PORTn
(n = 0 to 2, 5, 6)
AB
High current
(e) Signal is fetched
V
SS
CL2CL1
7.4.3 Divider
The divider divides the output of the system clock oscillator (fCC) to generate various clocks.
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 107
7.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode.
• System clock fCC
• CPU clock fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), as follows.
(a) The slow mode (2.0
µ
s: at 4.0 MHz operation) of the system clock is selected when the RESET signal is
generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the system clock
is stopped.
(b) Two types of minimum instruction execution time (0.5
µ
s and 2.0
µ
s: at 4.0 MHz operation) can be selected
by setting the PCC register.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except the external clock input operation).
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
108
7.6 Changing Setting of CPU Clock
7.6.1 Time required for switching CPU clock
The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is
used for the duration of several instructions after that (refer to Table 7-2).
Table 7-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching Set Value After Switching
PCC1 PCC1 PCC1
0 1
0 4 clocks
1 2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
CHAPTER 7 CLOCK GENERATOR (
µ
PD789124A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 109
7.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 7-5. Switching CPU Clock
V
DD
RESET
CPU clock
Slow
operation
Fastest
operation
Wait (32 s: at 4.0 MHz operation)
Internal reset operation
µ
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (2.0
µ
s: at 4.0 MHz
operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
User’s Manual U14643EJ2V0UD
110
CHAPTER 8 16-BIT TIMER 20
The 16-bit timer counter references the free-running counter and provides functions such as timer interrupt and
timer output. In addition, the count value can be captured by a capture trigger pin.
8.1 16-Bit Timer 20 Functions
16-bit timer 20 has the following functions.
• Timer interrupt
• Timer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when the count value and compare value match.
(2) Timer output
Timer output control is possible when the count value and compare value match.
(3) Count value capture
The TM20 count value is latched in synchronization with the capture trigger and held.
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 111
8.2 16-Bit Timer 20 Configuration
16-bit timer 20 consists of the following hardware.
Table 8-1. Configuration of 16-Bit Timer 20
Item Configuration
Timer counter 16 bits × 1 (TM20)
Registers Compare register: 16 bits × 1 (CR20)
Capture register: 16 bits × 1 (TCP20)
Timer output 1 (TO20)
Control registers 16-bit timer mode control register 20 (TMC20)
Port mode register 2 (PM2)
Port 2 (P2)
Figure 8-1. Block Diagram of 16-Bit Timer 20
CPT20/P23/
INTP0/SS20
Internal bus
Internal bus
16-bit timer mode
control register 20
(TMC20)
16-bit timer mode
control register 20
TOF20 CPT201CPT200 TOC20 TCL201TCL200 TOE20
f
CLK
/2
2
f
CLK
/2
6
Edge
detector
16-bit capture
register 20 (TCP20)
16-bit counter
read buffer
16-bit timer counter 20 (TM20)
16-bit compare register 20 (CR20)
Match
Selector
OVF
F/F
TOD20
TO20/P24/
INTP1/TO80
INTTM20
P24
output latch
PM24
Remark f
CLK: fX or fCC
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
112
(1) 16-bit compare register 20 (CR20)
This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when
they match, generates an interrupt request (INTTM20).
CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set.
RESET input sets this register to FFFFH.
Cautions 1. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
2. When rewriting CR20 during a count operation, set CR20 to the interrupt-disabled state
using interrupt mask flag register 0 (MK10) beforehand. Also, set the timer output data to
inversion disabled using 16-bit timer mode control register 20 (TMC20).
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at
the moment of rewrite.
(2) 16-bit timer counter 20 (TM20)
This is a 16-bit register that counts count pulses.
TM20 is read with a 16-bit memory manipulation instruction.
This register is free running during count clock input.
RESET input clears this register to 0000H and after which it resumes free running.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
3. When manipulating with an 8-bit memory manipulation instruction, readout should be
performed in the order of lower byte to higher byte and must be performed in pairs.
(3) 16-bit capture register 20 (TCP20)
This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20).
TCP20 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-bit
memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
(4) 16-bit counter read buffer
This buffer latches the counter value and holds the count value of 16-bit timer counter 20 (TM20).
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 113
8.3 Registers Controlling 16-Bit Timer 20
The following three registers control 16-bit timer 20.
• 16-bit timer mode control register 20 (TMC20)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) 16-bit timer mode control register 20 (TMC20)
16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc.
TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC20 to 00H.
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
114
Figure 8-2. Format of 16-Bit Timer Mode Control Register 20
CPT201
0
0
1
1
CPT200
0
1
0
1
Capture operation disabled
Rising edge of CPT20
Falling edge of CPT20
Both edges of CPT20
TOF20
0
1Set by overflow of 16-bit timer
TOC20
0
1
Timer output data inversion control
Inversion disabled
Inversion enabled
TOD20
0
1
Timer output data
Timer output of 0
Timer output of 1
Capture edge selection
TOE20
0
1
TCL201
0
0
Other than above
TCL200
0
1
f
X
/2
2
or f
CC
/2
2
f
X
/2
6
or f
CC
/2
6
Setting prohibited
16-bit timer 20 output control
Output disabled (port mode)
Output enabled
16-bit timer counter 20 count clock selection
Overflow flag set
Clear by reset and software
1
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
R/W
FF48H 00H R/W
Note 1
<6>543217 <0>
Symbol Address After reset
@ f
X
= 10.0 MHz
Note 2
operation
@ f
X
= 5.0 MHz operation
1.25 MHz
78.1 kHz
2.5 MHz
156.2 kHz
1.0 MHz
62.5 kHz
@ fCC = 4.0 MHz operation
Notes 1. Bit 7 is read-only.
2. Expanded-specification products only.
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 115
(2) Port mode register 2 (PM2)
This register sets the input/output of port 2 in 1-bit units.
To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 8-3. Format of Port Mode Register 2
11
PM25 PM24
PM23 PM22 PM21 PM20PM2
R/W
FF22H FFH R/W
654321
PM24
0
1
70
Input mode (output buffer off)
Symbol Address After reset
P24 pin I/O mode selection
Output mode (output buffer on)
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
116
8.4 16-Bit Timer 20 Operation
8.4.1 Operation as timer interrupt
An interrupt is generated rep eatedly eac h tim e the free-running count er value reaches the value set to CR20. After
interrupt occurs, the counter is not cleared and continues counting. Therefore, the interval time is equivalent to one
count clock cycle set by TCL201 and TCL20 0.
To operate the 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values to CR20.
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-4.
Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation
−0/1 0/1 0/1 0/1 0 0/1 0/1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Setting of count clock (see Table 8-2)
Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited.
When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 8-2 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation.
Caution When rewriting CR20 during count operation, be sure to follow the procedure below.
<1> Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1).
<2> Set inversion control of timer output data to disable (TOC20 = 0)
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the
moment of rewrite.
Table 8-2. Interval Time of 16-Bit Timer 20
Count Clock Interval Time TCL201 TCL200
@ fX = 10.0
MHzNote
Operation
@ fX = 5.0
MHz
Operation
@ fCC = 4.0
MHz
Operation
@ fX = 10.0
MHzNote
Operation
@ fX = 5.0
MHz
Operation
@ fCC = 4.0
MHz
Operation
0 0 22/fX or
22/fCC 0.4
µ
s 0.8
µ
s 1.0
µ
s 218/fX or
218/fCC 26.2 ms 52.4 ms 65.5 ms
0 1 26/fX or
26/fCC 6.4
µ
s 12.8
µ
s 16
µ
s 222/fX or
222/fCC 419.4 ms 838.9 ms 1048 ms
Other than above Setting prohibited
Note Expanded-spe cification produ cts only.
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 117
Figure 8-5. Timing of Timer Interrupt Operation
Count clock
TM20 count value
CR20
INTTM20
TO20
TOF20
NN N NN
Interrupt acknowledged Interrupt
acknowledged
Overflow flag set
t
0000H N
FFFFH
N
0000H 0001H0001H
Remark N = 0000H to FFFFH
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
118
8.4.2 Operation as timer output
The timer output is inverted repeatedly each time the free-running counter value reaches the value set to CR20.
After the timer output is inverted, the counter is not cleared and continues counting. Therefore, the interval time is
equivalent to one count clock cycle set by TCL201 and TCL200.
To operate the 16-bit timer 20 as a timer output, the following settings are required.
• Set P24 to output mode (PM24 = 0).
• Set the P24 output latch to 0.
• Set the count value to CR20.
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-6.
Figure 8-6. Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation
– 0/1 0/1 0/1 1 0 0/1 1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Setting of count clock (see Table 8-2)
Inversion enable for timer output data
TO20 output enable
Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation
prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the
TO20/P24/INTP1/TO80 pin is inverted. This enables timer output. At that time, TM20 continues counting and an
interrupt reques t signal (INTTM20) is generated.
Figure 8-7 shows the timing of timer output (refer to Table 8-2 for the interval time of 16-bit timer 20).
Figure 8-7. Timer Output Timing
Count clock
TM20 count value
CR20
INTTM20
TOF20
NN N NN
Interrupt acknowledged Interrupt
acknowledged
Overflow flag set
t
0000H N
FFFFH
N
0000H 0001H0001H
TO20Note
Note The TO20 initial value becomes low level while output is enabled (TOE20 = 1).
Remark N = 0000H to FFFFH
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 119
8.4.3 Capture operation
The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) in
synchronization with a capture trigger.
Set as shown in Figure 8-8 to allow 16-bit timer 20 to start the capture operation.
Figure 8-8. Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation
−0/1 0/1 0/1 0/1 0 0/1 0/1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Count clock selection
Capture edge selection (see Table 8-3)
16-bit capture register 20 (TCP20) starts the capture operation after the CPT20 capture trigger edge has been
detected, and latches and holds the count value of 16-bit timer counter 20. TCP20 fetches the count value within 2
clocks and holds the count value until the next capture edge detection.
Table 8-3 and Figure 8-9 show the setting contents of the capture edge and the capture operation timing,
respectively.
Table 8-3. Settings of Capture Edge
CPT201 CPT200 Capture Edge Selection
0 0 Capture operation prohibited
0 1 CPT20 pin rising edge
1 0 CPT20 pin falling edge
1 1 CPT20 pin both edges
Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable
capture trigger detection during TCP20 read.
Figure 8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified)
Count clock
TM20
Count read buffer
TCP20
CPT20
0000H
0000H
0001H
0001H
Undefined
N
N
N
M – 1 M
M
M
Capture start Capture start
Capture edge detection Capture edge detection
Remark N, M = 0000H to FFFFH
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
120
8.4.4 16-bit timer counter 20 readout
The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction.
TM20 readout is performed via a counter read buffer. The counter read buffer latches the TM20 count value. The
buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises
and the count value is held. The counter read buffer value in the hold state can be read out as the count value.
Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20
higher byte falls.
RESET input clears TM20 to 0000H and restarts free running.
Figure 8-10 shows the timing of 16-bit timer counter 20 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during oscillation stabilization time.
2. Although TM20 is a dedicated 16-bit transfer instruction register, an 8-bit transfer instruction
can also be used.
Execute an 8-bit transfer instruction by direct addressing.
3. When using an 8-bit transfer instruction, execute in the order of lower byte to higher byte in
pairs. If the only lower byte is read, the pending state of the counter read buffer is not
canceled, and if the only higher byte is read, an undefined count value is read.
Figure 8-10. 16-Bit Timer Counter 20 Readout Timing
CPU clock
Count clock
TM20
Count read buffer
TM20 read signal
0000H
0000H
0001H
0001H
N
N
N + 1
Read signal latch
prohibited period
Remark N = 0000H to FFFFH
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD 121
8.5 Notes on Using 16-Bit Timer 20
8.5.1 Restrictions on rewriting 16-bit compare register 20
(1) When rewriting the compare register (CR20), be sure to disable interrupts (TMMK20 = 1), and disable
inversion control of timer output (TOC20 = 0) first.
If CR20 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite.
(2) The interval time may be double the intended time depending on the timing at which the compare register
(CR20) is rewritten. Likewise, the timer output waveform may be shorter or double the intended outp ut.
To avoid this, rewrite using one of the following procedures.
<Prevention method A> Rewriting by 8-bit access
<1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0).
<2> Rewrit e the higher byte of CR20 (16 bits) first.
<3> Next, rewrite the lower byte of CR20 (16 bits).
<4> Clear th e interrupt request flag (TMIF20).
<5> After more than half the cycle of the count clock has passed from the star t of the interrupt, enable timer
interrupts and timer output inversion.
<Program example A> (When count clock = 64/fX, CPU clock = fX)
TM20_VCT: SET1 TMMK20 ;Timer interrupt disable (6 clocks)
CLR1 TMC20.3 ;Timer output inversion disable (6 clocks)
MOV A,#xxH ;Higher byte rewrite value setting (6 clocks)
MOV !0FF17H,A ;CR20 higher byte rewriting (8 clocks)
MOV A,#yyH ;Lower byte rewrite value setting (6 clocks)
MOV !0FF16H,A ;CR20 lower byte rewriting (8 clocks)
CLR1 TMIF20 ;Interrupt request flag clearing (6 clocks)
CLR1 TMMK20 ;Timer interrupt enable (6 clocks)
SET1 TMC20.3 ;Timer output inversion enable
Note This is because the INTTM20 signal is set to the high level for a period of half the cycle of the count
clock after an interrupt is generated, so the output will be inverted if TOC20 is set to 1 during this
period.
More than 32 clocks
in totalNote
CHAPTER 8 16-BIT TIMER 20
User’s Manual U14643EJ2V0UD
122
<Prevention method B> Rewriting by 16-bit access
<1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0).
<2> Rewrite CR2 0 (16 bits).
<3> Wait for more than one cycle of the count clock.
<4> Clear th e interrupt request flag (TMIF20).
<5> Enable timer interrupts and timer output inversion
<Program example B> (When count clock = 64/fX, CPU clock = fX)
TM20_VCT: SET1 TMMK20 ;Timer interrupt disable
CLR1 TMC20.3 ;Timer output inversion disable
MOVW AX,#xxyyH ;CR20 rewrite value setting
MOVW CR20,AX ;CR20 rewriting
NOP
NOP
:
NOP
NOP
CLR1 TMIF20 ;Interrupt request flag clearing
CLR1 TMMK20 ;Timer interrupt enable
SET1 TMC20.3 ;Timer output inversion enable
Note Wait for more t han one cycle of the count clock after the instruction rewriting CR20 (MOVW CR20, AX)
before clearing the interrupt request flag (TMIF20).
;32 NOP (Wait for 64/fX)Note
User’s Manual U14643EJ2V0UD 123
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square-wave output
and PWM output of arbitrary frequency.
9.1 Functions of 8-Bit Timer/Event Counter 80
8-bit timer/event counter 80 has the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
(1) 8-bit interval timer
When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time
interval set in advance.
Table 9-1. Interval Time of 8-Bit Timer/Event Counter 80
Minimum Interval Time Maximum Interval Time Resolution
1/fX (100 ns) 28/fX (25.6
µ
s) 1/fX (100 ns) At fX = 10.0 MHzNote
23/fX (0.8
µ
s) 211/fX (204.8
µ
s) 23/fX (0.8
µ
s)
1/fX (200 ns) 28/fX (51.2
µ
s) 1/fX (200 ns) At fX = 5.0 MHz
23/fX (1.6
µ
s) 211/fX (409.6
µ
s) 23/fX (1.6
µ
s)
1/fCC (250 ns) 28/fCC (64
µ
s) 1/fCC (250 ns) At fCC = 4.0 MHz
23/fCC (2.0
µ
s) 211/fCC (512
µ
s) 23/fCC (2.0
µ
s)
Note Expanded-specification products only
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
(2) External event counter
The number of pulses of an externally input signal can be measured.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
124
(3) Square-wave output
A square wave of arbitrary frequency can be output.
Table 9-2. Square-Wave Output Range of 8-Bit Timer/Event Counter 80
Minimum Pulse Width Maximum Pulse Width Resolution
1/fX (100 ns) 28/fX (25.6
µ
s) 1/fX (100 ns) At fX = 10.0 MHzNote
23/fX (0.8
µ
s) 211/fX (204.8
µ
s) 23/fX (0.8
µ
s)
1/fX (200 ns) 28/fX (51.2
µ
s) 1/fX (200 ns) At fX = 5.0 MHz
23/fX (1.6
µ
s) 211/fX (409.6
µ
s) 23/fX (1.6
µ
s)
1/fCC (250 ns) 28/fCC (64
µ
s) 1/fCC (250 ns) At fCC = 4.0 MHz
23/fCC (2.0
µ
s) 211/fCC (512
µ
s) 23/fCC (2.0
µ
s)
Note Expanded-specification products only
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
(4) PWM output
8-bit resolution PWM output can be produced.
9.2 8-Bit Timer/Event Counter 80 Configuration
8-bit timer/event counter 80 consists of the following hardware.
Table 9-3. 8-Bit Timer/Event Counter 80 Configuration
Item Configuration
Timer counter 8 bits × 1 (TM80)
Register Compare register: 8 bits × 1 (CR80)
Timer output 1 (TO80)
Control registers 8-bit timer mode control register 80 (TMC80)
Port mode register 2 (PM2)
Port 2 (P2)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 125
Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
Internal bus
8-bit compare register 80
(CR80)
Match
8-bit timer counter 80
(TM80)
Clear
OVF
Selector
INTTM80
TO20
output
Note
f
CLK
f
CLK
/2
3
TI80/P25/
INTP2
TO80/P24/
INTP1/TO20
PWME80
TCE80
TCL801 TCL800
TOE80
8-bit timer mode control
register 80 (TMC80)
P24 output
latch
PM24
R
QINV
S
Q
Note Refer to block diagram of 16-bit timer 20
Remark f
CLK: fX or fCC
(1) 8-bit compare register 80 (CR80)
This is an 8-bit register that compares the value set to CR80 with the 8-bit timer counter 80 (TM80) count
value, and if they match, generates an interrupt request (INTTM80).
CR80 is set with an 8-bit memory manipulation instruction. The values 00H to FFH can be set.
RESET input makes CR80 undefined.
Cautions 1. When rewriting CR80 in timer counter operation mode (i.e., PWME80 (bit 6 of 8-bit timer
mode control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before
hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request
signal may occur at the moment of rewrite.
2. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM
may not be output normally.
(2) 8-bit timer counter 80 (TM80)
This is an 8-bit register used to count count pulses.
TM80 is read with an 8-bit memory manipulation instruction.
RESET input clears TM80 to 00H.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
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9.3 Registers Controlling 8-Bit Timer/Event Counter 80
The following three registers are used to control 8-bit timer/ event counter 80.
• 8-bit timer mode control register 80 (TMC80)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) 8-bit timer mode control register 80 (TMC80)
This register enables/stops operation of 8-bit timer counter 80 (TM80), sets the counter clock of TM80, and
controls the operation of the output controller of 8-bit timer/event counter 80.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.
Figure 9-2. Format of 8-Bit Timer Mode Control Register 80
TOE80
0
1
TCE80
PWME80
000
TCL801TCL800 TOE80
TMC80 R/W
FF53H 00H R/W
<6>54321
TCE80
0
1
<7> <0>
Operation enable
Symbol Address After reset
8-bit timer/event counter 80 output control
Output disable (port mode)
Output enable
8-bit timer counter 80 operation control
Operation stop (TM80 cleared to 0)
PWME80
0
1PWM output operating mode
Operation mode selection
Timer counter operating mode
TCL801
0
0
TCL800
0
1
1
1
0
1
f
X
or f
CC
f
X
/2
3
or f
CC
/2
3
Rising edge of TI80
Falling edge of TI80
8-bit timer counter 80 count clock selection
@ f
X
= 10.0 MHz
Note
operation
@ f
X
= 5.0 MHz operation
5.0 MHz
625 kHz
10.0 MHz
1.25 MHz
4.0 MHz
500 kHz
@ f
CC
= 4.0 MHz operation
Note Expanded-specification products only
Caution Be sure to set TMC80 after stopping timer operation.
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 127
(2) Port mode register 2 (PM2)
This register sets port 2 to input/output in 1-bit units.
When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0. When
using it for timer input, set PM24 to 1.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 9-3. Format of Port Mode Register 2
PM2n
0
1
1 1 PM25 PM24 PM23 PM22 PM21 PM20PM2
7654 R/W
R/W
3210
Input mode (output buffer off)
Symbol Address
FF22H FFH
After reset
P2n pin I/O mode selection (n = 0 to 5)
Output mode (output buffer on)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
128
9.4 Operation of 8-Bit Timer/Event Counter 80
9.4.1 Operation as interval timer
The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit
compare register 80 (CR80) i n advance.
To operate the 8-bit timer/event counter as an interval timer, the following settings are required.
<1> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<2> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2)
<3> Set the count value to CR80
<4> Set TM80 to operation enable (TCE80 = 1)
When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, the value of TM80 is
cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Tables 9-4 and 9-5 show the interval time, and Figure 9-4 shows the timing of inter val timer operation.
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite .
2. If the count clock setting and TM80 operation-enabled are set in TMC80 si multaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
an interval timer.
Table 9-4. Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)
TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution
0 0 1/fX (100 ns) [200 ns] 28/fX (25.6
µ
s) [51.2
µ
s] 1/fX (100 ns) [200 ns]
0 1 23/fX (0.8
µ
s) [1.6
µ
s] 211/fX (204.8
µ
s) [409.6
µ
s] 23/fX (0.8
µ
s) [1.6
µ
s]
1 0 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
1 1 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
Remarks 1. f
X: System clock oscillation frequency (ceramic/crystal oscillation)
2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products
only).
3. The values in square brackets [ ] are for operation at fX = 5.0 MHz.
Table 9-5. Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)
TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution
0 0 1/fCC (250 ns) 28/fCC (64
µ
s) 1/fCC (250 ns)
0 1 23/fCC (2.0
µ
s) 211/fCC (512
µ
s) 23/fCC (2.0
µ
s)
1 0 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
1 1 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
Remark f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 129
Figure 9-4. Interval Timer Operation Timing
Clear Clear
Interrupt acknowledged Interrupt acknowledged
Count start
Interval time Interval time Interval time
Count clock
TM80 count value
CR80
TCE80
INTTM80
TO80
N01H00HN01H00HN00H 01H
NN NN
t
Remark Interval time = (N + 1) × t : N = 00H to FFH
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
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9.4.2 Operation as external event counter
The exter nal event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using 8-
bit timer counter 80 (TM80).
To operate 8-bit timer/event counter 80 as an external event counter, the following settings are required.
<1> Set P25 to input mode (PM25 = 1).
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<3> Specify the rising/falling edges of TI80 (refer to Figure 9-2), and set TO80 to output disabled (i.e., set TOE80
(bit 0 of TMC80) to 0) and PWM output to disabled (i.e., set PWME80 (bit 6 of TMC80) to 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
Each time the valid edge specified by bit 1 (TCL80 0) of TMC80 is input, the value of 8-bit timer counter 80 (TM80)
is incremented.
When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 0 and TM80
continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Figure 9-5 shows the timing of the external event counter operation (with the rising edge specified).
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite .
2. If the count clock setting and TM80 operation-enabled are set in TMC80 si multaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
an external event counter.
Figure 9-5. External Event Counter Operation Timing (with Rising Edge Specified)
TI80 pin input
TM80 count value
CR80
TCE80
INTTM80
00H 01H 02H 03H 04H 05H N − 1 N 00H 01H 02H 03H
N
Remark N = 00H to FFH
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 131
9.4.3 Operation as square-wave output
The 8-bit timer/event counter can output square waves of a given frequency at intervals specified by the count
value set to 8-bit compare register 80 (CR80) in advance.
To operate 8-bit timer/event counter 80 as square-wave output, the following settings are required.
<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0).
<3> Set the c ount clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1),
and PWM output to disabled (PWME80 = 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
When the count value of 8-bit timer counter 8 0 (TM80) matches the value set in CR80, the TO80/P24/INTP1/TO20
pin output will be i nver ted. Throu gh application of this mechanism, s quare waves of any frequency can be output. As
soon as a match occurs, the TM80 value is cleared to 0 and TM80 continues counting. At the same time, an interrupt
request signal (INTTM80) is generated.
Square-wave output is cleared (0) when bit 7 (TCE80) of TMC80 is set to 0.
Tables 9-6 and 9-7 show the square-wave output range, and Figure 9-6 shows the timing of square-wave output.
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite .
2. If the count clock setting and TM80 operation-enabled are set in TMC80 si multaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
square-wave output.
Table 9-6. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)
TCL801 TCL800 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 1/fX (100 ns) [200 ns] 28/fX (25.6
µ
s) [51.2
µ
s] 1/fX (100 ns) [200 ns]
0 1 23/fX (0.8
µ
s) [1.6
µ
s] 211/fX (204.8
µ
s) [409.6
µ
s] 23/fX (0.8
µ
s) [1.6
µ
s]
Remarks 1. f
X: System clock oscillation frequency (ceramic/crystal oscillation)
2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products
only).
3. The values in square brackets [ ] are for operation at fX = 5.0 MHz.
Table 9-7. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)
TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution
0 0 1/fCC (250 ns) 28/fCC (64
µ
s) 1/fCC (250 ns)
0 1 23/fCC (2.0
µ
s) 211/fCC (512
µ
s) 23/fCC (2.0
µ
s)
Remark f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
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Figure 9-6. Square-Wave Output Timing
Clear Clear
Interrupt acknowledged Interrupt acknowledged
Count start
Count clock
TM80 count value
CR80
TCE80
INTTM80
TO80
Note
N01H00HN01H00HN00H 01H
NN NN
Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1).
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 133
9.4.4 Operation as PWM output
PWM output enables interrupt generation repeatedly at inter vals specified by the count value set to 8-bit compar e
register 80 (CR80) in advance.
To use 8-bit timer/counter 80 for PWM output, the following settings are required.
<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0).
<3> Set the c ount clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1),
and PWM output to enabled (PWME80 = 1).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, TM80 continues counting,
and an interrup t request signal (INTTM80) is generated.
Cautions 1. When CR80 is rewritten during timer operation, a high level may be output for the next cycle
(refer to 9.5 (2) Setting of 8-bit compare register 80).
2. If the count clock setting and TM80 operation-enabled are set in TMC80 si multaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts. Therefore, always follow the above procedure when operating 8-
bit compare register 80 as a PWM output.
Figure 9-7. PWM Output Timing
Count clock
TM80
CR80
TCE80
INTTM80
M = 01H to FFH
OVF
TO80
Note
00H
01H
M
• • •
M
• • •
FFH 00H 01H 02H
• • •
M
M + 1 M + 2
• • •
FFH 00H 01H
• • •
M
• • • • • •
Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1).
Caution Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD
134
9.5 Notes on Using 8-Bit Timer/Event Counter 80
(1) Error on starting timer
An error of up to 1 clock occurs after the timer is star ted until a match sign al is generated. This is because 8-
bit timer counter 80 (TM80) is started asynchronous to the count pulse.
Figure 9-8. Start Timing of 8-Bit Timer Counter
Count pulse
TM80
count value
Timer start
00H 01H 02H 03H 04H
(2) Setting of 8-bit compare register 80
8-bit compare register 80 (CR80) can be set to 00H.
Therefore, one pulse can be counte d when the 8-bit timer/event counter operates as an event counter.
Figure 9-9. External Event Counter Operation Timing
Tl80 input
CR80 00H
TM80
count value 00H 00H 00H 00H
Interrupt request flag
Cautions 1. When rewriting CR80 in timer counter operation mode (i.e ., PWME80 (bit 6 of 8-bit timer mode
control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before hand. If
CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may
occur at the moment of rewrite.
2. If CR80 is rewritten while the timer is operating in PWM output operation mode (PWME80 = 1),
a pulse may not be generated just in the cycle immediately after the rewrite.
3. Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally.
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
User’s Manual U14643EJ2V0UD 135
(3) Operation after rewriting compare register during PWM output
When 8-bit compare register 80 (CR80) is rewritten dur ing PWM output, a high level may be output for a cycle
after rewriting CR80 (count pulse × 256) if the 8-bit compare register 80 value is smaller than the 8-bit timer
counter 80 (TM80) value. The timing in this case is shown in Figure 9-10.
Figure 9-10. Timing After Rewriting Compare Register During PWM Output
Count clock
TM80
CR80
TCE80
INTTM80
M = 02H to FFH
OVF
TO80
00H
01H
M
H
... M...
FFH 00H 01H 02H
...
FFH 00H 01H
... ...
01H
...
...
Rewriting CR80
(4) Notes on STOP mode setting
Before executing the STOP instruction, be sure to set the timer to operation stopped (TCE80 = 0).
(5) External event counter start timing
When the rising edge of TI80 is selecte d as the count clock, start the timer (TCE80 = 0 → 1) at the timing when
TI80 changes to low level. Similarly, when the falling edge of TI80 is selected as the count clock, start the timer
(TCE80 = 0 → 1) at the timing when TI80 changes to high level.
User’s Manual U14643EJ2V0UD
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CHAPTER 10 WATCHDOG TIMER
The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET at arbitrary preset
intervals.
10.1 Functions of Watchdog Timer
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect a program loop. When a program loop is detected, a non-maskable
interrupt or the RESET signal can be generated.
Table 10-1. Program Loop Detection Time of Watchdog Timer
Program Loop Detection
Time
At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
211 × 1/fW 205
µ
s 410
µ
s 512
µ
s
213 × 1/fW 819
µ
s 1.64 ms 2.05 ms
215 × 1/fW 3.28 ms 6.55 ms 8.19 ms
217 × 1/fW 13.1 ms 26.2 ms 32.8 ms
Note Expanded-specification products only
Remark f
W: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
(2) Interval timer
The interval timer generates an interrupt at a given interval set in advance.
Table 10-2. Interval Time
Interval Time At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
211 × 1/fW 205
µ
s 410
µ
s 512
µ
s
213 × 1/fW 819
µ
s 1.64 ms 2.05 ms
215 × 1/fW 3.28 ms 6.55 ms 8.19 ms
217 × 1/fW 13.1 ms 26.2 ms 32.8 ms
Note Expanded-specification products only
Remark f
W: fX or fCC
f
X: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
CHAPTER 10 WATCHDOG TIMER
User’s Manual U14643EJ2V0UD 137
10.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Table 10-3. Configuration of Watchdog Timer
Item Configuration
Control registers Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 10-1. Block Diagram of Watchdog Timer
Internal bus
Internal bus
Prescaler
Selector
f
W
2
6
f
W
2
8
f
W
2
10
3
7-bit counter
TMIF4
TMMK4
TCL22 TCL21 TCL20
Timer clock select register 2
(TCL2)
Watchdog timer mode register (WDTM)
Clear
WDTM4
RUN
WDTM3
INTWDT
maskable
interrupt request
RESET
INTWDT
non-maskable
interrupt request
f
W
2
4
Controller
Remark f
W: fX or fCC
CHAPTER 10 WATCHDOG TIMER
User’s Manual U14643EJ2V0UD
138
10.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instructio n.
RESET input clears TCL2 to 00H.
Figure 10-2. Format of Timer Clock Select Register 2
TCL22
0
0
1
1
00000TCL22 TCL21TCL20TCL2
R/W
R/W
76543210
TCL21
0
1
0
1
fX/24 or fCC/24
fX/26 or fCC/26
fX/28 or fCC/28
f
X
/210 or f
CC
/210
625 kHz
156.2 kHz
39.0 kHz
9.76 kHz
312.5 kHz
78.1 kHz
19.5 kHz
4.88 kHz
250 kHz
62.5 kHz
15.6 kHz
3.91 kHz
211/f
X
or 211/f
CC
213/f
X
or 213/f
CC
215/f
X
or 215/f
CC
217/f
X
or 217/f
CC
205 s
819 s
3.28 ms
13.1 ms
410 s
1.64 ms
6.55 ms
26.2 ms
512 s
2.05 ms
8.19 ms
32.8 ms
TCL20
0
0
0
0
Setting prohibited
Symbol Address
FF42H 00H
After reset
Other than above
Watchdog timer count clock selection Interval time
@ f
X
= 10.0 MHz
Note
operation
@ f
X
= 5.0
MHz operation
@ fCC = 4.0
MHz operation
@ f
X
= 10.0 MHz
Note
operation
@ f
X
= 5.0
MHz operation
@ fCC = 4.0
MHz operation
µ
µ
µµ
Note Expanded-specification prod ucts only
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 10 WATCHDOG TIMER
User’s Manual U14643EJ2V0UD 139
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instr uction.
RESET input clears WDTM to 00H.
Figure 10-3. Format of Watchdog Timer Mode Register
RUN
0
1
Selection of operation of watchdog timer
Note 1
RUN 0 0
WDTM4 WDTM3
000WDTM
Symbol Address After reset R/W
FFF9H 00H R/W
<7>6543210
Stop counting
Clear counter and start counting
WDTM4
Selection of operation mode of watchdog timer
Note 2
WDTM3
01
10
11
Operation stop
Interval timer mode (overflow and maskable interrupt occur)
Note 3
Watchdog timer mode 1 (overflow and non-maskable interrupt occur)
Watchdog timer mode 2 (overflow occurs and reset operation started)
00
Notes 1. Once RUN h as been s et (1), it cann ot be cle ared (0) by software. Therefore, when counting is started, it
cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts ope rations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to
0.8% shorter th an the time set by timer clock select register 2 (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt
request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under the
condition that TMIF4 is 1, a non-maskable interrupt occurs at the completion of rewriting.
CHAPTER 10 WATCHDOG TIMER
User’s Manual U14643EJ2V0UD
140
10.4 Operation of Watchdog Timer
10.4.1 Operation as watchdog timer
The watchdog timer operates to detect a program loop when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (program loop detection time inter val) of the watchdog timer can be selected by bits 0 to 2 (TCL20
to TCL22) of timer clock select register 2 (T CL2). The watchdog timer is started by setting bit 7 (RUN) of WDTM to 1.
Set RUN to 1 within the set program loop detection time int erval after the watchdog timer has been started. By setting
RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program loop
detection time is exceeded, the system is reset or a non-maskable interrupt is generated according to the value of bit
3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Caution The actual program loop detection time may be up to 0.8% shorter than the set time.
Table 10-4. Program Loop Detection Time of Watchdog Timer
TCL22 TCL21 TCL20 Program Loop
Detection T ime At fX = 10.0 MHzNote
Operation At fX = 5.0 MHz
Operation At fCC = 4.0 MHz
Operation
0 0 0 211 × 1/fW 205
µ
s 410
µ
s 512
µ
s
0 1 0 213 × 1/fW 819
µ
s 1.64 ms 2.05 ms
1 0 0 215 × 1/fW 3.28 ms 6.55 ms 8.19 ms
1 1 0 217 × 1/fW 13.1 ms 26.2 ms 32.8 ms
Note Expanded-spe cification produ cts only
Remark f
W: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
CHAPTER 10 WATCHDOG TIMER
User’s Manual U14643EJ2V0UD 141
10.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 1, the watchdog
timer also operates as an inter val timer that repeatedly generates an interrupt at time inter vals specified by the count
value set in advance.
Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2
(TCL2). The watchdog timer starts operation as an inter val timer when the RUN bit (bit 7 of WDTM) is set to 1.
In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
generated. The prio rity of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 10-5. Interval Time of Interval Timer
TCL22 TCL21 TCL20 Interval Time At fX = 10.0 MHzNote
Operation At fX = 5.0 MHz
Operation At fCC = 4.0 MHz
Operation
0 0 0 211 × 1/fW 205
µ
s 410
µ
s 512
µ
s
0 1 0 213 × 1/fW 819
µ
s 1.64 ms 2.05 ms
1 0 0 215 × 1/fW 3.28 ms 6.55 ms 8.19 ms
1 1 0 217 × 1/fW 13.1 ms 26.2 ms 32.8 ms
Note Expanded-spe cification produ cts only
Remark f
W: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
User’s Manual U14643EJ2V0UD
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CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
11.1 8-Bit A/D Converter Functions
The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs into digital signals. This
converter can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an
interrupt request (INTAD0) being issued each time an A/D session is completed.
11.2 8-Bit A/D Converter Configuration
The 8-bit A/D converter consists of the following hardware.
Table 11-1. Configuration of 8-Bit A/D Converter
Item Configuration
Analog input 4 channels (ANI0 to ANI3)
Registers Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
Figure 11-1. Block Diagram of 8-Bit A/D Converter
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
Selector
Sample & hold circuit
Voltage comparator
Successive
approximation
register (SAR)
Controller
2
A/D conversion result
register 0 (ADCR0)
Tap selector
AV
SS
INTAD0
A/D converter mode register 0
(ADM0)
Analog input channel
specification register 0
(ADS0)
Internal bus
AV
SS
ADCS0 FR02 FR01 FR00ADS01 ADS00
P-ch
AV
DD
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 143
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap
(comparison voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
Each time A/D conversion ends, the conversion result received from the successive approximation register is
loaded into ADCR0, which is an 8-bit register that holds the result of A/D conversion.
ADCR0 can be read with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI3 pins
Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.
Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.
(7) AVSS pin
The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
(8) AVDD pin
The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same potential
as the VDD pin, even while the A/D converter is not being used.
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD
144
11.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• Analog input channel specification register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADM0 to 00H.
Figure 11-2. Format of A/D Converter Mode Register 0
A/D conversion control
ADCS0
0 FR02 FR01 FR00 0 0 0ADM0
Symbol Address After reset R/W
FF80H 00H R/W
<7>6543210
ADCS0
0
1
A/D conversion time selection
Note 1
FR02
0
0
0
1
1
1
144/f
X
or 144/f
CC
120/f
X
or 120/f
CC
96/f
X
or 96/f
CC
72/f
X
or 72/f
CC
60/f
X
or 60/f
CC
48/f
X
or 48/f
CC
FR01
0
0
1
0
0
1
FR00
0
1
0
0
1
0
Other than above
Conversion disabled
Conversion enabled
Setting prohibited
@ f
CC
= 4.0 MHz operation
@ fX = 10.0 MHz
Note 2
operation
@ fX = 5.0 MHz operation
µ
µ
14.4 s
12 s
Setting prohibitedNote 3
Setting prohibitedNote 3
Setting prohibitedNote 3
Setting prohibitedNote 3
µ
µ
28.8 s
24 s
19.2 s
14.4 s
12 s
Note 4
Setting prohibitedNote 3
36 s
30 s
24 s
18 s
15 s
Setting prohibitedNote 3
µ
µ
µ
µ
µ
µ
µ
µ
Notes 1. Set the A/D conversion time to satisfy the following specifications.
<Expanded-specification products>
When 4.5 V ≤ VDD ≤ 5.5 V: 12
µ
s min.
When 2.7 V ≤ VDD < 4.5 V: 14
µ
s min.
When 1.8 V ≤ VDD < 2.7 V: 28
µ
s min.
<Conventional-specification products>
When 2.7 V ≤ VDD ≤ 5.5 V: 14
µ
s min.
When 1.8 V ≤ VDD < 2.7 V: 28
µ
s min.
2. Expanded-specification products only
3. Setting prohibited because the A/D conversi on time does not satisfy the rating shown in Note 1.
4. Can be set only for expanded-specification products when 4.5 V ≤ VDD ≤ 5.5 V. Otherwise, setting
prohibited.
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 145
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
11.5 (5) Timing when A/D conversion result become undefined).
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) Analog input channel specification register 0 (ADS0)
The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 11-3. Format of Analog Input Channel Specification Register 0
000000
ADS01 ADS00
ADS0
Symbol Address After reset R/W
FF84H 00H R/W
76543210
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS01
0
0
1
1
ADS00
0
1
0
1
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD
146
11.4 8-Bit A/D Converter Operation
11.4.1 Basic operation of 8-bit A/D converter
<1> Select the channel for A/D conversion using analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation register (SAR) is set. The tap selector sets the series resistor string
voltage tap to half AVDD.
<5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half
AVDD, the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows.
• Bit 7 = 1: Three quarters of AVDD
• Bit 7 = 0: One quarter of AVDD
The voltage tap is compared with the analog input voltage. Bit 6 is set or reset according to the result of
comparison.
• Analog input voltage ≥ voltage tap: Bit 6 = 1
• Analog input voltage < voltage tap: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation
may be undefined.
2. When in standby mode, the A/D converter stops operation.
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 147
Figure 11-4. Basic Operation of 8-Bit A/D Converter
Conversion
time
Sampling
time
Sampling A/D conversion
Undefined 80H C0H
or 40H
Conversion
result
Conversion
result
A/D converter
operation
SAR
ADCR0
INTAD0
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D
conversion, the A/D conversion in progress is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted
from the beginning.
RESET input makes A/D conversion result register 0 (ADCR0) undefined.
11.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
VIN
ADCR0 = INT ( AVDD
× 256 + 0.5)
or
AVDD AVDD
(ADCR0 − 0.5) × 256 ≤ VIN < (ADCR0 + 0.5) × 256
INT( ): Function that returns the integer part of the parenthesized value
VIN: Analog input voltage
AVDD: A/D converter supply voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result.
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD
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Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253
3
2
1
0
A/D conversion
result (ADCR0)
1
512
1
256
3
512
2
256
5
512
3
256
507
512
254
256
509
512
255
256
511
512
1
Input voltage/AVDD
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 149
11.4.3 Operation mode of 8-bit A/D converter
The 8-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0
(ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can only be started by software; that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to
the analog input pin specified by analog input channel specification register 0 (ADS0). Upon completion of A/D
conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an
interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another
session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data
where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion in progress is
discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written
to ADM0 again during A/D conversion, A/D conversion is completely stopped.
Figure 11-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1 ADCS0 = 0
A/D conversion
ADCR0
INTAD0
ANIn ANIn ANIn ANIm ANIm
Stop
ANIn ANIn ANIm
Conversion is
discontinued;
no conversion
result is preserved.
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD
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11.5 Notes on Using 8-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Clearing bit 7 (ADCS0) of A/D converter
mode register 0 (ADM0) to 0 can reduce the current consumption.
Figure 11-7 shows how to reduce the current consumption in the standby mode.
Figure 11-7. How to Reduce Current Consumption in Standby Mode
AV
DD
AV
SS
P-ch
Series resistor string
ADCS0
(2) Input range for the ANI0 to ANI3 pins
Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or grater or AVSS
or lower (even if within the absolute maximum ratings) is input to a conversion channel, the conversion output
of the channel becomes undefined, and the conversion output of the other channels may also be affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and
reading from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0.
<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0
(ADM0) or analog input channel specification register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end
interrupt request signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and
discarding the first conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 11-8 and 11-9.
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 151
Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end A/D conversion end
Normal conversion result Undefined value
Normal conversion result read out Undefined value read out
A/D operation stopped
ADCR0
INTAD0
ADCS0
Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
Normal conversion result
A/D conversion end
Normal conversion result read outA/D operation stopped
ADCR0
INTAD0
ADCS0
(6) Noise prevention
To maintain a resolution of 8 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 11-10.
Figure 11-10. Analog Input Pin Treatment
C = 100 to 1000 pF
If noise of AV
DD
or greater or AV
SS
or lower is
likely to come to the AV
DD
pin, clamp the voltage
at the pin by attaching a diode with a small V
F
(0.3 V or lower).
AV
SS
V
SS
AV
DD
V
DD
ANI0 to ANI3
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD
152
(7) ANI0 to ANI3
The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may
occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse
to pins adjacent to the analog input pin being A/D converted.
(8) Input impedance of ANI0 to ANI3 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs
sampling.
Therefore at times other than sampling, only the leakage current flows. During sampling, the current for
charging the capacitor also flows, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source
be set to 10 kΩ or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure
11-10).
(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In
this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even
when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.
Figure 11-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
A/D conversion
ADCR0
INTAD0
ANIn ANIn ANIm
ANIn ANIn ANIm
ANIm
ANIm
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD789104A, 789124A SUBSERIES)
User’s Manual U14643EJ2V0UD 153
(10) AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
input circuit.
Therefore, if the application is designed to be switched to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 11-12.
Figure 11-12. AVDD Pin Treatment
Main power
source Backup
capacitor
VDD
AVDD
VSS
AVSS
(11) Input impedance of the AVDD pin
A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher
reference voltage error.
User’s Manual U14643EJ2V0UD
154
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
12.1 10-Bit A/D Converter Functions
The 10-bit A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. This
converter can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an
interrupt request (INTAD0) being issued each time an A/D session is completed.
12.2 10-Bit A/D Converter Configuration
The A/D converter consists of the following hardware.
Table 12-1. Configuration of 10-Bit A/D Converter
Item Configuration
Analog input 4 channels (ANI0 to ANI3)
Registers Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
Figure 12-1. Block Diagram of 10-Bit A/D Converter
Sample & hold circuit
Voltage comparator
Successive
approximation
register (SAR)
Controller
2
A/D conversion result
register 0 (ADCR0)
Tap selector
AVSS
INTAD0
A/D converter mode register 0
(ADM0)
Analog input channel
specification register 0
(ADS0)
Internal bus
AVSS
P-ch
AVDD
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
Selector
ADCS0 FR02 FR01 FR00
ADS01 ADS00
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 155
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap
(comparison voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
ADCR0 is a 16-bit register that holds the result of A/D conversion. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0.
The results are stored in ADCR0 from the most significant bit.
The higher 8 bits of the conversion result are stored in FF15H and the lower 2 bits of the conversion result are
stored in FF14H.
ADCR0 can be read with a 16-bit memory manipulation instruction.
RESET input makes ADCR0 undefined.
ADCR0
Symbol FF15H
0
0
0
000
FF14H
FF14H,
FF15H
Address After reset
Undefined
R/W
R
Caution When using the
µ
PD78F9116A and 78F9116B as flash memory versions of the
µ
PD789101A,
789102A, and 789104A, or the
µ
PD78F9136A and 78F9136B as flash memory versions of the
µ
PD789121A, 789122A, and 789124A, an 8-bit access can be made by ADCR0. However, it is
performed only with the object file assembled by the
µ
PD789101A, 789102A, or 789104A, or
by the
µ
PD789121A, 789122A, or 789124A, respectively.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI3 pins
Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.
Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.
(7) AVSS pin
The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD
156
(8) AVDD pin
The AVDD pin is the analog power supply pin for the A/D converter. This pin must be hel d at the same potential
as the VDD pin, even while the A/D converter is not being used.
12.3 Register s Controlling 10-Bit A/D Converter
The following two registers are used to control the 10-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• Analog input channel specification register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears the ADM0 to 00H.
Figure 12-2. Format of A/D Converter Mode Register 0
A/D conversion control
ADCS0
0 FR02 FR01 FR00 0 0 0ADM0
Symbol Address After reset R/W
FF80H 00H R/W
<7>6543210
ADCS0
0
1
Conversion disabled
Conversion enabled
A/D conversion time selection
Note 1
FR02
0
0
0
1
1
1
144/f
X
or 144/f
CC
120/f
X
or 120/f
CC
96/f
X
or 96/f
CC
72/f
X
or 72/f
CC
60/f
X
or 60/f
CC
48/f
X
or 48/f
CC
FR01
0
0
1
0
0
1
FR00
0
1
0
0
1
0
Other than above Setting prohibited
@ fCC = 4.0 MHz operation
@ f
X
= 10.0 MHz
Note 2
operation
@ f
X
= 5.0 MHz operation
µ
µ
14.4 s
12 s
Setting prohibited
Note 3
Setting prohibited
Note 3
Setting prohibited
Note 3
Setting prohibited
Note 3
µ
µ
28.8 s
24 s
19.2 s
14.4 s
12 s
Note 4
Setting prohibited
Note 3
36 s
30 s
24 s
18 s
15 s
Setting prohibited
Note 3
µ
µ
µ
µ
µ
µ
µ
µ
Notes 1. Set the A/D conversion time to satisfy the following specifications.
<Expanded-specification products>
When 4.5 V ≤ VDD ≤ 5.5 V: 12
µ
s min.
When 2.7 V ≤ VDD < 4.5 V: 14
µ
s min.
When 1.8 V ≤ VDD < 2.7 V: 28
µ
s min.
<Conventional-specification products>
When 2.7 V ≤ VDD ≤ 5.5 V: 14
µ
s min.
When 1.8 V ≤ VDD < 2.7 V: 28
µ
s min.
2. Expanded-specification products only
3. Setting prohibited because the A/D conversion time does not satisfy the rating shown in Note 1.
4. Can be set only for expanded-specification products when 4.5 V ≤ VDD ≤ 5.5 V. Otherwise, setting
prohibited.
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 157
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
12.5 (5) Timing when A/D conversion result becomes undefined).
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) Analog input channel specification register 0 (ADS0)
The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 12-3. Format of Analog Input Channel Specification Register 0
000000
ADS01 ADS00
ADS0
Symbol Address After reset R/W
FF84H 00H R/W
76543210
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS01
0
0
1
1
ADS00
0
1
0
1
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
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12.4 10-Bit A/D Converter Operation
12.4.1 Basic operation of 10-bit A/D converter
<1> Select the channel for A/D conversion, using analog in put channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a cert ai n period of time, the sample & hold cir cuit is put on h old t o keep the input
analog voltage until A/D conve r sion is completed.
<4> Bit 9 of the successive approximation A/D conversion register (SAR) is set. The tap selector sets the series
resistor string voltage tap to half AVDD.
<5> The ser ies resistor str ing voltage tap is compared wit h the analog in put voltage using the voltage comparator.
If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half
AVDD, the MSB is reset.
<6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows.
• Bit 9 = 1: Three quarters of AVDD
• Bit 9 = 0: One quarter of AVDD
The voltage tap is compared with the analog input voltage. Bit 8 is set or reset according to the result of
comparison.
• Analog input voltage ≥ voltage tap: Bit 8 = 1
• Analog input voltage < voltage tap: Bit 8 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is complet ed for all of the 10 bits, a significant di gital result is left in th e SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The A/D conversion value immediately after starting the A/D conversion operation may
be undefined.
2. When in standby mode, the A/D converter stops operation.
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 159
Figure 12-4. Basic Operation of 10-Bit A/D Converter
Conversion
time
Sampling
time
Sampling A/D conversion
Undefined Conversion
result
Conversion
result
A/D converter
operation
SAR
ADCR0
INTAD0
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D
conversion, the A/D conversion in progress is canceled. In this case, A/D conversion is restarted from the beginning, if
ADCS0 is set (1).
RESET input makes A/D conversion result register 0 (ADCR0) undefined.
12.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
VIN
ADCR0 = INT ( AVDD
× 1,024 + 0.5)
or
AVDD AVDD
(ADCR0 − 0.5) × 1,024 ≤ VIN < (ADCR0 + 0.5) × 1,024
INT( ): Function that returns the integer part of the parenthesized value
VIN: Analog input voltage
AVDD: A/D converter supply voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 12-5 shows the relationship between the analog input voltage and the A/D conversion result.
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
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Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result
1,023
1,022
1,021
3
2
1
0
A/D conversion
result (ADCR0)
1
2,048
1
1,024
3
2,048
2
1,024
5
2,048
3
1,024
2,043
2,048
1,022
1,024
2,045
2,048
1,023
1,024
2,047
2,048
1
Input voltage/AVDD
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 161
12.4.3 Operation mode of 10-bit A/D converter
The 10-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0
(ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can be started only by software; that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to
the analog input pin specified by analog input channel specification register 0 (ADS0).
Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0).
At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and
completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to
ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion
in progress is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0
is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped.
Figure 12-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1 ADCS0 = 0
A/D conversion
ADCR0
INTAD0
ANIn ANIn ANIn ANIm ANIm
Stop
ANIn ANIn ANIm
Conversion is
discontinued;
no conversion
result is preserved.
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
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12.5 Notes on Using 10-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D conver ter enter s the standby mode, it stops operating. Clearing bit 7 (A DCS0) of A/D conver ter
mode register 0 (ADM0) to 0 can reduce the current consumption.
Figure 12-7 shows how to reduce the current consumption in the standby mode.
Figure 12-7. How to Reduce Current Consumption in Standby Mode
AV
DD
AV
SS
P-ch
Series resistor string
ADCS0
(2) Input range for the ANI0 to ANI3 pins
Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or greater or
AVSS or lower (even if within the absolute maximum ratings) is input a conversion channel, the conversion
output of the channel becomes undefined, and the conversion output of the other channels may also be
affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and
reading from ADCR0
Reading from ADCR0 takes precedence. After reading, the new convers ion result is written to ADCR0.
<2> Conflict between wr iting to A DCR0 at the end of conversion and wr iting t o A/D converter mode re gister 0
(ADM0) or analog input channel specificatio n register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end
interrupt reque st signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and
discarding the first conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of op eration of the A/C conver ter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 12-8 and 12-9.
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
User’s Manual U14643EJ2V0UD 163
Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end A/D conversion end
Normal conversion result Undefined value
Normal conversion result read out Undefined value read out
A/D operation stopped
ADCR0
INTAD0
ADCS0
Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
Normal conversion result
A/D conversion end
Normal conversion result read outA/D operation stopped
ADCR0
INTAD0
ADCS0
(6) Noise prevention
To maintain a resolution of 10 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 12-10.
Figure 12-10. Analog Input Pin Treatment
C = 100 to 1000 pF
If noise of AV
DD
or greater or AV
SS
or lower is
likely to come to the AV
DD
pin, clamp the voltage
at the pin by attaching a diode with a small V
F
(0.3 V or lower).
AV
SS
V
SS
AV
DD
V
DD
ANI0 to ANI3
CHAPTER 12 10-BIT A/D CONVERTER (
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(7) ANI0 to ANI3
The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise, the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may
occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse
to pins adjacent to the analog input pin being A/D converted.
(8) Input impedance of ANI0 to ANI3 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs
sampling.
Therefore at times other than sampling, only the leakage current flows. During sampling, the current for
charging the capacitor also flows, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source
be set to 10 kΩ or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure
12-10).
(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In
this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even
when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.
Figure 12-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
A/D conversion
ADCR0
INTAD0
ANIn ANIn ANIm
ANIn ANIn ANIm
ANIm
ANIm
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
CHAPTER 12 10-BIT A/D CONVERTER (
µ
PD789114A, 789134A SUBSERIES)
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(10) AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
input circuit.
Therefore, if the application is designed to be changed to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 12-12.
Figure 12-12. AVDD Pin Treatment
Main power
source
Backup
capacitor
V
DD
AV
DD
V
SS
AV
SS
(11) Input impedance of the AVDD pin
A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher
reference voltage error.
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CHAPTER 13 SERIAL INTERFACE 20
13.1 Functions of Serial Interface 20
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(2) Asynchronous serial interface (UART) mode
This mode is used to transmit and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface channel 0 contains a dedicated UART baud rate generator, enabling communication over a
wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock
pulse at the ASCK20 pin.
It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because
the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the
baud rate generator, there may be problems in transmit/receive operations.
(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines
(SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time
for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB
or LSB, channel 0 can be connected to any device regardless of whether that device is designed for MSB-first
or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional clocked serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.
13.2 Serial Interface 20 Configuration
Serial interface 20 consists of the following hardware.
Table 13-1. Configuration of Serial Interface 20
Item Configuration
Registers Transmit shift register 20 (TXS20)
Receive shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control registers Serial operating mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
Port mode register 2 (PM2)
Port 2 (P2)
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 167
Figure 13-1. Block Diagram of Serial Interface 20
Internal bus
Receive buffer
register 20 (RXB20)
Switching of first bit
Asynchronous serial
interface status register 20
Serial operation mode
register 20 (CSIM20)
Receive shift
register 20 (RXS20)
CSIE20
SSE20 DAP20 DIR20
CSCK20
CKP20 PE20 FE20
OVE20 TXE20 RXE20 PS201 PS200
CL20 SL20
Asynchronous serial
interface mode register 20
Transmit shift
register 20 (TXS20) Transmit
shift clock
Selector
CSIE20
DAP20
Data phase
control
Reception
shift clock
SI20/P22/
RxD20
SO20/P21/
TxD20
4
Parity detection
Stop bit detection
Reception data counter
Parity operation
Stop bit addition
Transmission data counter
SL20, CL20, PS200, PS201
Reception enabled
Reception clock
Detection clock
Start bit
detection
Output latch
(P21)
Port mode
register (PM21)
CSIE20
CSCK20
SCK20/P20/
ASCK20
SS20/P23/
CPT20/INTP0
Clock phase
control
Reception detected
Internal clock output
External clock input
Transmission
and reception
clock control
Baud rate
generatorNote
4
TPS203 TPS202 TPS201 TPS200
CSIE20
CSCK20
fX/2 to fX/28
Baud rate generator
control register 20 (BRGC20)
INTST20
INTSR20/INTCSI20
Internal bus
(ASIS20) (ASIM20)
Note Refer to Figure 13-2 for the configuration of the baud rate generator.
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Figure 13-2. Baud Rate Generator Block Diagram
Reception detection clock
Transmission shift clock
Reception shift clock
Reception detection
TXE20
RXE20
CSIE20
Selector
Selector
Selector
1/2
1/2
Transmission
clock counter
Reception
clock counter
4
f
X
/2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
2
SCK20/ASCK20/P20
TPS203 TPS202 TPS201 TPS200
Baud rate generator
control register 20
(BRGC20)
Internal bus
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User’s Manual U14643EJ2V0UD 169
(1) Transmit shift register 20 (TXS20)
TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20
triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any
attempt to read from TXS20 results in a value being read from RXB20.
(2) Receive shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 transfers the receive data to receive buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Receive buffer register 20 (RXB20)
RXB20 holds receive data. New receive data is transferred from receive shift register 0 (RXS20) per 1 byte of
data received.
When the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the
MSB is always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written to.
RESET input makes RXB20 undefined.
Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any
attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmission controller
The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data in
transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20
(ASIM20).
(5) Reception controller
The reception controller controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected,
asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error.
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13.3 Serial Interface 20 Control Registers
Serial interface 20 is controlled by the following six registers.
• Serial operating mode register 20 (CSIM20)
• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) Serial operating mode register 20 (CSIM20)
CSIM20 is used to make the settings related to 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
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User’s Manual U14643EJ2V0UD 171
Figure 13-3. Format of Serial Operating Mode Register 20
CSIE20
0
1
3-wire serial I/O mode operation control
CSIE20
SSE20
00
DAP20 DIR20 CSCK20 CKP20
CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation disabled
Operation enabled
DIR20
0
1
First-bit specification
MSB
LSB
CSCK20
0
1
3-wire serial I/O mode clock selection
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
SSE20
0
1
Not used
Used
DAP20
0
1
3-wire serial I/O mode data phase selection
Output at falling edge of SCK20
Output at rising edge of SCK20
SS20-pin selection Function of SS20/P23 pin
Port function
0
1
Communication status
Communication enabled
Communication enabled
Communication disabled
CKP20
0
1
3-wire serial I/O mode clock phase selection
Clock is active low, and SCK20 is at high level in the idle state
Clock is active high, and SCK20 is at low level in the idle state
Cautions 1. Bits 4 and 5 must be fixed to 0.
2. CSIM20 must be cleared to 00H if UART mode is selected.
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(2) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is used to make the settings related to asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Figure 13-4. Format of Asynchronous Serial Interface Mode Register 20
TXE20
0
1
Transmit operation control
TXE20 RXE20 PS201 PS200 CL20 SL20
00ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stop
Transmit operation enable
RXE20
0
1
Receive operation control
Receive operation stop
Receive operation enable
PS201
0
0
1
1
Parity bit specification
PS200
0
1
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
CL20
0
1
Transmit data character length specification
7 bits
8 bits
SL20
0
1
Transmit data stop bit length
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operating modes after halting the serial transmit/receive operation.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 173
Table 13-2. Serial Interface 20 Operating Mode Settings
(1) Operation stopped mode
ASIM20 CSIM20
TXE20 RXE20 CSIE20 DIR20 CSCK20
PM22 P21 PM21 P21 PM20 P20 First Bit Shift
Clock
P22/SI20/RxD20
Pin Function
P21/SO20/TxD20
Pin Function
P20/SCK20/
ASCK20 Pin
Function
0 0 0 × × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 − − P22 P21 P20
Other than above Setting prohibited
(2) 3-wire serial I/O mode
ASIM20 CSIM20
TXE20 RXE20 CSIE20 DIR20 CSCK20
PM22 P21 PM21 P21 PM20 P20 First Bit Shift
Clock
P22/SI20/RxD20
Pin Function
P21/SO20/TxD20
Pin Function
P20/SCK20/
ASCK20 Pin
Function
0 1 × External
clock
SCK20 input 1 0
1 0 1
MSB
Internal
clock
SCK20 output
0 1 × External
clock
SCK20 input
0 0
1 1
1
×Note 1 ×Note 2 0 1
0 1
LSB
Internal
clock
SI20Note 2 SCK20(CMOS
output)
SCK20 output
Other than above Setting prohibited
(3) Asynchronous serial interface mode
ASIM20 CSIM20
TXE20 RXE20 CSIE20 DIR20 CSCK20
PM22 P21 PM21 P21 PM20 P20 First Bit Shift
Clock
P22/SI20/RxD20
Pin Function
P21/SO20/TxD20
Pin Function
P20/SCK20/
ASCK20 Pin
Function
1 × External
clock
ASCK20 input 1 0 0 0 0
×Note 1 ×Note 1 0 1
×Note 1 ×Note 1 Internal
clock
P22 TxD20
(CMOS output)
P20
1 × External
clock
ASCK20 input 0 1 0 0 0 1 × ×Note 1 ×Note 1
×Note 1 ×Note 1 Internal
clock
P21
P20
1 × External
clock
ASCK20 input 1 1 0 0 0 1 × 0 1
×Note 1 ×Note 1
LSB
Internal
clock
RD20
TxD20
(CMOS output)
P20
Other than above Setting prohibited
Notes 1. These pins can be used for port functions.
2. When only transmission is used, these pins can be used as P22 (CMOS I/O).
Remark ×: don’t care.
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(3) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is
set.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.
Figure 13-5. Format of Asynchronous Serial Interface Status Register 20
PE20
0
1
Parity error flag
00000PE20 FE20
OVE20
ASIS20
Symbol Address After reset R/W
FF71H 00H R
76543210
No parity error has occurred.
A parity error has occurred (when the transmission parity and reception parity do not match).
FE20
0
1
Framing error flag
No framing error has occurred.
A framing error has occurred (when no stop bit is detected).Note 1
OVE20
0
1
Overrun error flag
No overrun error has occurred.
An overrun error has occurred.Note 2
(Before data was read from the reception buffer register, the subsequent reception sequence was
completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface
mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time
the data is received an overrun error will occur.
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User’s Manual U14643EJ2V0UD 175
(4) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the ser ial clock for the serial interface.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Figure 13-6. Format of Baud Rate Generator Control Register 20
TPS203
0
0
0
0
0
0
0
0
1
Selection of source clock for baud rate generator
TPS203 TPS202 TPS201 TPS200
0000BRGC20
Symbol Address After reset R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
External clock pulse input at the ASCK20 pin
Note 2
Setting prohibited
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
Other than above
TPS201
0
0
1
1
0
0
1
1
0
TPS200
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
−
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
@ f
X
= 10.0 MHz
Note 1
operation
@ f
X
= 5.0 MHz operation
Notes 1. Expanded-specification products only
2. An external clock can only be used in UA RT mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of
baud rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 2.5 MHz in UART mode because n = 1 exceeds the
rating of the baud rate.
3. Be sure not to select n = 2 when fX > 5.0 MHz in UART mode because n = 2 exceeds the
rating of the baud rate.
4. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1
exceeds the rating of the serial clock.
5. When the external input clock is selected, set port mode register 2 (PM2) in input mode.
Remarks 1. f
X: System clock oscillation frequency (ceramic/crystal oscillation)
2. n: Value specified in TPS200 to TPS203 (1 ≤ n ≤ 8)
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD
176
The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a
signal divided from the clock input from the ASCK20 pin.
(a) Generation of baud rate UART transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the
system clock is estimated by using the following expression.
fX
[Baud rate] = 2n + 1 × 8 [bps]
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Val ues in Figure 13-6 specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)
Table 13-3. Example of Relationship Between Syste m C lock and Baud Rate
fX = 10.0 MHzNote fX = 5.0 MHz fX = 4.9152 MHz Baud Rate
(bps) n BRGC20
Setting Error
(%) n BRGC20
Setting Error
(%) n BRGC20
Setting Error
(%)
1,200 − − 8 70H 8 70H
2,400 8 70H 7 60H 7 60H
4,800 7 60H 6 50H 6 50H
9,600 6 50H 5 40H 5 40H
19,200 5 40H 4 30H 4 30H
38,400 4 30H 3 20H 3 20H
76,800 3 20H
1.73
2 10H
1.73
2 10H
0
Note Expanded-spe cification produ cts only.
Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate.
2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 177
(b) Generation of baud rate UART transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate
generated from the clock input from the ASCK20 pin is estimated by using the following expression.
fASCK
[Baud rate] = 16 [bps]
fASCK: Frequency of clock pulse received at the ASCK20 pin
Table 13-4. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps) ASCK20 Pin Input Frequency (kHz)
75 1.2
150 2.4
300 4.8
600 9.6
1,200 19.2
2,400 38.4
4,800 76.8
9,600 153.6
19,200 307.2
31,250 500.0
38,400 614.4
(c) Generation of serial clock from system clock in 3-wire serial I/O mode
The serial clock is generated by dividing the system clock. The serial clock frequency is estimated by
using the following expression. BRGC20 does not need to be set when an external serial clock is input to
the SCK20 pin.
fX
Serial clock frequency = 2n + 1 [Hz]
fX: System clock oscillation frequency
n: Value determined by the settings of TPS200 to TPS203 as shown in Figure 13-6 (1 ≤ n ≤ 8)
CHAPTER 13 SERIAL INTERFACE 20
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13.4 Operation of Serial Interface 20
Serial interface 20 provides the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
13.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O port pins.
(1) Register setting
Operation stop mode is set by serial operating mode register 20 (CSIM20) and asynchronous serial interface
mode register 20 (ASIM20).
(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
CSIE20
0
1
Operation control in 3-wire serial I/O mode
CSIE20
SSE20 0 0
DAP20
DIR20
CSCK20
CKP20
CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation disabled
Operation enabled
Caution Be sure to clear bits 4 and 5 to 0.
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200 CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
Receive operation control
Caution Be sure to clear bits 0 and 1 to 0.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 179
13.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the star t bit is transmitted/received and thus full-duplex communication is
possible.
This device inc orporates a UART-dedicated b aud rate g ene rator that enables communication at the desired transfer
rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK pin.
The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI
standard.
It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because the
frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate
generator, there may be problems in transmit/receive operations.
(1) Register setting
The UART mode is set by serial operating mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control
register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2).
CHAPTER 13 SERIAL INTERFACE 20
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(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
CSIE20
0
1
3-wire serial I/O mode operation control
CSIE20
SSE20
00
DAP20 DIR20 CSCK20 CKP20
CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation disabled
Operation enabled
DIR20
0
1
First-bit specification
MSB
LSB
CSCK20
0
1
3-wire serial I/O mode clock selection
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
SSE20
0
1
Not used
Used
DAP20
0
1
3-wire serial I/O mode data phase selection
Output at falling edge of SCK20
Output at rising edge of SCK20
SS20-pin selection Function of SS20/P23 pin
Port function
0
1
Communication status
Communication enabled
Communication enabled
Communication disabled
CKP20
0
1
3-wire serial I/O mode clock phase selection
Clock is active low, and SCK20 is high level in the idle state
Clock is active high, and SCK20 is low level in the idle state
Cautions 1. Bits 4 and 5 must be fixed to 0.
2. When UART mode is selected, clear CSIM20 to 00H.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 181
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200 CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
0
1
0
0
0
1
0
1
1
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
Receive operation control
PS201 Parity bit specification
PS200
CL20
0
1
SL20
Character length specification
7 bits
8 bits
1 bit
2 bits
Transmit data stop bit length specification
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Switch operating modes after halting the serial transmit/receive operation.
CHAPTER 13 SERIAL INTERFACE 20
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(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.
00000PE20 FE20
OVE20
ASIS20
Symbol Address After reset R/W
FF71H 00H R
76543210
PE20
0
1
Parity error flag
No parity error has occurred.
A parity error has occurred (when the transmission parity and reception parity do not match).
FE20
0
1
Framing error flag
No framing error has occurred.
A framing error has occurred (when no stop bit is detected).Note 1
OVE20
0
1
Overrun error flag
No overrun error has occurred.
An overrun error has occurred.Note 2
(Before data was read from the reception buffer register, the subsequent reception sequence was
completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed
with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every
time the data is received an overrun error will occur.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 183
(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
TPS203
0
0
0
0
0
0
0
0
1
TPS203 TPS202 TPS201 TPS200
0000BRGC20
R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/22
f
X
/23
f
X
/24
f
X
/25
f
X
/26
f
X
/27
f
X
/28
TPS201
0
0
1
1
0
0
1
1
0
TPS200
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
−
Setting prohibited
Symbol Address After reset
Selection of source clock for baud rate generator
External clock input to ASCK20 pin
Other than above
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
@ f
X
= 10.0 MHz
Note
operation @ f
X
= 5.0 MHz operation
Note Expanded-specification prod ucts only
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output
of baud rate generator is disrupted and communications cannot be performed
normally. Be sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the
baud rate.
3. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the
baud rate.
4. When the external input clock is selected, set port mode register 2 (PM2) to input
mode.
Remarks 1. f
X: System clock oscillation frequency (ceramic/crystal oscillati on)
2. n: Values sp ecified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)
The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a
signal divided from the clock input from the ASCK20 p in.
(i) Generation of baud rate transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated from
the system clock is estimated by using the following expression.
fX
[Baud rate] = 2n + 1 × 8 [bps]
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Values in the above table specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)
CHAPTER 13 SERIAL INTERFACE 20
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Table 13-5. Example of Relationship Between Syste m C lock and Baud Rate
fX = 10.0 MHzNote fX = 5.0 MHz fX = 4.9152 MHz Baud Rate
(bps) n BRGC20
Setting Error
(%) n BRGC20
Setting Error
(%) n BRGC20
Setting Error
(%)
1,200 − − 8 70H 8 70H
2,400 8 70H 7 60H 7 60H
4,800 7 60H 6 50H 6 50H
9,600 6 50H 5 40H 5 40H
19,200 5 40H 4 30H 4 30H
38,400 4 30H 3 20H 3 20H
76,800 3 20H
1.73
2 10H
1.73
2 10H
0
Note Expanded-spe cification produ cts only.
Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate.
2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate.
(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud
rate generated from the clock input from the ASCK20 pin is estimated by using the following
expression.
fASCK
[Baud rate] = 16 [bps]
fASCK: Frequency of clock input to ASCK20 pin
Table 13-6. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps) ASCK20 Pin Input Frequency (kHz)
75 1.2
150 2.4
300 4.8
600 9.6
1,200 19.2
2,400 38.4
4,800 76.8
9,600 153.6
19,200 307.2
31,250 500.0
38,400 614.4
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 185
(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit,
character bits, parity bit and stop bit(s).
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out using asynchronous serial interface mode register 20 (ASIM20).
Figure 13-7. Asynchronous Serial Interface Transmit/Receive Data Format
D0 D1 D2 D3 D4 D5 D6 D7
Parity
bit Stop bit
Start
bit
One data frame
• Start bits ..................... 1 bit
• Character bits .............. 7 bits/8 bits
• Parity bits..................... Even parity/odd parity/0 parity/no parity
• Stop bits ...................... 1 bit/2 bits
When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always “0”.
The serial transfer rate is selected by baud rate generator control register 20 (BRGC20).
If a serial data receive error occurs, the receive error contents can be determined by reading the status of
asynchronous serial interface status register 20 (ASIS20).
CHAPTER 13 SERIAL INTERFACE 20
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit
is used on the transmitting side and the receiving side. With even parity and odd parity, a “1” bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The transmission operation is controlled so that the number of bits with a value of “1” in the transmit
data including parity bit is even. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data: 1
The number of bits with a value of “1” is an even number in transmit data: 0
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is odd, a parity error is generated.
(ii) Odd parity
• At transmission
Opposite to even parity, the transmission operation is controlled so that the number of bits with a
value of “1” in the transmit data including parity bit is odd. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data: 0
The number of bits with a value of “1” is an even number in transmit data: 1
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is even, a parity error is generated.
(iii) 0 Parity
When transmitting, the parity bit is set to “0” irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error does not occur, irrespective
of whether the parity bit is set to “0” or “1”.
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no
parity bit. Since there is no parity bit, a parity error does not occur.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 187
(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit,
parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.
Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
STOP
ParityD7D6D2D1D0
START
TxD20 (Output)
INTST20
(b) Stop bit length: 2
STOP
ParityD7D6D2D1D0
START
TxD20 (Output)
INTST20
Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit
operation. If the ASIM20 register is rewritten during transmission, subsequent
transmission may not be performed (the normal state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by
INTST20.
CHAPTER 13 SERIAL INTERFACE 20
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(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by BRGC20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time
determined by the specified baud rate has passed, the data sampling start timing signal is output. If the
RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the
3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a
parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20
is generated.
If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In
this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not
changed, and INTSR20 is not generated.
Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
ParityD7D6D2D1D0
START
RxD20 (Input)
INTSR20
Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 189
(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. The data reception result error flag is set in asynchronous serial interface status register 20
(ASIS20). Receive error causes are shown in Table 13-7.
It is possible to determine wh at kind of error occurred during reception by reading the co ntents of ASIS20
in the reception error interrupt servicing (refer to Table 13-7 and Figure 13-10).
The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 13-7. Receive Error Causes
Receive Errors Cause
Parity error Transmission-time parity specification and receive data parity do not match
Framing error Stop bit not detected
Overrun error Reception of next data is completed before data is read from receive register buffer
Figure 13-10. Receive Error Timing
(a) Parity error occurred
STOP
ParityD7D6D2D1D0
START
RxD20 (Input)
INTSR20
(b) Framing error or overrun error occurred
STOP
ParityD7D6D2D1D0
START
RxD20 (Input)
INTSR20
Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register 20
(RXB20) or receiving the next data. To ascertain the error contents, read ASIS20
before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
CHAPTER 13 SERIAL INTERFACE 20
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(f) Reading receive data
When the reception c ompletion interr upt (INTSR20) occurs, receive data can be read by reading the value
of receive buffer register 20 (RXB20).
To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled
(RXE20 = 1).
Remark However, if it is necessary to read receive data after reception has stopped (RXE20 = 0), read
using either of the following methods.
(a) Read after setting RXE20 = 0 after waiting for one cycle or more of the source clock
selected by BRGC20.
(b) Read after bit 2 (DIR20) of serial operating mode register 20 (CSIM20) is set (1).
Program example of (a) (BRGC20 = 00H (source clock = fX/2))
INTRXE: ;<Reception completion interrupt routine>
NOP ;2 clocks
CLR1 RXE20 ;Reception stopped
MOV A, RXB20 ;Read receive data
Program example of (b)
INTRXE: ;<Reception completion interrupt routine>
SET1 CSIM20.2 ;DIR20 flag is set to LSB first
CLR1 RXE20 ;Reception stopped
MOV A, RXB20 ;Read receive data
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 191
(3) UART mode cautions
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before
executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and receive completion interrupt 20 (INTSR20) are as
follows.
ParityRxD20 Pin
RXB20
INTSR20
<3><1>
<2>
When RXE20 is set to 0 at the time indicated by <1>, RXB20 holds the previous data and does not generate
INTSR20.
When RXE20 is set to 0 at the time indicated by <2>, RXB20 renews the data and does not generate
INTSR20.
When RXE20 is set to 0 at the time indicated by <3>, RXB20 renews the data and generates INTSR20.
CHAPTER 13 SERIAL INTERFACE 20
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13.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate a
conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input
(SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 20 (CSIM20), asynchronous
serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20), port mode
register 2 (PM2), and port 2 (P2).
(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
CSIE20
0
1
3-wire serial I/O mode operation control
CSIE20
SSE20
00
DAP20 DIR20 CSCK20 CKP20
CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation disabled
Operation enabled
DIR20
0
1
First-bit specification
MSB
LSB
CSCK20
0
1
3-wire serial I/O mode clock selection
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
SSE20
0
1
Not used
Used
DAP20
0
1
3-wire serial I/O mode data phase selection
Output at falling edge of SCK20
Output at rising edge of SCK20
SS20-pin selection Function of SS20/P23 pin
Port function
0
1
Communication status
Communication enabled
Communication enabled
Communication disabled
CKP20
0
1
3-wire serial I/O mode clock phase selection
Clock is active low, and SCK20 is at high level in the idle state
Clock is active high, and SCK20 is at low level in the idle state
Caution Bits 4 and 5 must be fixed to 0.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 193
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200 CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
0
1
0
0
0
1
0
1
1
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
Receive operation control
PS201 Parity bit specification
PS200
CL20
0
1
SL20
Character length specification
7 bits
8 bits
1 bit
2 bits
Transmit data stop bit length specification
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. When the 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switching operation modes must be performed after the serial transmit/receive
operation is halted.
CHAPTER 13 SERIAL INTERFACE 20
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
TPS203
0
0
0
0
0
0
0
0
TPS203 TPS202 TPS201 TPS200
0000BRGC20
R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
TPS201
0
0
1
1
0
0
1
1
TPS200
0
1
0
1
0
1
0
1
n
1
2
3
4
5
6
7
8
Setting prohibited
Symbol Address After reset
Other than above
fX/2
fX/22
fX/23
fX/24
fX/25
fX/26
fX/27
fX/28
Selection of source clock for baud rate generator
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
@ fX = 10.0 MHzNote operation @ fX = 5.0 MHz operation
Note Expanded-specification products only
Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud
rate generator output is disrupted and communication cannot be performed normally.
Be sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1
exceeds the rating of the serial clock.
Remarks 1. f
X: System clock oscillation frequency (ceramic/crystal oscillation)
2. n: Values specified by TPS200 to TPS203 (1 ≤ n ≤ 8)
If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203
bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following for mula.
When the seria l clock is input from off-chip, setting BRGC20 is not necessary.
fX
Serial clock frequency = 2n + 1 [Hz]
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Val ues in the above table specified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 195
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is
transmitted/received bit by bit in synchronization with the serial clock.
The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed in
synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and
output from the SO20 pin. Also, receive data input to the SI0 pin is latched in the receive buffer register
(RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and an interrupt
request signal (INTCSI20) is generated.
Figure 13-11. 3-Wire Serial I/O Mode Timing (1/7)
(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
12345678
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SCK20
SO20 Note
SI20
SIO20
Write
INTCSI20
Note The value of the last bit previously output is output.
CHAPTER 13 SERIAL INTERFACE 20
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Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7)
(ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SCK20
SI20
Note
SO20
SIO20
Write
INTCSI20
Note The value of the last bit previously output is output.
(iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7
Note 1
DO6 DO5 DO4 DO3 DO2 DO1
DO0Note 2
SCK20
SI20
SO20 Hi-Z Hi-Z
SS20
SIO20
Write
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 197
Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7)
(iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
12345678
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SCK20
SO20
SI20
SIO20
Write
INTCSI20
(v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SCK20
SI20
SO20
SIO20
Write
INTCSI20
SIO20 Write (master)
Note
Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first
bit before the first rising of SCK20.
CHAPTER 13 SERIAL INTERFACE 20
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Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7)
(vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 Note 2
SCK20
SI20
Hi-Z Hi-Z
SO20
SIO20
Write
SS20
INTCSI20
DO0
SIO20 Write (master)Note 1
Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the
first bit before the first rising of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
(vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
12345678
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SCK20
SO20
SI20
SIO20
Write
INTCSI20
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 199
Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7)
(viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SCK20
SI20
SO20
SIO20
Write
INTCSI20
SIO20 Write (master)
Note
Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first
bit before the first falling of SCK20.
(ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1
Note 2
SCK20
SI20
Hi-Z Hi-Z
SO20
SIO20
Write
SS20
INTCSI20
DO0
SIO20 Write (master)
Note 1
Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the
first bit before the first falling of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
CHAPTER 13 SERIAL INTERFACE 20
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Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7)
(x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
12345678
DO7Note DO6 DO5 DOI4 DO3 DO2 DO1
DI7 DI6 DI5 DI4 DI3 DI2 DI1
SCK20
SO20
SI20
SIO20
Write
INTCSI20
DI0
DO0
Note The value of the last bit previously output is output.
(xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1
SCK20
SI20
SO20
SIO20
Write
INTCSI20
DO7Note DO6 DO5 DOI4 DO3 DO2 DO1 DO0
DI0
Note The value of the last bit previously output is output.
CHAPTER 13 SERIAL INTERFACE 20
User’s Manual U14643EJ2V0UD 201
Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7)
(xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1)
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1
DO0
Note 2
SCK20
SI20
Note 1
SO20 Hi-Z Hi-Z
SS20
SIO20
Write
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
(3) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register (TXS20/SIO20) when the following
two conditions are satisfied.
• Serial operating mode register 20 (CSIM20) bit 7 (CSIE20) = 1
• Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer.
Caution If CSIE20 is set to “1” after data is written to TXS20/SIO20, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates an interrupt request signal
(INTCSI20).
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CHAPTER 14 MULTIPLIER
14.1 Multiplier Function
The multiplier has the following function.
• Calculation of 8 bits × 8 bits = 16 bits
14.2 Multiplier Configuration
(1) 16-bit multiplication result storage register 0 (MUL0)
This register stores the 16-bit result of multiplication.
This register holds the result of multiplication after 16 CPU clocks have elapsed.
MUL0 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can
also be manipulated with an 8-bit memory manipulation instruction. When using an 8-bit
memory manipulation instruction, however, access the register by means of direct
addressing.
(2) Multiplication data registers A and B (MRA0 and MRB0)
These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0.
MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instructions.
RESET input makes these registers undefined.
Figure 14-1 shows the block diagram of the multiplier.
CHAPTER 14 MULTIPLIER
User’s Manual U14643EJ2V0UD 203
Figure 14-1. Block Diagram of Multiplier
Internal bus
Selector
Counter value
3CPU clock
Start Clear
Counter output
16-bit
adder
16-bit multiplication result
storage register 0 (Master) (MUL0)
16-bit multiplication result
storage register 0 (Slave)
Multiplication data
register A (MRA0)
Multiplication data
register B (MRB0)
Internal bus
3-bit counter
MULST0 Reset
Multiplier control
register 0 (MULC0)
CHAPTER 14 MULTIPLIER
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14.3 Multiplier Control Register
The multiplier is controlled by the following register.
• Multiplier control register 0 (MULC0)
MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-2. Format of Multiplier Control Register 0
MULST0
0
1
Multiplier operation start control bit
0000000
MULST0
MULC0
Symbol Address After reset R/W
FFD2H 00H R/W
76543210
Stop operation after resetting counter to 0.
Enable operation
Operation stopped
Operation in progress
Operating status of multiplier
Caution Be sure to clear bits 1 to 7 to 0.
CHAPTER 14 MULTIPLIER
User’s Manual U14643EJ2V0UD 205
14.4 Multiplier Operation
The multiplier of the
µ
PD789104A/114A/124A/134A Subseries can execute the calculation of 8 bits × 8 bits = 16
bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting MULST0.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is
incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the
data.
<4> While MULST0 is low, the counter and slave are cleared.
Figure 14-3. Multiplier Operation Timing
AA
D3
000B
00AA
0000
001B 010B 011B 100B 101B 110B 111B 000B
0154 0000 0000 0AA0 0000 2A80 5500 00AA
00AA 01FE 01FE 01FE 0C9E 0C9E 371E 8C1E
00AA 01FE 01FE 01FE 0C9E 0C9E 371E 0000
CPU clock
MRA0
MRB0
MULST0
Counter
Selector output
MUL0
(Master)
(Slave)
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CHAPTER 15 INTERRUPT FUNCTIONS
15.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
There is one non-maskable interrupt source, which is from the watchdog timer.
(2) Maskable interrupt
These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Ta ble 15-1.
A standby release signal is generated.
There are nine maskable interrupt sources: three external interrupts and six internal interrupts.
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 207
15.2 Interrupt Sources and Configuration
There are total of 10 non-maskable and maskable interrupt sources (refer to Table 15-1).
Table 15-1. Interrupt Source List
Interrupt Source Interrupt Type PriorityNote 1
Name Trigger
Internal/
External Vector
Table
Address
Basic
Configuration
TypeNote 2
Non-
maskable − INTWDT Watchdog timer overflow (watchdog timer mode 1
selected) (A)
0 INTWDT Watchdog timer overflow (interval timer mode
selected)
Internal 0004H
(B)
1 INTP0 0006H
2 INTP1 0008H
3 INTP2
Pin input edge detection External
000AH
(C)
INTSR20 End of serial interface 20 UART reception 4
INTCSI20 End of serial interface 20 3-wire transfer
000CH
5 INTST20 End of serial interface 20 UART transmission 000EH
6 INTTM80 Generation of 8-bit timer/event counter 80 match
signal 0010H
7 INTTM20 Generation of 16-bit timer 20 match signal 0012H
Maskable
8 INTAD0 A/D conversion completion signal
Internal
0014H
(B)
Notes 1. Pr iority is the p rior ity applicable when two or more maskable interrupts are simultaneously generated. 0
is the highest priority and 8 is the lowest priority.
2. Basic configuration types A to C correspond to A to C in Figure 15-1.
Remark As the interrupt source of the watchdog timer (INTWD T), either a non-maskable interrupt or a maskable
interrupt (internal) can be selected.
CHAPTER 15 INTERRUPT FUNCTIONS
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Figure 15-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Interrupt request Vector table
address generator
Standby release signal
(B) Internal maskable interrupt
MK
IF
IE
Internal bus
Interrupt request
Vector table
address generator
Standby release signal
(C) External maskable interrupt
MK
IF
IE
Internal bus
External interrupt mode
register (INTM0)
Interrupt
request
Edge
detector
Vector table
address generator
Standby
release signal
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 209
15.3 Interrupt Function Control Registers
The following four registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0, IF1)
• Interrupt mask flag registers (MK0, MK1)
• External inter rupt mode register (INTM0)
• Program status word (PSW)
Table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.
Table 15-2. Flags Corresponding to Interrupt Request Signals
Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag
INTWDT
INTP0
INTP1
INTP2
INTSR20/INTCSI20
INTST20
INTTM80
INTTM20
INTAD0
TMIF4
PIF0
PIF1
PIF2
SRIF20
STIF20
TMIF80
TMIF20
ADIF0
TMMK4
PMK0
PMK1
PMK2
SRMK20
STMK20
TMMK80
TMMK20
ADMK0
CHAPTER 15 INTERRUPT FUNCTIONS
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(1) Interrupt request flag registers (IF0, IF1)
The interrupt request flag is set to 1 when th e corresponding interru pt request is generated or an instruction is
executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instructio n.
RESET input clears these registers to 00H.
Figure 15-2. Format of Interrupt Request Flag Register
0
1
TMIF20TMIF80 STIF20 SRIF20
PIF2 PIF1 PIF0 TMIF4IF0
R/W
FFE0H 00H R/W
Symbol Address After reset
Interrupt request flag
No interrupt request signal is generated
Interrupt request signal is generated; interrupt request state
××IF×
<6> <5> <4> <3> <2> <1><7> <0>
0000000ADIF0IF1
R/W
FFE1H 00H R/W
Symbol Address After reset
6543217 <0>
Cautions 1. TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If
watchdog timer mode 1 and 2 are used, set the TMIF4 flag to 0.
2. Because por t 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and
the interrupt routine is entered.
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 211
(2) Interrupt mask flag registers (MK0, MK1)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipula tion instruction.
RESET input sets these registers to FFH.
Figure 15-3. Format of Interrupt Mask Flag Register
0
1
TMMK20 TMMK80 STMK20 SRMK20
PMK2 PMK1 PMK0
TMMK4
MK0
R/W
FFE4H FFH R/W
Symbol Address After reset
Interrupt servicing control
Interrupt servicing enabled
Interrupt servicing disabled
<6> <5> <4> <3> <2> <1><7> <0>
××MK×
1111111
ADMK0
MK1
R/W
FFE5H FFH R/W
Symbol Address After reset
6543217 <0>
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 and
2, its value becomes undefined.
2. Because por t 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.
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(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 15-4. Format of External Interrupt Mode Register 0
0
0
1
1
ES21 ES20 ES11 ES10 ES01 ES00 0 0INTM0
R/W
FFECH 00H R/W
76543210
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Symbol Address After reset
INTP0 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP1 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP2 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES00
ES01
ES11 ES10
ES20ES21
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable
interrupts.
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 213
(4) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag used to set maskable interrupt enable/disable is mapped to the PSW.
This register can be read/written in 8-bit units and can carry out operations using bit manipulation and
dedicated instr uctions (EI, DI). W hen a vect ored interrupt request is acknowledged, the PSW is automatically
saved into a stack, and the IE flag is reset to 0. It is restored from the stack by the RETI and POP PSW
instructions.
RESET input sets the PSW to 02H.
Figure 15-5. Program Status Word Configuration
IE Z 0 AC 0 0 1 CYPSW
76543210
IE
0
1
02H
Symbol After reset
Used when normal instruction is executed
Interrupt acknowledgment enable/disable
Disabled
Enabled
CHAPTER 15 INTERRUPT FUNCTIONS
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15.4 Interrupt Servicing Operation
15.4.1 Non-maskable interrupt request acknowledgment operation
A non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control an d takes precedence over all other interrupts.
When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, th e
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 15-6 shows the flowchar t from non-maskable interrupt request g eneration to acknowledgment. Figure 15-7
shows the timing of non-maskable interrupt request acknowledgment. Figure 15-8 shows the acknowledgment
operation if multiple non-maskable interrupts are generated.
Caution During non-maskable interrupt servicing program execution, do not input another non-maskable
interrupt request; if it is input, the servicing program will be interrupted and the new interrupt
request will be acknowledged.
CHAPTER 15 INTERRUPT FUNCTIONS
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Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment
Start
WDTM4 = 1
(watchdog timer mode
is selected) Interval timer
No
WDT
overflows No
Yes
Reset processing
No
Yes
Yes
Interrupt request is generated
Interrupt servicing is started
WDTM3 = 0
(non-maskable interrupt
is selected)
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 15-7. Timing of Non-Maskable Interrupt Request Acknowledgment
Instruction Instruction
Save PSW and PC, and
jump to interrupt servicing
Interrupt servicing
program
CPU processing
TMIF4
Figure 15-8. Acknowledging Non-Maskable Interrupt Request
Second interrupt servicing
First interrupt servicing
NMI request
(second)
NMI request
(first)
Main routine
CHAPTER 15 INTERRUPT FUNCTIONS
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15.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interr upt servicing after a maskable interru pt request has been gene rated is shown in
Table 15-3.
Refer to Figures 15-10 and 15-11 for the interrupt request acknowledgment timing.
Table 15-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time Maximum TimeNote
9 clocks 19 clocks
Note The wait time is maximum when an
interrupt request is generated
immediately before the BT or BF
instruction.
1
Remark 1 clock: fCPU (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigne d the highest priority.
A pending interrupt is acknowledged when the status in which it can be acknowledged is set.
Figure 15-9 shows the algorithm of acknowledging interrupt requests.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded t o
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 217
Figure 15-9. Interrupt Acknowledgment Program Algorithm
Start
××IF = 1 ?
××MK = 0 ?
IE = 1 ?
Vectored interrupt
servicing
Yes (Interrupt request generated)
Yes
Yes
No
No
No
Interrupt request pending
Interrupt request pending
××IF: Interrupt request flag
××MK: Interrupt mask flag
IE: Flag to control maskable interrupt request acknowledgment (1 = Enable, 0 = Disable)
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD
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Figure 15-10. Interrupt Request Acknowledgment Timing (Example of MOV A,r)
Clock
CPU
Interrupt
MOV A,r
Save PSW and PC, jump
to interrupt servicing
8 clocks
Interrupt servicing program
If an interrupt request flag (××IF) is set before instruction clock n (n = 4 to 10) under execution becomes n − 1, the
interrupt is acknowledged after the instruction under execution is complete. Figure 15-10 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment
processing is performed after the MOV A,r instruction is completed.
Figure 15-11. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated at
Last Clock During Instruction Execution)
Save PSW and PC, jump
to interrupt servicing
8 clocks
Interrupt
servicing
program
Clock
CPU
Interrupt
NOP MOV A,r
If an interrupt r equest flag (××IF) is set at the last clock of the instruction, t he interr upt acknowledgment processin g
starts after the next instruction is executed.
Figure 15-11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at
the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is
executed, and then the interrupt acknowledgment processing is performed.
Caution Interrupt requests are held pending while the interrupt request flag register (IF0, IF1) or the
interrupt mask flag register (MK0, MK1) is being accessed.
15.4.3 Multiple interrupt servicing
Multiple interr upt ser vicing, in which an interr upt is acknowledged while another interrupt is be ing ser viced, can b e
executed by prior ity. W hen the prior ity is controlled by the default pr iority and two or more interr upts are generated at
the same time, interrupt ser vicing is p erfor med according to the pr ior ity assigned to each interr upt request in advance
(refer to Table 15-1).
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD 219
Figure 15-12. Example of Multiple Interrupt Servicing
Example 1. Multiple interrupts are acknowledged
INTyy
EI
Main processing
EI
INTyy servicingINTxx servicing
RETI
IE = 0
INTxx
RETI
IE = 0
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupt servicing occurs.
The EI instruction is issue d before each interrupt req uest acknowledgment, and the interr upt requ est acknowledgment
enabled state is set.
Example 2. Multiple interrupt servicing does not occur because interrupts are not enabled
INTyy
EI
Main processing
RETI
INTyy servicingINTxx servicing
IE = 0
INTxx
RETI
INTyy is held pending
IE = 0
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and a multiple interrupt ser vicing does not oc cur. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgment disabled
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U14643EJ2V0UD
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15.4.4 Interrupt request hold
Some instructions may hold the acknowledgment of an instruction request pending until completion of the
execution of the next instruction even if the interrupt reques t (maskable interrupt, non-maskable interrup t, and external
interrupt) is generated during the execution. The following shows such instructions (interrupt request hold
instructions).
• Manipulation instruction for the interrupt request flag registers (IF0, IF1)
• Manipulation instruction for the interrupt mask flag registers (MK0, MK1)
User’s Manual U14643EJ2V0UD 221
CHAPTER 16 STANDBY FUNCTION
16.1 Standby Function and Configuration
16.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as
much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this
mode.
The low voltage of the data memory (VDD = 1.8 V) can be held. Therefore, this mode is useful for holding the
contents of the data memory at an extremely low current consumption.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operations. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode
are all held. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD
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16.1.2 Standby function control register (
µ
PD789104A, 789114A Subseries)
The wait time after the STOP mode is rel eased upon interr upt request unt il the oscillation stabilizes is controlle d by
the oscillation stabilization time select register (OSTS)Note.
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of
217/fX.
Note
µ
PD789104A and 789114A Subseries only.
The
µ
PD789124A and 789134A Subseries do not provide an oscillation stabilization time select register.
The oscillation stabilizatio n time of the
µ
PD789124A and 789134A Subseries is fixed to 27/fCC.
Figure 16-1. Format of Oscillation Stabilization Time Select Register
OSTS2
0
0
1
00000
OSTS2 OSTS1 OSTS0
OSTS
R/W
FFFAH 04H R/W
76543210
OSTS1
0
1
0
2
12
/f
X
2
15
/f
X
2
17
/f
X
OSTS0
0
0
0
Setting prohibited
Symbol Address After reset
Oscillation stabilization time selection
Other than above
µ
@ f
X
= 10.0 MHz
Note
operation @ f
X
= 5.0 MHz operation
409 s
3.28 ms
13.1 ms
819 s
6.55 ms
26.2 ms
µ
Note Expanded-specification products only
Caution The wait time after the STOP mode is released when using a ceramic/crystal oscillator does not
include the time from STOP mode release to clock oscillation start (“a” in the figure below),
regardless of whether STOP mode was released by RESET input or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD 223
16.2 Operation of Standby Function
16.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.
Table 16-1. HALT Mode Operating Status
Item HALT Mode Operating Status
Clock generator System clock can be oscillated.
Clock supply to CPU stops.
CPU Operation stopped
Port (output latch) Holds status before setting the HALT mode.
16-bit timer 20 Operable
8-bit timer/event counter 80 Operable
Watchdog timer Operable
Serial interface 20 Operable
A/D converter Operation stopped
Multiplier Operation stopped
External interrupt OperableNote
Note Maskable interrupt that is not masked
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD
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(2) Releasing HALT mode
The HALT mode can be released by the following three sources.
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able
to be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 16-2. Releasing HALT Mode by Interrupt
HALT
instruction
Standby
release signal
Wait
WaitHALT mode
Operating
mode Operating mode
Clock Oscillation
Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed: 9 to 10 clocks
• When vectored interrupt servicing is not performed: 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD 225
(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as an ordinary reset operation, and program execution is started.
Figure 16-3. Releasing HALT Mode by RESET Input
HALT
instruction
RESET
signal
Wait
Note
Reset
period
HALT mode
Operating
mode
Oscillation
stabilization
wait status
Clock
Operating
mode
Oscillation
stop
Oscillation Oscillation
Note In the
µ
PD789104A and 789114A Subseries,
215/fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation)
In the
µ
PD789124A and 789134A Subseries,
2
7/fCC: 32
µ
s (at fCC = 4.0 MHz operation)
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC: System clock oscillation frequency (RC oscillation)
Table 16-2. Operation After Release of HALT Mode
Releasing Source MK×× IE Operation
0 0 Next address instruction is executed
0 1 Interrupt servicing is executed
Maskable interrupt request
1 × HALT mode is held
Non-maskable interrupt request − × Interrupt servicing is executed
RESET input − − Reset processing
×: don’t care
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD
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16.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Becau se the s tandby mode can be released by an interrupt request signal, the standby mode
is released as soon as it is set if there is an interrupt s ource whose i nterrupt request flag is
set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is
set immediately after the STOP instruction has been executed, the wait time set by the
oscillation stabilization time select register (OSTS) elapses, and then an operation mode is
set.
The operation status in the STOP mode is shown in the following table.
Table 16-3. STOP Mode Operating Status
Item STOP Mode Operating Status
Clock generator System clock oscillation stopped
CPU Operation stopped
Port (output latch) Holds the status before setting the STOP mode
16-bit timer 20 Operation stopped
8-bit timer/event counter 80 OperableNote 1
Watchdog timer Operation stopped
Serial interface 20 OperableNote 2
A/D converter Operation stopped
Multiplier Operation stopped
External interrupt OperableNote 3
Notes 1. Operation is possible only when TI80 is select ed as the count clock.
2. Operation is possible in both 3-wire serial I/O and UART modes while an external clock is being
used.
3. Maskable interrupt that is not masked
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD 227
(2) Releasing STOP mode
The STOP mode can be released by the following two sources.
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to
be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has
elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 16-4. Releasing STOP Mode by Interrupt
STOP
instruction
Standby
release signal
WaitNote
(set time by OSTS)
STOP mode
Operating
mode
Oscillation stabilization
wait status
Clock
Operating
mode
Oscillation
stop Oscillation
Oscillation
Note OSTS is not provided in the
µ
PD789124A and 789134A Subseries, and the wait time is fixed to
27/fCC.
Remark The broken lines indicate the case where the interrupt request that has released the standby
mode is acknowledged.
CHAPTER 16 STANDBY FUNCTION
User’s Manual U14643EJ2V0UD
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(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 16-5. Releasing STOP Mode by RESET Input
STOP
instruction
RESET
signal
Wait
Note
STOP mode
Operating
mode
Oscillation
stabilization
wait status
Clock
Operating
mode
Oscillation
stop Oscillation
Oscillation
Reset
period
Note In the
µ
PD789104A and 789114A Subseries,
215/fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation)
In the
µ
PD789124A and 789134A Subseries,
2
7/fCC: 32
µ
s (at fCC = 4.0 MHz operation)
Remark f
X: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
Table 16-4. Operation After Release of STOP Mode
Releasing Source MK×× IE Operation
0 0 Next address instruction is executed
0 1 Interrupt servicing is executed
Maskable interrupt request
1 × STOP mode is held
RESET input − − Reset processing
×: don’t care
User’s Manual U14643EJ2V0UD 229
CHAPTER 17 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input via RESE T pin
(2) Internal reset by program loop time detection with watchdog timer
External and inter nal resets have no functional differences. In both cases, program execution starts at addresses
0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardwar e
item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is star ted after the oscillation stabiliz ation time has elapsed (refer to Figures 17- 2
to 17-4).
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 17-1. Block Diagram of Reset Function
RESET
Interrupt function
Count clock
Reset controller
Watchdog timer
Over-
flow
Reset signal
Stop
CHAPTER 17 RESET FUNCTION
User’s Manual U14643EJ2V0UD
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Figure 17-2. Reset Timing by RESET Input
X1, CL1
RESET
Internal
reset signal
Port pin
During normal
operation
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Delay
Delay
Hi-Z
Figure 17-3. Reset Timing by Overflow in Watchdog Timer
X1, CL1
Internal
reset signal
Port pin
Overflow in
watchdog timer
During normal operation
Reset period
(oscillation
continues)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Hi-Z
Figure 17-4. Reset Timing by RESET Input in STOP Mode
X1, CL1
RESET
Internal
reset signal
Port pin Hi-Z
Delay
Delay
STOP instruction execution
During normal operation
Stop status
(oscillation
stops)
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
CHAPTER 17 RESET FUNCTION
User’s Manual U14643EJ2V0UD 231
Table 17-1. Hardware Status After Reset (1/2)
Hardware Status After Reset
Program counter (PC)Note 1 The contents of reset vector
tables (0000H and 0001H)
are set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory UndefinedNote 2 RAM
General-purpose registers UndefinedNote 2
Ports (P0 to P2, P5) (output latch) 00H
Port mode registers (PM0 to PM2, PM5) FFH
Pull-up resistor option register 0 (PU0) 00H
Pull-up resistor option register B2 (PUB2) 00H
Processor clock control register (PCC) 02H
Oscillation stabilization time select register (OSTS)Note 3 04H
Timer counter (TM20) 0000H
Compare register (CR20) FFFFH
Mode control register (TMC20) 00H
16-bit timer 20
Capture register (TPC20) Undefined
Timer counter (TM80) 00H
Compare register (CR80) Undefined
8-bit timer/event counter 80
Mode control register (TMC80) 00H
Timer clock select register (TCL2) 00H Watchdog timer
Mode register (WDTM) 00H
Mode register (ADM0) 00H
Input channel specification register (ADS0) 00H
A/D converter
Conversion result register (ADCR0) Undefined
Mode register (CSIM20) 00H
Asynchronous serial interface mode register (ASIM20) 00H
Asynchronous serial interface status register (ASIS20) 00H
Baud rate generator control register (BRGC20) 00H
Transmit shift register (TXS20) FFH
Serial interface 20
Receive buffer register (RXB20) Undefined
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined.
All other hardware remains unchanged after reset.
2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.
3.
µ
PD789104A, 789114A Subseries only
CHAPTER 17 RESET FUNCTION
User’s Manual U14643EJ2V0UD
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Table 17-1. Hardware Status After Reset (2/2)
Hardware Status After Reset
16-bit multiplication result storage register (MUL0) Undefined
Data register A (MRA0) Undefined
Data register B (MRB0) Undefined
Multiplier
Control register (MULC0) 00H
Request flag register (IF0, IF1) 00H
Mask flag register (MK0, MK1) FFH
Interrupts
External interrupt mode register (INTM0) 00H
User’s Manual U14643EJ2V0UD 233
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F913 6A, 78F9136B
The
µ
PD78F9116A and 78F911 6B are versions with flash memor y instead of the inter nal ROM of the mask ROM
versions in the
µ
PD789104A and 789114A Subseries. The
µ
PD78F9136A and 78F9136B are versions with flash
memory instead of the internal ROM of the mask ROM versions in the
µ
PD789124A and 789134A Subseries. The
differences between the flash memory and the mask ROM versions are shown in Table 18-1.
Table 18-1. Differences Bet ween Flash Memory and Mask ROM Versions
Flash Memory Mask ROM
µ
PD78F9116A
µ
PD78F9116B
µ
PD789101A
µ
PD789111A
µ
PD789102A
µ
PD789112A
µ
PD789104A
µ
PD789114A
Item
µ
PD78F9136A
µ
PD78F9136B
µ
PD789121A
µ
PD789131A
µ
PD789122A
µ
PD789132A
µ
PD789124A
µ
PD789134A
ROM 16 KB
(flash memory) 2 KB 4 KB 8 KB Internal
memory
High-speed RAM 256 bytes
Pull-up resistors 12
(software control only) 16 (software control: 12, mask option specification: 4)
VPP pin Provided Not provided
Electrical specifications Refer to the relevant electrical specifications chapt er.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory
versions and mask ROM versions. When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluations for the commercial samples (not engineering samples) of the mask
ROM versions.
2. A/D conversion result register 0 (ADCR0) is manipulated by an 8-bit memory manipulation
instruction or a 16-bit memory manipulation instruction, when used as an 8-bit A/D convert er
(
µ
PD789104A, 789124A Subseries) or 10-bit A/D converter (
µ
PD789114A, 789134A Subseries),
respectively.
However, if the
µ
PD78F9116A and 78F9116B are used as the flash memory versions of the
µ
PD789101A, 789102A, and 789104A, ADCR0 can be manipulated by an 8-bit memory
manipulation instruction, providing an object file has been assembled in the
µ
PD789101A,
789102A, 789104A. If the
µ
PD78F9136A and 78F9136B are used as the flash memor y versions
of the
µ
PD789121A, 789122A, and 789124A, ADCR0 can be manipulated by an 8-bit memory
manipulation instruction, providing an object file has been assembled in the
µ
PD789121A,
789122A, or 789124A.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
234
18.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the
target system (on-board programming). A flash memory writing adapter (program adapter), which is a target board
used exclusively for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities low-quantity, varied model prod uction
• Easy data adjustment when starting mass production
18.1.1 Programming environment
The following shows the environment required for
µ
PD78F9116A, 78F9116B, 78F9136A, and 78F9136B flash
memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (Part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to co ntrol the dedicated flash programmer. Communication between the
host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer to the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 18-1. Environment for Writing Program to Flash Memory
Host machine
RS-232C
USB
Dedicated flash programmer PD78F9116A, 78F9116B,
78F9136A, 78F9136B
VPP
VDD
VSS
RESET
3-wire serial I/O
or UART
or pseudo 3-wire
µ
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 235
18.1.2 Communication mode
Use the communication mode shown in Table 18-2 or 18-3 to perform communication between the dedic ated flash
programmer and the
µ
PD78F9116A, 78F9116B, 78F9136A, or 78F9136B.
Table 18-2. Communication Mode List (
µ
PD78F9116A, 78F9136A)
TYPE SettingNote 1 Communication
Mode COMM PORT SIO Clock CPU Clock Flash Clock Multiple Rate
Pins UsedNote 2 Number of
VPP Pulses
3-wire serial
I/O (SIO3) SIO ch-0
(3-wire, sync.) 100 Hz to
1.25 MHzNote 3 Optional 1 to 5 MHzNote 3 1.0 SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0
UART
(UART0) UART ch-0 4800 to 76800
bpsNote 3, 4 OptionalNote 5 4.91 or 5
MHzNote 3 1.0 TxD20/SO20/P21
RxD20/SI20/P22 8
Pseudo 3-wire Port A
(pseudo 3-
wire)
100 Hz to 1
MHzNote 3 Optional 1 to 5 MHzNote 3 1.0 P00
P01
P02
12
Table 18-3. Communication Mode List (
µ
PD78F9116B, 78F9136B)
TYPE SettingNote 1 Communication
Mode COMM PORT SIO Clock CPU Clock Flash Clock Multiple Rate
Pins UsedNote 2 Number of
VPP Pulses
SIO ch-0
(3-wire, sync.) SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0 3-wire serial
I/O
SIO ch-1
(3-wire, sync.)
100 Hz to
1.25 MHzNote 3 Optional 1 to 10 MHzNote 3 1.0
P00
P01
P02
1
UART UART ch-0 4800 to 76800
bpsNote 3, 4 OptionalNote 5 4.91, 5, or 10
MHzNote 3 1.0 TxD20/SO20/P21
RxD20/SI20/P22 8
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III/Flashpro IV).
2. When the system shifts to the flash memor y programming mode, all the pins that are not used for flash
memory programming are in the same status as that immediately after reset. If the external device
connected to each port does not recognize the status of the port immediately after reset, pins require
appropri ate processing, such as connecting to VDD or VSS via a resistor.
3. The possible setting range differs depending on the voltage. For details, refer to the relevant electrical
specifications chapter.
4. Because signal wave slew also affects UART communication, in addition to the baud rate error,
thoroughly evaluate the slew.
5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on
the board. UART cannot be used with the clock supplied by Flashpro III.
Caution Be sure to select the communication mode according to the number of VPP pulses shown in Table
18-2 or 18-3.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
236
Figure 18-2. Communication Mode Selection Format
10 V
V
SS
V
DD
V
PP
V
DD
V
SS
RESET
12 n
V
PP
pulses
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 237
Figure 18-3. Example of Connection with Dedicated Flash Programmer (1/2)
(a) 3-wire serial I/O mode (SIO ch-0)
VPP1
VDD
RESET
SCK
SO
SI
GND
VPP
VDD, AVDD
RESET
CLKNote 1 X1 (P03Note 2)
SCK20
SI20
SO20
VSS, AVSS
Dedicated flash programmer
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
(b) 3-wire serial I/O mode (SIO ch-1) (
µ
PD78F9116B, 78F9136B only)
VPP1
VDD
RESET
SCK
SO
SI
GND
VPP
VDD, AVDD
RESET
CLKNote 1 X1 (P03Note 2)
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
VSS, AVSS
PD78F9116B, 78F9136B
µ
Dedicated flash programmer
Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a
resonator has already been connected to the X1 pin, the CLK pin does not need to be connected.
2.
µ
PD78F9136A, 78F9136B only
Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of
the dedicated flash programmer. Before using the power supply connected to the VDD pin,
supply vo ltage before starti ng programming.
2. In the
µ
PD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the
dedicated flash programmer.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
238
Figure 18-3. Example of Connection with Dedicated Flash Programmer (2/2)
(c) UART mode
VPP1
VDD
RESET
SO
SI
GND
VPP
VDD, AVDD
RESET
CLKNote 1 X1 (P03Note 2)
RxD20
TxD20
VSS, AVSS
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
Dedicated flash programmer
(d) Pseudo 3-wire mode (
µ
PD78F9116A, 78F9136A only)
VPP1
VDD
RESET
SCK
SO
SI
GND
VPP
VDD, AVDD
RESET
CLKNote 1 X1 (P03Note 2)
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
VSS, AVSS
PD78F9116A, 78F9136A
µ
Dedicated flash programmer
Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a
resonator has already been connected to the X1 pin, the CLK pin does not need to be connected.
2.
µ
PD78F9136A, 78F9136B only
Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of
the dedicated flash programmer. Before using the power supply connected to the VDD pin,
supply vo ltage before starti ng programming.
2. In the
µ
PD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the
dedicated flash programmer.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 239
If Flashpro III/Flashpro IV is used as the dedicated flash programmer, the following signals are generated for the
µ
PD78F9116A, 78F9116B, 78F9136A, and 78F9136B. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 18-4. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART Pseudo 3-Wire
VPP1 Output Write voltage VPP ◎ ◎ ◎
VPP2 − − − × × ×
VDD I/O VDD voltage generation/
voltage monitoring VDD/AVDD ◎Note 1 ◎Note 1 ◎No te 1
GND − Ground VSS/AVSS ◎ ◎ ◎
CLK Output Clock output X1 (P03Note 2) ○ ○ ○
RESET Output Reset signal RESET ◎ ◎ ◎
SI Input Reception signal SO20/P01/TxD20 ◎ ◎ ◎
SO Output Transmit signal SI20/P02/RxD20
◎ ◎ ◎
SCK Output Transfer clock SCK20/P00 ◎ × ◎
HS − − − × × ×
Notes 1. V
DD voltage must be supplied before programming is started.
2.
µ
PD78F9136A, 78F9136B only
Remark ◎: Pin must be connected.
○: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not n eed to be connected.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
240
18.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between nor mal operation mode and flash memor y programming mode
may be required in some cas es.
<VPP pin>
In nor mal operation mode, input 0 V to the VPP pin. In flash memor y programming mode, a wr ite voltage of 10.0
V (TYP.) is supplied to the VPP pin, so perform the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jum per on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 18-4. VPP Pin Connection Example
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
V
PP
Connection pin of dedicated flash programmer
Pull-down resistor (RV
PP
)
µ
<Serial interface pins>
The following shows the pins used by the serial interface.
<
µ
PD78F9116A, 78F9136A>
Serial Interface Pins Used
3-wire serial I/O SCK20, SO20, SI20
UART TxD20, RxD20
Pseudo 3-wire P00, P01, P02
<
µ
PD78F9116B, 78F9136B>
Serial Interface Pins Used
SCK20, SO20, SI20 3-wire serial I/O
P00, P01, P02
UART TxD20, RxD20
When connecting th e dedicated flash programmer to a serial interface pin that is connected to another device on-
board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with
such connections.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 241
(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or
set the other device to the output high impedance status.
Figure 18-5. Signal Conflict (Input Pin of Serial Interface)
Input pin Signal conflict
Connection pin of
dedicated flash
programmer
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict;
therefore, isolate the signal of the other device.
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is
connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
input signals to the other device are ignored.
Figure 18-6. Abnormal Operation of Other Device
Pin
Connection pin of
dedicated flash
programmer
Other device
Input pin
If the signal output by the PD78F9116A, 78F9116B, 78F9136A, or
78F9136B affects another device in the flash memory programming mode,
isolate the signals of the other device.
Pin
Connection pin of
dedicated flash
programmer
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
µ
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
242
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the flas h memory programming mode, a nor mal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 18-7. Signal Conflict (RESET Pin)
RESET
Connection pin of
dedicated flash
programmer
Reset signal generator
Signal Conflict
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
<Port pins>
When the flash memor y programming mode is set, all the pi ns other than those that communicate with the flash
programmer are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS.
<Oscillation pins>
When using the on-board clock, connect X1 and X2 as required in the normal op eration mode.
When using the clock output of the flash programmer, connec t it directly to X1, disconnecting the main resonator
on-board, and leave the X2 pin open.
<Power supply>
When using the power supply output of the flash pr ogrammer, connect the VDD and VSS pins to VDD and GND of
the flash programmer, respectively.
When using the on-board power supply, connect it as required in the nor mal operation mode. Because the flash
programmer monitors the voltage, however, VDD of the flash programmer must be connected.
For the other power pins (AVDD and ASS), supply the same power supply as in the normal operation mode.
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 243
18.1.4 Connection when using flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 18-8. Example of Flash Memory Writing Adapter Connection
When Using 3-Wire Serial I/O Mode (SIO-ch0)
(a)
µ
PD78F9116A, 78F9116B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9116A
PD78F9116B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
V
DD
(2.7 to 5.5 V)
GND
µ
µ
(b)
µ
PD78F9136A, 78F9136B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9136A
PD78F9136B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
V
DD
(2.7 to 5.5 V)
GND
µ
µ
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
244
Figure 18-9. Example of Flash Memory Writing Adapter Connection
When Using 3-Wire Serial I/O Mode (SIO-ch1)
(a)
µ
PD78F9116B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9116B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
V
DD
(2.7 to 5.5 V)
GND
Flash programmer
interface
µ
(b)
µ
PD78F9136B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9136B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
VDD (2.7 to 5.5 V)
GND
Flash programmer
interface
µ
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD 245
Figure 18-10. Example of Flash Memory Writing Adapter Connection When Using UART Mode
(a)
µ
PD78F9116A, 78F9116B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9116A
PD78F9116B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
V
DD
(2.7 to 5.5 V)
GND
Flash programmer
interface
µ
µ
(b)
µ
PD78F9136A, 78F9136B
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9136A
PD78F9136B
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
V
DD
(2.7 to 5.5 V)
GND
Flash programmer
interface
µ
µ
CHAPTER 18
µ
PD78F9116A, 78F9116B, 78F9136A, 78F9136B
User’s Manual U14643EJ2V0UD
246
Figure 18-11. Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode
(a)
µ
PD78F9116A
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9116A
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
VDD (2.7 to 5.5 V)
GND
Flash programmer
interface
µ
(b)
µ
PD78F9136A
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
PD78F9136A
VDD2 (LVDD)
VDD
GND
SI SO SCK CLKOUT RESET VPP RESERVE/HS
V
DD
(2.7 to 5.5 V)
GND
Flash programmer
interface
µ
User’s Manual U14643EJ2V0UD 247
CHAPTER 19 MASK OPTION (MASK ROM VERSION)
Table 19-1. Selection of Mask Option for Pins
Pin Mask Option
P50 to P53 On-chip pull-up resistor can be specified in 1-bit units.
For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is
specified in 1-bit units.
Caution The flash memory versions do not provide the on-chip pull-up resistor function.
User’s Manual U14643EJ2V0UD
248
CHAPTER 20 INSTRUCTI ON SET
This chapter lists the instruction set of the
µ
PD789104A/114A/124A/134A Subseries. For details of the operation
and machine languag e (instruction code) of each instruction, refer to the 78K/0S Series Instructions User’s Manual
(U11047E).
20.1 Operation
20.1.1 Operand identifiers and description methods
Operands are described i n the “Operand” column of each instruction in accordance with the descr iption method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification • $: Relative address specification
• !: Absolute address specification • [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For the operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 20-1. Operand Identifiers and Description Methods
Identifier Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
saddr
saddrp FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark Refer to Table 4-3 Special-Function Register List for the symbols of the special-function registers.
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD 249
20.1.2 Description of “operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register p air
DE: DE register p ai r
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parentheses
×H, ×L: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logic al product (AND)
∨: Logical sum (OR)
∀: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
20.1.3 Description of “flag operation” column
(Blank): Unchanged
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD
250
20.2 Operation List
Flag Mnemonic Operands Bytes Clocks Operation
Z AC CY
r, #byte 3 6 r ← byte
saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A, rNote 1 2 4 A ← r
r, ANote 1 2 4 r ← A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte × × ×
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A × × ×
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL+byte] 2 6 A ← (HL+byte)
MOV
[HL+byte], A 2 6 (HL+byte) ← A
A, X 1 4 A ↔ X
A, rNote 2 2 6 A ↔ r
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ sfr
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
XCH
A, [HL+byte] 2 8 A ↔ (HL+byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD 251
Flag Mnemonic Operands Bytes Clocks Operation
Z AC CY
rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rpNote 1 4 AX ← rp
MOVW
rp, AXNote 1 4 rp ← AX
XCHW AX, rpNote 1 8 AX ↔ rp
A, #byte 2 4 A, CY ← A + byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × ×
A, r 2 4 A, CY ← A + r × × ×
A, saddr 2 4 A, CY ← A + (saddr) × × ×
A, !addr16 3 8 A, CY ← A + (addr16) × × ×
A, [HL] 1 6 A, CY ← A + (HL) × × ×
ADD
A, [HL+byte] 2 6 A, CY ← A + (HL+byte) × × ×
A, #byte 2 4 A, CY ← A + byte + CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × ×
A, r 2 4 A, CY ← A + r + CY × × ×
A, saddr 2 4 A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 8 A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 6 A, CY ← A + (HL) + CY × × ×
ADDC
A, [HL+byte] 2 6 A, CY ← A + (HL+byte) + CY × × ×
A, #byte 2 4 A, CY ← A − byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte × × ×
A, r 2 4 A, CY ← A − r × × ×
A, saddr 2 4 A, CY ← A − (saddr) × × ×
A, !addr16 3 8 A, CY ← A − (addr16) × × ×
A, [HL] 1 6 A, CY ← A − (HL) × × ×
SUB
A, [HL+byte] 2 6 A, CY ← A − (HL+byte) × × ×
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD
252
Flag Mnemonic Operands Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A, CY ← A − byte − CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × ×
A, r 2 4 A, CY ← A − r − CY × × ×
A, saddr 2 4 A, CY ← A − (saddr) − CY × × ×
A, !addr16 3 8 A, CY ← A − (addr16) − CY × × ×
A, [HL] 1 6 A, CY ← A − (HL) − CY × × ×
SUBC
A, [HL+byte] 2 6 A, CY ← A − (HL+byte) − CY × × ×
A, #byte 2 4 A ← A ∧ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte ×
A, r 2 4 A ← A ∧ r ×
A, saddr 2 4 A ← A ∧ (saddr) ×
A, !addr16 3 8 A ← A ∧ (addr16) ×
A, [HL] 1 6 A ← A ∧ (HL) ×
AND
A, [HL+byte] 2 6 A ← A ∧ (HL+byte) ×
A, #byte 2 4 A ← A ∨ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r ×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
OR
A, [HL+byte] 2 6 A ← A ∨ (HL+byte) ×
A, #byte 2 4 A ← A ∀ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∀ byte ×
A, r 2 4 A ← A ∀ r ×
A, saddr 2 4 A ← A ∀ (saddr) ×
A, !addr16 3 8 A ← A ∀ (addr16) ×
A, [HL] 1 6 A ← A ∀ (HL) ×
XOR
A, [HL+byte] 2 6 A ← A ∀ (HL+byte) ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD 253
Flag Mnemonic Operands Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A − byte × × ×
saddr, #byte 3 6 (saddr) − byte × × ×
A, r 2 4 A − r × × ×
A, saddr 2 4 A − (saddr) × × ×
A, !addr16 3 8 A − (addr16) × × ×
A, [HL] 1 6 A − (HL) × × ×
CMP
A, [HL+byte] 2 6 A − (HL+byte) × × ×
ADDW AX, #word 3 6 AX, CY ← AX + word × × ×
SUBW AX, #word 3 6 AX, CY ← AX − word × × ×
CMPW AX, #word 3 6 AX − word × × ×
r 2 4 r ← r + 1 × × INC
saddr 2 4 (saddr) ← (saddr) + 1 × ×
r 2 4 r ← r − 1 × × DEC
saddr 2 4 (saddr) ← (saddr) − 1 × ×
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 ×
ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 ×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 ×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×
saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 × × ×
SET1
[HL].bit 2 10 (HL).bit ← 1
saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 × × ×
CLR1
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD
254
Flag Mnemonic Operands Bytes Clocks Operation
Z AC CY
CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
R R R
PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 PUSH
rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R POP
rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP, AX 2 8 SP ← AX MOVW
AX, SP 2 6 AX ← SP
!addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
BR
AX 1 6 PCH ← A, PCL ← X
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1
BT
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0
BF
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
DBNZ
saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD 255
20.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOVNote
XCHNote
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV MOV INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV
[HL+byte] MOV
Note Except r = A.
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD
256
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word AX rpNote saddrp SP None
AX ADDW
SUBW
CMPW
MOVW
XCHW
MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
saddrp MOVW
SP MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16 None
A.bit BT
BF
SET1
CLR1
sfr.bit BT
BF
SET1
CLR1
saddr.bit BT
BF
SET1
CLR1
PSW.bit BT
BF
SET1
CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1
CHAPTER 20 INSTRUCTION SET
User’s Manual U14643EJ2V0UD 257
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX !addr16 [addr5] $addr16
Basic instructions BR CALL
BR
CALLT BR
BC
BNC
BZ
BNZ
Compound instructions DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
User’s Manual U14643EJ2V0UD
258
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(EXPANDED-SPECIFICATION PRODUCTS)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD, AVDD VDD = AVDD –0.3 to +6.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V
With N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
With an on-chip pull-u p resist or –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA
Total for all pins
µ
PD78910xA, 78911xA
–30 mA
Per pin –7 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A),
78911xA(A) –22 mA
Per pin 30 mA
Total for all pins
µ
PD78910xA, 78911xA
160 mA
Per pin 10 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A),
78911xA(A) 120 mA
Operating ambient temperature TA –40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 259
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = oscillation voltage
range 1.0 10 MHz
Ceramic
resonator
X2X1IC0
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
Oscillation frequency (fX)Note 1 1.0 10 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X2X1IC0
C2C1
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 30 ms
X1 input frequency (fX)Note 1 1.0 10 MHz
VDD = 4.5 to 5.5 V 45 500 ns
VDD = 3.0 to 5.5 V 75 500 ns
X1 X2
X1 input high-/low-level
width (tXH, tXL)
VDD = 1.8 to 5.5 V 85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscill ation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
260
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C)
(
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (Expanded-specification products)
Recommended
Circuit Constant (pF) Oscillation Voltage
Range (VDD)
Manufacturer Part Number
Frequency
(MHz)
C1 C2 MIN. MAX.
Remark
CSBLA1M00J58-B0Note
CSBFB1M00J58-R1Note
1.0 100 100 2.1 Rd = 2.2 kΩ
CSTCC2M00G56-R0
CSTLS2M00G56-B0
2.0
CSTCR4M00G53-R0
CSTLS4M00GG53-B0
4.0
CSTCR4M19G53-R0
CSTLS4M19GG53-B0
4.194
CSTCR4M91G53-R0
CSTLS4M91GG53-B0
4.915
CSTCR5M00G53-R0
CSTLS5M00GG53-B0
5.0
CSTCR6M00G53-R0
CSTLS6M00GG53-B0
6.0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
8.0
CSTCE8M38G52-R0
CSTLS8M38G53-B0
8.388
CSTCE10M0G52-R0
Murata Mfg.
Co., Ltd.
CSTLS10M00G53-B0
10.0
– – 1.8
5.5
On-chip capacitor
version
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0
MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is
not necessary when other recommended resonators are used.
X2X1
C2C1
CSBLA1M00J58-B0
CSBFB1M00J58-R1 Rd
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µ
PD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are
within the specifications of the DC and AC characteristics.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 261
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78910xA, 78911xA
–15 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A), 78911xA(A)
–11 mA
Per pin 10 mA
Total for all pins
µ
PD78910xA, 78911xA
80 mA
Per pin 3 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A), 78911xA(A)
60 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V
With N-ch open
drain VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.7VDD VDD V
VIH2 P50 to P53
With on-chip
pull-up resistor VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1, X2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1, X2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78910xA, 78911xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78910xA(A), 78911xA(A)) 1.0 V
VOL1 Pins other
than P50 to
P53
VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78910xA, 78911xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78910xA(A), 78911xA(A)) 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
262
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than X1, X2,
or P50 to P53 3
µ
A
ILIH2 X1, X2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than X1, X2,
or P50 to P53 –3
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 200 kΩ
Mask option pull-up
resistance R2 VI = 0 V, P50 to P53 10 30 60 kΩ
10.0 MHz crystal
oscillation operating mode VDD = 5.0 V ±10%Note 4 3.2 8.0 mA
6.0 MHz crystal oscillation
operating mode VDD = 5.0 V ±10%Note 4 2.0 4.7 mA
VDD = 5.0 V ±10%Note 4 1.8 3.2 mA
VDD = 3.0 V ±10%Note 5 0.45 0.9 mA
IDD1Note 2
5.0 MHz crystal
oscillation operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 0.25 0.45 mA
10.0 MHz crystal
oscillation HALT mode VDD = 5.0 V ±10%Note 4 1.5 3.0 mA
6.0 MHz crystal
oscillation HALT mode VDD = 5.0 V ±10%Note 4 0.9 1.8 mA
VDD = 5.0 V ±10%Note 4 0.8 1.6 mA
VDD = 3.0 V ±10%Note 5 0.3 0.6 mA
IDD2Note 2
5.0 MHz crystal
oscillation HALT mode
(C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 0.15 0.3 mA
VDD = 5.0 V ±10% 0.1 10
µ
A
VDD = 3.0 V ±10% 0.05 5.0
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 5.0
µ
A
10.0 MHz crystal oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4 4.4 10.3 mA
6.0 MHz crystal oscillation
A/D operating mode VDD = 5.0 V ±10%Note 4 3.2 7.0 mA
VDD = 5.0 V ±10%Note 4 3.0 5.5 mA
VDD = 3.0 V ±10%Note 5 1.65 3.2 mA
Power supply
current
IDD4Note 3
5.0 MHz crystal
oscillation A/D operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 1.25 2.7 mA
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 263
Notes 1. When pu ll-up resistors are no t connected to P50 to P5 3 (specified by the mask optio n) and when port 5
is in input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time after a
read instruction has been executed to p ort 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
264
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 4.5 to 5.5 V 0.2 8
µ
s
VDD = 3.0 to 5.5 V 0.33 8
µ
s
VDD = 2.7 to 5.5 V 0.4 8
µ
s
Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 8
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
12 4356
0.1
0.4
1.0
10
60
Guaranteed
operation range
µ
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 265
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
266
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 267
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
268
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 269
8-Bit A/D Converter Characteristics (
µ
PD78910xA, 78910xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 Bits
VDD = 2.7 to 5.5 V ±0.4 ±0.6 %FSR Overall errorNotes 1, 2
VDD = 1.8 to 5.5 V ±0.8 ±1.2 %FSR
VDD = 4.5 to 5.5 V 12 100
µ
s
VDD = 2.7 to 5.5 V 14 100
µ
s
Conversion time tCONV
VDD = 1.8 to 5.5 V 28 100
µ
s
Analog input
voltage
VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.2%).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (
µ
PD78911xA, 78911xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V 12 100
µ
s
2.7 V ≤ VDD < 4 .5 V 14 100
µ
s
Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 21 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
270
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 271
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(CONVENTIONAL-SPE C I FICATION PRODUCTS)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD, AVDD VDD = AVDD –0.3 to +6.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V
With N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
With an on-chip pull-u p resist or –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA
Total for all pins
µ
PD78910xA, 78911xA
–30 mA
Per pin –7 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A),
78911xA(A) –22 mA
Per pin 30 mA
Total for all pins
µ
PD78910xA, 78911xA
160 mA
Per pin 10 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A),
78911xA(A) 120 mA
Operating ambient temperature TA –40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
272
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = oscillation voltage
range 1.0 5.0 MHz
Ceramic
resonator
X2X1IC0
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
Oscillation frequency (fX)Note 1 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X2X1IC0
C2C1
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 30
X1 input frequency (fX)Note 1 1.0 5.0 MHz
X1 X2
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 273
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C)
(
µ
PD78910xA, 7891 1xA, 78910xA(A), 78911xA(A)) (Conventional-specification products)
Recommended
Circuit Constant (pF) Oscillation Voltage
Range (VDD)
Manufacturer Part Number
Frequency
(MHz)
C1 C2 MIN. MAX.
Remark
CSBLA1M00J58-B0Note
CSBFB1M00J58-R1Note
1.0 100 100 2.1 Rd = 2.2 kΩ
CSTCC2M00G56-R0
CSTLS2M00G56-B0
2.0
CSTCR4M00G53-R0
CSTLS4M00GG53-B0
4.0
CSTCR4M19G53-R0
CSTLS4M19GG53-B0
4.194
CSTCR4M91G53-R0
CSTLS4M91GG53-B0
4.915
CSTCR5M00G53-R0
Murata Mfg.
Co., Ltd.
CSTLS5M00GG53-B0
5.0
– – 1.8
5.5
On-chip capacitor
version
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0
MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is
not necessary when other recommended resonators are used.
X2X1
C2C1
CSBLA1M00J58-B0
CSBFB1M00J58-R1 Rd
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µ
PD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are
within the specifications of the DC and AC characteristics.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
274
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78910xA, 78911xA
–15 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A), 78911xA(A)
–11 mA
Per pin 10 mA
Total for all pins
µ
PD78910xA, 78911xA
80 mA
Per pin 3 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A), 78911xA(A)
60 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V
With N-ch open
drain VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.7VDD VDD V
VIH2 P50 to P53
With on-chip
pull-up resistor VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1, X2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1, X2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78910xA, 78911xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78910xA(A), 78911xA(A)) 1.0 V
VOL1 Pins other
than P50 to
P53
VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78910xA, 78911xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78910xA(A), 78911xA(A)) 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 275
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than X1, X2,
or P50 to P53 3
µ
A
ILIH2 X1, X2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than X1, X2,
or P50 to P53 –3
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 200 kΩ
Mask option pull-up
resistance R2 VI = 0 V, P50 to P53 10 30 60 kΩ
VDD = 5.0 V ±10%Note 4 1.8 3.2 mA
VDD = 3.0 V ±10%Note 5 0.45 0.9 mA
IDD1Note 2 5.0 MHz crystal
oscillation operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 0.25 0.45 mA
VDD = 5.0 V ±10%Note 4 0.8 1.6 mA
VDD = 3.0 V ±10%Note 5 0.3 0.6 mA
IDD2Note 2 5.0 MHz crystal
oscillation HALT mode
(C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 0.15 0.3 mA
VDD = 5.0 V ±10% 0.1 10
µ
A
VDD = 3.0 V ±10% 0.05 5.0
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 5.0
µ
A
VDD = 5.0 V ±10%Note 4 3.0 5.5 mA
VDD = 3.0 V ±10%Note 5 1.65 3.2 mA
Power supply
current
IDD4Note 3 5.0 MHz crystal
oscillation A/D operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 1.25 2.7 mA
Notes 1. When pu ll-up resistors are no t connected to P50 to P5 3 (specified by the mask optio n) and when port 5
is in input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time after a
read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
276
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 8
µ
s Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 8
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage VDD [V]
123456
0.1
0.4
1.0
10
60
Cycle time TCY [ s]
Guaranteed
operation range
µ
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 277
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
278
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 279
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
280
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD 281
8-Bit A/D Converter Characteristics (
µ
PD78910xA, 78910xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 Bits
VDD = 2.7 to 5.5 V ±0.4 ±0.6 %FSR Overall errorNotes 1, 2
VDD = 1.8 to 5.5 V ±0.8 ±1.2 %FSR
VDD = 2.7 to 5.5 V 14 100
µ
s Conversion time tCONV
VDD = 1.8 to 5.5 V 28 100
µ
s
Analog input
voltage
VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (
µ
PD78911xA, 78911xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
2.7 V ≤ VDD ≤ 5.5 V 14 100
µ
s Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 22 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A) ) (CONVENTIONAL-SPECIFICATION PRODUCTS)
User’s Manual U14643EJ2V0UD
282
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 283
CHAPTER 23 ELECTRICAL SPECIFICATIONS
(
µ
PD78910xA(A1), 78911 xA(A1), 78910xA(A2), 78911xA(A2))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD, AVDD VDD = AVDD –0.3 to +6.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V
With N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
With an on-chip pull-u p resist or –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –4 mA
Total for all pins
µ
PD78910xA(A1),
78911xA(A1) –14 mA
Per pin –2 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A2),
78911xA(A2) –6 mA
Per pin 5 mA
Total for all pins
µ
PD78910xA(A1),
78911xA(A1) 80 mA
Per pin 2 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A2),
78911xA(A2) 40 mA
µ
PD78910xA(A1), 78911xA(A1) –40 to +110 °C Operating ambient temperature TA
µ
PD78910xA(A2), 78911xA(A2) –40 to +125 °C
Storage temperature Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
284
System Clock Oscillator Characteristics
(VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2)) )
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = oscillation voltage
range 1.0 5.0 MHz
Ceramic
resonator
X2X1IC0
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
X1 input frequency (fX)Note 1 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscill ation wait time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate under
the following conditions.
µ
PD78910xA(A1), 78911x A(A1): TA = 110°C
µ
PD78910xA(A2), 78911x A(A2): TA = 125°C
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufactu rer for evaluation.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 285
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2), 78911x A(A2)) ) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78910xA(A1),
78911xA(A1) –7 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78910xA(A2),
78911xA(A2) –3 mA
Per pin 1.6 mA
Total for all pins
µ
PD78910xA(A1),
78911xA(A1) 40 mA
Per pin 1.6 mA
Output current, low IOL
Total for all pins
µ
PD78910xA(A2),
78911xA(A2) 20 mA
VIH1 Pins other than described below 0.7VDD VDD V
With N-ch open drain 0.7VDD 10 V VIH2 P50 to P53
With on-chip pull-up resistor 0.7VDD VDD V
VIH3 RESET, P20 to P25 0.8VDD VDD V
Input voltage, high
VIH4 X1, X2 VDD – 0.1 VDD V
VIL1 Pins other than described below 0 0.3VDD V
VIL2 P50 to P53 0 0.3VDD V
VIL3 RESET, P20 to P25 0 0.2VDD V
Input voltage, low
VIL4 X1, X2 0 0.1 V
VOH1 IOH = –1 mA VDD – 2.0 V Output voltage, high
VOH2 IOH = –100
µ
A VDD – 1.0 V
IOL = 1.6 mA 2.0 V VOL1 Pins other than
P50 to P53 IOL = 400
µ
A 1.0 V
Output voltage, low
VOL2 P50 to P53 IOL = 1.6 mA 1.0 V
ILIH1 Pins other than X1, X2, or P50
to P53 10
µ
A
ILIH2 X1, X2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80
µ
A
ILIL1 Pins other than X1, X2, or P50
to P53 –10
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open drain)
VI = 0 V
–10Note
µ
A
Output leakage
current, high ILOH VO = VDD 10
µ
A
Output leakage
current, low ILOL VO = 0 V –10
µ
A
Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in
input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time after a read
instruction has been executed to port 5.
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
286
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2)) ) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 300 kΩ
Mask option pull-up
resistance R2 VI = 0 V, P50 to P53 10 30 100 kΩ
IDD1Note 1 5.0 MHz crystal oscillation operating mode
(C1 = C2 = 22 pF) Note 3 1.8 8.0 mA
IDD2Note 1 5.0 MHz crystal oscillation HALT mode
(C1 = C2 = 22 pF) Note 3 0.8 5.0 mA
IDD3Note 1 STOP mode 0.1 1000
µ
A
Power supply
current
IDD4Note 2 5.0 MHz crystal oscillation A/D operating mode
(C1 = C2 = 22 pF) Note 3 3.0 10 mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 287
AC Characteristics
(1) Basic operation (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time
(minimum instruction
execution time)
TCY 0.4 8
µ
s
TI80 input high-/low-
level width tTIH,
tTIL 0.1
µ
s
TI80 input frequency fTI 0 4
MHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
288
(2) Serial interface (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2)) )
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY1 800 ns
SCK20 high-/low-
level width tKH1,
tKL1 t
KCY1/2 – 50 ns
SI20 setup time
(to SCK20↑) tSIK1 150 ns
SI20 hold time
(from SCK20↑) tKSI1 400 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ, C = 100 pFNote 0 250 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY2 800 ns
SCK20 high-/low-
level width tKH2,
tKL2 400 ns
SI20 setup time
(to SCK20↑) tSIK2 100 ns
SI20 hold time
(from SCK20↑) tKSI2 400 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ, C = 100 pFNote 0 300 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2 120 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2 240 ns
SS20 setup time
(to SCK20 first edge) tSSK2 100 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2 400 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 78125 bps
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 289
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK20 cycle time tKCY3 800 ns
ASCK20 high-/low-
level width tKH3,
tKL3 400 ns
Transfer rate 39063 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
290
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
t
CPL
t
CPH
Interrupt Input Timing
INTP0 to INTP2
t
INTL
t
INTH
RESET Input Timing
RESET
tRSL
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 291
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
t
R
t
F
t
KL3
t
KCY3
t
KH3
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
292
8-Bit A/D Converter Characteristics (
µ
PD78910xA(A1), 78910xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (
µ
PD78910xA(A1)),
–40 to +125°C (
µ
PD78910xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 Bits
Overall errorNotes 1, 2
±0.4 ±1.0 %FSR
Conversion time tCONV 14 28
µ
s
Analog input
voltage
VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (
µ
PD78911xA(A1), 78911xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (
µ
PD78911xA(A1)),
–40 to +125°C (
µ
PD78911xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
Overall errorNotes 1, 2 ±0.4 ±0.6 %FSR
Conversion time tCONV 14 28
µ
s
Zero-scale errorNo tes 1, 2 ±0.6 %FSR
Full-scale errorNotes 1, 2 ±0.6 %FSR
Integral linearity
errorNote 1 ILE ±4.5 LSB
Differential linearity
errorNote 1 DLE ±2.0 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 23 ELECTRICAL SPECIFICATIONS (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 293
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = –40 to +110°C (
µ
PD78910xA(A1), 78911xA(A1)), –40 to +125°C (
µ
PD78910xA(A2), 78911xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
VDD
Data retention mode
STOP mode
HALT mode
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD
294
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116 B(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin
µ
PD78F9116B –10 mA
Total for all pins –30 mA
Per pin
µ
PD78F9116B(A) –7 mA
Output current, high IOH
Total for all pins –22 mA
Per pin
µ
PD78F9116B 30 mA
Total for all pins 160 mA
Per pin
µ
PD78F9116B(A) 10 mA
Output current, low IOL
Total for all pins 120 mA
In normal operation mode –40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
0 V
V
PP
1.8 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 295
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = 4.5 to 5.5 V 1.0 10.0 MHz
VDD = 3.0 to 5.5 V 1.0 6.0 MHz
VDD = 1.8 to 5.5 V 1.0 5.0 MHz
Ceramic
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
Oscillation frequency (fX)Note 1 VDD = 4.5 to 5.5 V 1.0 10.0 MHz
VDD = 3.0 to 5.5 V 1.0 6.0 MHz
VDD = 1.8 to 5.5 V 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 30
X1 input frequency (fX)Note 1 VDD = 4.5 to 5.5 V 1.0 10.0 MHz
VDD = 3.0 to 5.5 V 1.0 6.0 MHz
VDD = 1.8 to 5.5 V 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 45 500 ns
X1 X2
VDD = 3.0 to 5.5 V 75 500 ns
X1 input high-/low-level
width (tXH, tXL)
VDD = 1.8 to 5.5 V 85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscill ation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
296
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C) (
µ
PD78F9116B, 78F9116B(A))
Recommended
Circuit Constant (pF) Oscillation Voltage
Range (VDD)
Manufacturer Part Number Frequency
(MHz)
C1 C2 MIN. MAX.
Remark
CSBLA1M00J58-B0Note 1.0 100 100 Rd = 2.2 kΩ
CSTCC2M00G56-R0 2.0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
4.0
2.0
CSTCR5M00G53-R0
CSTLS5M00G53-B0
5.0
CSTCR6M00G53-R0
2.1
CSTLS6M00G53-B0
6.0
2.2
CSTCE8M38G52-R0 2.0
CSTLS8M38G53-B0
8.388
2.2
CSTCE10M0G52-R0 2.1
Murata Mfg.
Co., Ltd.
(Standard
products)
CSTLS10M0G53-B0
10.0
– –
2.4
5.5
On-chip capacitor
version
CSTCR4M00G53U-R0
CSTLS4M00G53093-B0
4.0
CSTCR5M00G53U-R0
CSTLS5M00G53U-B0
5.0
1.8
CSTCR6M00G53093-R0
CSTLS6M00G53U-B0
6.0 1.9
CSTLS8M38G53193-B0 8.0
Murata Mfg.
Co., Ltd.
(Low-voltage
drive type)
CSTLS10M0G53U-B0 10.0
– –
2.0
5.5 On-chip capacitor
version
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. Co.,
Ltd. is used as the ceramic resonator (see the figure below). A limiting res istor is not necessary when ot her
recommended resonators are used.
X2X1
C2C1
CSBLA1M00J58-B0 Rd
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µ
PD78F9116B and 78F9116B(A) so that the internal operating conditions are within the
specifications of the DC and AC characteristics.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 297
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin
µ
PD78F9116B –1 mA Output current, high IOH
Total for all pins –15 mA
Per pin
µ
PD78F9116B(A) –1 mA
Total for all pins –11 mA
Per pin
µ
PD78F9116B 10 mA
Total for all pins 80 mA
Per pin
µ
PD78F9116B(A) 3 mA
Output current, low IOL
Total for all pins 60 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V VIH2 P50 to P53 N-ch open drain
VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1, X2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
N-ch open drain
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1, X2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78F9116B) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78F9116B(A)) 1.0 V
VOL1 Pins other
than P50 to
P53
VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78F9116B) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78F9116B(A)) 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
298
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than X1, X2, or
P50 to P53 VI = VDD 3
µ
A
ILIH2 X1, X2 20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open drain) VI = 12 V 20
µ
A
ILIL1 Pins other than X1, X2, or
P50 to P53 VI = 0 V –3
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open drain) –3Note 1
µ
A
Output leakage current,
high ILOH VO = VDD 3
µ
A
Output leakage current,
low ILOL VO = 0 V –3
µ
A
Software pull-up resistance R1 VI = 0 V , for pins o t h er th a n P50 t o P53 o r P 6 0 to P6 3 50 100 200 kΩ
10.0 MHz crystal oscillation
operating mode
V
DD
= 5.0 V
±
10%
Note 4 10.0 20.0 mA
6.0 MHz crystal oscillation
operating mode
V
DD
= 5.0 V
±
10%
Note 4 6.0 12.0 mA
V
DD
= 5.0 V
±
10%
Note 4 4.0 10.0 mA
V
DD
= 3.0 V
±
10%
Note 5 1.0 2.5 mA
IDD1Note 2
5.0 MHz crystal oscillation
operating mode
(C1 = C2 = 22 pF)
V
DD
= 2.0 V
±
10%
Note 5 0.8 2.0 mA
10.0 MHz crystal oscillation
HALT mode
V
DD
= 5.0 V
±
10%
Note 4 1.2 6.0 mA
6.0 MHz crystal oscillation
HALT mode
V
DD
= 5.0 V
±
10%
Note 4 0.9 2.8 mA
V
DD
= 5.0 V
±
10%
Note 4 0.6 2.5 mA
V
DD
= 3.0 V
±
10%
Note 5 0.3 2.0 mA
IDD2Note 2
5.0 MHz crystal oscillation
HALT mode
(C1 = C2 = 22 pF)
V
DD
= 2.0 V
±
10%
Note 5 0.2 1.5 mA
VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 10
µ
A
10.0 MHz crystal oscillation
A/D operating mode
V
DD
= 5.0 V
±
10%
Note 4 11.0 22.5 mA
6.0 MHz crystal oscillation
A/D operating mode
V
DD
= 5.0 V
±
10%
Note 4 7.0 14.5 mA
V
DD
= 5.0 V
±
10%
Note 4 5.0 12.5 mA
V
DD
= 3.0 V
±
10%
Note 5 2.0 5.0 mA
Power supply current
IDD4Note 3
5.0 MHz crystal oscillation
A/D operating mode
(C1 = C2 = 22 pF)
V
DD
= 2.0 V
±
10%
Note 5 1.8 4.5 mA
Notes 1. When port 5 is in i nput mode, a low-level input leakag e current of –60
µ
A (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 299
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency VDD = 4.5 to 5.5 V 1.0 10.0 MHz
VDD = 3.0 to 5.5 V 1.0 6.0 MHz
VDD = 2.7 to 5.5 V 1.0 5.0 MHz
fX
VDD = 1.8 to 5.5 V 1.0 1.25 MHz
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 21 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 21 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.2 0.2 0.2 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
300
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 4.5 to 5.5 V 0.2 8
µ
s
VDD = 3.0 to 5.5 V 0.33 8
µ
s
VDD = 2.7 to 5.5 V 0.4 8
µ
s
Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 8
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage VDD [V]
Cycle time TCY [ s]
12 4356
0.1
0.4
1.0
10
60
Guaranteed
operation range
µ
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 301
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
302
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 303
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
tTIL tTIH
1/fTI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
304
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD 305
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V 12 100
µ
s
2.7 V ≤ VDD < 4 .5 V 14 100
µ
s
Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 24 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B, 78F9116B(A))
User’s Manual U14643EJ2V0UD
306
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 307
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –4 mA Output current, high IOH
Total for all pins –14 mA
Per pin 5 mA Output current, low IOL
Total for all pins 80 mA
In normal operation mode –40 to +105 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (4.5 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (4.5 V) of the operating
voltage range of VDD (see b in the figure below).
4.5 V
VDD
0 V
0 V
VPP 4.5 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD
308
System Clock Oscillator Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = oscillation voltage
range 1.0 5.0 MHz
Ceramic
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
X1 input frequency (fX)Note 1 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscill ation wait time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate at TA =
105°C.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufactu rer for evaluation.
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD 309
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA Output current, high IOH
Total for all pins –7 mA
Per pin 1.6 mA Output current, low IOL
Total for all pins 40 mA
VIH1 Pins other than described below 0.7VDD VDD V
VIH2 P50 to P53 With N-ch open drain 0.7VDD 10 V
VIH3 RESET, P20 to P25 0.8VDD VDD V
Input voltage, high
VIH4 X1, X2 VDD – 0.1 VDD V
VIL1 Pins other than described below 0 0.3VDD V
VIL2 P50 to P53 0 0.3VDD V
VIL3 RESET, P20 to P25 0 0.2VDD V
Input voltage, low
VIL4 X1, X2 0 0.1 V
VOH1 IOH = –1 mA VDD – 2.0 V Output voltage, high
VOH2 IOH = –100
µ
A VDD – 1.0 V
IOL = 1.6 mA 2.0 V VOL1 Pins other than
P50 to P53 IOL = 400
µ
A 1.0 V
Output voltage, low
VOL2 P50 to P53 IOL = 1.6 mA 1.0 V
ILIH1 Pins other than X1, X2, or P50
to P53 10
µ
A
ILIH2 X1, X2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80
µ
A
ILIL1 Pins other than X1, X2, or P50
to P53 –10
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open drain)
VI = 0 V
–10Note
µ
A
Output leakage
current, high ILOH VO = VDD 10
µ
A
Output leakage
current, low ILOL VO = 0 V –10
µ
A
Note When port 5 is in input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time
after a read instruction has been exec uted to port 5.
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD
310
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 300 kΩ
IDD1Note 1 5.0 MHz crystal oscillation operating mode
(C1 = C2 = 22 pF) Note 3 7.5 20.0 mA
IDD2Note 1 5.0 MHz crystal oscillation HALT mode
(C1 = C2 = 22 pF) Note 3 3.0 5.5 mA
IDD3Note 1 STOP mode 1 1000
µ
A
Power supply
current
IDD4Note 2 5.0 MHz crystal oscillation A/D operating mode
(C1 = C2 = 22 pF) Note 3 8.7 22.3 mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 4.5 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 21 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 21 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.2 0.2 0.2 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD 311
AC Characteristics
(1) Basic operation (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time
(minimum instruction
execution time)
TCY 0.4 8
µ
s
TI80 input high-/low-
level width tTIH,
tTIL 0.1
µ
s
TI80 input frequency fTI 0 4
MHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD
312
(2) Serial interface (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY1 800 ns
SCK20 high-/low-
level width tKH1,
tKL1 t
KCY1/2 – 50 ns
SI20 setup time
(to SCK20↑) tSIK1 150 ns
SI20 hold time
(from SCK20↑) tKSI1 400 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ, C = 100 pFNote 0 250 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY2 800 ns
SCK20 high-/low-
level width tKH2,
tKL2 400 ns
SI20 setup time
(to SCK20↑) tSIK2 100 ns
SI20 hold time
(from SCK20↑) tKSI2 400 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ, C = 100 pFNote 0 300 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2 120 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2 240 ns
SS20 setup time
(to SCK20 first edge) tSSK2 100 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2 400 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 78125 bps
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD 313
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK20 cycle time tKCY3 800 ns
ASCK20 high-/low-
level width tKH3,
tKL3 400 ns
Transfer rate 39063 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD
314
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
t
CPL
t
CPH
Interrupt Input Timing
INTP0 to INTP2
t
INTL
t
INTH
RESET Input Timing
RESET
tRSL
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD 315
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
t
R
t
F
t
KL3
t
KCY3
t
KH3
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD
316
10-Bit A/D Converter Characteristics (TA = –40 to +105°C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
Overall errorNotes 1,2 ±0.4 ±0.6 %FSR
Conversion time tCONV 14 28
µ
s
Zero-scale errorNo tes 1,2 ±0.6 %FSR
Full-scale errorNotes 1,2 ±0.6 %FSR
Integral linearity
errorNote 1 ILE ±4.5 LSB
Differential linearity
errorNote 1 DLE ±2.0 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 25 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116B(A1))
User’s Manual U14643EJ2V0UD 317
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +105°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
VDD
Data retention mode
STOP mode
HALT mode
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD
318
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA Output current, high IOH
Total for all pins –30 mA
Per pin 30 mA Output current, low IOL
Total for all pins 160 mA
In normal operation mode –40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
0 V
V
PP
1.8 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 319
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 VDD = oscillation voltage
range 1.0 5.0 MHz
Ceramic
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2 After VDD reaches
oscillation voltage range
MIN.
4 ms
Oscillation frequency (fX)Note 1 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X2X1V
PP
C2C1
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 30
X1 input frequency (fX)Note 1 1.0 5.0 MHz
X1 X2
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X1 X2
OPEN
X1 input high-/low-level
width (tXH, tXL) 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscill ation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufactu rer for evaluation.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD
320
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA Output current, high IOH
Total for all pins –15 mA
Per pin 10 mA Output current, low IOL
Total for all pins 80 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V VIH2 P50 to P53 N-ch open drain
VDD = 1.8 to 5.5 V,
TA = 25 to 85°C
0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1, X2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
N-ch open drain
VDD = 1.8 to 5.5 V,
TA = 25 to 85°C
0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1, X2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VOL1 Pins other
than P50 to
P53 VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 321
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than X1, X2,
or P50 to P53 3
µ
A
ILIH2 X1, X2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than X1, X2,
or P50 to P53 –3
µ
A
ILIL2 X1, X2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 200 kΩ
VDD = 5.0 V ±10%Note 4 5.0 15.0 mA
VDD = 3.0 V ±10%Note 5 1.9 4.9 mA
IDD1Note 2 5.0 MHz crystal
oscillation operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 1.5 3.0 mA
VDD = 5.0 V ±10%Note 4 2.5 5.0 mA
VDD = 3.0 V ±10%Note 5 1.0 2.0 mA
IDD2Note 2 5.0 MHz crystal
oscillation HALT mode
(C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 0.75 1.5 mA
VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 10
µ
A
VDD = 5.0 V ±10%Note 4 6.2 17.3 mA
VDD = 3.0 V ±10%Note 5 3.1 7.2 mA
Power supply
current
IDD4Note 3 5.0 MHz crystal
oscillation A/D operating
mode (C1 = C2 = 22 pF) VDD = 2.0 V ±10%Note 5 2.5 5.0 mA
Notes 1. When port 5 is in i nput mode, a low-level input leakag e current of –60
µ
A (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD
322
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 18 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1
(@ 5.0 MHz operation) 18 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.5 1 1 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 323
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 8
µ
s Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 8
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD
324
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 325
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD
326
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
t
INTL
t
INTH
RESET Input Timing
RESET
tRSL
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 327
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
t
R
t
F
t
KL3
t
KCY3
t
KH3
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD
328
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
2.7 V ≤ VDD ≤ 5.5 V 14 100
µ
s Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 26 ELECTRICAL SPECIFICATIONS (
µ
PD78F9116A)
User’s Manual U14643EJ2V0UD 329
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 215/fX s Oscillation
stabilization wait
timeNote 1
tWAIT
Release by interrupt request Note 2 s
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register.
Remark f
X: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
VDD
Data retention mode
STOP mode
HALT mode
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD
330
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 7891 2xA(A), 78913xA(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD, AVDD VDD = AVDD –0.3 to +6.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V
With N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
With an on-chip pull-u p resist or –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA
Total for all pins
µ
PD78912xA, 78913xA
–30 mA
Per pin –7 mA
Output current, high IOH
Total for all pins
µ
PD78912xA(A),
78913xA(A) –22 mA
Per pin 30 mA
Total for all pins
µ
PD78912xA, 78913xA
160 mA
Per pin 10 mA
Output current, low IOL
Total for all pins
µ
PD78912xA(A),
78913xA(A) 120 mA
Operating ambient temperature TA –40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD 331
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
oscillator
CL2CL1
Oscillation frequency (fCC)Note 2.0 4.0 MHz
CL1 input frequency (fCC)Note 1.0 5.0 MHz
CL1 CL2
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
CL1 input frequency (fCC)Note VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
CL1 CL2
OPEN
CL1 input high-/low-level
width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCC1 VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz
fCC2 VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz
fCC3
R = 11.0 kΩ, C = 22 pF
Target: 2 MHz
VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz
fCC4 VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz
fCC5 VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz
fCC6
R = 6.8 kΩ, C = 22 pF
Target: 3 MHz
VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz
fCC7 VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz
fCC8 VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz
Oscillator frequency
fCC9
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz
Remark So that the TYP. spec. is satisfied between 2.0 to 4. 0 MHz , set one of the abov e nine pa tterns for R an d
C.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD
332
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78912xA, 78913xA
–15 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78912xA(A), 78913xA(A)
–11 mA
Per pin 10 mA
Total for all pins
µ
PD78912xA, 78913xA
80 mA
Per pin 3 mA
Output current, low IOL
Total for all pins
µ
PD78912xA(A), 78913xA(A)
60 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V
With N-ch open
drain VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.7VDD VDD V
VIH2 P50 to P53
With on-chip
pull-up resistor VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 CL1, CL2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 CL1, CL2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78912xA, 78913xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78912xA(A), 78913xA(A)) 1.0 V
VOL1 Pins other
than P50 to
P53
VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78912xA, 78913xA) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78912xA(A), 78913xA(A)) 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD 333
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than CL1,
CL2, or P50 to P53 3
µ
A
ILIH2 CL1, CL2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than CL1,
CL2, or P50 to P53 –3
µ
A
ILIL2 CL1, CL2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistor R1 VI = 0 V, for pins other than P50 to P53 50 100 200 kΩ
Mask option pull-up
resistor R2 VI = 0 V, P50 to P53 10 30 60 kΩ
VDD = 5.0 V ±10%Note 4 1.8 3.2 mA
VDD = 3.0 V ±10%Note 5 0.45 0.9 mA
IDD1Note 2 4.0 MHz RC oscillation
operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 0.25 0.45 mA
VDD = 5.0 V ±10%Note 4 0.8 1.6 mA
VDD = 3.0 V ±10%Note 5 0.3 0.6 mA
IDD2Note 2 4.0 MHz RC oscillation
HALT mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 0.15 0.3 mA
VDD = 5.0 V ±10% 0.1 10
µ
A
VDD = 3.0 V ±10% 0.05 5.0
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 5.0
µ
A
VDD = 5.0 V ±10%Note 4 3.0 5.5 mA
VDD = 3.0 V ±10%Note 5 1.65 3.2 mA
Power supply
current
IDD4Note 3 4.0 MHz RC oscillation
A/D operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 1.25 2.7 mA
Notes 1. When pu ll-up resistors are no t connected to P50 to P5 3 (specified by the mask optio n) and when port 5
is in input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time after a
read instruction has been executed to p ort 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD
334
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 16
µ
s Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 16
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage VDD [V]
123456
0.1
0.4
1.0
10
60
Cycle time TCY [ s]
Guaranteed
operation range
µ
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD 335
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD
336
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD 337
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
tXL tXH
CL1 input VIH4 (MIN.)
VIL4 (MAX.)
TI Timing
TI80
tTIL tTIH
1/fTI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD
338
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD 339
8-Bit A/D Converter Characteristics (
µ
PD78912xA, 78912xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 Bits
VDD = 2.7 to 5.5 V ±0.4 ±0.6 %FSR Overall errorNotes 1, 2
VDD = 1.8 to 5.5 V ±0.8 ±1.2 %FSR
VDD = 2.7 to 5.5 V 14 100
µ
s Conversion time tCONV
VDD = 1.8 to 5.5 V 28 100
µ
s
Analog input
voltage
VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (
µ
PD78913xA, 78913xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V 14 100
µ
s
2.7 V ≤ VDD ≤ 5.5 V 14 100
µ
s
Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 27 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA, 78913xA, 78912xA(A), 78913xA(A))
User’s Manual U14643EJ2V0UD
340
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 27/fCC s Oscillation
stabilization wait
timeNote
tWAIT
Release by interrupt request 27/fCC s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark f
CC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 341
CHAPTER 28 ELECTRICAL SPECIFICATIONS
(
µ
PD78912xA(A1), 78913 xA(A1), 78912xA(A2), 78913xA(A2))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD, AVDD VDD = AVDD –0.3 to +6.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V
With N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
With an on-chip pull-u p resist or –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –4 mA
Total for all pins
µ
PD78912xA(A1),
78913xA(A1) –14 mA
Per pin –2 mA
Output current, high IOH
Total for all pins
µ
PD78912xA(A2),
78913xA(A2) –6 mA
Per pin 5 mA
Total for all pins
µ
PD78912xA(A1),
78913xA(A1) 80 mA
Per pin 2 mA
Output current, low IOL
Total for all pins
µ
PD78912xA(A2),
78913xA(A2) 40 mA
µ
PD78912xA(A1), 78913xA(A1) –40 to +110 °C Operating ambient temperature TA
µ
PD78912xA(A2), 78913xA(A2) –40 to +125 °C
Storage temperature Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
342
System Clock Oscillator Characteristics
(VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2)) )
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
oscillator
CL2CL1
Oscillation frequency (fCC)Note 2.0 4.0 MHz
CL1 input frequency (fCC)Note 1.0 5.0 MHz
External
clock
CL1 CL2
OPEN
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Construct the oscillator with R and C devices that are guaranteed to operate under the
following temperature conditions.
µ
PD78912xA(A1), 78913x A(A1): TA = 110°C
µ
PD78912xA(A2), 78913x A(A2): TA = 125°C
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD 343
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2), 78913x A(A2)) ) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78912xA(A1),
78913xA(A1) –7 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78912xA(A2),
78913xA(A2) –3 mA
Per pin 1.6 mA
Total for all pins
µ
PD78912xA(A1),
78913xA(A1) 40 mA
Per pin 1.6 mA
Output current, low IOL
Total for all pins
µ
PD78912xA(A2),
78913xA(A2) 20 mA
VIH1 Pins other than described below 0.7VDD VDD V
With N-ch open drain 0.7VDD 10 V VIH2 P50 to P53
With on-chip pull-up resistor 0.7VDD VDD V
VIH3 RESET, P20 to P25 0.8VDD VDD V
Input voltage, high
VIH4 CL1, CL2 VDD – 0.1 VDD V
VIL1 Pins other than described below 0 0.3VDD V
VIL2 P50 to P53 0 0.3VDD V
VIL3 RESET, P20 to P25 0 0.2VDD V
Input voltage, low
VIL4 CL1, CL2 0 0.1 V
VOH1 IOH = –1 mA VDD – 2.0 V Output voltage, high
VOH2 IOH = –100
µ
A VDD – 1.0 V
IOL = 1.6 mA 2.0 V VOL1 Pins other than
P50 to P53 IOL = 400
µ
A 1.0 V
Output voltage, low
VOL2 P50 to P53 IOL = 1.6 mA 1.0 V
ILIH1 Pins other than CL1, CL2, or
P50 to P53 10
µ
A
ILIH2 CL1, CL2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80
µ
A
ILIL1 Pins other than CL1, CL2, or
P50 to P53 –10
µ
A
ILIL2 CL1, CL2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open drain)
VI = 0 V
–10Note
µ
A
Output leakage
current, high ILOH VO = VDD 10
µ
A
Output leakage
current, low ILOL VO = 0 V –10
µ
A
Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in
input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time after a read
instruction has been executed to port 5.
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
344
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2)) ) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 300 kΩ
Mask option pull-up
resistance R2 VI = 0 V, P50 to P53 10 30 100 kΩ
IDD1Note 1 4.0 MHz crystal oscillation operating mode
(R = 4.7 kΩ, C = 22 pF) Note 3 1.8 8.0 mA
IDD2Note 1 4.0 MHz crystal oscillation HALT mode
(R = 4.7 kΩ, C = 22 pF) Note 3 0.8 5.0 mA
IDD3Note 1 STOP mode 0.1 1000
µ
A
Power supply
current
IDD4Note 2 4.0 MHz crystal oscillation A/D operating mode
(R = 4.7 kΩ, C = 22 pF) Note 3 3.0 10 mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD 345
AC Characteristics
(1) Basic operation (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time
(minimum instruction
execution time)
TCY 0.4 8
µ
s
TI80 input high-/low-
level width tTIH,
tTIL 0.1
µ
s
TI80 input frequency fTI 0 4
MHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
346
(2) Serial interface (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2)) )
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY1 800 ns
SCK20 high-/low-
level width tKH1,
tKL1 t
KCY1/2 – 50 ns
SI20 setup time
(to SCK20↑) tSIK1 150 ns
SI20 hold time
(from SCK20↑) tKSI1 400 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ, C = 100 pFNote 0 250 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY2 800 ns
SCK20 high-/low-
level width tKH2,
tKL2 400 ns
SI20 setup time
(to SCK20↑) tSIK2 100 ns
SI20 hold time
(from SCK20↑) tKSI2 400 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ, C = 100 pFNote 0 300 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2 120 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2 240 ns
SS20 setup time
(to SCK20 first edge) tSSK2 100 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2 400 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 78125 bps
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD 347
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK20 cycle time tKCY3 800 ns
ASCK20 high-/low-
level width tKH3,
tKL3 400 ns
Transfer rate 39063 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
348
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
CC
t
XL
t
XH
CL1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
t
CPL
t
CPH
Interrupt Input Timing
INTP0 to INTP2
t
INTL
t
INTH
RESET Input Timing
RESET
tRSL
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD 349
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
t
R
t
F
t
KL3
t
KCY3
t
KH3
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
350
8-Bit A/D Converter Characteristics (
µ
PD78912xA(A1), 78912xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (
µ
PD78912xA(A1)),
–40 to +125°C (
µ
PD78912xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 Bits
Overall errorNotes 1, 2
±0.4 ±1.0 %FSR
Conversion time tCONV 14 28
µ
s
Analog input
voltage
VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (
µ
PD78913xA(A1), 78913xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (
µ
PD78913xA(A1)),
–40 to +125°C (
µ
PD78913xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
Overall errorNotes 1, 2 ±0.4 ±0.6 %FSR
Conversion time tCONV 14 28
µ
s
Zero-scale errorNo tes 1, 2 ±0.6 %FSR
Full-scale errorNotes 1, 2 ±0.6 %FSR
Integral linearity
errorNote 1 ILE ±4.5 LSB
Differential linearity
errorNote 1 DLE ±2.0 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 28 ELECTRICAL SPECIFICATIONS (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD 351
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = –40 to +110°C (
µ
PD78912xA(A1), 78913xA(A1)), –40 to +125°C (
µ
PD78912xA(A2), 78913xA(A2)) )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 27/fCC s Oscillation
stabilization wait
timeNote
tWAIT
Release by interrupt request 27/fCC s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark f
cc: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD
352
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136 B(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA
Total for all pins
µ
PD78F9136B
–30 mA
Per pin –7 mA
Output current, high IOH
Total for all pins
µ
PD78F9136B(A)
–22 mA
Per pin 30 mA
Total for all pins
µ
PD78F9136B
160 mA
Per pin 10 mA
Output current, low IOL
Total for all pins
µ
PD78F9136B(A)
120 mA
In normal operation mode –40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
0 V
V
PP
1.8 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 353
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
oscillator
CL2CL1
Oscillation frequency (fCC)Note 2.0 4.0 MHz
CL1 input frequency (fCC)Note 1.0 5.0 MHz
CL1 CL2
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
CL1 input frequency (fCC)Note VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
CL1 CL2
OPEN
CL1 input high-/low-level
width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCC1 VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz
fCC2 VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz
fCC3
R = 11.0 kΩ, C = 22 pF
Target: 2 MHz
VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz
fCC4 VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz
fCC5 VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz
fCC6
R = 6.8 kΩ, C = 22 pF
Target: 3 MHz
VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz
fCC7 VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz
fCC8 VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz
Oscillator frequency
fCC9
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz
Remark So that the TYP. spec. is satisfied between 2.0 to 4. 0 MHz , set one of the abov e nine pa tterns for R an d
C.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD
354
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA
Total for all pins
µ
PD78F9136B
–15 mA
Per pin –1 mA
Output current, high IOH
Total for all pins
µ
PD78F9136B(A)
–11 mA
Per pin 10 mA
Total for all pins
µ
PD78F9136B
80 mA
Per pin 3 mA
Output current, low IOL
Total for all pins
µ
PD78F9136B(A)
60 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V VIH2 P50 to P53 With N-ch open
drain VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 CL1, CL2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 CL1, CL2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78F9136B) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78F9136B(A)) 1.0 V
VOL1 Pins other
than P50 to
P53
VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA
(
µ
PD78F9136B) 1.0 V
VDD = 4.5 to 5.5 V, IOL = 3 mA
(
µ
PD78F9136B(A)) 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 355
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than CL1,
CL2, or P50 to P53 3
µ
A
ILIH2 CL1, CL2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than CL1,
CL2, or P50 to P53 –3
µ
A
ILIL2 CL1, CL2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 50 100 200 kΩ
VDD = 5.0 V ±10%Note 4 6.5 18.0 mA
VDD = 3.0 V ±10%Note 5 3.9 7.9 mA
IDD1Note 2 4.0 MHz RC oscillation
operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 3.0 5.0 mA
VDD = 5.0 V ±10%Note 4 2.5 5.0 mA
VDD = 3.0 V ±10%Note 5 1.0 2.0 mA
IDD2Note 2 4.0 MHz RC oscillation
HALT mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 0.75 1.5 mA
VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 10
µ
A
VDD = 5.0 V ±10%Note 4 7.7 20.3 mA
VDD = 3.0 V ±10%Note 5 5.1 10.2 mA
Power supply
current
IDD4Note 3 4.0 MHz RC oscillation
A/D operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 4.0 7.0 mA
Notes 1. When port 5 is in i nput mode, a low-level input leakag e current of –60
µ
A (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD
356
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V, RC Oscillation Mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1 21 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1 21 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.2 0.2 0.2 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 357
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 16
µ
s Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 16
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD
358
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 k Ω,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 359
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD
360
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
CC
t
XL
t
XH
CL1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
tTIL tTIH
1/fTI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
t
INTL
t
INTH
RESET Input Timing
RESET
t
RSL
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 361
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
t
R
t
F
t
KL3
t
KCY3
t
KH3
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD
362
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V 14 100
µ
s
2.7 V ≤ VDD ≤ 5.5 V 14 100
µ
s
Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1, 2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 29 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B, 78F9136B(A))
User’s Manual U14643EJ2V0UD 363
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 27/fCC s Oscillation
stabilization wait
timeNote
tWAIT
Release by interrupt request 27/fCC s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark f
CC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD
364
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –4 mA Output current, high IOH
Total for all pins –14 mA
Per pin 5 mA Output current, low IOL
Total for all pins 80 mA
In normal operation mode –40 to +105 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (4.5 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (4.5 V) of the operating
voltage range of VDD (see b in the figure below).
4.5 V
V
DD
0 V
0 V
V
PP
4.5 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD 365
System Clock Oscillator Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
oscillator
CL2CL1
Oscillation frequency (fCC)Note 2.0 4.0 MHz
CL1 input frequency (fCC)Note 1.0 5.0 MHz
External
clock
CL1 CL2
OPEN
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Construct the oscillator with R and C devices that are guaranteed to operate at TA = 105°C.
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD
366
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA Output current, high IOH
Total for all pins –7 mA
Per pin 1.6 mA Output current, low IOL
Total for all pins 40 mA
VIH1 Pins other than described below 0.7VDD VDD V
VIH2 P50 to P53 With N-ch open drain 0.7VDD 10 V
VIH3 RESET, P20 to P25 0.8VDD VDD V
Input voltage, high
VIH4 CL1, CL2 VDD – 0.1 VDD V
VIL1 Pins other than described below 0 0.3VDD V
VIL2 P50 to P53 0 0.3VDD V
VIL3 RESET, P20 to P25 0 0.2VDD V
Input voltage, low
VIL4 CL1, CL2 0 0.1 V
VOH1 IOH = –1 mA VDD – 2.0 V Output voltage, high
VOH2 IOH = –100
µ
A VDD – 1.0 V
IOL = 1.6 mA 2.0 V VOL1 Pins other than
P50 to P53 IOL = 400
µ
A 1.0 V
Output voltage, low
VOL2 P50 to P53 IOL = 1.6 mA 1.0 V
ILIH1 Pins other than CL1, CL2, or
P50 to P53 10
µ
A
ILIH2 CL1, CL2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open drain) VI = 10 V 80
µ
A
ILIL1 Pins other than CL1, CL2, or
P50 to P53 –10
µ
A
ILIL2 CL1, CL2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open drain)
VI = 0 V
–10Note
µ
A
Output leakage
current, high ILOH VO = VDD 10
µ
A
Output leakage
current, low ILOL VO = 0 V –10
µ
A
Note When port 5 is in input mode, a low-level input leakage current of –60
µ
A (MAX.) flows only for 1 cycle time
after a read instruction has been exec uted to port 5.
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD 367
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 or P60 to
P63 50 100 300 kΩ
IDD1Note 1 4.0 MHz RC oscillation operating mode
(R = 4.7 kΩ, C = 22 pF) Note 3 7.5 20.0 mA
IDD2Note 1 4.0 MHz RC oscillation HALT mode
(R = 4.7 kΩ, C = 22 pF) Note 3 3.0 5.5 mA
IDD3Note 1 STOP mode 1 1000
µ
A
Power supply
current
IDD4Note 2 4.0 MHz RC oscillation A/D operating mode
(R = 4.7 kΩ, C = 22 pF) Note 3 8.7 22.3 mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Flash Memory Write/Erase Characteristics
(TA = 10 to 40°C, VDD = 4.5 to 5.5 V, RC Oscillation Operating Mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1 21 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1
22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1 21 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.2 0.2 0.2 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD
368
AC Characteristics
(1) Basic operation (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time
(minimum instruction
execution time)
TCY 0.4 8
µ
s
TI80 input high-/low-
level width tTIH,
tTIL 0.1
µ
s
TI80 input frequency fTI 0 4
MHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage VDD [V]
123456
0.1
0.4
1.0
10
60
Cycle time TCY [ s]
Guaranteed
operation range
µ
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD 369
(2) Serial interface (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY1 800 ns
SCK20 high-/low-
level width tKH1,
tKL1 t
KCY1/2 – 50 ns
SI20 setup time
(to SCK20↑) tSIK1 150 ns
SI20 hold time
(from SCK20↑) tKSI1 400 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ, C = 100 pFNote 0 250 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK20 cycle time tKCY2 800 ns
SCK20 high-/low-
level width tKH2,
tKL2 400 ns
SI20 setup time
(to SCK20↑) tSIK2 100 ns
SI20 hold time
(from SCK20↑) tKSI2 400 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ, C = 100 pFNote 0 300 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2 120 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2 240 ns
SS20 setup time
(to SCK20 first edge) tSSK2 100 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2 400 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 78125 bps
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD
370
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK20 cycle time tKCY3 800 ns
ASCK20 high-/low-
level width tKH3,
tKL3 400 ns
Transfer rate 39063 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD 371
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
tXL tXH
CL1 input VIH4 (MIN.)
VIL4 (MAX.)
TI Timing
TI80
t
TIL
t
TIH
1/f
TI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD
372
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD 373
10-Bit A/D Converter Characteristics (TA = –40 to +105°C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
Overall errorNotes 1,2 ±0.4 ±0.6 %FSR
Conversion time tCONV 14 28
µ
s
Zero-scale errorNo tes 1,2 ±0.6 %FSR
Full-scale errorNotes 1,2 ±0.6 %FSR
Integral linearity
errorNote 1 ILE ±4.5 LSB
Differential linearity
errorNote 1 DLE ±2.0 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 30 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136B(A1))
User’s Manual U14643EJ2V0UD
374
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +105°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 27/fCC s Oscillation
stabilization wait
timeNote
tWAIT
Release by interrupt request 27/fCC s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark f
cc: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 375
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD, AVDD VDD = AVDD –0.3 to +6.5 V Supply voltage
VPP Note –0.3 to +10.5 V
VI1 Pins other than P50 to P53 –0.3 to VDD + 0.3 V Input voltage
VI2 P50 to P53 With N-ch open drain –0.3 to +13 V
Output voltage VO –0.3 to VDD + 0.3 V
Per pin –10 mA Output current, high IOH
Total for all pins –30 mA
Per pin 30 mA Output current, low IOL
Total for all pins 160 mA
In normal operation mode –40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Storage temperature Tstg –40 to +125 °C
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
VDD
0 V
0 V
VPP 1.8 V
a b
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
376
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended
Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
oscillator
CL2CL1
Oscillation frequency (fCC)Note 1 VDD = oscillation voltage
range 2.0 4.0 MHz
CL1 input frequency (fCC)Note 1 1.0 5.0 MHz
CL1 CL2
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
CL1 input frequency (fCC)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
CL1 CL2
OPEN
CL1 input high-/low-level
width (tXH, tXL) 85 500 ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCC1 VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz
fCC2 VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz
fCC3
R = 11.0 kΩ, C = 22 pF
Target: 2 MHz
VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz
fCC4 VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz
fCC5 VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz
fCC6
R = 6.8 kΩ, C = 22 pF
Target: 3 MHz
VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz
fCC7 VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz
fCC8 VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz
Oscillator frequency
fCC9
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz
Remark So that the TYP. Spec is satisfied between 2.0 to 4.0 MHz , set one of the abov e nine patterns for R an d
C.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD 377
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin –1 mA Output current, high IOH
Total for all pins –15 mA
Per pin 10 mA Output current, low IOL
Total for all pins 80 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 Pins other than described
below VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V VIH2 P50 to P53 With N-ch open
drain VDD = 1.8 to 5.5 V
TA = 25 to 85°C
0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 CL1, CL2
VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 Pins other than described
below VDD = 1.8 to 5.5 V 0 0.1VDD V
VIL2 P50 to P53 VDD = 2.7 to 5.5 V 0 0.3VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P20 to P25
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 CL1, CL2
VDD = 1.8 to 5.5 V 0 0.1 V
VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V Output voltage, high
VOH2 VDD = 1.8 to 5.5 V, IOH = –100
µ
A VDD – 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VOL1 Pins other
than P50 to
P53 VDD = 1.8 to 5.5 V, IOL = 400
µ
A 0.5 V
VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V
Output voltage, low
VOL2 P50 to P53
VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V
Remark Unless specifi ed otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
378
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 Pins other than CL1,
CL2, or P50 to P53 3
µ
A
ILIH2 CL1, CL2
VI = VDD
20
µ
A
Input leakage current,
high
ILIH3 P50 to P53 (N-ch open
drain) VI = 12 V 20
µ
A
ILIL1 Pins other than CL1,
CL2, or P50 to P53 –3
µ
A
ILIL2 CL1, CL2 –20
µ
A
Input leakage current,
low
ILIL3 P50 to P53 (N-ch open
drain)
VI = 0 V
–3Note 1
µ
A
Output leakage
current, high ILOH VO = VDD 3
µ
A
Output leakage
current, low ILOL VO = 0 V –3
µ
A
Software pull-up
resistance R1 VI = 0 V, for pins other than P50 to P53 50 100 200 kΩ
VDD = 5.0 V ±10%Note 4 5.0 15.0 mA
VDD = 3.0 V ±10%Note 5 1.9 4.9 mA
IDD1Note 2 4.0 MHz RC oscillation
operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 1.5 3.0 mA
VDD = 5.0 V ±10%Note 4 2.5 5.0 mA
VDD = 3.0 V ±10%Note 5 1.0 2.0 mA
IDD2Note 2 4.0 MHz RC oscillation
HALT mode (R = 4.7
kΩ, C = 22 pF) VDD = 2.0 V ±10%No te 5 0.75 1.5 mA
VDD = 5.0 V ±10% 0.1 30
µ
A
VDD = 3.0 V ±10% 0.05 10
µ
A
IDD3Note 2 STOP mode
VDD = 2.0 V ±10% 0.05 10
µ
A
VDD = 5.0 V ±10%Note 4 6.2 17.3 mA
VDD = 3.0 V ±10%Note 5 3.1 7.2 mA
Power supply
current
IDD4Note 3 4.0 MHz RC oscillation
A/D operating mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 5 2.5 5.0 mA
Notes 1. When port 5 is in i nput mode, a low-level input leakag e current of –60
µ
A (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode op eration (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operatio n (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD 379
Flash Memory Write/Erase Characteristics (TA = 10 to 40 °C, VDD = 1.8 to 5.5 V, RC Oscillation Operating Mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Write current
(VDD pin) Note IDDW When VPP supply voltage = VPP1 18 mA
Write current
(VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA
Erase current
(VDD pin) Note IDDE When VPP supply voltage = VPP1 18 mA
Erase current
(VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA
Unit erase time ter 0.5 1 1 s
Total erase time tera 20 s
Rewrite count Erase/write are regarded as 1 cycle 20 20 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
380
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 16
µ
s Cycle time
(minimum instruction
execution time)
TCY
VDD = 1.8 to 5.5 V 1.6 16
µ
s
VDD = 2.7 to 5.5 V 0.1
µ
s TI80 input high-/low-
level width tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz
TI80 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
Interrupt input high-
/low-level width tINTH,
tINTL INTP0 to INTP2 10
µ
s
RESET low-level
width tRSL 10
µ
s
CPT20 input high-
/low-level width tCPH,
tCPL 10
µ
s
TCY vs VDD
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD 381
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
SCK20 high-/low-
level width tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2 – 150 ns
VDD = 2.7 to 5.5 V 150 ns
SI20 setup time
(to SCK20↑) tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns
SO20 output delay
time from SCK20↓ tKSO1 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCK20 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
SCK20 high-/low-
level width tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns
SI20 setup time
(to SCK20↑) tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SI20 hold time
(from SCK20↑) tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns
SO20 output delay
time from SCK20↓ tKSO2 R = 1 kΩ,
C = 100 pFNote VDD = 1.8 to 5.5 V 0 1000 ns
VDD = 2.7 to 5.5 V 120 ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 1.8 to 5.5 V 400 ns
VDD = 2.7 to 5.5 V 240 ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 1.8 to 5.5 V 800 ns
VDD = 2.7 to 5.5 V 100 ns
SS20 setup time
(to SCK20 first edge) tSSK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V 600 ns
Note R and C are the load resistance and load capacitance of the SO output line.
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
382
(iii) UART mode (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(iv) UART mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns
ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns
ASCK20 high-/low-
level width tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps
Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF 1
µ
s
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD 383
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
CC
t
XL
t
XH
CL1 input V
IH4
(MIN.)
V
IL4
(MAX.)
TI Timing
TI80
tTIL tTIH
1/fTI
Capture Input Timing
CPT20
tCPL tCPH
Interrupt Input Timing
INTP0 to INTP2
tINTL tINTH
RESET Input Timing
RESET
t
RSL
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
384
Serial Transfer Timing
3-wire serial I/O mode:
SCK20
t
KLm
t
KCYm
t
KHm
SI20 Input data
t
KSIm
t
SIKm
Output data
t
KSOm
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
t
KAS2
SO20
SS20
Output data
t
KDS2
tSSK2 tKSS2
SS20
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
ASCK20
tRtF
tKL3
tKCY3
tKH3
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD 385
10-Bit A/D Converter Characteristics
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 Bits
4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR
Overall errorNotes 1,2
1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR
2.7 V ≤ VDD ≤ 5.5 V 14 100
µ
s Conversion time tCONV
1.8 V ≤ VDD < 2 .7 V 28 100
µ
s
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Zero-scale errorNo tes 1,2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ VDD < 4.5 V ±0.6 %FSR
Full-scale errorNotes 1,2
1.8 V ≤ VDD < 2.7 V ±1.2 %FSR
4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB
2.7 V ≤ VDD < 4.5 V ±4.5 LSB
Integral linearity
errorNote 1 ILE
1.8 V ≤ VDD < 2.7 V ±8.5 LSB
4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB
2.7 V ≤ VDD < 4.5 V ±2.0 LSB
Differential linearity
errorNote 1 DLE
1.8 V ≤ VDD < 2.7 V ±3.5 LSB
Analog input voltage VIAN 0 AVDD V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-sc ale value (%FSR).
CHAPTER 31 ELECTRICAL SPECIFICATIONS (
µ
PD78F9136A)
User’s Manual U14643EJ2V0UD
386
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention
supply voltage VDDDR 1.8 5.5 V
Release signal
set time tSREL 0
µ
s
Release by RESET 27/fCC s Oscillation
stabilization wait
timeNote
tWAIT
Release by interrupt request 27/fCC s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark f
CC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
User’s Manual U14643EJ2V0UD 387
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES)
(
µ
PD78910xA, 78911xA, 7891 0xA(A), 78911xA(A))
IDD vs VDD (System clock: 5.0 MHz crystal resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Crystal resonator
5.0 MHz
22 pF 22 pF
(TA = 25˚C)
Power supply voltage V
DD
(V)
Power supply current I
DD
(mA)
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
User’s Manual U14643EJ2V0UD
388
IDD vs VDD (System clock: 4.0 MHz crystal resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Crystal resonator
4.0 MHz
22 pF 22 pF
(T
A
= 25˚C)
Power supply voltage V
DD
(V)
Power supply current I
DD
(mA)
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (
µ
PD78910xA, 78911xA, 78910xA(A), 78911xA(A))
User’s Manual U14643EJ2V0UD 389
IDD vs VDD (System clock: 2.0 MHz crystal resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Crystal resonator
2.0 MHz
47 pF 47 pF
(T
A
= 25˚C)
Power supply current I
DD
(mA)
Power supply voltage V
DD
(V)
User’s Manual U14643EJ2V0UD
390
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
(
µ
PD78910xA(A1), 78911 xA(A1), 789 10xA(A2), 78911xA(A2))
IDD vs VDD (System clock: 5.0 MHz ceramic resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Ceramic resonator
5.0 MHz
22 pF 22 pF
(T
A
= 25˚C)
Power supply voltage VDD (V)
Power supply current IDD (mA)
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD 391
IDD vs VDD (System clock: 4.0 MHz ceramic resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Ceramic resonator
4.0 MHz
22 pF 22 pF
(T
A
= 25˚C)
Power supply voltage V
DD
(V)
Power supply current I
DD
(mA)
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (
µ
PD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
User’s Manual U14643EJ2V0UD
392
IDD vs VDD (System clock: 2.0 MHz ceramic resonator)
01 2345678
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
X2
X1
Ceramic resonator
2.0 MHz
47 pF 47 pF
(T
A
= 25˚C)
Power supply current I
DD
(mA)
Power supply voltage V
DD
(V)
User’s Manual U14643EJ2V0UD 393
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARAC TERI STICS
(REFERENCE VALUES) (
µ
PD78912xA, 78913xA, 7891 2xA(A), 78913xA(A), 78F9136A)
fCC vs VDD (RC oscillation, R = 11 kΩ, C= 22 pF)
23456
Supply voltage V
DD
[V]
1.4
1.6
1.8
2.0
2.2
2.4
2.6
System clock frequency f
CC
[MHz]
(T
A
= –40
˚C
)
Sample A
Sample B
Sample C
CL2CL1 11 kΩ
22 pF
1.4
1.6
1.8
2.0
2.2
2.4
2.6
23456
Supply voltage V
DD
[V]
System clock frequency f
CC
[MHz]
(T
A
= 25
˚C
)
CL2CL1 11 kΩ
22 pF
Sample A
Sample B
Sample C
1.4
1.6
1.8
2.0
2.2
2.4
2.6
System clock frequency f
CC
[MHz]
23456
Supply voltage V
DD
[V]
(T
A
= 85
˚C
)
Sample A
Sample B
Sample C
CL2CL1 11 kΩ
22 pF
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (
µ
PD78912xA, 78913xA, 78912xA(A) , 78913xA(A), 78F9136(A)
User’s Manual U14643EJ2V0UD
394
fCC vs VDD (RC oscillation, R = 4.7 kΩ, C= 22 pF)
(T
A
= –40
˚C
)
23456
Supply voltage V
DD
[V]
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency fCC [MHz]
Sample A
Sample B
Sample C
CL2CL1 4.7 kΩ
22 pF
(T
A
= 25
˚C
)
23456
Supply voltage V
DD
[V]
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency f
CC
[MHz]
Sample A
Sample B
Sample C
CL2CL1 4.7 kΩ
22 pF
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency f
CC
[MHz]
23456
Supply voltage VDD [V]
(TA = 85
˚C
)
Sample A
Sample B
Sample C
CL2CL1 4.7 kΩ
22 pF
User’s Manual U14643EJ2V0UD 395
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARAC TERI STICS
(REFERENCE VALUES) (
µ
PD78912xA(A1), 78913 xA(A1), 78912xA(A2), 78913xA(A2))
fCC vs VDD (RC oscillation, R = 11 kΩ, C= 22 pF)
23456
Supply voltage V
DD
[V]
1.4
1.6
1.8
2.0
2.2
2.4
2.6
System clock frequency f
CC
[MHz]
(T
A
= –40
˚C
)
CL2CL1 11 kΩ
22 pF
Sample A
Sample B
Sample C
1.4
1.6
1.8
2.0
2.2
2.4
2.6
23456
Supply voltage V
DD
[V]
System clock frequency fCC [MHz]
(T
A
= 25
˚C
)
CL2CL1 11 kΩ
22 pF
Sample A
Sample B
Sample C
1.4
1.6
1.8
2.0
2.2
2.4
2.6
System clock frequency fCC [MHz]
23456
Supply voltage V
DD
[V]
(T
A
= 85
˚C
)
Sample A
Sample B
Sample C
CL2CL1 11 kΩ
22 pF
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (
µ
PD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
User’s Manual U14643EJ2V0UD
396
fCC vs VDD (RC oscillation, R = 4.7 kΩ, C= 22 pF)
(T
A
= –40
˚C
)
23456
Supply voltage V
DD
[V]
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency fCC [MHz]
CL2CL1 4.7 kΩ
22 pF
Sample A
Sample B
Sample C
(T
A
= 25
˚C
)
23456
Supply voltage V
DD
[V]
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency f
CC
[MHz]
CL2CL1 4.7 kΩ
22 pF
Sample A
Sample B
Sample C
3.4
3.6
3.8
4.0
4.2
4.4
4.6
System clock frequency f
CC
[MHz]
23456
Supply voltage VDD [V]
(TA = 85
˚C
)
CL2CL1 4.7 kΩ
22 pF
Sample A
Sample B
Sample C
User’s Manual U14643EJ2V0UD 397
CHAPTER 36 PACKAG E DRA WI NG
S
S
H
J
T
I
G
D
E
F
CB
K
PL
U
N
ITEM
B
C
I
L
M
N
30-PIN PLASTIC SSOP (7.62 mm (300))
A
K
D
E
F
G
H
J
P
30 16
115
A
detail of lead end
M
M
T
MILLIMETERS
0.65 (T.P.)
0.45 MAX.
0.13
0.5
6.1±0.2
0.10
9.85±0.15
0.17±0.03
0.1±0.05
0.24
1.3±0.1
8.1±0.2
1.2
+0.08
−0.07
1.0±0.2
3°+5°
−3°
0.25
0.6±0.15
U
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
S30MC-65-5A4-2
User’s Manual U14643EJ2V0UD
398
CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
The
µ
PD789104A, 789114A, 789124A, and 789134A Subseries should be soldered and mounted under the
following recommended con ditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 37-1. Surface Mounting Type Soldering Conditions (1/2)
(1)
µ
PD789101AMC-×××-5A4,
µ
PD789102AMC-×××-5A4,
µ
PD789104AMC-×××-5A4
µ
PD789111AMC-×××-5A4,
µ
PD789112AMC-×××-5A4,
µ
PD789114AMC-×××-5A4
µ
PD789121AMC-×××-5A4,
µ
PD789122AMC-×××-5A4,
µ
PD789124AMC-×××-5A4
µ
PD789131AMC-×××-5A4,
µ
PD789132AMC-×××-5A4,
µ
PD789134AMC-×××-5A4
µ
PD789101AMC(A)-×××-5A4,
µ
PD789102AMC(A)-×××-5A4,
µ
PD789104AMC(A)-×××-5A4
µ
PD789111AMC(A)-×××-5A4,
µ
PD789112AMC(A)-×××-5A4,
µ
PD789114AMC(A)-×××-5A4
µ
PD789121AMC(A)-×××-5A4,
µ
PD789122AMC(A)-×××-5A4,
µ
PD789124AMC(A)-×××-5A4
µ
PD789131AMC(A)-×××-5A4,
µ
PD789132AMC(A)-×××-5A4,
µ
PD789134AMC(A)-×××-5A4
µ
PD789101AMC(A1)-×××-5A4,
µ
PD789102AMC(A1)-×××-5A4,
µ
PD789104AMC(A1)-×××-5A4
µ
PD789111AMC(A1)-×××-5A4,
µ
PD789112AMC(A1)-×××-5A4,
µ
PD789114AMC(A1)-×××-5A4
µ
PD789121AMC(A1)-×××-5A4,
µ
PD789122AMC(A1)-×××-5A4,
µ
PD789124AMC(A1)-×××-5A4
µ
PD789131AMC(A1)-×××-5A4,
µ
PD789132AMC(A1)-×××-5A4,
µ
PD789134AMC(A1)-×××-5A4
µ
PD789101AMC(A2)-×××-5A4,
µ
PD789102AMC(A2)-×××-5A4,
µ
PD789104AMC(A2)-×××-5A4
µ
PD789111AMC(A2)-×××-5A4,
µ
PD789112AMC(A2)-×××-5A4,
µ
PD789114AMC(A2)-×××-5A4
µ
PD789121AMC(A2)-×××-5A4,
µ
PD789122AMC(A2)-×××-5A4,
µ
PD789124AMC(A2)-×××-5A4
µ
PD789131AMC(A2)-×××-5A4,
µ
PD789132AMC(A2)-×××-5A4,
µ
PD789134AMC(A2)-×××-5A4
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less IR35-00-3
VPS Package peak temperature: 215°C, Time: 40 se conds max. (at 200°C or higher),
Count: Three times or less VP15-00-3
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature) WS60-00-1
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) –
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U14643EJ2V0UD 399
Table 37-1. Surface Mounting Type Soldering Conditions (2/2)
(2)
µ
PD78F9116BMC-5A4,
µ
PD78F9136BMC-5A4,
µ
PD78F9116BMC(A)-5A4,
µ
PD78F9136BMC(A)-5A4,
µ
PD78F9116BMC(A1)-5A4,
µ
PD78F9136BMC(A1)-5A4
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 10 hours)
IR35-107-2
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 10 hours)
VP15-107-2
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: Once
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) –
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage perio d.
Caution Do not use different soldering methods together (except for partial heating).
(3)
µ
PD78F9116AMC-5A4,
µ
PD78F9136AMC-5A4
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less, Exposure limit: 7 days Note
(after that, prebake at 125°C for 10 hours)
IR35-107-3
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less, Exposure limit: 7 days Note
(after that, prebake at 125°C for 10 hours)
VP15-107-3
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once
Preheating temperature: 120°C max.(package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) –
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage perio d.
Caution Do not use different soldering methods together (except for partial heating).
User’s Manual U14643EJ2V0UD
400
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the
µ
PD789104A/114A/124A/134A Subseries.
Figure A-1 shows the development tool configuration.
• Support of the PC98-NX Series
Unless otherwise specified, the
µ
PD789104A/114A/124A/134A Subseries supported by IBM PC/ATTM and
compatibles can be used for the PC98-NX Ser ies. When using the PC98-NX Ser ies, refer to the descriptions of
IBM PC/AT and compatibles.
• Windows
Unless otherwise specified, “Windows” indicates the following OSs.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Ver . 4.0
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14643EJ2V0UD 401
Figure A-1. Development Tools
·
Software package
Software package
·
Assembler package
·
C compiler package
·
Device file
·
C library source file
Note 1
·
Integrated debugger
·
System simulator
·
Project manager
(Windows version only)
Note 2
Language processing software Debugging software
Control software
Host machine
(PC or EWS)
Interface adapter
Flash memory writing tools
Flash programmer In-circuit emulator
Power supply unit
Emulation board
Emulation probe
Target system
Conversion socket or
conversion adapter
Flash memory
writing adapter
Flash memory
Notes 1. The C library source file is not included in the software package.
2. The project manager is included in the asse mbler package and is available only for Windows.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14643EJ2V0UD
402
A.1 Software Package
Various software tools for 78K/0S development are integrated in one package.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files
SP78K0S
Software package
Part number:
µ
S××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µ
S×××× SP78K0S
×××× Host Machine OS Supply Medium
AB17 Japanese Windows
BB17
PC-9800 series,
IBM PC/AT and compatibles English Windows
CD-ROM
A.2 Language Processing Software
Program that converts program written in mnemonic into object codes that can be executed by a
microcontroller.
In addition, automatic functions to generate a symbol table and optimize branch instructions are also
provided.
Used in combination with a device file (DF789136) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the package).
RA78K0S
Assembler package
Part number:
µ
S××××RA78K0S
Program that converts program written in C language into object codes that can be executed by a
microcontroller.
Used in combination with an assembler package (RA78K0S) and device file (DF789136) (both sold
separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the assembler package).
CC78K0S
C compiler package
Part number:
µ
S××××CC78K0S
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
DF789136Note 1
Device file
Part number:
µ
S××××DF789136
Source file of functions constituting the object library included in the C compiler package.
Necessary for changing the object library included in the C compiler package according to the
customer’s specifications.
Since this is the source file, its working environment does not depend on any particular operating
system.
CC78K0S-LNote 2
C library source file
Part number:
µ
S××××CC78K0S-L
Notes 1. DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14643EJ2V0UD 403
Remark ×××× in the part number differs depending on the host machine and o pe rating system to be use d.
µ
S××××RA78K0S
µ
S××××CC78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5” 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series,
IBM PC/AT and compatibles
English Windows
3P17 HP9000 series 700TM HP-UXTM (Rel.10.10)
3K17 SPARCstationTM SunOSTM (Rel.4.1.1),
SolarisTM (Rel.2.5.1)
CD-ROM
µ
S××××DF789136
µ
S××××CC78K0S-L
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13
PC-9800 series,
IBM PC/AT and compatibles English Windo ws
3.5” 2HD FD
3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT
3K13 3.5” 2HD FD
3K15
SPARCstation SunOS (Rel.4.1.1),
Solaris (Rel.2.5.1) 1/4” CGMT
A.3 Control Software
Project Manager Control software provided for efficient user program development in the Windows
environment. The Project Manager allows a series of tasks required for user program
development to be performed, including starting the editor, building, and starting the
debugger.
<Caution>
The Project Manager is included in the assembler package (RA78K0S).
It cannot be used in an environment other than Windows.
A.4 Flash Memory Writing Tools
Flashpro III
(part number: FL-PR3, PG-FP3)
Flashpro IV
(part number: FL-PR4, PG-FP4)
Flash programmer
Flash programmer dedicated to microcontrollers incorporating flash memory.
FA-30MC
Flash memory writing adapter Flash memory wr iting adapter. Used connected to Flashpro III.
30-pin plastic SSOP (MC-5A4 type)
Remark FL-PR3, FL-PR4, and FA-30MC are produc ts of Naito Densei Machida Mfg. Co., Ltd.
For further information, conta ct: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4 191)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14643EJ2V0UD
404
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator In-circuit emulator for debugging the hardware and software of an application system using the
78K/0S Series. Used with an integrated debugger (ID78K0S-NS). Used in combination with
an AC adapter, emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
In-circuit emulator In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further
enhanced by adding a coverage function and enhancing the tracer and timer functions.
IE-70000-MC-PS-B
AC adapter Adapter for supplying power from a 100 to 240 VAC outlet.
IE-70000-98-IF-C
Interface adapter Adapter required when using a PC-9800 series (except notebook type) as the host machine (C
bus supporte d).
IE-70000-CD-IF-A
PC card interface PC card and interface cable required when using a notebook type PC as the host machine
(PCMICA socket supported).
IE-70000-PC-IF-C
Interface adapter Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus
supported).
IE-70000-PCI-IF-A
Interface adapter Adapter required when using a personal computer incorporating a PCI bus as the host
machine.
IE-789136-NS-EM1
Emulation board Emulation board for emulating the peripheral hardware inherent to the device.
Used in combination with an in-circuit emulator.
NP-30MC
Emulation probe Probe for connecting the in-circuit emulator and target system.
Used in combination with the NSPACK30BK and YSPACK30BK.
NSPACK30BK
YSPACK30BK
Conversion adapter
Conversion adapter used to connect a target system board designed to allow mounting a 30-
pin plastic SSOP (MC-5A4 type) and the NP-30MC.
Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)
2. The NSPACK30BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14643EJ2V0UD 405
A.6 Debugging Tools (Software)
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing with the
source program using an integrating window function that associates the source program,
disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789136) (sold separately).
ID78K0S-NS
Integrated debugger
Part number:
µ
S××××ID78K0S-NS
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
It can be used to debug the target system at C source level or assembler level while simulating
the operation of the target system on the host machine.
Using SM78K0S, the logic and performance of the application can be verified independently of
hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used in combination with a device file (DF789136) (sold separately).
SM78K0S
System simulator
Part number:
µ
S××××SM78K0S
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
DF789136Note
Device file
Part number:
µ
S××××DF789136
Note DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µ
S××××ID78K0S-NS
µ
S××××SM78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5” 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series,
IBM PC/AT and compatibles
English Windows
CD-ROM
User’s Manual U14643EJ2V0UD
406
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the
configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter
150 mm
Emulation board
IE-789136-NS-EM1
CN2
Emulation probe
NP-30MC Conversion adapter:
YSPACK30BK,
NSPACK30BK
Board on end of NP-30MC
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Remarks 1. The NP-30MC is a product of Naito De nsei Machida Mfg. Co., Ltd.
2. The YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION.
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
User’s Manual U14643EJ2V0UD 407
Figure B-2. Connection Condition of Target System
31 mm
37 mm
Emulation probe
NP-30MC
13 mm
Emulation board
IE-789136-NS-EM1
15 mm
20 mm
5 mm
Board on end of NP-30MC
Conversion adapter
YSPACK30BK,
NSPACK30BK
Guide pin
YQGUIDE
Target system
Remarks 1. The NP-30MC is a product of Naito De nsei Machida Mfg. Co., Ltd.
2. The YSPACK30BK, NSPACK30BK, and YQGUIDE are products of TOKYO ELETECH
CORPORATION.
User’s Manual U14643EJ2V0UD
408
APPENDIX C REGISTER INDEX
C.1 Register Name Index (Alphabetical Order)
[A]
A/D conversion result register 0 (ADCR0)...........................................................................................................143, 155
A/D converter mode register 0 (ADM0)...............................................................................................................144, 156
Analog input channel specification register 0 (ADS0) .........................................................................................145, 157
Asynchronous serial interface mode register 20 (ASIM20) .................................................................172, 178, 181, 193
Asynchronous serial interface status register 20 (ASIS20) .................................................................................174, 182
[B]
Baud rate generator control register 20 (BRGC20).....................................................................................175, 183, 194
[E]
8-bit compare register 80 (CR80)............................................................................................................................... 125
8-bit timer counter 80 (TM80)..................................................................................................................................... 125
8-bit timer mode control register 80 (TMC80)............................................................................................................. 126
Exter nal interrupt mode register 0 (INTM0)................................................................................................................ 212
[I]
Interrupt mask flag register 0 (MK0)............................................................................................................................211
Interrupt mask flag register 1 (MK1)............................................................................................................................211
Interrupt request flag register 0 (IF0).......................................................................................................................... 210
Interrupt request flag register 1 (IF1).......................................................................................................................... 210
[M]
Multiplication data register A0 (MRA0)....................................................................................................................... 202
Multiplication data register B0 (MRB0)....................................................................................................................... 202
Multiplier control register 0 (MULC0).......................................................................................................................... 204
[O]
Oscillation stabilization time select register (OSTS)................................................................................................... 222
[P]
Port 0 (P0).................................................................................................................................................................... 82
Port 1 (P1).................................................................................................................................................................... 83
Port 2 (P2).................................................................................................................................................................... 84
Port 5 (P5).................................................................................................................................................................... 88
Port 6 (P6).................................................................................................................................................................... 89
Port mode register 0 (PM0).......................................................................................................................................... 90
Port mode register 1 (PM1).......................................................................................................................................... 90
Port mode register 2 (PM2)...........................................................................................................................90, 115, 127
Port mode register 5 (PM5).......................................................................................................................................... 90
Processor clock control register (PCC) .................................................................................................................96, 103
Pull-up resistor option register 0 (PU0) ........................................................................................................................ 91
Pull-up resistor option register B2 (PUB2).................................................................................................................... 92
APPENDIX C REGISTER INDEX
User’s Manual U14643EJ2V0UD 409
[R]
Receive buffer register 20 (RXB20) ............................................................................................................................169
Receive shift register 20 (RXS20)...............................................................................................................................169
[S]
Serial operating mode register 20 (CSIM20).......................................................................................170, 178, 180, 192
16-bit capture register 20 (TCP20)..............................................................................................................................112
16-bit compare register 20 (CR20)..............................................................................................................................112
16-bit multiplication result storage register 0 (MUL0)..................................................................................................202
16-bit timer counter 20 (TM20)....................................................................................................................................112
16-bit timer mode control register 20 (TMC20) ...........................................................................................................113
[T]
Timer clock select register 2 (TCL2)...........................................................................................................................138
Transmit shift register 20 (TXS20)...............................................................................................................................169
[W]
Watchdog timer mode register (WDTM)......................................................................................................................139
APPENDIX C REGISTER INDEX
User’s Manual U14643EJ2V0UD
410
C.2 Register Symbol Index (Alphabetical Order)
[A]
ADCR0: A/D conversion result register 0 .........................................................................................................143, 155
ADM0: A/D converter mode register 0............................................................................................................144, 156
ADS0: Analog input channel specification register 0 .....................................................................................145, 157
ASIM20: Asynchronous serial interface mode register 20.................................................................172, 178, 181, 193
ASIS20: Asynchronous serial interface status register 20................................................................................174, 182
[B]
BRGC20: Baud rate generator control register 20......................................................................................175, 183, 194
[C]
CR20: 16-bit compare register 20 .........................................................................................................................112
CR80: 8-bit compare register 80 .......................................................................................................................... 125
CSIM20: Serial operating mode register 20 ......................................................................................170, 17 8, 180, 192
[I]
IF0: Interrupt request flag register 0................................................................................................................. 210
IF1: Interrupt request flag register 1................................................................................................................. 210
INTM0: External interrupt mode register 0............................................................................................................. 212
[M]
MK0: Interrupt mask flag register 0......................................................................................................................211
MK1: Interrupt mask flag register 1......................................................................................................................211
MRA0: Multiplication data register A0 ................................................................................................................... 202
MRB0: Multiplication data register B0 ................................................................................................................... 202
MUL0: 16-bit multiplication result storage register 0............................................................................................. 202
MULC0: Multiplier control register 0 ........................................................................................................................ 204
[O]
OSTS: Oscillation stabilization time select register............................................................................................... 222
[P]
P0: Port 0........................................................................................................................................................... 82
P1: Port 1........................................................................................................................................................... 83
P2: Port 2........................................................................................................................................................... 84
P5: Port 5........................................................................................................................................................... 88
P6: Port 6........................................................................................................................................................... 89
PCC: Processor clock control register ........................................................................................................... 96, 103
PM0: Port mode register 0.................................................................................................................................... 90
PM1: Port mode register 1.................................................................................................................................... 90
PM2: Port mode register 2.....................................................................................................................90, 115, 127
PM5: Port mode register 5.................................................................................................................................... 90
PU0: Pull-up resistor option register 0.................................................................................................................. 91
PUB2: Pull-up resistor option register B2 ............................................................................................................... 92
APPENDIX C REGISTER INDEX
User’s Manual U14643EJ2V0UD 411
[R]
RXB20: Receive buffer register 20..........................................................................................................................169
RXS20: Receive shift register 20.............................................................................................................................169
[T]
TCL2: Timer clock select register 2 ......................................................................................................................138
TCP20: 16-bit capture register 20...........................................................................................................................112
TM20: 16-bit timer counter 20...............................................................................................................................112
TM80: 8-bit timer counter 80.................................................................................................................................125
TMC20: 16-bit timer mode control register 20..........................................................................................................113
TMC80: 8-bit timer mode control register 80 ...........................................................................................................126
TXS20: Transmit shift register 20............................................................................................................................169
[W]
WDTM: Watchdog timer mode register...................................................................................................................139
User’s Manual U14643EJ2V0UD
412
APPENDIX D REVISION HISTORY
The following table shows the revisi on history up to this edition. The “Applied to:” column indicates the chapters of
each edition in which the revision was applied. (1/2)
Edition Major Revision from Previous Edition Applied to:
• Addition of
µ
PD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1),
789114A(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1),
789134A(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2),
789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2),
789134A(A2), 78F9116B, 78F9136B, 78F9116B(A), 78F9136B(A), 78F9116B(A1),
78F9136B(A1)
• Addition of description related to expanded-specification products
Throughout
• Addition of 1.1 Expanded-Specification Products and Conventional-Specification
Products
• Addition of 1.10 Differences Between Standard Quality Grade Products and (A),
(A1), (A2) Products
CHAPTER 1 GENERAL
(
µ
PD789104A, 789114A
SUBSERIES)
Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1),
(A2) Products CHAPTER 2 GENERAL
(
µ
PD789124A, 789134A
SUBSERIES)
• Modification of description in 8.4.1 Operation as timer interrupt
• Modification of Figure 8-5 Timing of Timer Interrupt Operation
• Modification of description in 8.4.2 Operation as timer output
• Modification of description in Figure 8-7 Timer Output Timing
• Addition of 8.5 Notes on Using 16-Bit Timer 20
CHAPTER 8 16-BIT TIMER
20
Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80 CHAPTER 9 8-BIT
TIMER/EVENT COUNTER
80
Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins CHAPTER 11 8-BIT A/D
CONVERTER
(
µ
PD789104A, 789124A
SUBSERIES)
• Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0)
• Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins CHAPTER 12 10-BIT A/D
CONVERTER
(
µ
PD789114A, 789134A
SUBSERIES)
• Modification of Figure 13-1 Block Diagram of Serial Interface 20
• Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial
I/O mode
• Addition of 13.4.2 (2) (f) Reading receive data
CHAPTER 13 SERIAL
INTERFACE 20
Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register CHAPTER 15 INTERRUPT
FUNCTIONS
2nd
Revision of chapter CHAPTER 18
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
APPENDIX D REVISION HISTORY
User’s Manual U14643EJ2V0UD 413
(2/2)
Edition Major Revision from Previous Edition Applied to:
CHAPTER 21 to CHAPTER
31 ELECTRICAL
SPECIFICATIONS
CHAPTER 32, CHAPTER 33
CHARACTERISTICS
CURVES (REFERENCE
VALUES)
CHAPTER 34, CHAPTER 35
EXAMPLE OF RC
OSCILLATOR FREQUENCY
CHARACTERISTICS
(REFERENCE V ALUES)
CHAPTER 36 PACKAGE
DRAWING
Addition of chapters
CHAPTER 37
RECOMMENDED
SOLDERING CONDITIONS
Revision of appendix APPENDIX A
DEVELOPMENT TOOLS
APPENDIX B NOTES ON
TARGET SYSTEM DESIGN
Addition of appendices
APPENDIX D REVISION
HISTORY
2nd
Deletion of APPENDIX B EMBEDDED SOFTWARE −
