VNA7NV04D "OMNIFET II": FULLY AUTOPROTECTED POWER MOSFETS TARGET SPECIFICATION TYPE VNA7NV04D RDS(on) 60 m (*) Ilim 6 A (*) Vclamp 40 V (*) (*) Per each device LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTIONS INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PINS DIAGNOSTIC FEEDBACK THROUGH INPUT PINS ESD PROTECTION DIRECT ACCESS TO THE GATE OF EACH POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFETS DESCRIPTION The VNA7NV04D is a device |formed by two| monolithic OMNIFET II chips housed in a standard SO-16 package with double island. The OMNIFET II are designed in STMicroelectronics VIPower M0 Technology; they are intended for replacement of standard Power SO-16 (DOUBLE ISLAND) MOSFETS from DC up to 50KHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chips in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pins. BLOCK DIAGRAM DRAIN1 DRAIN2 OVERVOLTAGE CLAMP OVERVOLTAGE CLAMP INPUT1 GATE CONTROL GATE CONTROL OVER TEMPERATURE LINEAR CURRENT LIMITER LINEAR CURRENT LIMITER SOURCE1 October 2000 INPUT2 OVER TEMPERATURE SOURCE2 1/10 1 VNA7NV04D ABSOLUTE MAXIMUM RATING (per each device) Symbol VDS VIN IIN ID IR VESD Ptot Tj Tc Tstg Parameter Drain-source Voltage (VIN=0V) Input Voltage Input Current Drain Current Reverse DC Output Current Electrostatic Discharge (R=1.5K; C=100pF) Total Dissipation at Tc=25C Operating Junction Temperature Case Operating Temperature Storage Temperature Value Internally clamped Internally clamped +/- 20 Internally Limited - 12 4000 TBD Internally Limited Internally Limited -55 to 150 CONNECTION DIAGRAM (TOP VIEW) 1 N.C. 16 DRAIN 1 DRAIN 1 SOURCE 1 SOURCE 1 DRAIN 1 SOURCE 1 INPUT 1 N.C. DRAIN 2 SOURCE 2 SOURCE 2 DRAIN 2 8 DRAIN 2 9 SOURCE 2 INPUT 2 CURRENT AND VOLTAGE CONVENTIONS IIN1 VIN2 1 DRAIN 1 INPUT 2 DRAIN 2 IIN2 VIN1 2/10 ID1 INPUT 1 ID2 SOURCE 1 SOURCE 2 VDS1 VDS1 Unit V V mA A A V W C C C VNA7NV04D THERMAL DATA Symbol Rthj-case Parameter Thermal Resistance Junction-case Rthj-amb Thermal Resistance Junction-ambient Max Max Value 13 Unit C/W TBD C/W ELECTRICAL CHARACTERISTICS (per each device) -40C < Tj < 150C, unless otherwise specified OFF Symbol VCLAMP VCLTH VINTH IISS VINCL IDSS Parameter Drain-source Clamp Voltage Drain-source Clamp Threshold Voltage Input Threshold Voltage Supply Current from Input Pin Input-Source Clamp Voltage Zero Input Voltage Drain Current (VIN=0V) Test Conditions Min Typ Max Unit VIN=0V; ID=3.5A 40 45 50 V VIN=0V; ID=2mA 36 VDS=V IN; ID=1mA 0.5 VDS=0V; VIN=5V IIN=1mA IIN=-1mA VDS=13V; VIN=0V; T j=25C VDS=25V; VIN=0V 6.5 -1.0 V 2.5 V 100 250 A 7.4 8.5 -0.3 50 150 V A ON Symbol RDS(on) Parameter Static Drain-source On Resistance Test Conditions VIN=5V; ID=3.5A; Tj=25C Min Typ VIN=5V; ID=3.5A Max 60 120 Unit m DYNAMIC Symbol gfs (*) COSS Parameter Forward Transconductance Output Capacitance Test Conditions Min Typ Max Unit VDD=13V; ID=3.5A 10 S VDS=13V; f=1MHz; VIN=0V 230 pF SWITCHING Symbol td(on) tr td(off) tf td(on) tr td(off) tf Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time (dI/dt)on Turn-on Current Slope Qi Total Input Charge Test Conditions VDD=15V; ID=3.5A Vgen=5V; Rgen=10 (see figure 1) VDD=15V; ID=3.5A Vgen=5V; Rgen=1000 (see figure 1) VDD=15V; ID=3.5A Vgen=5V; Rgen=0 VDD=12V; ID=3.5A; VIN=5V (see figure 5) Min Typ 40 100 250 90 0.6 4.7 7.6 4.6 Max TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns s s s s 28 A/s TBD nC 3/10 1 VNA7NV04D ELECTRICAL CHARACTERISTICS (continued) (Tj=25C, unless otherwise specified) SOURCE DRAIN DIODE Symbol VSD (*) trr Qrr IRRM Parameter Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Test Conditions ISD=3.5A; VIN=0V ISD=3.5A; dI/dt=20A/s VDD=30V Min Reverse Recovery Current (see test circuit, figure 2) Typ 0.8 TBD TBD Max TBD Unit V ns C A PROTECTIONS (-40C < Tj < 125C, unless otherwise specified) Symbol Ilim tdlim T jsh Tjrs Igf Eas Parameter Drain Current Limit Step Response Current Limit Overtemperature Shutdown Overtemperature Reset Fault Sink Current Single Pulse Avalanche Energy Test Conditions VIN=6.5V; VDS=13V VIN=6.5V; VDS=13V 150 2 Typ 9 Max 12 Unit A 20 TBD s 175 C 15 C mA 135 VIN=5V; VDS=13V; Tj =Tjsh starting T j=25C; VDD=24V VIN=5V; Rgen=TBD; L=TBD (see figures 3 & 4) (*) Pulsed: Pulse duration = 300s, duty cycle 1.5% 4/10 Min 6 200 mJ VNA7NV04D PROTECTION FEATURES (per each device) During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 50KHz. The only difference from the user's standpoint is that a small DC current IISS (typ. 100A) flows into the INPUT pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current ID to Ilim whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. - OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 C, a typical value being 170 C. The device is automatically restarted when the chip temperature falls of about 15C below shut-down temperature. - STATUS FEEDBACK: in the case of an overtemperature fault condition (T j > Tjsh), the device tries to sink a diagnostic current Igf through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current Igf, the INPUT pin will fall to 0V. This will not however affect the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current IISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. 5/10 1 VNA7NV04D Fig.1: Switching Time Test Circuit for Resistive Load (per single chip) VD Rgen Vgen ID 90% tr tf 10% t Vgen td(on) td(off) t Fig.2: Test Circuit for Diode Recovery Times (per single chip) A A D I FAST DIODE OMNIFET S L=100uH B B 25 D Rgen Vgen VDD I OMNIFET S 8.5 6/10 1 VNA7NV04D Fig. 3: Unclamped Inductive Load Test Circuits (per single chip) Fig. 4: Unclamped Inductive Waveforms (per single chip) Fig. 5: Input Charge Test Circuit (per single chip) VIN GEN ND8003 7/10 1 VNA7NV04D SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. 0.35 b1 0.19 MAX. 0.068 0.2 0.004 0.007 0.46 0.013 0.018 0.25 0.007 1.65 b C 0.064 0.5 0.010 0.019 c1 45 (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 F 3.8 4.0 0.149 1.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 M S 1 TYP. 1.75 0.1 a2 8/10 MIN. 0.62 0.050 0.024 8 (max.) VNA7NV04D SO-16 TUBE SHIPMENT (no suffix) B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C A 50 1000 532 3.2 6 0.6 All dimensions are in mm. TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 8 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 9/10 1 VNA7NV04D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2000 STMicroelectronics - Printed in ITALY- All Rights Reserved. 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