October 2000 1/10
VNA7NV04D
“OMNIFET II”:
FULLY AUTOPROTECTED POWER MOSFETS
TARGET SPECIFICATION
1
■LINEAR CURRENT LIMITATION
■THERMAL SHUT DOWN
■SHORT CIRCUIT PROTECTIONS
■INTEGRATED CLAMP
■LOW CURRENT DRAWN FROM INPUT PINS
■DIAGNOSTIC FEEDBACK THROUGH INPUT
PINS
■ESD PROTECTION
■DIRECT ACCESS TO THE GATE OF EACH
POWER MOSFET (ANALOG DRIVING)
■COMPATIBLE WITH STANDARD POWER
MOSFETS
DESCRIPTION
The VNA7NV04D is a device |formed by two|
monolithic OMNIFET II chips housed in a
standard SO-16 package with double island.
The OMNIFET II are designed in
STMicroelectronics VIPower M0 Technology; they
are intended for replacement of standard Power
MOSFETS from DC up to 50KHz applications.
Built in thermal shutdown, linear current limitation
and overvoltage clamp protect the chips in harsh
environments.
Fault feedback can be detected by monitoringthe
voltage at the input pins.
TYPE RDS(on) Ilim Vclamp
VNA7NV04D 60 mΩ (*) 6 A (*) 40 V (*)
SO-16 (DOUBLE ISLAND)
BLOCK DIAGRAM
SOURCE2
OVERVOLTAGE
LINEAR
DRAIN1
SOURCE1
CLAMP
CURRENT
LIMITER
OVER
TEMPERATURE
GATE
CONTROL
DRAIN2
OVERVOLTAGE
CLAMP
LINEAR
CURRENT
LIMITER
GATE
CONTROL
OVER
TEMPERATURE
INPUT2
INPUT1
(*) Per each device
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VNA7NV04D
ABSOLUTE MAXIMUM RATING
(per each device)
CONNECTION DIAGRAM (TOP VIEW)
CURRENT AND VOLTAGE CONVENTIONS
Symbol Parameter Value Unit
VDS Drain-source Voltage (VIN=0V) Internally clamped V
VIN Input Voltage Internally clamped V
IIN Input Current +/- 20 mA
IDDrain Current Internally Limited A
IRReverse DC Output Current - 12 A
VESD Electrostatic Discharge (R=1.5KΩ; C=100pF) 4000 V
Ptot Total Dissipation at Tc=25°C TBD W
TjOperating Junction Temperature Internally Limited °C
TcCase Operating Temperature Internally Limited °C
Tstg Storage Temperature -55 to 150 °C
1
DRAIN 1
INPUT 1
SOURCE 2
IIN1
VIN1 INPUT 2
IIN2
SOURCE 1
DRAIN 2
VIN2
ID2
ID1
VDS1
VDS1
INPUT 2
SOURCE 2
SOURCE 2
SOURCE 2
INPUT 1
DRAIN 1
DRAIN 1
DRAIN 1
DRAIN 2
DRAIN 2
DRAIN 2
N.C.
SOURCE 1
N.C.
SOURCE 1
SOURCE 1 1
89
16
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VNA7NV04D
THERMAL DATA
ELECTRICAL CHARACTERISTICS (per each device) -40°C<T
j< 150°C, unlessotherwise specified
OFF
ON
DYNAMIC
SWITCHING
Symbol Parameter Value Unit
Rthj-case Thermal Resistance Junction-case Max 13 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max TBD °C/W
Symbol Parameter Test Conditions Min Typ Max Unit
VCLAMP Drain-source Clamp
Voltage VIN=0V; ID=3.5A 40 45 50 V
VCLTH Drain-source Clamp
Threshold Voltage VIN=0V; ID=2mA 36 V
VINTH Input Threshold Voltage VDS=VIN; ID=1mA 0.5 2.5 V
IISS SupplyCurrent fromInput
Pin VDS=0V; VIN=5V 100 250 µA
VINCL Input-Source Clamp
Voltage IIN=1mA
IIN=-1mA 6.5
-1.0 7.4 8.5
-0.3 V
IDSS Zero Input Voltage Drain
Current (VIN=0V) VDS=13V; VIN=0V; Tj=25°C
VDS=25V; VIN=0V 50
150 µA
Symbol Parameter Test Conditions Min Typ Max Unit
RDS(on) Static Drain-source On
Resistance VIN=5V; ID=3.5A; Tj=25°C
VIN=5V; ID=3.5A 60
120 mΩ
Symbol Parameter Test Conditions Min Typ Max Unit
gfs (*) Forward
Transconductance VDD=13V; ID=3.5A 10 S
COSS Output Capacitance VDS=13V; f=1MHz; VIN=0V 230 pF
Symbol Parameter Test Conditions Min Typ Max Unit
td(on) Turn-on Delay Time VDD=15V; ID=3.5A
Vgen=5V; Rgen=10Ω
(see figure 1)
40 TBD ns
trRise Time 100 TBD ns
td(off) Turn-off Delay Time 250 TBD ns
tfFall Time 90 TBD ns
td(on) Turn-on Delay Time VDD=15V; ID=3.5A
Vgen=5V; Rgen=1000Ω
(see figure 1)
0.6 TBD µs
trRise Time 4.7 TBD µs
td(off) Turn-off Delay Time 7.6 TBD µs
tfFall Time 4.6 TBD µs
(dI/dt)on Turn-on Current Slope VDD=15V; ID=3.5A
Vgen=5V; Rgen=0Ω28 A/µs
QiTotal Input Charge VDD=12V; ID=3.5A; VIN=5V
(see figure 5) TBD nC
1
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VNA7NV04D
ELECTRICAL CHARACTERISTICS (continued) (Tj=25°C, unless otherwise specified)
SOURCE DRAIN DIODE
PROTECTIONS (-40°C<T
j< 125°C, unless otherwise specified)
(*) Pulsed: Pulse duration = 300µs, dutycycle 1.5%
Symbol Parameter Test Conditions Min Typ Max Unit
VSD (*) Forward On Voltage ISD=3.5A; VIN=0V 0.8 V
trr Reverse Recovery Time ISD=3.5A; dI/dt=20A/µs
VDD=30V
(see test circuit, figure 2)
TBD ns
Qrr Reverse Recovery Charge TBD µC
IRRM Reverse Recovery Current TBD A
Symbol Parameter Test Conditions Min Typ Max Unit
Ilim Drain Current Limit VIN=6.5V; VDS=13V 6 9 12 A
tdlim Step Response Current
Limit VIN=6.5V; VDS=13V 20 TBD µs
Tjsh Overtemperature
Shutdown 150 175 °C
Tjrs Overtemperature Reset 135 °C
Igf Fault Sink Current VIN=5V; VDS=13V; Tj=Tjsh 15 mA
Eas Single Pulse
Avalanche Energy
starting Tj=25°C; VDD=24V
VIN=5V; Rgen=TBD; L=TBD
(see figures 3 & 4) 200 mJ
2
5/10
VNA7NV04D
PROTECTION FEATURES (per each device)
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC up
to 50KHz. The only difference from the user’s
standpoint is that a small DC current IISS (typ.
100µA) flows into the INPUT pin in order to supply
the internal circuitry.
The device integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics of the Power MOSFET
stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current IDto Ilim whatever the
INPUT pin voltages. When the current limiter is
active, the device operates in the linear region, so
power dissipation mayexceed the capability ofthe
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold Tjsh.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip temperature
and are not dependent on the input voltage. The
location of the sensing element on the chip in the
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs in the range 150 to 190 °C, a typical
value being 170 °C. The device is automatically
restarted when the chip temperature falls of about
15°C below shut-down temperature.
- STATUS FEEDBACK:
in the case of an overtemperature fault condition
(Tj>T
jsh), the device tries to sink a diagnostic
current Igf through the INPUT pin in order to
indicate fault condition. If driven from a low
impedance source, this current may be used in
order to warn the control circuit of a device
shutdown. If the drive impedance is high enough
so that the INPUT pin driver is not able to supply
the current Igf, the INPUT pin will fall to 0V. This
will not however affect the device operation:
no requirement is put on the current capability
of the INPUT pin driver except to be able to
supply the normal operation drive current IISS.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
1
6/10
VNA7NV04D
1
Fig.2: Test Circuit for Diode Recovery Times (per single chip)
Fig.1: Switching TimeTest Circuit for Resistive Load (per single chip)
Rgen
Vgen
VD
t
ID
90%
10%
t
Vgen td(on) td(off)
tf
tr
L=100uH
A
B
8.5 Ω
VDD
Rgen
FAST
DIODE
OMNIFET
A
D
I
S
25 ΩB
OMNIFET
D
S
I
Vgen
7/10
VNA7NV04D
1
Fig. 3: Unclamped Inductive Load Test Circuits
(per single chip) Fig. 4: Unclamped Inductive Waveforms
(per single chip)
Fig. 5: Input Charge Test Circuit
(per single chip)
GEN
ND8003
VIN
8/10
VNA7NV04D
1
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.004 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45°(typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
F 3.8 4.0 0.149 1.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S8°(max.)
SO-16 MECHANICAL DATA
9/10
VNA7NV04D
1
SO-16 TUBE SHIPMENT (no suffix)
1
All dimensions are in mm.
Base Q.ty 50
Bulk Q.ty 1000
Tube length (±0.5) 532
A3.2
B6
C(±0.1) 0.6
TAPE AND REEL SHIPMENT (suffix “13TR”)
All dimensions are in mm.
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C(±0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 16
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 8
Hole Diameter D (±0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (±0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNocomponents Components
500mm min 500mmmin
Emptycomponents pockets
saledwithcover tape.
User directionof feed
REEL DIMENSIONS
C
B
A
10/10
VNA7NV04D
Information furnished is believed to be accurate and reliable. However,STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publicationsupersedes and replaces all information previously supplied. STMicroelectronicsproducts
are not authorized for use as critical components in life support devices or systems without express written approvalof STMicroelectronics.
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