1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Extended Data Out (EDO) DRAM SMALL OUTLINE DIMM 641006EWS1G05TC 144 Pin 1Mx64 EDO SODIMM Unbuffered, 1k Self Refresh, 3.3V with SPD Pin Assignment General Description Pin# The 641006EWS1G05TC is a 1Mx64 bit, 5 chip, 3.3V, 144 Pin DIMM module consisting of (4) 1Mx16 (TSOP) DRAM and (1) 256x8 EEPROM for serial presence detect. The module is unbuffered and supports Extended Data Out (EDO) page mode access. Features * * * * * * * * * * * JEDEC-Standard 144-pin Small Outline Dual Inline Memory Module (SODIMM) Unbuffered Supports Extended Data-out (EDO) access cycles Based on 1Mx16 DRAM Power Supply: 3.3V 0.3V 64ms, 1024-cycle refresh Supports Self Refresh, RAS-Only-Refresh (ROR), CAS-before-RAS (CBR) refresh and Hidden refresh cycles Serial Presence Detect (SPD) LVTTL Compatible Inputs and Outputs One External Bank Gold PCB connector Valid Part Numbers Pin# Pin# Pin# 1 Vss 37 DQ8 73 OE* 109 A9 2 Vss 38 DQ40 74 RFU 110 A12 3 DQ0 39 DQ9 75 Vss 111 A10/AP 4 DQ32 40 DQ41 76 Vss 112 A13 5 DQ1 41 DQ10 77 RSVD 113 Vcc 6 DQ33 42 DQ42 78 RSVD 114 Vcc 7 DQ2 43 DQ11 79 RSVD 115 CAS2* 8 DQ34 44 DQ43 80 RSVD 116 CAS6* 9 DQ3 45 Vcc 81 Vcc 117 CAS3* 10 DQ35 46 Vcc 82 Vcc 118 CAS7* 11 Vcc 47 DQ12 83 DQ16 119 Vss 12 Vcc 48 DQ44 84 DQ48 120 Vss 13 DQ4 49 DQ13 85 DQ17 121 DQ24 14 DQ36 50 DQ45 86 DQ49 122 DQ56 15 DQ5 51 DQ14 87 DQ18 123 DQ25 16 DQ37 52 DQ46 88 DQ50 124 DQ57 17 DQ6 53 DQ15 89 DQ19 125 DQ26 18 DQ38 54 DQ47 90 DQ51 126 DQ58 19 DQ7 55 Vss 91 Vss 127 DQ27 20 DQ39 56 Vss 92 Vss 128 DQ59 21 Vss 57 RSVD 93 DQ20 129 Vcc 22 Vss 58 RSVD 94 DQ52 130 Vcc 23 CAS0* 59 RSVD 95 DQ21 131 DQ28 24 CAS4* 60 RSVD 96 DQ53 132 DQ60 25 CAS1* 61 RFU 97 DQ22 133 DQ29 26 CAS5* 62 RFU 98 DQ54 134 DQ61 27 Vcc 63 Vcc 99 DQ23 135 DQ30 28 Vcc 64 Vcc 100 DQ55 136 DQ62 29 A0 65 RFU 101 Vcc 137 DQ31 30 A3 66 RFU 102 Vcc 138 DQ63 31 A1 67 WE* 103 A6 139 Vss 32 A4 68 RFU 104 A7 140 Vss 33 A2 69 RAS0* 105 A8 141 SDA 34 A5 70 RFU 106 BA0 142 SCL 35 Vss 71 NC 107 Vss 143 Vcc 36 Vss 72 RFU 108 Vss 144 Vcc * Active Low Part Number 641006EWS1G05TC 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 Access Time 60ns Supply Voltage 3.3V 1 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Block Diagram X64 DRAM SODIMM, 1BANK with X16 DRAMs RAS0 CAS0 CAS4 U1 DQ(0:7) U3 DQ(32:39) CAS1 CAS5 DQ(8:15) DQ(40:16) CAS2 CAS6 U2 DQ(16:23) U4 DQ(48:55) CAS3 CAS7 DQ(24:31) DQ(56:63) CE CE : DRAMs U1 - U4 WE WE : DRAMs U1 - U4 A0 - AN A0 - AN : DRAMs U1 - U4 Bypass: SERIAL PD One 0.22uF capacitor per DRAM device. VCC U1 - U4 SCL SDA A0 VSS 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 U1 - U4 2 A1 A2 SA0 SA1 SA2 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Pin Descriptions Pin RAS# CAS# WE# OE# A# DQ0-DQ63 Vdd Vss SDA, SCL Name Row Address Strobe Column Address Strobe Write Enable Output Enable Address Lines Data Lines Power Supply Ground SPD Data/Clock Lines RFU Reserved for Future Use Reserved No Connection RSVD NC 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 Function RAS# is used to strobe the row address. CAS# is used to strobe the column address. WE# is used to control read/write cycles. OE# is the input/output control for the DQ lines. Address lines are multiplexed to specify the row and column address. Data input/output lines. Power Supply 3.3V0.3V Ground Serial Presence Detect (SPD) EEPROM bus lines. These line provides bi-directional data transfer over an I2C bus. Line is not connected in DIMM. Line is not connected in DIMM. Line is not connected in DIMM. 3 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Serial Presence Detect Matrix Byte # Function Binary 0 Define # of bytes written into EEPROM 10000000 80 1 Total # of bytes of SPD memory device 00001000 08 256 2 3 Fundamental memory type (EDO,SDRAM...) # of row addresses 00000010 00001010 02 0A EDO 10 4 # of column addresses 00001010 0A 10 5 # of module rows 00000001 01 1 6 Data width... 01000000 40 64 7 ...Data width continued 00000000 00 00 8 Voltage interface 00000011 03 3.3V 9 tRAC (-60) 00111100 3C 60ns 9 tRAC (-50) 00110010 32 50ns 10 tCAC (-60) 00001111 0F 15ns 10 tCAC (-50) 00001101 0D 13ns 11 DIMM configuration type (non-parity,ECC...) 00000000 00 non-parity 12 Refresh rate/type 10000000 80 Self Refresh (15.6s) 13 Primary DRAM width 00010000 10 16 14 Error checking DRAM width 00000000 00 0 15-127 Reserved 00000000 00 0 128-255 Not Used 00000000 00 0 76543210 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 4 Hex Description MS-LS 128 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature NOTE: Symbol Vin Iout Pt Topr Tst Value -0.5 to 4.6 50 5 0 to +70 -55 to +125 Units V mA W C C Permanent damage may occur if absolute maximum ratings are exceeded. Device should be operated within recommended operating conditions only. DC Characteristics (TA = 0 to 70C, Vcc = 3.3V 0.3V) Parameter Supply voltage Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Symbol Vss Vcc Vih Vil Voh Vol Min 0 3.0 2.0 -0.5 2.4 - Typ 0 3.3 - Max 0 3.6 Vcc+0.3 0.8 0.8 Units V V V V V V Note 16 16 16 DC Current Consumption (TA = 0 to 70C, Vcc = 3.3V 0.3V) Parameter Standby Current (TTL) Standby Current (CMOS) Operating Current Random Read/Write Operating Current Fast Page Mode Operating Current EDO Page Mode Refresh Current: RAS#-Only Refresh Current: CAS# before RAS# 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 Test Condition (RAS# = CAS# = VIH) All inputs = Vcc - 0.2V RAS#, CAS#, address cycling. tRC = tRC[MIN] RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] RAS# cycling, CAS#=VIH; tRC = tRC[MIN] RAS#, CAS#, address cycling tRC = tRC[MIN] 5 -50 8 4 770 N/A 580 770 960 -60 8 4 720 N/A 530 720 960 Unit mA mA mA mA mA mA mA Note 17 17 17, 18 17, 18 17, 18 17 17 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM Capacitance (TA = 0 to 70C, Vcc = 3.3V 0.3V, Vss = 0V) Parameter Input capacitance (Address) Symbol CI1 Typ - Max 20 Units pF Input capacitance (WE#, OE#) CI2 - 28 pF Input/Output capacitance (Data) CI/O - 7 pF Input capacitance (CAS#) CI3 - 7 pF - 10 pF - 28 pF Input/Output capacitance (SDA,SCL,SAm) Input capacitance (RAS#) C14 Note AC Characteristics (TA = 0 to 70C, Vcc = 3.3V 0.3V, Vss = 0V) Parameter Symbol -50 Min -60 Max 25 Min Max 30 Units Note ns 3, 5, 14 Access time from column address tAA Column address setup to CAS# precharge tACH 12 15 ns Column address hold time (from RAS#) tAR 40 50 ns Column address setup time tASC 0 0 ns Row address setup time tASR 0 0 Access time from CAS# tCAC Column address hold time tCAH 8 CAS# pulse width tCAS 8 CAS# to output in Low-Z tCLZ 3 3 Data output hold after CAS# LOW tCOH 3 3 ns CAS# precharge time tCP 8 10 ns Access time from CAS# precharge tCPA CAS# to RAS# precharge time tCRP 5 5 ns CAS# hold time tCSH 40 50 ns WRITE command to CAS# lead time tCWL 8 10 ns Data-in hold time tDH 8 10 ns 11 Data-in setup time tDS 0 0 ns 11 Output buffer turn-off delay tOFF 0 EDO Page-mode read or write cycle time tPC 20 Access time from RAS# tRAC RAS# to column address delay time tRAD 15 Row-address hold time tRAH 10 RAS# pulse width 15 ns 17 10 10 000 10 28 12 10 000 25 15 15 ns ns ns 2, 3 30 ns 9 ns tRAS, tRASP 50 Random read/write cycle time tRC 84 RAS# to CAS# delay time tRCD 20 Read command hold time tRCH 0 Read command setup time tRCS 0 Refresh Period (1024 cycles) tREF RAS# precharge time tRP 30 40 ns RAS# to CAS# precharge time tRPC 5 5 ns READ command hold time tRRH 0 0 ns RAS# hold time tRSH 13 17 ns WRITE command to RAS# lead time tRWL 13 15 t 2 Transition Time 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 60 ns 60 10 10 000 ns ns 25 50 10 000 104 35 20 6 8 ns 64 2 ns ns 0 50 ns ns 43 0 64 3, 4, 14 ns 35 0 ns ms 15 ns 50 ns 7 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM AC Characteristics (TA = 0 to 70C, Vcc = 3.3V 0.3V, Vss = 0V) Parameter Symbol -50 -60 WRITE command hold time tWCH Min 8 Max WRITE command hold time (RAS# referenced) tWCR 38 45 WE# command setup time tWCS 0 0 Output disable delay from WE# tWHZ 0 Write command pulse width tWP 5 12 Min 10 0 5 Units Note Max ns ns ns 15 10 ns ns Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. AC measurements assume tT = 5ns Assumes that tRCD tRCD (max.) and tRAD tRAD (max.). If tRCD or tRAD is greater that the maximum recommended value shown in this table, tRAC exceeds the value shown. Measured with a load circuit equivilaent to 1 TTL load and 100pF. Assumes that tRCD tRCD (max.), tRAD tRAD (max.). Assumes that tRCD tRCD (max.), tRAD tRAD (max.). tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vih and Vil. Operation with the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only, if tRCD is greater that the specified tRCD (max.) limit, then the access time is controlled exclusively by tCAC. Operation with the tRAD (max.) limit insures that tRAC (max.) can be met, tRAD (max.) is specified as a reference point only, if tRAD is greater that the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. Early write cycle only (tWCS tWCS (min.)) These parameters are referenced to CAS* leading edge in an early write cycle. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS* clock such as RAS* only refresh) tRASC defines RAS* pulse width in fast page mode cycles. Access time is determined by the longer of tAA or tCAC or tACP tREF defined is 1,024 refresh cycle. All voltages referenced to Vss Typical maximum current consumption levels Column address changed once per cycle 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 7 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM READ CYCLE tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tRRH tCAS CAS tAR tRAD tASR tASC tRAH ROW ADDR tCAH tACH COLUMN ROW tRCS WE tRCH tAA tRAC tCAC tCLZ DQ OPEN tOFF VALID DATA OPEN DON'T CARE UNDEFINED EARLY WRITE CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD CAS tRAD tASR ADDR tAR tASC tRAH tCAH tACH ROW COLUMN ROW tCWL tRWL tWCR tWCH tWCS tWP WE tDS DQ tDH VALID DATA DON'T CARE UNDEFINED 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 8 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tPC tRCD tCAS tCP tRSH tCAS tCP tCAS tCP CAS tAR tRAD tASR ADDR tACH tASC tRAH ROW tCAH COLUMN tCAH tASC tCAH tASC tCAH COLUMN tCAH COLUMN ROW tRCS tRCH WE tCLZ DQ tAA tAA tAA tRRH tRAC tCAC tCPA tCAC tCPA tCAC tOFF tCOH tCLZ VALID DATA OPEN VALID DATA VALID DATA OPEN DON'T CARE UNDEFINED EDO-PAGE-MODE READ-EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS tRCD tPC tCP tCAS tRSH tCAS tCP tCP CAS tAR tRAD tASR ADDR tRAH tACH tASC ROW tCAH tASC COLUMN (A) tCAH tASC COLUMN (B) tCAH ROW COLUMN (N) tRCH tRCS tWCS tAA tCPA WE tAA tRAC tCAC tCOH tCAC DQ OPEN tWCH VALID Dout tWHZ VALID Dout tDS tDH VALID Din DON'T CARE UNDEFINED 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 9 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM FAST/EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tRCD tCAS tCP tCAS tRSH tCAS tCP tCP CAS tAR tRAD tASR ADDR tACH tRAH tASC ROW tACH tCAH tASC COLUMN tACH tCAH tASC COLUMN tCWL tWCS tCWL tWCH tWP tWCS tCAH ROW COLUMN tCWL tWCH tWP tWCS tWCH tWP WE tWCR tDS DQ tRWL tCAC tDS VALID DATA tDH tDS VALID DATA tDH VALID DATA DON'T CARE UNDEFINED EDO READ CYCLE ( with /WE-controlled disable ) RAS tCSH tRCD tCRP tCAS tCP CAS t AR tRAD tASR ADDR tRAH ROW tASC t CAH tASC COLUMN COLUMN tRCH tWPZ tRCS tRCS WE tAA tRAC tCAC tWHZ tCLZ VALID DATA OPEN tCLZ DQ OPEN DON'T CARE UNDEFINED 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 10 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM /RAS-ONLY REFRESH CYCLE tRC tRAS tRP RAS tRPC tCRP CASL / CASH tASR tRAH ROW ADDR ROW OPEN Q WE DON'T CARE UNDEFINED CBR REFRESH CYCLE ( Addresses = DON'T CARE ) tRP RAS tRAS tRP tRAS tRPC tCP tCSR tRPC tCHR tCSR tCHR CAS OPEN DQ tWRP tWRH tWRP tWRH WE DON'T CARE UNDEFINED 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 11 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc. 1M x 64 Bit 3.3V UNBUFFERED EDO SODIMM OUTLINE DRAWING SIDE VIEW .055" .055" .150" FRONT SIDE BACK SIDE Note: Drawing is for component location only, assembly may not have all components installed. 1Mx64 UNBUFFERED 3.3V EDO SODIMM DS456-1 - 4/7/00 12 PNY Technologies Reserves the right to change product or specifications without notice 2000 PNY Technologies, Inc.